ispLSI 3160 Data Sheet

ispLSI 3160
®
Features
Functional Block Diagram
ORP
E3
E2
E1
E0
A0
ORP
OR
Array
A3
AND Array
D Q
D2
D Q
D Q
D Q
OR
Array
D Q
Twin
GLB
D1
ORP
ORP
A2
D3
D Q
A1
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
ISP and
Boundary
Scan TAP
ORP
ORP
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 160 I/O Pins
— 7000 PLD Gates
— 320 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
D0
D Q
D Q
B0
B1
C1
B3
C0
ORP
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
C2
B2
ORP
• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmability (ISP™) Using
Lattice ISP or Boundary Scan Test (IEEE 1149.1)
Protocol
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
Global Routing Pool
(GRP)
ORP
ORP
C3
Description
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The ispLSI 3160 is a High-Density Programmable Logic
Devices containing 320 Registers, 160 Universal I/O
pins, five Dedicated Clock Input Pins, five Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3160 features 5V in-system programmability and in-system diagnostic capabilities. The
ispLSI 3160 offers non-volatile reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems.
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
The basic unit of logic on the ispLSI 3160 device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...E3.
There are a total of 20 of these Twin GLBs in the ispLSI
3160 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and
eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from
the GRP.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
3160_09
1
December 2003
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
In-System Programmable High Density PLD
Specifications ispLSI 3160
I/O 48
I/O 50
I/O 52
I/O 54
I/O 57
I/O 59
I/O 61
I/O 63
I/O 56
I/O 58
I/O 60
I/O 62
I/O 143
I/O 141
I/O 139
I/O 137
I/O 135
I/O 133
I/O 131
I/O 129
I/O 142
I/O 140
I/O 138
I/O 136
I/O 134
I/O 132
I/O 130
I/O 128
TMS/MODE
I/O 110
I/O 108
I/O 106
I/O 104
I/O 111
I/O 109
I/O 107
I/O 105
A2
D1
A3
D0
I/O 102
I/O 100
I/O 98
I/O 96
I/O 103
I/O 101
I/O 99
I/O 97
B0
C3
I/O 94
I/O 92
I/O 90
I/O 88
I/O 95
I/O 93
I/O 91
I/O 89
B1
C2
I/O 86
I/O 84
I/O 82
I/O 80
I/O 87
I/O 85
I/O 83
I/O 81
B2
C1
I/O 78
I/O 76
I/O 74
I/O 72
I/O 79
I/O 77
I/O 75
I/O 73
B3
C0
I/O 70
I/O 68
I/O 66
I/O 64
I/O 71
I/O 69
I/O 67
I/O 65
ORP
I/O 49
I/O 51
I/O 53
I/O 55
I/O 119
I/O 117
I/O 115
I/O 113
D2
ORP
I/O 40
I/O 42
I/O 44
I/O 46
I/O 118
I/O 116
I/O 114
I/O 112
A1
Global Routing Pool
(GRP)
ORP
I/O 41
I/O 43
I/O 45
I/O 47
I/O 127
I/O 125
I/O 123
I/O 121
D3
ORP
I/O 32
I/O 34
I/O 36
I/O 38
Input Bus
I/O 33
I/O 35
I/O 37
I/O 39
Input Bus
I/O 24
I/O 26
I/O 28
I/O 30
I/O 126
I/O 124
I/O 122
I/O 120
A0
Input Bus
I/O 25
I/O 27
I/O 29
I/O 31
TDO/SDO
ORP
I/O 16
I/O 18
I/O 20
I/O 22
TRST
ORP
I/O 17
I/O 19
I/O 21
I/O 23
E0
TDI/SDI
ORP
I/O 8
I/O 10
I/O 12
I/O 14
E1
ISP and
Boundary
Scan TAP
Input Bus
I/O 9
I/O 11
I/O 13
I/O 15
E2
ORP
ORP
I/O 0
I/O 2
I/O 4
I/O 6
TCK/SCLK
I/O 151
I/O 149
I/O 147
I/O 145
I/O 150
I/O 148
I/O 146
I/O 144
ORP
E3
I/O 1
I/O 3
I/O 5
I/O 7
BSCAN/ispEN
I/O 159
I/O 157
I/O 155
I/O 153
I/O 158
I/O 156
I/O 154
I/O 152
Input Bus
Generic
Logic
Blocks
CLK 0
CLK 1
CLK 2
IOCLK 1
IOCLK 0
TOE
GOE1
GOE0
Figure 1. ispLSI 3160 Functional Block Diagram
Megablock
Y0
Y1
Y2
Y3
Y4
RESET
0139isp/3160
2
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Functional Block Diagram
Specifications ispLSI 3160
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 160 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Clocks in the ispLSI 3160 device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
The table below lists key attributes of the device along
with the number of resources available.
An additional feature of the ispLSI 3160 is the Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device's input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.
The 160 I/O cells are grouped into ten sets of 16 bits.
Pairs of these I/O groups are associated with a logic
Megablock through the use of the ORP. Each Megablock
is able to provide one Product Term Output Enable
(PTOE) signal which is globally distributed to all I/O cells.
The PTOE can be generated by any GLB in the Megablock.
Each I/O cell can select one of the seven available OEs
(two Global OEs and five PTOEs).
The ispLSI 3160 supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
Key Attributes of the ispLSI 3160
Attribute
Four Twin GLBs, 32 I/O cells and two ORPs are connected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of one pair of Twin GLBs are connected to a set
of 16 I/O cells by the ORP. The ispLSI 3160 device
contains five of these Megablocks.
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching.
Quantity
Twin GLBs
20
Registers
320
I/O Pins
160
Global Clocks
5
Global OE
2
Test OE
1
Table 1-0003A/3160
3
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Description (Continued)
Specifications ispLSI 3160
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
PARAMETER
SYMBOL
TA
VCC
VIL
VIH
Ambient Temperature
Supply Voltage
MIN.
MAX.
UNITS
0
70
°C
4.75
5.25
V
V
Input Low Voltage
0
0.8
Input High Voltage
2.0
VCC +1
V
Table 2-0005/3160
Capacitance (TA=25°C,f=1.0 MHz)
TYPICAL
UNITS
I/O Capacitance
10
pf
VCC = 5.0V, VI/O = 2.0V
Clock Capacitance
15
pf
VCC = 5.0V, VY = 2.0V
SYMBOL
C1
C2
PARAMETER
TEST CONDITIONS
Table 2-0006/3160
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
Data Retention
ispLSI Erase/Reprogram Cycles
Table 2-0008/3160
4
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Absolute Maximum Ratings 1
Specifications ispLSI 3160
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
Input Rise and Fall Time
10% to 90%
-125
≤ 2 ns
Others
≤ 3 ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 5V
R1
Device
Output
See Figure 2
Table 2-0003/3160
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
CL*
R2
*CL includes Test Fixture and Probe Capacitance.
Output Load conditions (See Figure 2)
0213A/3160
TEST CONDITION
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
A
B
C
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
CONDITION
PARAMETER
3
MIN.
TYP.
MAX. UNITS
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
Output Low Voltage
IOL= 8 mA
–
–
0.4
V
Output High Voltage
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
–
–
10
µA
Bscan/ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
ICC2,4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
–
275
–
mA
Table 2-0007/3160
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using ten 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC.
5
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Switching Test Conditions
Specifications ispLSI 3160
Over Recommended Operating Conditions
PARAMETER
TEST5
#2
COND.
-125
DESCRIPTION1
-100
-70
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
tpd1
A
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
—
7.5
—
10.0
—
15.0
ns
tpd2
A
2 Data Propagation Delay
—
10.0
—
13.0
—
18.0
ns
fmax
A
3 Clock Frequency with Internal Feedback
125
—
100
—
70.0
—
MHz
fmax (Ext.)
—
4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)
95.0
—
87.0
—
50.0
—
MHz
fmax (Tog.)
—
5 Clock Frequency, Max Toggle4
125
—
100
—
83.0
—
MHz
tsu1
—
6 GLB Reg. Setup Time before Clock, 4PT bypass
5.0
—
5.5
—
9.0
—
ns
3
tco1
A
7 GLB Reg. Clock to Output Delay, ORP bypass
—
4.5
—
5.0
—
9.0
ns
th1
—
8 GLB Reg. Hold Time after Clock, 4PT bypass
0.0
—
0.0
—
0.0
—
ns
tsu2
—
9 GLB Reg. Setup Time before Clock
6.0
—
6.5
—
11.0
—
ns
tco2
—
10 GLB Reg. Clock to Output Delay
—
5.0
—
5.5
—
10.0
ns
th2
—
11 GLB Reg. Hold Time after Clock
0.0
—
0.0
—
0.0
—
ns
t r1
A
12 Ext. Reset Pin to Output Delay
—
10.0
—
13.5
—
15.0
ns
trw1
—
13 Ext. Reset Pulse Duration
5.5
—
6.5
—
12.0
—
ns
tptoeen
B
14 Input to Output Enable
—
12.0
—
15.0
—
18.0
ns
tptoedis
C
15 Input to Output Disable
—
12.0
—
15.0
—
18.0
ns
tgoeen
B
16 Global OE Output Enable
—
7.0
—
9.0
—
12.0
ns
tgoedis
C
17 Global OE Output Disable
—
7.0
—
9.0
—
12.0
ns
ttoeen
—
18 Test OE Output Enable
—
8.0
—
12.0
—
15.0
ns
ttoedis
—
19 Test OE Output Disable
—
8.0
—
12.0
—
15.0
ns
twh
—
20 Ext. Sync. Clock Pulse Duration, High
4.0
—
5.0
—
6.0
—
ns
twl
—
21 Ext. Sync. Clock Pulse Duration, Low
4.0
—
5.0
—
6.0
—
ns
tsu3
—
22 I/O Reg. Setup Time before Ext. Sync. Clock (Y3, Y4)
4.0
—
4.5
—
5.0
—
ns
th3
—
23 I/O Reg. Hold Time after Ext. Sync. Clock (Y3, Y4)
0.0
—
0.0
—
0.0
—
ns
1.
2.
3.
4.
5.
Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions section.
6
Timing Ext.3160.eps
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External Switching Characteristics1, 2, 3
Specifications ispLSI 3160
Over Recommended Operating Conditions
PARAMETER
#2
-125
DESCRIPTION
-100
-70
MAX.
UNITS
MIN.
MAX.
MIN.
MAX.
MIN.
24 I/O Register Bypass
—
0.8
—
1.3
—
4.0
ns
25 I/O Latch Delay
—
7.4
—
9.2
—
13.5
ns
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
26 I/O Register Setup Time before Clock
4.3
—
4.8
—
5.8
—
ns
27 I/O Register Hold Time after Clock
-1.6
—
-1.6
—
-2.5
—
ns
28 I/O Register Clock to Out Delay
—
3.1
—
4.7
—
8.5
ns
29 I/O Register Reset to Out Delay
—
5.5
—
5.8
—
8.0
ns
30 GRP Delay
—
1.8
—
2.3
—
2.6
ns
GRP
tgrp
GLB
t4ptbp
t4ptbr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
ORP
torp
torpbp
31 4 Product Term Bypass Path Delay (Comb.)
—
3.1
—
3.1
—
4.2
ns
32 4 Product Term Bypass Path Delay (Reg.)
—
3.2
—
3.2
—
3.4
ns
33 1 Product Term/XOR Path Delay
—
3.9
—
4.1
—
4.6
ns
34 20 Product Term/XOR Path Delay
—
4.0
—
4.0
—
4.5
ns
35 XOR Adjacent Path Delay3
—
4.3
—
4.3
—
5.3
ns
36 GLB Register Bypass Delay
—
0.6
—
1.6
—
1.7
ns
37 GLB Register Setup Time before Clock
-0.2
—
-0.2
—
0.9
—
ns
38 GLB Register Hold Time after Clock
4.6
—
5.6
—
8.0
—
ns
39 GLB Register Clock to Output Delay
—
1.6
—
0.6
—
2.9
ns
40 GLB Register Reset to Output Delay
—
4.7
—
5.1
—
5.1
ns
41 GLB Product Term Reset to Register Delay
—
4.0
—
4.0
—
4.2
ns
42 GLB Product Term Output Enable to I/O Cell Delay
—
5.5
—
5.5
—
5.3
ns
43 GLB Product Term Clock Delay
3.0
3.6
3.0
3.6
3.2
4.0
ns
44 ORP Delay
—
1.2
—
1.2
—
1.9
ns
45 ORP Bypass Delay
—
0.2
—
0.7
—
0.9
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Timing Int.3160.eps
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Internal Timing Parameters1
Specifications ispLSI 3160
Over Recommended Operating Conditions
PARAMETER
#2
-125
DESCRIPTION
-100
-70
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNITS
Outputs
tob
46 Output Buffer Delay
—
1.6
—
2.6
—
3.3
ns
tobs
47 Output Buffer Delay, Slew Limited Adder
—
11.6
—
12.6
—
13.3
ns
toen
48 I/O Cell OE to Output Enabled
—
3.9
—
5.9
—
6.1
ns
todis
49 I/O Cell OE to Output Disabled
—
3.9
—
5.9
—
6.1
ns
tgy0/1/2
50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clk Line
0.6
1.1
1.1
1.1
1.9
1.9
ns
tioy3/4
51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line
0.3
1.6
0.3
1.6
0.8
2.5
ns
t gr
52 Global Reset to GLB and I/O Registers
—
3.5
—
4.6
—
4.7
ns
tgoe
53 Global OE Pad Buffer
—
3.1
—
3.1
—
5.9
ns
ttoe
54 Test OE Pad Buffer
—
4.1
—
6.1
—
8.9
ns
Clocks
Global Reset
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
8
Timing Int.2.3160.eps
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Internal Timing Parameters1
Specifications ispLSI 3160
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
#31
I/O Reg Bypass
I/O Pin
(Input)
#24
#52
GRP
#30
Input
D Register Q
RST
#25 - 29
4 PT Bypass
GLB Reg Bypass
ORP Bypass
#32
#36
#45
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
#33 - 35
Q
#44
RST
#52
Reset
Y3,4
#37 - 40
#51
Control RE
PTs
OE
#41 - 43 CK
#50
Y0,1,2
#53
GOE0,1
#54
TOE
0902/3160
Derivations of tsu, th and tco from the Product Term Clock 1
tsu
=
=
=
0.8ns =
Logic + Reg su - Clock (min)
(tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min))
(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)
(0.8 + 1.8 + 4.0) + (-0.2) - (0.8 + 1.8 + 3.0)
th
=
=
=
4.2ns =
Clock (max) + Reg h - Logic
(tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)
(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)
(0.8 + 1.8 + 3.6) + (4.6) - (0.8 + 1.8 + 4.0)
tco
=
=
=
10.1ns =
Clock (max) + Reg co + Output
(tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#24 + #30 + #43) + (#39) + (#44 + #46)
(0.8 + 1.8 + 3.6) + (1.1) + (1.2 + 1.6)
Table 2-0042/3160
Note: Calculations are based upon timing specifications for the ispLSI 3160-125L.
9
#46, 47
#48, 49
I/O Pin
(Output)
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
ispLSI 3160 Timing Model
Specifications ispLSI 3160
Power consumption in the ispLSI 3160 device depends
on two primary factors: the speed at which the device is
operating and the number of product terms used.
Figure 3 shows the relationship between power and
operating speed.
Figure 3. Typical Device Power Consumption vs fmax
600
ispLSI 3160
ICC (mA)
500
400
300
200
0
20
40
60
80
100 120 140
fmax (MHz)
Notes: Configuration of ten 16-bit Counters
Typical Current at 5V, 25° C
ICC can be estimated for the ispLSI 3160 using the following equation:
ICC = 50 + (# of PTs * 0.73) + (# of nets * Max. freq * 0.0105) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
0127/3160
Package Thermal Characteristics
For the ispLSI 3160-125LB272, it is strongly recommended that the actual Icc be verified to ensure that the
maximum junction temperature (TJ) with power supplied
is not exceeded. Depending on the specific logic design
and clock speed, airflow may be required to satisfy the
10
maximum allowable junction temperature (TJ) specification. Please refer to the Thermal Management section of
the Lattice Semiconductor Data Book or CD-ROM for
additional information on calculating TJ.
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Power Consumption
Specifications ispLSI 3160
Signal Name
GOE0, GOE1
Global Output Enable input pins.
Description
I/O
Input/Output Pins – These are the general purpose I/O pins used by the logic array.
TOE
Test Output Enable pin. This pin tristates all I/O pins when a logic low is driven.
RESET
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
Y0, Y1, Y2
Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on
the device.
Y3, Y4
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the I/O cells on the
device.
BSCAN/ispEN
Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP
controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State
Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put
the device in the programming mode and put all I/O pins in the high-Z state.
TDI/SDI
Input – This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When
ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used
as one of the two control pins for the ISP State Machine.
TCK/SCLK
Input – This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When
ispEN is logic low, it functions as a clock pin for the Serial Shift Register.
TMS/MODE
Input – This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high.
When ispEN is logic low, it functions as a pin to control the operation of the ISP State Machine.
TRST
Input – Test Reset, active low to reset the Boundary Scan State Machine.
TDO/SDO
Output – This pin performs two functions. When ispEN is logic low, it functions as the pin to read the ISP
data. When ispEN is high, it functions as Test Data Out.
GND
Ground (GND)
VCC
Vcc
NC1
No Connect.
Signal Locations
Signal
208-Pin PQFP
272-Ball BGA
GOE0, GOE1
133, 134
J19, J18
TOE
30
M3
RESET
28
M1
Y0, Y1, Y2, Y3, Y4 132, 130, 129, 128, 127
J20, K19, K20, L20, L18
BSCAN/ispEN
27
L4
TDI/SDI
25
L3
TCK/SCLK
24
L2
TMS/MODE
23
L1
TRST/NC1
29
M2
TDO/SDO
185
C10
GND
11, 26, 42, 53, 65, 78, 92, 104, 115,
131, 146, 157, 169, 183, 196, 208
A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, K9, K10,
K11, K12, L9, L10, L11, L12, M9, M10, M11, M12, N4, N17,
U4, U8, U13, U17
VCC
14, 39, 58, 80, 99, 118, 143, 162, 181, 203 D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15
NC1
76, 77, 79, 81, 180, 182, 184
A2, A6, A10, A14, A19, A20, B1, B2, B4, B10, B14, B16,
B17, B18, B19, C2, C3, C5, C7, C16, D2, D3, F18, F19, G3,
H3, K1, K17, K18, P20, R2, R3, R20, U11, U19, V5, V7, V11,
V14, V18, V19, W2, W3, W7, W11, W15, W17, W19, W20,
Y1, Y2, Y4, Y10, Y11, Y18, Y20
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Signal Descriptions
Specifications ispLSI 3160
Signal
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
PQFP BGA
31
32
33
34
35
36
37
38
40
41
43
44
45
46
47
48
49
50
51
52
54
55
56
57
59
60
61
62
63
64
66
67
M4
N1
N2
N3
P1
P2
R1
P3
T1
P4
T2
U1
T3
U2
V1
T4
U3
V2
W1
V3
W4
V4
U5
Y3
W5
Y5
V6
U7
W6
Y6
Y7
V8
Signal
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
PQFP BGA
68
69
70
71
72
73
74
75
82
83
84
85
86
87
88
89
90
91
93
94
95
96
97
98
100
101
102
103
105
106
107
108
W8
Y8
U9
V9
W9
Y9
W10
V10
Y12
W12
V12
U12
Y13
W13
V13
Y14
W14
Y15
Y16
U14
V15
W16
Y17
V16
U16
V17
W18
Y19
U18
T17
V20
U20
Signal
I/O 64
I/O 65
I/O 66
I/O 67
I/O 68
I/O 69
I/O 70
I/O 71
I/O 72
I/O 73
I/O 74
I/O 75
I/O 76
I/O 77
I/O 78
I/O 79
I/O 80
I/O 81
I/O 82
I/O 83
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
PQFP BGA
109
110
111
112
113
114
116
117
119
120
121
122
123
124
125
126
135
136
137
138
139
140
141
142
144
145
147
148
149
150
151
152
12
T18
T19
T20
R18
P17
R19
P18
P19
N18
N19
N20
M17
M18
M19
M20
L19
J17
H20
H19
H18
G20
G19
F20
G18
E20
G17
E19
D20
E18
D19
C20
E17
Signal
I/O 96
I/O 97
I/O 98
I/O 99
I/O 100
I/O 101
I/O 102
I/O 103
I/O 104
I/O 105
I/O 106
I/O 107
I/O 108
I/O 109
I/O 110
I/O 111
I/O 112
I/O 113
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
I/O 122
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
PQFP
153
154
155
156
158
159
160
161
163
164
165
166
167
168
170
171
172
173
174
175
176
177
178
179
186
187
188
189
190
191
192
193
BGA
Signal PQFP BGA
D18
C19
B20
C18
C17
D16
A18
A17
A16
C15
D14
B15
A15
C14
C13
B13
A13
D12
C12
B12
A12
B11
C11
A11
D10
A9
B9
C9
D9
A8
B8
C8
I/O 128
I/O 129
I/O 130
I/O 131
I/O 132
I/O 133
I/O 134
I/O 135
I/O 136
I/O 137
I/O 138
I/O 139
I/O 140
I/O 141
I/O 142
I/O 143
I/O 144
I/O 145
I/O 146
I/O 147
I/O 148
I/O 149
I/O 150
I/O 151
I/O 152
I/O 153
I/O 154
I/O 155
I/O 156
I/O 157
I/O 158
I/O 159
194
195
197
198
199
200
201
202
204
205
206
207
1
2
3
4
5
6
7
8
9
10
12
13
15
16
17
18
19
20
21
22
A7
B7
B6
A5
D7
C6
B5
A4
A3
D5
C4
B3
E4
C1
D1
E3
E2
E1
F3
G4
F2
F1
G2
G1
H2
H1
J4
J3
J2
J1
K2
K3
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
I/O Locations
Specifications ispLSI 3160
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
GND
I/O 139
I/O 138
I/O 137
I/O 136
VCC
I/O 135
I/O 134
I/O 133
I/O 132
I/O 131
I/O 130
GND
I/O 129
I/O 128
I/O 127
I/O 126
I/O 125
I/O 124
I/O 123
I/O 122
I/O 121
I/O 120
TDO/SDO
NC1
GND
NC1
VCC
NC1
I/O 119
I/O 118
I/O 117
I/O 116
I/O 115
I/O 114
I/O 113
I/O 112
I/O 111
I/O 110
GND
I/O 109
I/O 108
I/O 107
I/O 106
I/O 105
I/O 104
VCC
I/O 103
I/O 102
I/O 101
I/O 100
GND
ispLSI 3160 208-Pin PQFP (with Heat Spreader) Pinout Diagram
ispLSI 3160
Top View
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
I/O 99
I/O 98
I/O 97
I/O 96
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
GND
I/O 89
I/O 88
VCC
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
GOE1
GOE0
Y0
GND
Y1
Y2
Y3
Y4
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
VCC
I/O 71
I/O 70
GND
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GND
I/O 20
I/O 21
I/O 22
I/O 23
VCC
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
GND
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
1NC
1NC
GND
1NC
VCC
1NC
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
GND
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
VCC
I/O 56
I/O 57
I/O 58
I/O 59
GND
I/O 140
I/O 141
I/O 142
I/O 143
I/O 144
I/O 145
I/O 146
I/O 147
I/O 148
I/O 149
GND
I/O 150
I/O 151
VCC
I/O 152
I/O 153
I/O 154
I/O 155
I/O 156
I/O 157
I/O 158
I/O 159
TMS/MODE
TCK/SCLK
TDI/SDI
GND
BSCAN/ispEN
RESET
1TRST/NC
TOE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
VCC
I/O 8
I/O 9
GND
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
208-MQFP/3160
1. NC pins are not to be connected to any active signal, VCC or GND.
13
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Pin Configuration
Specifications ispLSI 3160
ispLSI 3160 272-Ball BGA Signal Diagram
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
NC1
NC1
I/O
102
I/O
103
I/O
104
I/O
108
NC1
I/O
112
I/O
116
I/O
119
NC1
I/O
121
I/O
125
I/O
128
NC1
I/O
131
I/O
135
I/O
136
NC1 GND
A
B
I/O 98 NC1
NC1
NC1
NC1
I/O
107
NC1
I/O
111
I/O
115
I/O
117
NC1
I/O
122
I/O
126
I/O
129
I/O
130
I/O
134
NC1
I/O
139
NC1
NC1
B
C
I/O
I/O 94 I/O 97 I/O 99 100
NC1
I/O
105
I/O
109
I/O
110
I/O
114
I/O
118
TDO/
SDO
I/O
123
I/O
127
NC1
I/O
133
NC1
I/O
138
NC1
NC1
I/O
141
C
D
I/O 91 I/O 93 I/O 96 GND
I/O
101
VCC
I/O
106
GND
I/O
113
VCC
I/O
120
I/O
124
GND
I/O
132
VCC
I/O
137
GND NC1
NC1
I/O
142
D
E
I/O 88 I/O 90 I/O 92 I/O 95
F
I/O 86 NC1
G
I/O 84 I/O 85 I/O 87 I/O 89
H
I/O 81 I/O 82 I/O 83 GND
A
NC1
VCC
2
1
I/O
140
I/O
143
I/O
144
I/O
145
E
ispLSI 3160
VCC
I/O
146
I/O
148
I/O
149
F
Bottom View
I/O
147
NC1
I/O
150
I/O
151
G
GND NC1
I/O
152
I/O
153
H
GOE GOE I/O 80
0
1
GND GND GND GND
I/O
154
I/O
155
I/O
156
I/O
157
J
Y1
NC1
NC1
GND GND GND GND
VCC
I/O
159
I/O
158
NC1
K
I/O 79
Y4
VCC
GND GND GND GND
BSCAN/
ispEN
TDI/
SDI
TCK/
TMS/
SCLK MODE
L
M
I/O 78 I/O 77 I/O 76 I/O 75
GND GND GND GND
I/O
0
TOE
TRST/ RESET
NC
M
N
I/O 74 I/O 73 I/O 72 GND
GND
I/O
3
I/O
2
I/O
1
N
P
NC1 I/O 71 I/O 70 I/O 68
I/O
9
I/0
7
I/O
5
I/O
4
P
R
NC1 I/O 69 I/O 67 VCC
NC1
I/O
6
R
T
I/O 66 I/O 65 I/O 64 I/O 61
U
I/O 63 NC1 I/O 60 GND I/O 56 VCC I/O 51 GND I/O 43 NC1
V
I/O 62 NC1
J
Y0
K
Y2
L
Y3
VCC NC1
I/O 15 I/O 12 I/O 10 I/O 8
T
VCC I/O 34 GND I/O 27 VCC I/O 22 GND I/O 16 I/O 13 I/O 11
U
NC1 I/O 57 I/O 55 I/O 52 NC1 I/O 46 I/O 42 NC1 I/O 39 I/O 35 I/O 31 NC1 I/O 26 NC1 I/O 21 I/O 19 I/O 17 I/O 14
V
W
NC1
Y
NC1 I/O 59 NC1 I/O 54 I/O 50 I/O 49 I/O 47 I/O 44 I/O 40 NC1
NC1 I/O 37 I/O 33 I/O 30 I/O 29 I/O 25 NC1 I/O 23 NC1
20
10
NC1 I/O 58 NC1 I/O 53 NC1 I/O 48 I/O 45 I/O 41 NC1 I/O 38 I/O 36 I/O 32 NC1 I/O 28 I/O 24 I/O 20 NC1
19
18
17
16
15
14
13
12
11
1. NCs are not to be connected to any active signals, Vcc or GND.
Note: Ball A1 indicator dot on top side of package.
14
9
8
7
6
5
4
3
NC1 I/O 18
2
NC1
1
W
Y
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Signal Configuration
Specifications ispLSI 3160
ispLSI
3160 – XXX X XXXX X
Device Family
Grade
Blank = Commercial
Device Number
Package
Q = PQFP (with Heat Spreader)
B272 = BGA
Speed
125 = 125 MHz fmax
100 = 100 MHz fmax
70 = 70 MHz fmax
Power
L = Low
0212B/3160
Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
125
7.5
ispLSI 3160-125LQ
208-Pin PQFP
125
7.5
ispLSI 3160-125LB272
272-Ball BGA
100
10
ispLSI 3160-100LQ
208-Pin PQFP
100
10
ispLSI 3160-100LB272
272-Ball BGA
70
15
ispLSI 3160-70LQ
208-Pin PQFP
70
15
ispLSI 3160-70LB272
272-Ball BGA
Table 2-0041B/3160
15
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Part Number Description