IDT 874005AG-04LF

ICS874005-04
PCI EXPRESS™ JITTER ATTENUATOR
GENERAL DESCRIPTION
FEATURES
The ICS874005-04 is a high performance DiffICS
erential-to-LVDS Jitter Attenuator designed for use
HiPerClockS™ in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The
ICS874005-04 has 2 PLL bandwidth modes: 300kHz and
2MHz. The 300kHz mode will provide maximum jitter
attenuation, but higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. The 2MHz bandwidth provides the best tracking
skew and will pass most spread profiles. The ICS874005-04
supports Serdes reference clock frequencies of 100MHz,
125MHz and 250MHz.
• Five differential LVDS output pairs
rd
• One differential clock input
• Supports 100MHz, 125MHz, and 250MHz Serdes reference
clocks
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 320MHz
• Input frequency range: 98MHz - 128MHz
• PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
• RMS phase jitter @ 100MHz (1.875MHz – 20MHz):
0.88ps (typical)
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4
TM
The ICS874005-04 uses IDT’s 3 Generation FemtoClock
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
• 3.3V operating supply
• Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
PLL BANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~300kHz (default)
1 = PLL Bandwidth: ~2MHz
BLOCK DIAGRAM
OEA Pullup
F_SELA Pulldown
QA0
BW_SEL Pulldown
0 = ~300kHz
1 = ~2MHz
F_SELA
0 ÷5 (default)
1 ÷4
nQA0
QA1
CLK Pulldown
nCLK Pullup
Phase
Detector
VCO
nQA1
490 - 640MHz
QB0
F_SELB
0 ÷2 (default)
1 ÷4
nQB0
QB1
M = ÷5 (fixed)
nQB1
QB2
nQB2
F_SELB Pulldown
nQB2
nQA1
QA1
VDDO
QA0
nQA0
MR
BW_SEL
VDDA
F_SELA
VDD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
QB2
VDDO
QB1
nQB1
QB0
nQB0
F_SELB
OEB
GND
GND
nCLK
CLK
ICS874005-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
MR Pulldown
OEB Pullup
IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
PIN ASSIGNMENT
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ICS874005AG-04 REV. A JULY 29, 2008
ICS874005-04
PCI EXPRESS™ JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1, 24
nQB2, QB2
Output
Differential output pair. LVDS interface levels.
2, 3
nQA1, QA1
Output
Differential output pair. LVDS interface levels.
4, 23
VDDO
Power
Output supply pins.
5, 6
QA0, nQA0
Output
7
MR
Input
8
BW_SEL
Input
9
VDDA
Power
10
F_SELA
Input
11
VDD
Power
12
OE A
Input
13
CLK
Input
14
nCLK
Input
15, 16
GND
Power
17
OEB
Input
18
F_SELB
Input
19, 20
nQB0, QB0
Output
21, 22
nQB1, QB1
Output
Description
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inver ted outputs
Pulldown
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pulldown PLL bandwidth input. See Table 3B. LVCMOS/LVTTL interface levels.
Analog supply pin.
Frequency select pin for QAx/nQAx outputs. See Table 3C.
Pulldown
LVCMOS/LVTTL interface levels.
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
active. When LOW, the QAx/nQAx outputs are in a high impedance
Pullup
state. LVCMOS/LVTTL interface levels. See Table 3A.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx/nQBx outputs are in a high impedance
Pullup
state. LVCMOS/LVTTL interface levels. See Table 3A.
Frequency select pin for QBx/nQBx outputs. See Table 3C.
Pulldown
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
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PCI EXPRESS™ JITTER ATTENUATOR
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs
TABLE 3B. PLL BANDWIDTH CONTROL, fREF = 100MHZ
Outputs
Inputs
OEA/OEB
QAx/nQAx
QBx/nQBx
0
High Impedance
High Impedance
BW_SEL
0
PLL Bandwidth
~300kHz (default)
1
Enabled
Enabled
1
~2MHz
TABLE 3C. OUTPUT FREQUENCY FOR INPUT FREQUENCY = 100MHZ
Inputs
Outputs
F_SELA
F_SELB
QAx/nQAx
QBx/nQBx
0 (default)
0 (default)
VCO/5, 100MHz
VCO/2, 250MHz
0
1
VCO/5, 100MHz
VCO/4, 125MHz
1
0
VCO/4, 125MHz
VCO/2, 250MHz
1
1
VCO/4, 125MHz
VCO/4, 125MHz
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 82.3°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3. 3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.10
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
80
mA
IDDA
Analog Supply Current
10
mA
IDDO
Output Supply Current
75
mA
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PCI EXPRESS™ JITTER ATTENUATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Maximum
Units
CLK
VDD = VIN = 3.465V
Test Conditions
15 0
µA
nCLK
VDD = VIN = 3.465V
5
µA
CLK
VDD = VIN = 3.465V
-5
µA
nCLK
VDD = VIN = 3.465V
-150
µA
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage; NOTE 1
Minimum
VCMR
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
Typical
0.15
1. 3
V
GND + 0.5
VDD - 0.85
V
Maximum
Units
454
mV
50
mV
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
247
1.125
1.25
1.375
V
50
mV
Maximum
Units
320
MHz
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fMAX
tjit(θ)
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
tjit(cc)
Cycle-to-Cycle Jitter, NOTE 2
tsk(o)
Output Skew; NOTE 3
tsk(b)
Bank Skew: NOTE 4
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
98
100MHz, Integration Range:
(1.875MHz – 20MHz)
QA, QB = ÷4
0.88
QA = ÷5
ps
35
ps
75
ps
90
ps
QAx
15
ps
QBx
68
ps
500
ps
20% to 80%
30 0
odc
Output Duty Cycle
48
52
%
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and frequency, and with equal load conditions.
Measured at the differential cross points.
NOTE 4: Defined as skew within a bank of outputs at the same supply voltage and frequency, and with equal load
conditions.
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PCI EXPRESS™ JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
VDD,
VDDO
3.3V±5%
POWER SUPPLY
+ Float GND –
nCLK
Qx
VDDA
V
V
Cross Points
PP
LVDS
CMR
CLK
nQx
GND
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQA0, nQA1
nQB0:nQB2
nQx
QA0, QA1
QB0:QB2
Qx
➤
➤
tcycle n
➤
tcycle n+1
➤
nQy
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Qy
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nQA0, nQA1
nQB0:nQB2
nQx
Qx
QA0, QA1
QB0:QB2
nQy
t PW
t
Qy
tsk(b)
odc =
PERIOD
t PW
x 100%
t PERIOD
BANK SKEW
IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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PCI EXPRESS™ JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
VDD
VDD
out
100
➤
DC Input
LVDS
VOD/Δ VOD
out
out
➤
LVDS
➤
DC Input
➤
out
➤
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
nQA0, nQA1
nQB0:nQB2
80%
80%
VOD
QA0, QA1
QB0:QB2
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
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PCI EXPRESS™ JITTER ATTENUATOR
APPLICATION INFORMATION
POWER SUPPLY F ILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter
perfor mance, pow er supply isolation is required. The
ICS874005-04 provides separate power supplies to isolate
any high switching noise from the outputs to the internal PLL.
VDD , V DDA and V DDO should be individually connected to the
power supply plane through vias, and 0.01µF bypass
capacitors should be used for each pin. Figure 1 illustrates
this for a generic VDD pin and also shows that VDDA requires
that an additional10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LVDS OUTPUTS
All unused LVDS output pairs can be either left floating or
ter minated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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PCI EXPRESS™ JITTER ATTENUATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL and LVHSTL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 3A to 3F show interface examples for the
HiPerClockS CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm
the driver termination requirements. For example in Figure 3A,
the input termination applies for IDT HiPerClockS open emitter
LVHSTL drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
2.5V
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
2.5V
3.3V
3.3V
2.5V
*R3
33
R3
120
Zo = 50Ω
R4
120
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
HCSL
*R4
33
R1
50
R2
50
nCLK
HiPerClockS
Input
HiPerClockS
SSTL
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
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PCI EXPRESS™ JITTER ATTENUATOR
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS output buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
The decoupling capacitor should be located as close as possible
to the power pin. The input is driven by a 3.3V LVPECL driver.
Figure 5 shows an example of ICS874005-04 application
schematic. In this example, the device is operated at VDD= 3.3V.
VDD = 3.3V
VDDO = 3.3V
Zo = 50 Ohm
+
U1
R1
10
C3
10uF
C4
0.01u
MR
BW_SEL
F_SELA
OEA
1
2
3
4
5
6
7
8
9
10
11
12
R2
100
nQB2
nQA1
QA1
VDDO
QA0
nQAO
MR
BW_SEL
VDDA
F_SELA
VDD
OEA
QB2
VDDO
QB1
nQB1
QB0
nQB0
F_SELB
OEB
GND
GND
nCLK
CLK
24
23
22
21
20
19
18
17
16
15
14
13
-
Zo = 50 Ohm
F_SELB
OEB
Zo = 50 Ohm
+
874005_tssop24
ICS874005-04
R3
100
Zo = 50 Ohm
Zo = 50 Ohm
-
nCLK
Zo = 50 Ohm
CLK
LVPECL Driv er
(U1:11)
C5
10uf
(U1:4)
C6
.1uf
R4
50
R5
50
(U1:23)
C7
.1uf
R6
50
C8
.1uf
FIGURE 5. ICS874005-04 SCHEMATIC EXAMPLE
IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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ICS874005AG-04 REV. A JULY 29, 2008
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PCI EXPRESS™ JITTER ATTENUATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874005-04.
Equations and example calculations are also provided.
1. Power Dissipation (typical).
The total power dissipation for the ICS874005-04 is the sum of the core power plus the analog power plus the power dissipated in
the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 10mA) = 311.85mW
•
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.875mW
Total Power_MAX = 311.85mW + 259.875mW = 571.725mW
2. Junction Temperature (typical).
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.572W * 82.3°C/W = 117.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board.
TABLE 6. THERMAL RESISTANCE θJA FOR 24-LEAD TSSOP, FORCED CONVECTION
θ JA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
10
0
1
2.5
82.3°C/W
78.0°C/W
75.9°C/W
ICS874005AG-04 REV. A JULY 29, 2008
ICS874005-04
PCI EXPRESS™ JITTER ATTENUATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θ JA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
82.3°C/W
78.0°C/W
75.9°C/W
TRANSISTOR COUNT
The transistor count for ICS874005-04 is: 1428
PACKAGE OUTLINE AND PACKAGE DIMENSIONS
PACKAGE OUTLINE - G SUFFIX
FOR
24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
24
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
E
E1
7.90
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
874005AG-04LF
ICS874005A04L
24 Lead "Lead-Free" TSSOP
tube
0°C to 70°C
874005AG-04LFT
ICS874005A04L
24 Lead "Lead-Free" TSSOP
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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PCI EXPRESS™ JITTER ATTENUATOR
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
Corporate Headquarters
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
[email protected]
+480-763-2056
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
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