IDT 840S06AKILF

PRELIMINARY
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
General Description
Features
The ICS840S06I is a PLL-based clock generator
specifically designed for Cavium Networks SoC
HiPerClockS™
processors. This high performance device is
optimized to generate the processor core reference
clock, the DDR reference clocks, the PCI/PCI-X bus
clocks, and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs,
and edge rates that easily meet the input requirements for the
OCTEON processors. The output frequencies are generated from
a 25MHz external input source or an external 25MHz parallel
resonant crystal. The extended temperature range of the
ICS840S06I supports telecommunication, networking, and
storage requirements.
•
Six LVCMOS/ LVTTL outputs, 20Ω typical output impedance
- One selectable core clock for the processor
- One selectable clock for the PCI/ PCI-X bus
- One 125MHz clock reference for GbE MAC
- Three 25MHz clock references for GbE PHY
•
Selectable external crystal or differential (single-ended) input
source
•
Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
•
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS,
LVHSTL, SSTL, HCSL input levels
•
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
•
•
•
Full 3.3V or mixed 3.3V core/2.5V output supply mode
ICS
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Applications
•
•
Systems using OCTEON MIPS64 Broadband Processors
•
802.11 a/b/g/n wireless for home data and multimedia
distribution
•
•
•
•
•
QoS for high quality Voice, Video, and Data service
Networking, control and storage equipment, including routers,
switches, application-aware gateways, triple-play gateways,
WLAN and 3G/4G access and aggregation devices, storage
arrays, storage networking equipment, servers, and intelligent
NICs
Audio/Video Storage and distribution
VDDO_C
QC
GND
VDDO_REF
QREF2
High-performance NAS
QREF1
Next-generationPON, VDSL2, and Cable networks
QREF0
VDDO_REF
Pin Assignment
32 31 30 29 28 27 26 25
nXTAL_SEL
5
CLK
6
nCLK
7
GND
8
32-Lead VFQFN
32-Lead VFQFN
5mm x 5mm x 0.75mm
5mm x 5mm x 0.75mm
package body
Package body
K Package
K Package
Top View
Top View
22
CORE_SEL
21
GND
20
GND
9
10 11 12 13 14 15 16
19
nOE_REF
18
QA
17
VDDO_A
VDDA
XTAL_OUT 4
QB
VDD
3
23
nc
XTAL_IN
ICS840S06I
ICS8430S07I
nc
2
VDDO_B
nc
nPLL_SEL
24
nc
1
PCI_SEL0
VDD
PCI_SEL1
Consumer space media server
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ CLOCK GENERATOR
1
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Block Diagram
nPLL_SEL
nXTAL_SEL
XTAL_IN
25 MHz
XTAL
OSC
XTAL_OUT
25 MHz
0
1
PLL
QA
Processor Core Clock
(LVCMOS)
00 = 133.333 MHz
01 = 100.000 MHz
10 = 66.667 MHz
11 = 33.333 MHz
QB
PCI or PCI-X Clock
(LVCMOS)
125 MHz GbE CLK
QC
Gigabit Ethernet MAC
Clock (LVCMOS)
0
1
CLK
nCLK
0 = 50.000 MHz
1 = 33.333 MHz
CORE_SEL
QREF0
PCI_SEL1:0
Clock Output
Control Logic
25 MHz GbE CLK
nOE_REF
IDT™ / ICS™ CLOCK GENERATOR
2
\
\ Gigabit Ethernet
QREF1 / PHY Clocks
/ (LVCMOS)
QREF2
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 15
VDD
Power
2
nPLL_SEL
Input
3,
4
XTAL_IN,
XTAL_OUT
Input
5
nXTAL_SEL
Input
Pulldown
Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK)
input when HIGH. LVCMOS/LVTTL interface levels.
6
CLK
Input
Pulldown
Non-inverting differential clock input.
7
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
8, 20, 21, 27
GND
Power
9,
10
PCI_SEL1,
PCI_SEL0
Input
11, 12, 13, 14
nc
Unused
16
VDDA
Power
Analog supply pin.
17
VDDO_A
Power
Bank A output supply pin. 3.3 V or 2.5V supply.
18, 23, 26, 29,
30, 31
QA, QB, QC,
QREF2,
QREF1, QREF0
Output
Single-ended outputs. LVCMOS/LVTTL interface levels.
19
nOE_REF
Input
Pulldown
Active LOW output enable. When logic HIGH, the outputs are in high
impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/
LVTTL interface levels.
22
CORE_SEL
Input
Pulldown
Selects the processor core clock output frequency. The output frequency is
50MHz when LOW, and 33.333MHz when HIGH. See Table 3A.
LVCMOS/LVTTL interface levels.
24
VDDO_B
Power
Bank B output supply pin. 3.3 V or 2.5V supply.
25
VDDO_C
Power
Bank C output supply pin. 3.3 V or 2.5V supply.
28, 32
VDDO_REF
Power
REF bank output supply pins. 3.3 V or 2.5V supply.
Core supply pins.
Pulldown
PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, deselects
the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
Power supply ground.
Pulldown
Selects the PCI/PCI-X reference clock output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ CLOCK GENERATOR
3
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
Input Pullup Resistor
Output Impedance
Typical
Maximum
Units
4
pF
VDD, VDDO_X = 3.465V
TBD
pF
VDD = 3.465V, VDDO_X = 2.625V
TBD
pF
51
kΩ
51
kΩ
RPULLDOWN Input Pulldown Resistor
ROUT
Minimum
QA, QB, QC,
QREF[0:2]
VDDO_X = 3.465V
20
Ω
QA, QB, QC,
QREF[0:2]
VDDO_X = 2.625V
25
Ω
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF.
Function Tables
Table 3A. Control Input Function Table
Input
Output Frequency
CORE_SEL
QA
0
50MHz
1
33.333MHz
Table 3B. Control Input Function Table
Inputs
Output Frequency
PCI_SEL1
PCI_SEL0
QB
0
0
133.333MHz
0
1
100.000MHz
1
0
66.6667MHz
1
1
33.333MHz
IDT™ / ICS™ CLOCK GENERATOR
4
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO (LVCMOS)
-0.5V to VDD + 0.5V
Outputs, IO (LVPECL)
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
39.5°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.16
3.3
VDD
V
VDDO_X
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
140
mA
IDDA
Analog Supply Current
16
mA
IDDO_X
Output Supply Current
20
mA
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF.
Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.16
3.3
VDD
V
VDDO_X
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
130
mA
IDDA
Analog Supply Current
16
mA
IDDO_X
Output Supply Current
16
mA
NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF.
IDT™ / ICS™ CLOCK GENERATOR
5
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
150
µA
Input
High Current
nPLL_SEL,
CORE_SEL,
nXTAL_SEL,
PCI_SEL[0:1],
nOE_REF
VDD = VIN = 3.465V
IIL
Input
Low Current
nPLL_SEL,
CORE_SEL,
nXTAL_SEL,
PCI_SEL[0:1],
nOE_REF
VDD = 3.465V, VIN = 0V
-10
µA
V
Output High Voltage; NOTE 1
VDDO_X = 3.465V
2.6
VOH
VDDO_X = 2.625V
1.8
V
VOL
Output Low Voltage: NOTE 1
IIH
VDDO_X = 3.465V or 2.625V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagram.
Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.5
VDD – 0.85
V
CLK/nCLK
Minimum
Typical
VDD = VIN = 3.465V
Maximum
Units
150
µA
CLK
VDD = 3.465V, VIN = 0V
-10
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
µA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2. Common mode voltage is defined as VIH.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
300
µW
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
IDT™ / ICS™ CLOCK GENERATOR
6
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Parameter Symbol
fMAX
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
QA
CORE_SEL = 0
50
MHz
QA
CORE_SEL = 1
33.333
MHz
QB
PCI_SEL[1:0] = 00
133.333
MHz
QB
PCI_SEL[1:0] = 01
100
MHz
QB
PCI_SEL[1:0] = 10
66.667
MHz
QB
PCI_SEL[1:0] = 11
33.333
MHz
QC
125
MHz
QREF[0:2]
25
MHz
400
ps
tsk(b)
Bank Skew;
NOTE 2, 4
QREF[0:2]
tsk(pp)
Part-to-Part Skew;
NOTE 3, 4
QREF[0:2]
tjit(cc)
Cycle-to-Cycle
Jitter
QA, QB,
60
ps
QC
100
ps
tjit(Ø)
RMS Phase Jitter,
(Random); NOTE 1
QREF[0:2]
tR / tF
Output
Rise/Fall Time
QA, QB, QC,
QREF[0:2]
odc
Output Duty Cycle
QA, QB, QC,
QREF[0:2]
QC
ps
25MHz (10kHz to 5MHz)
0.73
ps
125MHz (1.875MHz to 20MHz)
0.78
ps
20% to 80%
0.80
ns
40
60
%
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Refer to the phase noise plot.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ CLOCK GENERATOR
7
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Parameter Measurement Information
2.05V±5%
1.65V±5%
1.25V±5%
1.65V±5%
2.05V±5%
SCOPE
VDD,
SCOPE
VDD
VDDO_X
VDDA
VDDO_X
Qx
LVCMOS
Qx
VDDA
LVCMOS
GND
GND
-
-1.65V±5%
-1.25V±5%
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
VDD
Par t 1
V
DDOX
Qx
nCLK
V
V
Cross Points
PP
2
CMR
Par t 2
CLK
Qy
V
DDOX
2
tsk(pp)
GND
LVCMOS Part-to-Part Skew
Differential Input Level
Noise Power
Phase Noise Plot
80%
80%
Phase Noise Mask
QA:QC,
QREF[0:2]
20%
20%
tR
f1
Offset Frequency
tF
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
IDT™ / ICS™ CLOCK GENERATOR
Output Rise/Fall Time
8
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Parameter Measurement Information, continued
VDDOX
2
V
VDDOX
2
DDOX
2
➤
QREF[0:2]
V
V
DDOX
QA:QC,
QREF[0:2]
DDOX
2
tcycle n
➤
QREF[0:2]
➤
2
tcycle n+1
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
tsk(b)
Bank Skew
Cycle-to-Cycle Jitter
V
DDOX
QA:QC,
QREF[0:2]
2
t PW
t
PERIOD
t PW
odc =
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
IDT™ / ICS™ CLOCK GENERATOR
9
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS840S06I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO_X
should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 2 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the VDDA pin.
IDT™ / ICS™ CLOCK GENERATOR
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 2. Power Supply Filtering
10
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
All unused LVCMOS outputs can be left floating We recommend
that there is no trace attached.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ CLOCK GENERATOR
11
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
HiPerClockS
Input
LVHSTL
R1
50
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
LVPECL
R2
50
R1
50
R2
50
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
2.5V
*R3
33
R3
120
Zo = 50Ω
R4
120
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33
R1
50
R2
50
HiPerClockS
Input
HiPerClockS
SSTL
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
IDT™ / ICS™ CLOCK GENERATOR
12
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Crystal Input Interface
The ICS840S06I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 4 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
22p(TBD)
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p(TBD)
Figure 4. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 5. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 5. General Diagram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ CLOCK GENERATOR
13
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 6. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as many
vias connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz
copper via barrel plating. This is desirable to avoid any solder
wicking inside the via during the soldering process which may
result in voids in solder between the exposed pad/slug and the
thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
IDT™ / ICS™ CLOCK GENERATOR
14
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS840S06I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS840S06I is the sum of the core power, analog power, and power dissipated in the load. The following
is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core Output Power Dissipation
•
Power (core)_MAX = VDD_MAX * (IEE_MAX + IDDA + IDDO) = 3.465V * (140mA + 16mA + 20mA) = 609.84mW
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.8mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (24.8mA)2 = 12.3mW per output
•
Total Power Dissipation on the ROUT
Total Power (ROUT) = 12.3mW * 6 = 73.8mW
•
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465V)2 = 3mW per output
Total Power (25MHz) = 3mW * 3 = 9mW
•
Dynamic Power Dissipation at 133MHz
Power (133MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133MHz * (3.465V)2 = 16mW per output
Total Power (133MHz) = 16mW * 3 = 48mW
Total Power Dissipation
•
Total Power
= Power (core) + Total Power (ROUT) + Total Power (25MHz) + Total Power (133MHz)
= 610mW + 73.8mW + 9mW + 48mW
= 741mW
IDT™ / ICS™ CLOCK GENERATOR
15
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 39.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.741W * 39.5°C/W = 114°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection
θJA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT™ / ICS™ CLOCK GENERATOR
0
1
2.5
39.5°C/W
34.5°C/W
31.0°C/W
16
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Reliability Information
Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN
θJA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
39.5°C/W
34.5°C/W
31.0°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS840S06I is: 10,871
IDT™ / ICS™ CLOCK GENERATOR
17
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
L
N
e (Ty p.)
2 If N & N
1
Anvil
Singula tion
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
C
D2
2
Th er mal
Ba se
D2
C
The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package
dimensions are in Table 9 below.
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ CLOCK GENERATOR
18
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Ordering Information
Table 10. Ordering Information
Part/Order Number
840S06AKILF
840S06AKILFT
Marking
ICS40S06AIL
ICS40S06AIL
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ CLOCK GENERATOR
19
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Contact Information:
www.IDT.com
www.IDT.com
Sales
Technical Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
[email protected]
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA