CA3060 Semiconductor T UCT ROD ACEMEN 47 P E 7 T L OLE REP 00-442-7 OBS ENDED 8 110kHz, Operational M ns 1 .com COM pplicatio @harris E R NO ntral A entapp Transconductance Amplifier Array Ce : c Call or email January 1999 Description • Low Power Consumption as Low as 100mW Per Amplifier The CA3060 monolithic integrated circuit consists of an array of three independent Operational Transconductance Amplifiers (see Note). This type of amplifier has the generic characteristics of an operational voltage amplifier with the exception that the forward gain characteristic is best described by transconductance rather than voltage gain (open-loop voltage gain is the product of the transconductance and the load resistance, gMRL). When operated into a suitable load resistor and with provisions for feedback, these amplifiers are well suited for a wide variety of operational-amplifier and related applications. In addition, the extremely high output impedance makes these types particularly well suited for service in active filters. • Independent Biasing for Each Amplifier • High Forward Transconductance • Programmable Range of Input Characteristics • Low Input Bias and Input Offset Current • High Input and Output Impedance • No Effect on Device Under Output Short-Circuit Conditions • Zener Diode Bias Regulator Applications • For Low Power Conventional Operational Amplifier Applications • Active Filters • Comparators • Gyrators • Mixers The three amplifiers in the CA3060 are identical push-pull Class A types which can be independently biased to achieve a wide range of characteristics for specific application. The electrical characteristics of each amplifier are a function of the amplifier bias current (IABC). This feature offers the system designer maximum flexibility with regard to output current capability, power consumption, slew rate, input resistance, input bias current, and input offset current. The linear variation of the parameters with respect to bias and the ability to maintain a constant DC level between input and output of each amplifier also makes the CA3060 suitable for a variety of nonlinear applications such as mixers, multipliers, and modulators. In addition, the CA3060 incorporates a unique Zener diode regulator system that permits current regulation below supply voltages normally associated with such systems. • Modulators • Multiplexers • Multipliers • Sample and Hold Functions NOTE: Generic applications of the OTA are described in AN-6668. For improved input operating ranges, refer to CA3080 and CA3280 data sheets (File Nos. 475 and 1174) and application notes AN6668 and AN6818. Pinout Part Number Information • Strobing and Gating Functions CA3060 (PDIP) TOP VIEW PART NUMBER CA3060E REGULATOR OUT 1 REGULATOR IN 2 V+ 3 INV. INPUT NO. 3 4 NON-INV. INPUT NO. 3 5 + BIAS NO. 3 6 AMP 3 7 V- 8 -40 to 85 16 Ld PDIP PKG. NO. E16.3 14 NON-INV. INPUT NO. 1 13 INV. INPUT NO. 1 12 INV. INPUT NO. 2 AMP 2 11 NON-INV. INPUT NO. 2 10 BIAS NO. 2 9 OUTPUT NO. 2 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright PACKAGE 15 BIAS NO. 1 + OUTPUT NO. 3 AMP 1 TEMP. RANGE (oC) 16 OUTPUT NO. 1 BIAS REG. + [ /Title (CA30 60) /Subject (110k Hz, Operational Transc onductance Amplifier Array) /Autho r () /Keywords (Harris Semiconductor, triple, transco nductance amplifier, low power op amp, Features © Harris Corporation 1999 3-1 File Number 537.4 CA3060 Absolute Maximum Ratings Operating Conditions Supply Voltage (Between V+ and V- Terminals) . . . . . . . 36V (±18V) Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VDifferential Input Voltage (Each Amplifier) . . . . . . . . . . . . . . . . . . 5V Input Current (Each Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1mA Amplifier Bias Current (Each Amplifier) . . . . . . . . . . . . . . . . . . . 2mA Bias Regulator Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA Output Short Circuit Duration (Note 1) . . . . . . . . . . . . . . . . Indefinite Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, VSUPPLY = ±15V AMPLIFIER BIAS CURRENT IABC = 1µA PARAMETER IABC = 10µA IABC = 100µA SYMBOL MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage (See Figure 1) VIO - 1 - - 1 - - 1 5 mV Input Offset Current (See Figure 2) IIO - 3 - - 30 - - 250 1000 nA Input Bias Current (See Figures 3, 4) IIB - 33 - - 300 - - 2500 5000 nA IOM - 2.3 - - 26 - 150 240 - µA VOM+ - 13.6 - - 13.6 - 12 13.6 - V Peak Output Current (See Figures 5, 6) Peak Output Voltage (See Figure 7) Positive VOM- - 14.7 - - 14.7 - 12 14.7 - V Amplifier Supply Current (Each Amplifier) (See Figures 8, 9) IA - 8.5 - - 85 - - 850 1200 µA Power Consumption (Each Amplifier) P - 0.26 - - 2.6 - - 26 36 mW ∆VIO/∆V+ - 1.5 - - 2 - - 2 150 µV/V ∆VIO/∆V- - 20 - - 20 - - 30 150 µV/V VABC - 0.54 - - 0.60 - - 0.66 - V Negative Input Offset Voltage Sensitivity (Note 3) Positive Negative Amplifier Bias Voltage (Note 4, See Figure 10) DYNAMIC CHARACTERISTICS At 1kHz, Unless Otherwise Specified Forward Transconductance (Large Signal) (See Figures 11, 12) Common Mode Rejection Ratio Common Mode Input Voltage Range Slew Rate (Test Circuit) (See Figure 17) Open Loop (g21) Bandwidth (See Figure 13) g21 - 1.55 - - 18 - 30 102 - mS CMRR - 110 - - 110 - 70 90 - dB VICR +12 to -12 +13 to -14 - +12 to -12 +13 to -14 - +12 to -12 +13 to -14 - V SR - 0.1 - - 1 - - 8 - V/µs BWOL - 20 - - 45 - - 110 - kHz 3-2 CA3060 Electrical Specifications TA = 25oC, VSUPPLY = ±15V (Continued) AMPLIFIER BIAS CURRENT IABC = 1µA PARAMETER IABC = 10µA IABC = 100µA SYMBOL MIN TYP MAX MIN TYP MAX MIN Input Impedance Components Resistance (See Figure 14) RI - 1600 - - 170 - Capacitance at 1MHz CI - 2.7 - - 2.7 - RO - 200 - - 20 - - CO - 4.5 - - 4.5 - - 6.2 6.7 7.9 V - 200 300 Ω Output Impedance Components Resistance (See Figure 15) Capacitance at 1MHz TYP MAX UNITS 10 20 - kΩ - 2.7 - pF 2 - MΩ 4.5 - pF ZENER BIAS REGULATOR CHARACTERISTICS I2 = 0.1mA Voltage (See Figure 16) VZ Impedance ZZ Temperature Coefficient = 3mV/oC NOTES: 3. Conditions for Input Offset Voltage Sensitivity: a. Bias current derived from the regulator with an appropriate resistor connected from Terminal 1 to the bias terminal on the amplifier under test V+ is reduced to +13V for V+ sensitivity and V- is reduced to -13V for V- sensitivity. VO ffset – VO ffset for +13V and -15V Supplies µV ⁄ V = ------------------------------------------------------------------------------------------------------------------------------ , 1V b. V+ Sensitivity in V- Sensitivity in VO ffset – VO ffset for -13V and +15V Supplies µV ⁄ V = ------------------------------------------------------------------------------------------------------------------------------. 1V 4. Temperature Coefficient; -2.2mV/oC (at VABC = 0.54, IABC = 1µA); -2.1mV/oC (at VABC = 0.060V, IABC = 10µA); -1.9mV/oC (at VABC = 0.66V, IABC = 100µA) Schematic Diagram BIAS REGULATOR AND ONE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER ZENER BIAS REGULATOR D4 2 3 Q4 Q10 1 V+ D2 Q5 Q6 Q7 D5 INVERTING INPUT (NOTE 5) - NON-INVERTING INPUT (NOTE 6) + AMPLIFIER BIAS INPUT (NOTE 7) Q1 Q2 OUTPUT (NOTE 8) Q8 IABC Q3 D3 D1 8 NOTES: 5. Inverting Input of Amplifiers 1, 2 and 3 is on Terminals 13, 12 and 4, respectively. 6. Non-inverting Input of Amplifiers 1, 2 and 3 is Terminals 14, 11 and 5, respectively. 7. Amplifier Bias Current of Amplifiers 1, 2 and 3 is on Terminals 15, 10 and 6, respectively. 8. Output of Amplifiers 1, 2 and 3 is on Terminals 16, 9 and 7, respectively. 3-3 V- CA3060 Typical Performance Curves 1000 MAXIMUM SUPPLY VOLTAGE: VS = ±6 VS = ±15 INPUT OFFSET CURRENT (nA) INPUT OFFSET VOLTAGE (mV) 2.0 1.5 125oC 1.0 25oC -55oC 0.5 100 1 10 100 TA = 25oC SUPPLY VOLTAGE: VS = ±6 VS = ±15 10 0.0 1 TYPICAL 1000 1 10 AMPLIFIER BIAS CURRENT (µA) FIGURE 1. INPUT OFFSET VOLTAGE vs AMPLIFIER BIAS CURRENT 10 INPUT BIAS CURRENT (µA) INPUT BIAS CURRENT (µA) MAXIMUM TYPICAL 1 TA = 25oC SUPPLY VOLTAGE: VS = ±6 VS = ±15 10 100 SUPPLY VOLTAGE: VS = ±6 VS = ±15 IABC = 100µA 1.0 IABC = 10µA 0.1 IABC = 1µA 0.01 -75 0.01 1 1000 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) AMPLIFIER BIAS CURRENT (µA) FIGURE 3. INPUT BIAS CURRENT vs AMPLIFIER BIAS CURRENT FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 1000 1000 TYPICAL IABC = 100µA PEAK OUTPUT CURRENT (µA) PEAK OUTPUT CURRENT (µA) 1000 FIGURE 2. INPUT OFFSET CURRENT vs AMPLIFIER BIAS CURRENT 10 0.1 100 AMPLIFIER BIAS CURRENT (µA) MINIMUM 100 TA = 25oC 10 SUPPLY VOLTAGE: VS = ±6 VS = ±15 10 100 100 IABC = 10µA IABC = 3µA 10 IABC = 1µA 1 -75 1 1 IABC = 30µA 1000 SUPPLY VOLTAGE: VS = ±6 VS = ±15 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) AMPLIFIER BIAS CURRENT (µA) FIGURE 5. PEAK OUTPUT CURRENT vs AMPLIFIER BIAS CURRENT FIGURE 6. PEAK OUTPUT CURRENT vs TEMPERATURE 3-4 CA3060 Typical Performance Curves (Continued) 14 10,000 PEAK OUTPUT VOLTAGE (V) 12 AMPLIFIER SUPPLY CURRENT (µA) VOM+ (TYP) ±15V SUPPLY 13 VOM+ (MIN) ±15V SUPPLY 6 5 4 3 VOM+ (MIN) ±6V SUPPLY -3 VOM+ (TYP) ±6V SUPPLY VOM- (MIN) ±6V SUPPLY -4 -5 -6 -12 VOM- (MIN) ±15V SUPPLY -13 -14 VOM- (TYP) ±6V SUPPLY VOM- (TYP) ±15V SUPPLY TA = 25oC SUPPLY VOLTAGE: VS = ±6 VS = ±15 TYPICAL 1000 MAXIMUM 100 10 -15 1 10 100 1 1000 10 FIGURE 7. PEAK OUTPUT VOLTAGE vs AMPLIFIER BIAS CURRENT 800 AMPLIFIER BIAS VOLTAGE (mV) AMPLIFIER SUPPLY CURRENT (µA) SUPPLY VOLTAGE: VVS = ±6 VS = ±15 IABC = 100µA IABC = 30µA 100 IABC = 10µA IABC = 3µA 10 IABC = 1µA SUPPLY VOLTAGE: V+ = 6V, V- = -6V V+ = 15V, V- = -15V 750 700 650 600 550 500 -50 -25 0 25 50 75 100 1 125 10 TEMPERATURE (oC) 1000 FORWARD TRANSCONDUCTANCE (S) FORWARD TRANSCONDUCTANCE (mS) 1000 FIGURE 10. AMPLIFIER BIAS VOLTAGE vs AMPLIFIER BIAS CURRENT TA = 25oC, f = 1kHz SUPPLY VOLTAGE: VS = ±6 VS = ±15 100 TYPICAL MINIMUM 10 100 AMPLIFIER BIAS CURRENT (µA) FIGURE 9. AMPLIFIER SUPPLY CURRENT (EACH AMPLIFIER) vs TEMPERATURE 1000 1000 FIGURE 8. AMPLIFIER SUPPLY CURRENT (EACH AMPLIFIER) vs AMPLIFIER BIAS CURRENT 1000 1 -75 100 AMPLIFIER BIAS CURRENT (µA) AMPLIFIER BIAS CURRENT (µA) 1 TA = 25oC, f = 1kHz SUPPLY VOLTAGE: VS = ±6 VS = ±15 IABC = 100µA 100 IABC = 30µA IABC = 10µA 10 IABC = 1µA 1 1 10 100 -50 1000 -25 0 25 50 75 100 TEMPERATURE (oC) AMPLIFIER BIAS CURRENT (µA) FIGURE 11. FORWARD TRANSCONDUCTANCE vs AMPLIFIER BIAS CURRENT FIGURE 12. FORWARD TRANSCONDUCTANCE vs TEMPERATURE 3-5 125 CA3060 Typical Performance Curves (Continued) 0 10,000 IABC = 100µA TA = 25oC, f = 1kHz -50 -100 IABC = 10µA IABC = 1µA -150 1.0 -200 -250 0.1 TA = 25oC SUPPLY VOLTAGE: VS = ±6 VS = ±15 0.01 0.001 -300 IABC = 10µA 0.01 IABC = 1µA 0.1 PHASE ANGLE FORWARD TRANS. 1.0 10 SUPPLY VOLTAGE: VS = ±6 VS = ±15 INPUT RESISTANCE (kΩ) 10 PHASE ANGLE (DEGREES) FORWARD TRANSCONDUCTANCE (mS) 100 1000 100 -350 TYPICAL MINIMUM 10 100 1 FREQUENCY (MHz) 10 1000 AMPLIFIER BIAS CURRENT (µA) FIGURE 13. FORWARD TRANSCONDUCTANCE vs FREQUENCY FIGURE 14. INPUT RESISTANCE vs AMPLIFIER BIAS CURRENT 7.0 1000 TA = 25oC BIAS REGULATOR VOLTAGE (V) TA = 25oC, f = 1kHz OUTPUT RESISTANCE (MΩ) 100 SUPPLY VOLTAGE: VS = ±6 VS = ±15 100 10 SUPPLY VOLTAGE: VS = ±6 VS = ±15 TYPICAL 6.75 6.5 TYPICAL 6.25 1 1 10 100 1000 0 200 400 600 800 1000 1200 1400 BIAS REGULATOR CURRENT (µA) AMPLIFIER BIAS CURRENT (µA) FIGURE 15. OUTPUT RESISTANCE vs AMPLIFIER BIAS CURRENT FIGURE 16. BIAS REGULATOR VOLTAGE vs BIAS REGULATOR CURRENT Test Circuit VZ is measured between Terminal 1 and 8 VABC is measured between Terminals 15 and 8 RF V+ INPUT RS 13 OUTPUT RC AMPLIFIER 1 CC V Z – VA BC [ ( V+ ) – ( V- ) – 0.7 ] R Z = ------------------------------------------------, R ABC = ----------------------------I2 I ABC 3 + 16 13 pF 15 14 EXTERNAL LOAD Supply Voltage: For both ±6V and ±15V TYPICAL SLEW RATE TEST CIRCUIT PARAMETERS 10 MΩ IABC SLEW RATE I2 RABC RS RF RB RC CC µA V/µs µA Ω Ω Ω Ω Ω µF 100 8 200 62K 100K 100K 51K 100 0.02 10 1 200 620K 1M 1M 510K 1K 0.005 1 0.1 2 6.2M 10M 10M 5.1M ∞ 0 1 8 2 RB IABC RZ RABC I2 V- FIGURE 17. SLEW RATE TEST CIRCUIT FOR AMPLIFIER 1 OF CA3060 3-6 CA3060 Application Information In addition, the high output impedance makes these amplifiers ideal for applications where current summing is involved. The CA3060 consists of three operational amplifiers similar in form and application to conventional operational amplifiers but sufficiently different from the standard operational amplifier (op amp) to justify some explanation of their characteristics. The amplifiers incorporated in the CA3060 are best described by the term Operational Transconductance Amplifier (OTA). The characteristics of an ideal OTA are similar to those of an ideal op amp except that the OTA has an extremely high output impedance. Because of this inherent characteristics the output signal is best defined in terms of current which is proportional to the difference between the voltages of the two input terminals. Thus, the transfer characteristics is best described in terms of transconductance rather than voltage gain. Other than the difference given above, the characteristics tabulated are similar to those of any typical op amp. The design of a typical operational amplifier circuit (Figure 19) would proceed as follows: Circuit Requirements Closed Loop Voltage Gain = 10 (20dB) Offset Voltage Adjustable to Zero Current Drain as Low as Possible Supply Voltage = ±6V Maximum Input Voltage = ±50mV Input Resistance = 20kΩ Load Resistance = 20kΩ Device: CA3060 +6V 0.1 RS 20kΩ 13 INPUT 14 ROFFSET <4MΩ AMPLIFIER 1 +6V + -6V D5 D6 RABC 560kΩ 0.1 Q10 - Q2 D3 Q4 AMPLIFIER BIAS CURRENT (ABC) D1 V- Calculation D7 1. Required Transconductance g21. Assume that the open loop gain AOL must be at least ten times the closed loop gain. Therefore, the forward transconductance required is given by: g21 = AOL/RL = 100/18kΩ ≅ 5.5mS (RL = 20kΩ in parallel with 200kΩ ≅ 18kΩ) Q14 D8 D2 INVERTING INPUT Q9 Q5 Q13 + OUTPUT Q12 Q1 NONINVERTING INPUT Q6 Q8 2. Selection of Suitable Amplifier Bias Current. The amplifier bias current is selected from the minimum value curve of transconductance (Figure 11) to assure that the amplifier will provide sufficient gain. For the required g21 of 5.5mS an amplifier bias current IABC of 20µA is suitable. D4 COMPLETE OTA CIRCUIT TO +6V FIGURE 19. 20dB AMPLIFIER USING THE CA3060 Q15 Q3 RL 20kΩ 8 -6V Q11 16 15 2.2MΩ 18kΩ V+ Q7 RF 200kΩ 3 The OTA circuitry incorporated in the CA3060 (Figure 18) provides the equipment designer with a wider variety of circuit arrangements than does the standard op amp; because as the curves indicate, the user may select the optimum circuit conditions for a specific application simply by varying the bias conditions of each amplifier. If low power consumption, low bias, and low offset current, or high input impedance are primary design requirements, then low current operating conditions may be selected. On the other hand, if operation into a moderate load impedance is the primary consideration, then higher levels of bias may be used. V- FIGURE 18. COMPLETE SCHEMATIC DIAGRAM SHOWING BIAS REGULATOR AND ONE OF THE THREE OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS Bias Consideration for Op Amp Applications The operational transconductance amplifiers allow the circuit designer to select and control the operating conditions of the circuit merely by the adjustment of the amplifier bias current IABC. This enables the designer to have complete control over transconductance, peak output current and total power consumption independent of supply voltage. 3-7 3. Determination of Output Swing Capability. For a closed loop gain of 10 the output swing is ±0.5V and the peak load current is 25µA. However, the amplifier must also supply the necessary current through the feedback resistor and if RS = 20kΩ, then RF = 200kΩ for ACL = 10. Therefore, the feedback loading = 0.5V/200kΩ = 2.5µA. The total amplifier current output requirements are, therefore, ±27.5µA. Referring to the data given in Figure 5, we see that for an amplifier bias current of 20µA the amplifier output current is ±40µA. This is obviously adequate and it is not necessary to change the amplifier bias current IABC. CA3060 4. Calculation of Bias Resistance. For minimum supply current drain the amplifier bias current IABC should be fed directly from the supplies and not from the bias regulator. The value of the resistor RABC may be directly calculated using Ohm’s law. RELATIVE GAIN (dB) 0 V SUP – VA BC R ABC = ------------------------------------I ABC 12 – 0.63 R ABC = ------------------------–6 20 × 10 RL = 10kΩ CL = 0 -20 -40 -60 RL = 10kΩ CL = 15pF R ABC = 568.5kΩ or ≅ 560kΩ -80 0.01 5. Calculation of Offset Adjustment Circuit. In order to reduce the loading effect of the offset adjustment circuit on the power supply, the offset control should be arranged to provide the necessary offset current. The source resistance of the non-inverting input is made equal to the source resistance of the inverting input, 0.1 10 100 FIGURE 20. EFFECT OF CAPACITIVE LOADING ON FREQUENCY RESPONSE A B C D E F G 1000 20kΩ × 200kΩ ---------------------------------------- ≅ 18kΩ 20kΩ + 200kΩ H PEAK OUTPUT CURRENT (mA) i.e., 1.0 FREQUENCY (MHz) Because the maximum offset voltage is 5mV plus an additional increment due to the offset current (Figure 2) flowing through the source resistance (i.e., 200 x 10-9 x 18 x 103V), the Offset Voltage Range = 5mV + 3.6mV = ±8.6mV. The current necessary to provide this offset is: 8.6mV ------------------ ≅ 0.48µA 18kΩ With a supply voltage of ±6V, this current can be provided by a 10MΩ resistor. However, the stability of such a resistor is often questionable and a more realistic value of 2.2MΩ was used in the final circuit. Capacitive loading also has an effect on slew rate; because the peak output current is established by the amplifier bias current, IABC (Figure 5), the maximum slew rate is limited to the maximum rate at which the capacitance can be charged by the IOM. Therefore, SR = dv/dt = IOM/CL, where CL is the total load capacitance including strays. This relationship is shown graphically in Figure 21. When measuring slew rate for this data sheet, care was taken to keep the total capacitive loading to 13pF. J K 10 L 1 0.01 0.1 1.0 10 100 SLEW RATE (V/µs) A. CL = 10,000pF B. CL = 3,000pF C. CL = 1000pF D. CL = 300pF E. CL = 100pF F. CL = 30pF Capacitance Effects The CA3060 is designed to operate at such low power levels that high impedance circuits must be employed. In designing such circuits, particularly feedback amplifiers, stray circuit capacitance must always be considered because of its adverse effect on frequency response and stability. For example a 10kΩ load with a stray capacitance of 15pF has a time constant of 1MHz. Figure 20 illustrates how a 10kΩ 15pF load modifies the frequency characteristic. I 100 G. CL = 10pF H. CL = 3pF I. CL = 1pF J. CL = 0.3pF K. CL = 0.1pF L. CL = 0.03pF FIGURE 21. EFFECT OF LOAD CAPACITANCE ON SLEW RATE Phase Compensation In many applications phase compensation will not be required for the amplifiers of the CA3060. When needed, compensation may easily be accomplished by a simple RC network at the input of the amplifier as shown in Figure 17. The values given in Figure 17 provide stable operation for the critical unity gain condition, assuming that capacitive loading on the output is 13pF or less. Input phase compensation is recommended in order to maintain the highest possible slew rate. In applications such as integrators, two OTAs may be cascaded to improve current gain. Compensation is best accomplished in this case with a shunt capacitor at the output of the first amplifier. The high gain following compensation assures a high slew rate. 3-8 CA3060 Typical Applications Circuit Description Having determined the operating points of the CA3060 amplifiers, they can now function in the same manner as conventional op amps, and thus, are well suited for most op amp applications, including inverting and non-inverting amplifiers, integrators, differentiators, summing amplifiers etc. Tri-Level Comparator Tri-level comparator circuits are an ideal application for the CA3060 since it contains the requisite three amplifiers. A trilevel comparator has three adjustable limits. If either the upper lower limit is exceeded, the appropriate output is activated until the input signal returns to a selected intermediate limit. Tri-level comparators are particularly suited to many industrial control applications. Figure 23 shows the block diagram of a tri-level comparator using the CA3060. Two of the three amplifiers are used to compare the input signal with the upper limit and lower limit reference voltages. The third amplifier is used to compare the input signal with a selected value of intermediate limit reference voltage. By appropriate selection of resistance ratios this intermediate limit may be set to any voltage between the upper limit and lower limit values. The output of the upper limit and lower limit comparator sets the corresponding upper or lower limit flip-flop. The activated flip-flop retains its state until the third comparator (intermediate limit) in the CA3060 initiates a reset function, thereby indicating that the signal voltage has returned to the intermediate limit selected. The flip-flops employ two CA3086 transistor array ICs, with circuitry to provide separate “SET” and “POSITIVE OUTPUT” terminals. V+ = 6V INPUT SIGNAL (ES) REGULATOR IN CA3060 1 20K V+ = 6V 2 100 CA3086 LOAD 10K 8 15 EU + R2 1K 10 5.1K UPPER LIMIT REFERENCE VOLTAGE 16 11 WHEN UPPER LIMIT IS EXCEEDED - R4 10K 12 - 11 1/3 CA3060 + IABC LOWER LIMIT REFERENCE VOLTAGE 9 10 4 2 3 13 UPPER LIMIT FLIP-FLOP 12 14 RESET WHEN INTERMEDIATE REFERENCE LIMIT IS EXCEEDED SATURATES WHEN LOWER LIMIT IS EXCEEDED V+ = 6V 100 CA3086 LOAD 4.7K EU - EL IABC 2 150K 1 9 INTERMEDIATE LIMIT REFERENCE VOLTAGE R3 10K 5 SET 1/3 CA3060 13 Q1 7 V- = -6V 5.1K 6 IABC 5.1K 14 8 4.7K 5.1K 25K 13K SATURATES WHEN UPPER LIMIT IS EXCEEDED V+ = 6V 3 6 150K 6 8 10K Q2 7 5.1K 4 - 5 1/3 CA3060 + EL 5.1K 5 SET 7 10 WHEN LOWER LIMIT IS EXCEEDED R1 1K 11 9 5.1K 1 4 2 3 LOWER LIMIT FLIP-FLOP 12 14 13 NOTES: 9. Items in dashed boxes are external to the CA3086. All resistance values are in ohms. 10. E > E = Q (ON), Q (OFF) S U 1 2 E L < E U = Q 2 (ON), Q 1 (OFF) FIGURE 22. TRI-LEVEL COMPARATOR CIRCUIT 3-9 EU – EL E S < -------------------- = Q 1 (OFF), Q 2 (OFF) 2 CA3060 Active Filters - Using the CA3060 as a Gyrator V+ CA3060 TRI-LEVEL DETECTOR UPPER LIMIT REFERENCE VOLTAGE V+ SET - + INPUT SIGNAL CA3086 FLIP-FLOP (WHEN UPPER LIMIT IS REACHED) RESET + - INTERMEDIATE LIMIT REFERENCE VOLTAGE LOWER LIMIT REFERENCE VOLTAGE POSITIVE OUTPUT V+ SET + - CA3086 FLIP-FLOP V- POSITIVE OUTPUT (WHEN LOWER LIMIT IS REACHED) The high output impedance of the OTAs makes the CA3060 ideally suited for use as a gyrator in active filter applications. Figure 24 shows two OTAs of the CA3060 connected as a gyrator in an active filter circuit. The OTAs in this circuit can make a 3µF capacitor function as a floating 10kH inductor across Terminals A and B. The measured Q of 13 (at a frequency of 1Hz) of this inductor compares favorably with a calculated Q of 16. The 20kΩ to 2MΩ attenuators in this circuit extend the dynamic range of the OTA by a factor of 100. The 100kΩ potentiometer, across V+ and V-, tunes the inductor by varying the g21 of the OTAs, thereby changing the gyration resistance. Three Channel Multiplexer FIGURE 23. FUNCTIONAL BLOCK DIAGRAM OF A TRI-LEVEL COMPARATOR The circuit diagram of a tri-level comparator appears in Figure 22. Power is provided for the CA3060 via terminal 3 and 8 by ±6V supplies and the built-in regulator provides amplifier bias current (IABC) to the three amplifiers via terminal 1. Lower limit and upper limit reference voltages are selected by appropriate adjustment of potentiometers R1 and R2, respectively. When resistors R3 and R4 are equal in value (as shown), the intermediate limit reference voltage is automatically established at a value midway between the lower limit and upper limit values. Appropriate variation of resistors R3 and R4 permits selection of other values of intermediate limit voltage. Input signal (ES) is applied to the three comparators via terminals 5, 12 and 14. The “SET” output lines trigger the appropriate flip-flop whenever the input signal reaches a limit value. When the input signal returns to an intermediate value, the common flip-flop “RESET” line is energized. The loads in the circuits, shown in Figure 22 are 5V, 25mA lamps. Figure 25 shows a schematic of a three channel multiplexer using a single CA3060 and a 3N153 MOSFET as a buffer and power amplifier. V+ = 15V 0.01µF 3 2kΩ 4 - 5 + 7 2kΩ 8 6 0.02 µF V- = -15V 300kΩ STROBE 3N153 2kΩ 12 - 11 + 9 2kΩ V+ = 6V TERMINAL A V+ = 15V 3 390Ω 3 10 20kΩ 4 2 0.001µF 300kΩ 14 STROBE 16 AMP 1 20kΩ 13 OUTPUT 2kΩ 13 15 3kΩ 16 2kΩ V+ 14 + 560kΩ L = 10kH V- = -15V 100kΩ 2MΩ 20 kΩ 20 kΩ 15 300kΩ 560kΩ STROBE V- 10 3µF +15V STROBE “ON” -15V STROBE “OFF” FIGURE 25. THREE CHANNEL MULTIPLEXER 12 9 AMP 2 11 8 TERMINAL B 2MΩ V- = -6V FIGURE 24. TWO OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS OF THE CA3060 CONNECTED AS A GYRATOR IN AN ACTIVE FILTER CIRCUIT When the CA3060 is connected as a high input impedance voltage follower, and strobe “ON”, each amplifier is activated and the output swings to the level of the input of the amplifier. The cascade arrangement of each CA3060 amplifier with the MOSFET provides an open loop voltage gain in excess of 100dB, thus assuring excellent accuracy in the voltage follower mode with 100% feedback. Operation at ±6V is also possible with several minor changes. First, the resistance in series with the amplifier bias current (IABC) terminal of each amplifier should be decreased to maintain 100µA of strobe “ON” current at this lower supply voltage. Second, the drain resistance for the MOSFET should be 3-10 CA3060 decreased to maintain the same value of source current. The low cost dual gate protected MOSFET, 40841 type, may be used when operating at the low supply voltage. The phase compensation network consists of a single 390Ω resistor and a 1000pF capacitor, located at the interface of the CA3060 output and the MOSFET gate. The bandwidth of the system is 1.5MHz and the slew rate is 0.3V/µs. The system slew rate is directly proportional to the value of the phase compensation capacitor. Thus, with higher gain settings where lower values of phase compensation capacitors are possible, the slew rate is proportionally increased. Non-Linear Applications AM Modulator (Two Quadrant Multiplier) Figure 26 shows Amplifier 3 of the CA3060 used in an AM modulator or two quadrant multiplier circuit. When modulation is applied to the amplifier bias input, Terminal B, and the carrier frequency to the differential input, Terminal A, the waveform, shown in Figure 26 is obtained. Figure 26 is a result of adjusting the input offset control to balance the circuit so that no modulation can occur at the output without a carrier input. The linearity of the modulator is indicated by the solid trace of the superimposed modulating frequency. The maximum depth of modulation is determined by the ratio of the peak input modulating voltage to V-. The two quadrant multiplier characteristic of this modulator is easily seen if modulation and carrier are reversed as shown in Figure 26. The polarity of the output must follow that of the differential input; therefore, the output is positive only during, the positive half cycle of the modulation and negative only in the second half cycle. Note, that both the input and output signals are referenced to ground. The output signal is zero when either the differential input or IABC are zero. Four Quadrant Multiplier and 3 is shown in Figure 27 and a typical circuit is shown in Figure 28. The multiplier consists of a single CA3060 and, as in the two quadrant multiplier, exhibits no level shift between input and output. In Figure 27, Amplifier 1 is connected as an inverting amplifier for the X-input signal. The output current of Amplifier 1 is calculated as follows: IO(1) = [-VX] [g21(1)] EQ. 1 Amplifier 2 is a non-inverting amplifier so that IO(2) = [+VX] [g21(2)] Because the amplifier output impedances are high, the load current is the sum of the two output currents, for an output voltage VO = VXRL [g21(2) - g21(1)] EQ. 3 The transconductance is approximately proportional to the amplifier bias current; therefore, by varying the bias current the g21 is also controlled. Amplifier 2 bias current is proportional to the Y-input signal and is expressed as ( V- ) + V Y I ABC(2) ≈ -----------------------R1 Hence, g21(2) ≈ k [(V-) + VY] Combining Equations 3, 5 and 6 yields: VO ≈ VX x k x RL {[(V-) + VY] - [(V-) - VY]} or VO ≈ 2kRLVXVY +6V 3 CARRIER - 4 MODULATED OUTPUT 10kΩ 7 AMP 3 1kΩ 5 + 100kΩ 8 1kΩ 1MΩ 6 -6V V+ MODULATION V- EQ. 4 EQ. 5 Bias for Amplifier 1 is derived from the output of Amplifier 3 which is connected as a unity gain inverting amplifier. IABC(1), therefore, varies inversely with VY. And by the same reasoning as above EQ. 6 g21(1) ≈ k [(V-) - VY] The CA3060 is also useful as a four quadrant multiplier. A block diagram of such a multiplier, utilizing Amplifiers 1, 2 TERM. A EQ. 2 1MΩ 100kΩ TERM. B 10kΩ FIGURE 26. TWO QUADRANT MULTIPLIER CIRCUIT USING THE CA3060 WITH ASSOCIATED WAVEFORMS 3-11 CA3060 + Figures 29B and 29C, respectively, show the squaring of a triangular wave and a sine wave. Notice that in both cases the output is always positive and returns to zero after each cycle. IO(1) AMP 1 X INPUT IABC (1) VO R1 RL X INPUT + - IO(2) 1MΩ R2 RIN Y INPUT - 16 1MΩ 15 270Ω 14 51kΩ 4 0.02µF 24kΩ 5 560kΩ 7 240kΩ 6 3 Figure 28 shows the actual circuit including all the adjustments associated with differential input and an adjustment for equalizing the gains of Amplifiers 1 and 2. Adjustment of the circuit is quite simple. With both the X and Y voltages at zero, connect Terminal 10 to Terminal 8. This procedure disables Amplifier 2 and permits adjusting the offset voltage of Amplifier 1 to zero by means of the 100kΩ potentiometer. Next, remove the short between Terminal 10 and 8 and connect Terminal 15 to Terminal 8. This step disables Amplifier 1 and permits Amplifier 2 to be zeroed with the other potentiometer. With AC signals on both the X and Y inputs, R3 and R11 are adjusted for symmetrical output signals. Figure 29 shows the output waveform with the multiplier adjusted. The voltage waveform in Figure 29A shows suppressed carrier modulation of 1kHz carrier with a triangular wave. 270Ω 51 kΩ AMP 3 100Ω FIGURE 27. FOUR QUADRANT MULTIPLIER 1MΩ 200kΩ 4 + AMP 3 FIGURE 29A. 270Ω OUTPUT AMP 1 100Ω RF Y INPUT 1MΩ 13 AMP 2 IABC (2) CA3060 V+ 100kΩ 100kΩ V- 1.1MΩ 10 11 12 AMP 2 9 560kΩ 8 270Ω FIGURE 28. TYPICAL FOUR QUADRANT MULTIPLIER CIRCUIT FIGURE 29B. FIGURE 29C. FIGURE 29. VOLTAGE WAVEFORMS OF FOUR QUADRANT MULTIPLIER CIRCUIT 3-12