HSP43168 Data Sheet November 1999 File Number 2808.8 Dual FIR Filter Features The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be configured to provide quadrature filtering, complex filtering, 2-D convolution, 1-D/2-D correlations, and interpolating/decimating filters. • Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication. This allows an 8-tap FIR to be implemented using only 4 multipliers per filter cell. These cells can be configured as either a single 16-tap FIR filter or dual 8-tap FIR filters. Asymmetric filtering is also supported. • Standard Microprocessor Interface Decimation of up to 16 is provided to boost the effective number of filter taps from 2 to 16 times. Further, the Decimation Registers provide the delay necessary for fractional data conversion and 2-D filtering with kernels to 16 x16. • Polyphase Filtering • 10-Bit Data and Coefficients • On-Board Storage for 32 Programmable Coefficient Sets • Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit Data and Coefficients • Programmable Decimation to 16 • Programmable Rounding on Output Applications • Quadrature, Complex Filtering • Image Processing • Adaptive Filtering Ordering Information The flexibility of the Dual is further enhanced by 32 sets of user programmable coefficients. Coefficient selection may be changed asynchronously from clock to clock. The ability to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering. PART NUMBER The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of the device is controlled through a standard microprocessor interface. TEMP. RANGE (oC) PACKAGE PKG. NO. HSP43168VC-33 0 to 70 100 Ld MQFP Q100.14x20 HSP43168VC-40 0 to 70 100 Ld MQFP Q100.14x20 HSP43168VC-45 0 to 70 100 Ld MQFP Q100.14x20 HSP43168JC-33 0 to 70 84 Ld PLCC N84.1.15 HSP43168JC-40 0 to 70 84 Ld PLCC N84.1.15 HSP43168JC-45 0 to 70 84 Ld PLCC N84.1.15 HSP43168JI-40 -40 to 85 84 Ld PLCC N84.1.15 0 to 70 84 Ld CPGA G84.A HSP43168GC-45 Block Diagram 10 CIN0 - 9 A0 - 8 WR CSEL0 - 4 CONTROL/ CONFIGURATION 9 COEFFICIENT BANK A COEFFICIENT BANK B 10 INA0 - 9 INB0 - 9/ OUT0 - 8 FIR CELL A FIR CELL B MUX MUX 10 MUX / ADDER 9 19 OUT9 - 27 OEL OEH 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999 HSP43168 Pinouts 84 LEAD CPGA BOTTOM VIEW GND MUX0 MUX1 A3 A2 VCC A5 A6 CSEL0 GND 9 8 OUT15 OUT14 OUT12 CIN3 D H OUT21 OUT20 CIN2 CIN1 CIN0 E G OUT24 OUT23 OUT25 INA8 INA9 VCC F F OUT27 OUT22 OUT26 INA7 INA5 INA6 G E OEH GND INA3 INA4 H D VCC ACCEN INA0 INA2 J C TXFR FWRD OEL INB3 VCC INB0 INB2 GND INB7 INB8 INA1 K B SHFTEN INB1 INB4 INB5 INB6 INB9 L A 3 2 1 7 6 OUT10 OUT11 5 3 2 1 INB1 INB4 INB5 INB6 INB9 L 6 5 4 OUT16 OUT13 GND INB7 INB8 INA1 K INA0 INA2 J INA3 INA4 H INA7 INA5 INA6 G INA8 INA9 VCC F CIN2 CIN1 CIN0 E GND CIN3 D CIN6 CIN4 C CIN7 CIN5 B VCC INB0 INB2 OUT9 OEL INB3 4 HSP43168 TOP VIEW CLK A5 A6 CSEL0 MUX0 MUX1 A0 A3 A2 VCC RVRS WR GND A1 A4 A7 A8 11 10 9 8 7 6 5 MUX 0 2 MUX 1 3 WR 4 GND 5 A0 6 A1 7 A2 8 A3 11 10 9 A4 84 LEAD PLCC TOP VIEW 1 84 83 82 81 80 79 78 77 76 75 CIN 7 12 74 RVRS CIN 6 13 73 FWD CIN 5 14 72 SHFTEN CIN 4 15 71 TXFR GND 16 70 CIN 3 17 69 ACCEN VCC CIN 2 18 68 CLK CIN 1 19 67 GND CIN 0 20 66 OEH INA 9 21 65 OUT 27 INA 8 22 64 OUT 26 INA 7 23 63 OUT 25 INA 6 24 62 OUT 24 INA 5 25 61 OUT 23 VCC 26 60 OUT 22 INA 4 27 59 OUT 21 INA 3 28 58 OUT 20 INA 2 29 57 OUT 19 INA 1 30 56 OUT 18 INA 0 31 55 OUT 17 INB 9 32 54 VCC 2 GND OUT 16 OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 VCC 7 A5 8 GND OUT9 OUT15 OUT14 OUT12 OUT10 OUT11 9 OUT17 OUT 10 GND J OUT19 A6 L HSP43168 BOTTOM VIEW OUT16 OUT13 C OUT 9 OUT18 CIN4 A7 K CIN6 OEL OUT19 OUT17 VCC A8 J K OUT18 INB 0 OUT21 OUT20 B VCC H CIN5 INB 1 OUT24 OUT23 OUT25 CIN7 CIN9 CSEL 0 G 10 CSEL2 INB 2 OUT27 OUT22 OUT26 11 A0 CLK F VCC L 10 A CSEL 1 GND CIN8 INB 3 OEH 11 PIN 'A1' ID CSEL 2 E 1 CSEL1 CSEL3 CSEL4 INB 4 ACCEN 2 CSEL 3 VCC 3 GND D A8 4 CSEL 4 FWRD A7 5 INB 5 TXFR A4 6 CIN 9 C A1 7 INB 6 B SHFTEN WR 8 CIN 8 RVRS 9 INB 7 A 10 INB 8 11 84 LEAD CPGA TOP VIEW CSEL2 CIN9 CSEL1 CSEL3 CSEL4 4 3 2 CIN8 1 A PIN 'A1' ID HSP43168 (Continued) CIN9 CSEL4 CSEL3 CSEL2 CSEL1 CSEL0 VCC VCC A8 A7 A6 A5 A4 A3 A2 A1 A0 GND GND WR 100 LEAD MQFP TOP VIEW 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CIN8 NC CIN7 NC CIN6 CIN5 CIN4 GND GND CIN3 CIN2 CIN1 CIN0 INA9 INA8 INA7 INA6 INA5 VCC VCC INA4 INA3 INA2 INA1 INA0 NC NC INB9 INB8 INB7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 INB6 INB5 GND GND INB4 INB3 INB2 INB1 INB0 OEL OUT9 OUT10 VCC VCC OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 Pinouts 3 MUX1 MUX0 RVRS NC FWRD SHIFTEN TXFR ACCEN VCC VCC CLK GND GND OEH OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 NC VCC VCC GND GND HSP43168 Pin Description SYMBOL TYPE DESCRIPTION VCC VCC: +5V power supply pin. GND Ground. CIN0-9 I Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB. A0-8 I Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the LSB. WR I Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of WR. CSEL0-4 I Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input is registered and CSEL0 is the LSB. INA0-9 I Input to FIR A. INA0 is the LSB. INB0-9 I/O Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the output bus, and INB9 is the MSB of these bits. OUT9-27 O 19 MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27 is the MSB. SHFTEN I Shift Enable. This active low input enables clocking of data into the part and shifting of data through the Decimation Registers. FWRD I Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALUs through the “a” input. When high, the “a” inputs to the ALUs are zeroed. RVRS I Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through the “b” input. When high, the “b” inputs to the ALUs are zeroed. TXFR I Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with the LIFO being written from the forward decimation path (see Figure 1). MUX0-1 I Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various configurations. CLK I Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables (OEL, OEH) are registered by the rising edge of CLK. OEL I Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low. OEH I Output Enable High. This three-state control enables OUT9-27 when OEH is low. ACCEN I Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the Accumulator. 4 1 TXFR DELAY 4 0 DELAY 3 DELAY 4 DELAY 1-16 †† DELAY 1-16 †† DELAY 1-16 †† DELAY 1-16 †† DELAY 1-16 †† DELAY 1-16 †† D E M M U U X X LIFO B DELAY 1-16 †† M U X 0 † ODD/EVEN SYMMETRY † MODE SELECT LIFO A M U X DECIMATION REGISTERS FIR A FORWARD PATH DELAY 3 DATA FEEDBACK CIRCUITRY † FIR A ODD/EVEN # TAPS FIR A REVERSE PATH SHFTEN 1 † DATA REVERSAL ENABLE M U X DATA FEEDBACK CIRCUITRY † FIR B M U X DECIMATION REGISTERS DELAY 1-16 †† DELAY 1-16 †† DELAY 1-16 †† DELAY 1-16 †† DELAY 1-16 †† DELAY 1-16 †† † ODD/EVEN NUMBER OF TAPS LIFO A ODD/EVEN # TAPS D E M M U U X X LIFO B DELAY 1-16 DELAY 3 5 † DATA REVERSAL ENABLE INA0-9 10 INB0 9 DELAY 3 M U X DELAY 1-16 †† M U X DELAY 3 10 FIR B REVERSE PATH FIR B FORWARD PATH † ODD/EVEN † ODD/EVEN 10 SYMMETRY SYMMETRY INB1-9/ OUT0-8 A B ALU FWRD DELAY 3 RVRS DELAY 3 A B ALU A B ALU A B ALU REG REG A B ALU A B ALU A B ALU A B ALU REG REG REG REG 11 † FIR B INPUT REG SOURCE REG † MODE SELECT HSP43168 11 X 10 COEF BANK COEF BANK 0 5 CSEL0-4 X X COEF BANK 1 X 2 COEF BANK COEF BANK X X COEF BANK 0 3 X COEF BANK 1 X 2 COEF BANK 3 DELAY 4 21 REG REG REG REG REG 0 M U X R E G 0 ADDER 22 REG ACCEN REG REG FIR B ACCUMULATOR FIR A ACCUMULATOR CLK REG OUTPUT HOLDING REGISTER M U X FIR CELL A R E G ADDER REG OUTPUT HOLDING REGISTER FIR CELL B DELAY 5 2 MUX0-1 DELAY 6 10 CIN0-9 9 A0-8 WR CONTROL † MODE SELECT † ODD EVEN SYMMETRY † FIR A ODD/EVEN # TAPS † FIR B ODD/EVEN # TAPS † FIR B INPUT SOURCE † DATA REVERSAL ENABLE † ROUND ENABLE † DECIMATION FACTOR † ROUND ENABLE MUX/ ADDER 28 DELAY 2 9 19 OUT9-27 † Processor control words †† Decimation factor OEL OEH FIGURE 1. DUAL FIR FILTER HSP43168 Functional Description The Dual FIR Filter has a “pipeline” delay of 8 CLK periods, once normal filtering operations begin. Five typical filtering operation examples are provided in the Applications Examples Section as a guide to configuration and control of the Dual FIR Filter. As shown in Figure 1, the HSP43168 consists of two 4-multiplier FIR filter cells which process 10-bit data and coefficients. The FIR cells can operate as two independent 8-tap FIR filters or two 4-tap asymmetric filters at maximum I/O rates. A single filter mode is provided which allows the FIR cells to operate as one 16-tap FIR filter or one 8-tap asymmetric filter. On board coefficient storage for up to 32 sets of 8 coefficients is provided. The coefficient sets are user selectable and are programmed through a microprocessor interface. Programmable decimation to 16 is also provided. By utilizing Decimation Registers together with the coefficient sets, polyphase filters are realizable which allow the user to trade data rate for filter taps. The MUX/Adder can be configured to either add or multiplex the outputs of the filter cells depending upon whether the cells are operating in single or dual filter mode. In addition, a shifter in the MUX/Adder is provided for implementation of filters with 10-bit data and 20-bit coefficients or vice versa. During normal filter operations, the location and duration of the TXFR signal assertions are determined by the filter configuration and operation mode. Once set, these signal parameters must be maintained during normal operation to ensure proper data alignment in the part. Once the part is reset, do not change TXFR unless you load the configuration again. Preparing the Dual FIR for Operation Microprocessor Interface Two configuration steps are required to prepare the Dual FIR Filter for normal operation: 1) loading the Configuration Control Registers, and 2) loading the FIR Filter Coefficients. The Dual FIR has a 20 pin write only microprocessor interface for loading data into the Control Block and Coefficient Banks. The interface consists of a 10-bit data bus (CIN0-9), a 9-bit address bus (A0-8), and a write input (WR) to latch the data into the on-board registers on a rising edge. The configuration control and coefficient data loading is asynchronous to CLK. Configuration Control Registers are loaded by placing the control register address on address lines A0-8, placing the configuration data on the configuration input lines CIN0-9, and asserting the WR line (followed by a release of the assertion). This action creates a rising edge on the WR line, which clocks the address and configuration data into the part. The details of the “Load Configuration” process are outlined in the Microprocessor Interface Section. FIR Coefficients are loaded by placing the address of the Coefficient Data Bank on the address lines A0-8, placing the FIR 10-bit coefficient values on the configuration input lines CIN0-9 and then asserting the WR line (followed by a release of the assertion). This action creates a rising edge on the WR line, which clocks the FIR Coefficient Band address and FIR Coefficient data into the part. The details of the “Load FIR Coefficient” process are outlined in the FIR Filter Cells Section, Coefficient Bank Subsection. Both the Configuration Load and FIR Coefficient Load can be done as a sequence of asynchronous write commands to the Dual FIR Filter. Once these actions are complete, the part is ready for normal filter operation. The CLK, TXFR, FWRD, RVRS, ACCEN, and SHFTEN signals must be asserted in a manner determined by the application. MUX0-1 must meet the setup and hold times with respect to clock for proper filter operation. Details of the MUX1-0 control can be found in the Output MUX/Adder Section. Details of the ACCEN control can be found in the Fir Cell Accumulator Section. Bit locations for the various filter control/configuration signals can be found in the Input/Output Formats Section. 6 NOTE: The fixed or periodic relationship between the TXFR signal and CLK must be maintained for valid filter operation. This relationship can only change when CLK is halted and new configuration control words are loaded into the device. Control Block The Dual FIR is configured by writing to the registers within the Control Block. Figure 2 shows the timing diagram for writing to the Configuration Control Registers. These Control Registers are memory mapped to Address 000H (H = Hexadecimal) and 001H on A0-8. The Filter Coefficient Registers are mapped to 1XXH (X = value described in the “Coefficient Banks” chapter of the ALU Section). RESET WR A8-0 000H 001H C9-0 FIGURE 2. LATCHING C9-0 VALUES INTO ADDRESS A8-0 REGISTERS The format of the Control Registers is shown in Table 1 and Table 2. Writing to any of the Control/Configuration Registers causes a reset which lasts for 6 CLK cycles following the assertion of WR. The reset caused by Writing Registers in the Control Block will not clear the contents of the Coefficient HSP43168 Bank. As shown in Figure 2, either Configuration Control Register can be written to during reset. TABLE 1. CONFIGURATION/CONTROL WORD 0 BIT DEFINITIONS CONTROL ADDRESS 000H BITS 3-0 FUNCTION DESCRIPTION Decimation Factor (N) R = N + 1 0000 = No Decimation. 1111 = Decimation by 16. 4 Mode Select 0 = Single Filter Mode. 1 = Dual Filter Mode. (also 20-Bit Coefficient Filter) 5 Odd/Even Filter 0 = Even Symmetric Coefficients. Coefficient Symmetry 1 = Odd Symmetric Coefficients. 6 FIR A Odd/Even Number of Taps 0 = Odd Number of Taps in Filter. 1 = Even Number of Taps in Filter. 7 FIR B Odd/Even Number of Taps (Defined Same as FIR A Above). 8 FIR B Input Source 0 = Input from INA0-9. 1 = Input from INB0-9. 9 Not Used Set to 0 for Proper Operation. NOTE: Address locations 002H to 011H are reserved, and writing to these locations will have unpredictable effects on part configuration. TABLE 2. CONFIGURATION/CONTROL WORD 1 BIT DEFINITIONS CONTROL ADDRESS 001H BITS FUNCTION DESCRIPTION 0 = Unsigned. 1 = Two's Complement. and B before entering the reverse paths of Filters A and B (see Figure 1). Coefficient symmetry is selected by bit 5. Bits 6 and 7 are programmed to configure the FIR cells for odd or even filter lengths (number of taps). Bit 8 selects the FIR B input source when the FIR cells are configured for independent operation. Bit 9 must be programmed to 0. NOTE: When the filter is programmed for even-taps, the TXFR signal is delayed by only three CLKS (see Figure 1). For odd-taps, the TXFR signal is delayed by four CLKS. The 4 LSBs of the control word loaded at address 001H are used to configure the format of the FIR cell's data and coefficients. Bit 4 is programmed to enable or disable the reversal of data sample order prior to entering the Reverse Path Decimation Registers. Data reversal is required for symmetric filter coefficient sets of both even or odd numbers of filter taps. Asymmetric filters and some decimated symmetric filters require the data reversal to be off. Bits 5-9 are used to support programmable rounding on the output. FIR Filter Cells Each FIR filter cell is based on an array of four 11x10-bit two's complement multipliers. One input of the multipliers comes from the ALU’s which combine data shifting through the Forward and Reverse Decimation Registers. The second multiplier input comes from the user programmable coefficient bank. The multiplier outputs are fed to an accumulator whose result is passed to the output section where it is multiplexed or added with the result from the other FIR cell. 0 FIR A Input Format 1 FIR A Coefficient Format (Defined same as FIR A input). Decimation Registers 2 FIR B Input Format (Defined same as FIR A input). 3 FIR B Coefficient (Defined same as FIR A input). 4 Data Reversal Enable 0 = Enabled. 1 = Disabled. 8-5 Round Position 0000 = 2-10. 1011 = 21. (See Figure 4) The Forward and Reverse Decimation Shift Registers can be configured for decimation factors from 1 to 16 (see Table 1, bits 0-3). NOTE: Setting the decimation factor only affects the Delay Registers between filter taps, not the filter control multiplexers. Example 4 and Example 5 in the Applications Section discuss how to configure the part for actual decimation applications. 9 Round Enable 0 = Enabled. 1 = Disabled. (EQ. 1) The Reverse Shifting Registers with the data reversal logic are used to take advantage of symmetry in linear phase filters by aligning data at the ALUs for pre-addition prior to multiplication by the common coefficient. When the FIR cells are configured in single filter mode, the Decimation Registers in FIR cell A and FIR cell B are cascaded. This extended filter tap delay path allows computation of a filter which is twice the size of that capable using a single cell. The Decimation Registers also provide data storage for polyphase or 2-D filtering applications (See Applications Examples Section). For example, if the 4 LSBs are programmed with a value of 0010, the Forward and Reverse Shifting Decimation Registers are each configured with a delay of 3. Bit 4 is used to select whether the FIR cells operate as two independent filters or one extended length filter. Dual filter mode assumes Filter A and Filter B are separate independent filters. In the single filter mode, the data is routed through the forward paths of Filters A The Data Feedback Circuitry in each FIR cell is responsible for transferring data from the Forward to the Reverse Shifting Decimation Registers. This circuitry feeds blocks of samples into the reverse shifting decimation path in either reversed or non-reversed sample order. The MUX/DEMUX structure at the input to the Feedback Circuitry routes data to the LIFOs or the delay stage depending on the selected NOTE: Address locations 002H to 011H are reserved, and writing to these locations will have unpredictable effects on part configuration. The 4 LSBs of the control word loaded at address 000H are used to select the decimation factor. The Decimation Factor is programmed to one less than the number of delays between filter taps DF = ( CLK delays between taps ) – 1 7 HSP43168 configuration. The MUX on the Feedback Circuitry Output selects which storage element feeds the Reverse Shifting Decimation Registers. In applications requiring reversal of sample order, the FIR cells are configured with data reversal enabled (see Table 2, CW5, bit 4 = 0). In this mode, data is transferred from the forward to the backward Shifting Registers through a pingponged LIFO structure. While one LIFO is being read into the backward shifting path, the other LIFO is written with data samples. The MUX/DEMUX controls which LIFO is being written, and the MUX on the Feedback Circuitry output controls which LIFO is being read. A low on TXFR and SHIFTEN, switches the LIFOs being read and written, which causes the block of data to be read from the structure in reversed in sample order (See Example 4 in the Application Examples Section). The frequency with which TXFR is asserted determines size of the data blocks in which sample order is reversed. For example, if TXFR is asserted once every three CLKs, blocks of 3 data samples with order reversed, would be fed into the Backward Decimation Registers. NOTE: Altering the frequency or phase of TXFR assertion once a filtering operation has begun will invalidate the filtering result. In applications which do not require sample order reversal, the FIR cells must be configured with data reversal disabled (see Table 2, CW5, bit 4 = 1). In addition, TXFR must be asserted to ensure proper data flow. In this configuration, data to the backward shifting decimation path is routed though a delay stage instead of the pingpong LIFOs. The number of registers in the delay stage is based on the programmed decimation factor. NOTE: Data reversal must be disabled and TXFR must be asserted for filtering applications which do not use decimation. The shifting of data through the Forward and Reverse Decimation Registers is enabled by asserting the SHFTEN input. When SHFTEN is high, data shifting is disabled, and the data sample latched into the part on the previous clock is the last input to the filter structure. The data sample at the filter input when SHFTEN is asserted, will be the next data sample into the forward decimation path. When operating the FIR cells as two independent filters, FIR A receives input data via INA0-9 and FIR B receives data from either INA0-9 or INB0-9 depending on the application (see Table 1). When the FIR cells are configured as a single extended length filter, the forward and reverse decimation paths of the two FIR cells are cascaded. In this mode, data is transferred from the forward decimation path to the reverse decimation path by the Data Feedback Circuitry in FIR B. Thus, the manner in which data is read into the reverse decimation path is determined by FIR B's configuration. When the decimation paths are cascaded, data is routed through the fourth delay stage in FIR A's forward path to FIR B. 8 The configuration of the FIR cells as even or odd length filters determines the point in the forward decimation path from which data is multiplexed to the Data Feedback Circuitry. For example, if the FIR cell is configured as an odd length filter, data prior to the last register in the third forward decimation stage is routed to the Feedback Circuitry. If the FIR cell is configured as an even length filter, data output from the third forward decimation stage is multiplexed to the Feedback Circuitry. This is required to ensure proper data alignment with symmetric filter coefficients (See Application Examples). ALUs Data shifting through the forward and reverse decimation paths feed the “a” and “b” inputs of the ALUs respectively. The ALUs perform an “b+a” operation if the FIR cell is configured for even symmetric coefficients or an “b-a” operation if configured for odd symmetric coefficients. Control Word 0, Bit 5 is used to set the ALU operation. For applications in which a pre-add or subtract is not required, the “a” or “b” input can be zeroed by disabling FWRD or RVRS respectively. This has the effect of producing an ALU output which is either “a”, “-a”, or “b” depending on the filter symmetry chosen. For example, if the FIR cell is configured for an even symmetric filter with FWRD low and RVRS high, the data shifting through the Forward Decimation Registers would appear on the ALU output. Table 3 details the ALU configurations, where “a” is the ALU data input from the front decimation delay registers and “b” is the ALU data from the back decimation delay registers. TABLE 3. ALU CONFIGURATIONS ALU OUT SYMMETRY FWD RVS a+b 0 (Even) 0 0 Even Number of Taps, Even Symmetry (Example 1) +b 0 (Even) 0 1 Even Symmetry DESCRIPTION +a 0 (Even) 1 0 Even Symmetry - 0 (Even) 1 1 Even Symmetry b-a 1 (Odd) 0 0 Even Number of Taps, Odd Symmetry (Example 2) +b 1 (Odd) 0 1 Odd Symmetry -a 1 (Odd) 1 0 Odd Symmetry - 1 (Odd) 1 1 Odd Symmetry Coefficient Bank The output of the ALU is multiplied by a coefficient from one of 32 user programmable coefficient sets. Each set consists of 8 coefficients (4 coefficients for FIR A and 4 for FIR B). CSEL0-4 is used to select a coefficient set to be used. Coefficient sets may be switched every clock to support polyphase filtering operations. The coefficients are loaded into On-Board Registers using the microprocessor interface, CIN0-9, A0-8, and WR. Each multiplier within the FIR Cells is driven by a coefficient bank HSP43168 with one of 32 coefficients. These coefficients are addressed as shown in Table 4. The inputs A0-1 specify the Coefficient Bank for one of the four multipliers in each FIR Cell; A2 specifies FIR Cell A or B; Bits A7-3 specify one of 32 sets in which the coefficient is to be stored. For example, an address of 10dH would access the coefficient for the second multiplier in FIR B in the second coefficient set. TABLE 4. FIR COEFFICIENT WRITE ADDRESSES FIR COEFF. CSEL (4-0) COEFF. SET CELL A/B MULTIP LIER A8 A7-3 A2 A1-0 FIR BANK 1 xxxx x 0 00 A 0 1 xxxx x 0 01 A 1 1 xxxx x 0 10 A 2 1 xxxx x 0 11 A 3 1 xxxx x 1 00 B 0 1 xxxx x 1 01 B 1 1 xxxx x 1 10 B 2 1 xxxx x 1 11 B 3 DESTINATION Input/Output Formats The Dual FIR supports mixed mode arithmetic with both unsigned and two's complement data and coefficients. The input and output formats for both data types are shown below. If the Dual FIR is configured as an even symmetric filter with unsigned data and coefficients, the output will be unsigned. Otherwise, the output will be two's complement. The MUX/Adder can be configured to implement programmable rounding at bit locations 2-10 through 21. The round is implemented by adding a 1 to the specified location (see Table 2). Figure 4 illustrates the rounding operation. For example, to configure the part such that the output is rounded to the 10 MSBs, OUT18 - 27, the round position would be chosen to be 2-1. The negative sign on the MSB indicates 2’s complement format. INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL TWO’S COMPLEMENT 9 8 7 6 5 4 3 2 1 0 -20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 FIR Cell Accumulator The registered outputs from the multipliers in each FIR cell feed an accumulator. The ACCEN input controls each accumulator's running sum and the latching of data from the accumulator into the Output Holding Registers. When ACCEN is low, feedback from the accumulator adder is zeroed which disables accumulation. Also, output from the accumulator is latched into the Output Holding Registers. When ACCEN is asserted, accumulation is enabled and the contents of the Output Holding Registers remain unchanged. OUTPUT DATA FORMAT OUT9-27 FRACTIONAL TWO'S COMPLEMENT 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 -29 28 27 26 25 24 23 22 21 20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 OUTPUT DATA FORMAT OUT0-8 FRACTIONAL TWO'S COMPLEMENT 8 7 6 5 4 3 2 1 0 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 Output MUX/Adder The contents of each FIR Cell's Output Holding Register is summed or multiplexed in the Mux/Adder. The operation of the Mux/Adder is controlled by the MUX1-0 inputs as shown in Table 5. Applications requiring 10-bit data and 20bit coefficients or 20-bit data and 10-bit coefficients are made possible by configuring the MUX/Adder to scale FIR B's output by 2-10 prior to summing with FIR A. When the Dual FIR is configured as two independent filters, the MUX1-0 inputs would be used to multiplex the filter outputs of each cell. For applications in which FIR A and B are configured as a single filter, the MUX/Adder is configured to sum the output of each FIR cell. NOTE: While a 20-bit coefficient filter is a single filter, the mode select is set to 1 and MUX1-0 is set to 00. INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL UNSIGNED 9 8 7 6 5 4 3 2 1 0 20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 OUTPUT DATA FORMAT OUT9-27 FRACTIONAL UNSIGNED 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 29 28 27 26 25 24 23 22 21 20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 OUTPUT DATA FORMAT OUT0-8 FRACTIONAL UNSIGNED 8 7 6 5 4 3 2 1 0 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 TABLE 5. MUX1-0 BIT DEFINITIONS MUX1-0 DECODING MUX1-0 OUT0-27 00 FIRA + FIRB (FIR B Scaled by 2-10) 01 FIRA + FIRB 10 FIRA 11 FIRB 9 FIGURE 3. INPUT/OUTPUT FORMAT DEFINITIONS HSP43168 27 26 25 24 23 22 21 20 IOUT 19 18 9-27 17 16 15 14 13 12 11 10 9 8 7 6 IOUT 5 4 0-8 3 2 1 0 Two programmable Configuration Control Registers define a unique FIR filter configuration. Register 000H has all filter configuration unique parameters, while Register 001H, bit 4, is filter configuration unique. Table 7 details the configuration control register values, the number of filter coefficient banks required and the MUX1-0 control values for each filter example. 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 8 9 10 11 12 13 14 15 16 17 18 19 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 TABLE 7. CONFIGURATION CONTROL REGISTER VALUES FILTER TYPE REG 000 HEX REG # OF FILTER 001 COEFFICIENT HEX BANKS 1d0 010 Even Tap Even Symmetric “ROUND POSITION” VALUE NUMBER OF OUTPUT BITS 10 Odd Tap Even Symmetric 110 010 1 10 Asymmetric 110 010 2 10 Even Tap Decimate by N+1 1dN 000 N+1 10 Odd Tap Decimate by N+1 11N 000 N+1 10 15N or 19N 000 N+1 10 and 11 Dual: Even and Odd Tap Decimate by N+1 LOCATION OF ADDITION OF 1 1 MUX 1-0 Bit 4 OUTPUT BITS FIGURE 4. ROUND POSITION BIT DEFINITION Application Examples In this section a number of examples are presented which detail even, odd, symmetric, asymmetric, decimating and dual FIR filter configurations. These examples are intended to illustrate the different operational features of the HSP43168 and should be used as a guide in developing an application specific filter configuration. Use Table 6 to select and find the example that best matches your application. Example 1. Even-Tap Even Symmetric Filter Example The HSP43168 may be configured as two independent 8-tap symmetric filters as shown by the Block Diagram in Figure 5. Each of the FIR cells takes advantage of symmetric filter coefficients by pre-adding data samples common to a given coefficient. As a result, each FIR cell can implement an 8-tap symmetric filter using only four multipliers. Similarly, when the HSP43168 is configured in single filter mode a 16-tap symmetric filter is possible by using the multipliers in both cells. TABLE 6. FILTER EXAMPLE SELECTION GUIDE FILTER TYPE HSP43168 EXAMPLE NUMBER Even Tap Even Symmetric 8-TAP EVEN SYMMETRIC 1 INA0-9 Odd Tap Even Symmetric 2 A Asymmetric 3 Even Tap Decimating 4 Odd Tap Decimating 5 Dual Decimating 6 Examples 1-5 are explained using a single four tap FIR cell, but the same concept applies to FIR filters which use both FIR cells (A and B) in a single filter configuration. Example 6 details a dual filter mode where FIR cell A and B implement different digital filters. All examples are functionally verified configurations. Each example details a complete design solution, including a block diagram, a data/coefficient alignment illustration, a data flow diagram and a control signal timing diagram. 10 FIR A A 8-TAP EVEN SYMMETRIC B B INB0-9 M U X OUT9-27 FIR B FIGURE 5. USING HSP43168 AS TWO INDEPENDENT FILTERS The operation of the FIR cell is better understood by comparing the data and coefficient alignment for a given filter output, Figure 6, with the data flow through the FIR cell, as shown in Figure 7. The Block Diagrams in Figure 7 are a simplification of the FIR cell shown in Figure 1. For simplicity, the ALUs and FIR Cell Accumulators were replaced by adders, and the Pipeline Delay Registers were omitted. In this example, we will only show the data flow through one of the two FIR cells. In Figure 7, the order of the data samples within the filter cell is shown by the numbers in the forward and backward shifting decimation paths. The output of the filter cell is HSP43168 given by the equation at the bottom of each block diagram. Figure 7A shows the data sample alignment at the preadders for the data/coefficient alignment shown in Figure 6. C3 8 TAPS C3 C2 1 2 6 5 4 3 C2 C1 h(n) 7 0 C1 C0 + + + + C0 C0 C1 C2 x(n) C3 + X9 X8 X7 X6 X5 X4 X3 X2 X1 (X7+X0)C0+(X6+X1)C1+(X5+X2)C2+(X4+X3)C3 X0 FIGURE 6. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP EVEN SYMMETRIC FILTER The dual filter application is configured by writing 1d0H to address 000H via the microprocessor interface, CIN0-9, A0-8, and WR. Since this application does not use decimation, the 4th bit of the Control Register at Address 001H must be set to disable data reversal (see Table 2). Failure to disable data reversal will produce erroneous results. FIGURE 7A. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED INTO THE FEED FORWARD STAGE 8 To operate the HSP43168 in this mode, TXFR is tied low to ensure proper data flow; both FWRD and RVRS are tied low to enable data samples from the forward and reverse data paths to the ALUs for pre-adding; ACCEN is tied low to prevent accumulation over multiple CLKs; SHFTEN is tied low to allow shifting of data through the Decimation Registers; MUX0-1 is programmed to multiplex the output the of either FIR A or FIR B; CSEL0-4 is programmable to access the stored coefficient set, in this example CSEL = 00000. 2 3 7 6 5 + C0 Using this architecture, only the unique coefficients need to be stored in the Coefficient Bank. For example, the above filter would be stored in the first coefficient set for FIR A by writing C0, C1, C2, and C3 to Address 100H, 101H, 102H, and 103H respectively. To write the same filter to the first coefficient set for FIR B, the address sequence would change to 104H, 105H, 106H, and 107H. 1 + C1 + C2 4 + C3 + (X8+X1)C0+(X7+X2)C1+(X6+X3)C2+(X5+X4)C3 FIGURE 7B. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE FEED FORWARD STAGE 9 2 3 4 8 7 6 + C0 + C1 + C2 5 + C3 + (X9+X2)C0+(X8+X3)C1+(X7+X4)C2+(X6+X5)C3 FIGURE 7C. DATA FLOW AS DATA SAMPLE 9 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 7. DATA FLOW DIAGRAMS FOR 8-TAP SYMMETRIC FILTER 11 HSP43168 Example 2. Odd-Tap Even Symmetric Filter Example The HSP43168 may be configured as two independent 7-tap symmetric filters with a Functional Block Diagram shown in Figure 8. Again, this example shows data flow through one of the two FIR cells. As in the 8-tap filter example, the HSP43168 implements the filtering operation by summing data samples sharing a common coefficient prior to multiplication by that coefficient. However, for odd length filters the pre-addition requires that the center coefficient be scaled by 1/2. 6 0 1 2 5 4 3 + C0 + C1 + C2 3 + C3/2 + (X6+X0)C0+(X5+X1)C1+(X4+X2)C2+(X3+X3)C3/2 HSP43168 FIGURE 10A. DATA FLOW AS DATA SAMPLE 6 IS CLOCKED INTO THE FEED FORWARD STAGE 7-TAP EVEN SYMMETRIC FIR A INA0-9 A A 7-TAP EVEN SYMMETRIC B B INB0-9 M U X OUT9-27 1 2 4 3 FIR B 6 7 FIGURE 8. USING HSP43168 AS TWO INDEPENDENT FILTERS The operation of the FIR cell for odd length filters is better understood by comparing the data/coefficient alignment in Figure 9 with the Data Flow Diagrams in Figure 10. The Block Diagrams in Figure 10 are a simplification of the FIR cell shown in Figure 1. C2 C1 h(n) C0 C1 C0 C0 + C1 4 + C2 + C3/2 + (X7+X1)C0+(X6+X2)C1+(X5+X3)C2+(X4+X4)C3/2 7-TAPS C3 C2 + 5 FIGURE 10B. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED INTO THE FEED FORWARD STAGE 2 3 4 7 6 5 5 x(n) 8 X9 X8 X7 X6 X5 X4 X3 X2 X1 FIGURE 9. DATA/COEFFICIENT ALIGNMENT FOR 7-TAP SYMMETRIC FILTER For odd length filters, proper data/coefficient alignment is ensured by routing data entering the last register in the third forward decimation stage to the Backward Shifting Registers. In this configuration, the center coefficient must be scaled by 1/2 to compensate for the summation of the same data sample from both the Forward and Backward Shifting Registers. 12 + X0 C0 + C1 + C2 + C3/2 + (X8+X2)C0+(X7+X3)C1+(X6+X4)C2+(X5+X5)C3/2 FIGURE 10C. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 10. DATA FLOW DIAGRAMS FOR 7-TAP SYMMETRIC FILTER HSP43168 In the Data Flow Diagrams of Figure 10, the order of the data samples input in to the filter cell is shown by the numbers in the forward and backward shifting decimation paths. The output of the filter cell is given by the equation at the bottom of the block. The Diagram in Figure 10A shows data sample alignment at the pre-adders for the Data/Coefficient Alignment shown in Figure 9. This dual filter application is configured by writing 110H to Address 000H via the microprocessor interface, CIN0-9, A0-8, and WR. Also, data reversal must be disabled by setting bit 4 of the Control Register at Address 0001H. As in the 8-tap example, only the unique coefficients need to be stored in the Coefficient Bank. These coefficients are stored in the first coefficient set for FIR A by writing C0, C1, C2, and C3 to Address 100H, 101H, 102H, and 103H respectively. To write the same filter to the first coefficient set for FIR B, the address sequence would change to 104H, 105H, 106H, and 107H. The control signals TXFR, FWRD, RVRS, ACCEN, SHFTEN, and CSEL0-4 are controlled as described in Example 1. HSP43168 8-TAP ASYMMETRIC FIR A INA0-9 A M U X A 8-TAP ASYMMETRIC B B INB0-9 FIR B FIGURE 11. USING HSP43168 AS TWO INDEPENDENT FILTERS The operation of this configuration is better understood by comparing the Data/Coefficient Alignment in Figure 12 with the Data Flow Diagrams in Figure 13. The ALUs have been omitted from the FIR cell diagrams because data is fed to the multipliers directly from the forward and reverse decimation paths. The data samples within the FIR cell are shown by the numbers in the decimation paths. C7 C6 C5 C4 C2 Example 3. Asymmetric Filter Example For this example, the FIR cells are configured as two 8-tap asymmetric filters which are clocked at twice the input data rate. New data is shifted into the forward and backward decimation paths every other CLK by the assertion of SHFTEN. The filter output is computed by passing data from each decimation path to the multipliers on alternating clocks. Two sets of coefficients are required, one for data on the forward decimation path, and one for data on the reverse path. The filter output is generated by accumulating the multiplier outputs for two CLKs. 13 8-TAPS C3 h(n) The FIR cells within the HSP43168 can each calculate 4 asymmetric taps on each clock. Thus, a single FIR cell can implement an 8-tap asymmetric filter if the HSP43168 is clocked at twice the input data rate. Similarly, if the Dual is configured as a single filter, a 16-tap asymmetric filter is realizable. Only one of the two FIR cells are used in this example for the Block Diagram shown in Figure 11. OUT9-27 C1 C0 x(n) X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 FIGURE 12. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP ASYMMETRIC FILTER HSP43168 0 1 2 6 5 4 C1 C2 C3 7 C0 0 1 2 6 5 4 C6 C5 C4 C7 ACCUMULATOR ACCUMULATOR (X0)C0+(X1)C1+(X2)C2+(X3)C3 +(X7)C7+(X6)C6+(X5)C5+(X4)C4 (X0)C0+(X1)C1+(X2)C2+(X3)C3 FIGURE 13A. DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS 1 2 3 FIGURE 13B. SHIFTING OF DATA SAMPLE 7 INTO FIR CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS 7 6 5 C1 C2 C3 1 2 3 7 6 5 C6 C5 C4 4 4 8 C7 C0 3 3 ACCUMULATOR ACCUMULATOR (X1)C0+(X2)C1+(X3)C2+(X4)C3 FIGURE 13C. DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS (X1)C0+(X2)C1+(X3)C2+(X4)C3 +(X8)C7+(X7)C6+(X6)C5+(X5)C4 FIGURE 13D. SHIFTING OF DATA SAMPLE 8 INTO FIR CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS FIGURE 13. DATA FLOW DIAGRAMS FOR 8-TAP ASYMMETRIC FILTER For this application, each filter cell is configured as an odd length filter by writing 110H to the Control Register at Address 000H. Even though an even tap filter is being implemented, the filter cells must be configured as odd length to ensure proper data flow. In addition, the filters must be set to even symmetry. Also, the 4th bit at Control Address 001H must be set to disable data reversal, and TXFR must be tied low. Since an 8-tap asymmetric filter is being implemented, two sets of coefficients must be stored. 14 These eight coefficients could be loaded into the first two coefficient sets for FIR A by writing C0, C1, C2, C3, C7, C6, C5, and C4 to address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, and 10bH respectively. The sum of products required for this 8-tap filter require dynamic control over FWRD, RVRS, ACCEN, and CSEL0-4. The relative timing of these signals is shown in Figure 14. HSP43168 0 1 2 3 13 14 15 The alignment of data relative to the 24 filter coefficients for a particular output is depicted graphically in Figure 16. As in previous examples, the HSP43168 implements the filtering operation by summing data samples prior to multiplication by the common coefficient. In this example an output is required every third CLK which allows 3 CLKs for computation. On each CLK, one of three sets of coefficients are used to calculate 8 of the filter taps. The Block Diagrams in Figure 17 show the data flow and accumulator output for the data/coefficient alignment in Figure 16. 16 CLK † X0 INA0-9 CSEL0-4 1 X1 0 X6 1 0 X7 0 1 X8 0 1 0 ACCEN FWRD Proper data and coefficient alignment is achieved by asserting TXFR once every three CLKs to switch the LIFOs which are being read and written. This has the effect of feeding blocks of three samples into the backward shifting decimation path which are reversed in sample order. In addition, ACCEN is deasserted once every three clocks to allow accumulation over three CLKs. The three sets of coefficients required in the calculation of a 24-tap symmetric filter are cycled through using CSEL0-4. The timing relationship between the CSEL0-4, ACCEN, and TXFR are shown in Figure 18. RVRS SHFTEN (TIED LOW) TXFR †Note that CLK is 2X data rate. FIGURE 14. CONTROL TIMING FOR 8-TAP ASYMMETRIC FILTER Example 4. Even-Tap Decimating Filter Example The HSP43168 supports filtering applications requiring decimation to 16. In these applications the output data rate is reduced by a factor of N. As a result, N clock cycles can be used for the computation of the filter output. For example, each FIR cell can calculate 8 symmetric or 4 asymmetric taps in one clock. If the application requires decimation by two, the filter output can be calculated over two clocks thus, boosting the number of taps per FIR cell to 16 symmetric or 8 asymmetric. For this example, each FIR cell is configured as an independent 24-tap decimate x3 filter. Again, the data flow diagrams show only one of the FIR cells shown in Figure 15. HSP43168 To operate in this mode the Dual is configured by writing 1d2 to Address 000H via the microprocessor interface, CIN0-9, A0-8, and WR. Data reversal must be enabled see (Table 2). The 12 unique coefficients for this example are stored as three sets of coefficients for either FIR cell. For FIR A, the coefficients are loaded into the Coefficient Bank by writing C2, C5, C8, C11, C1, C4, C7, C10, C0, C3, C6, and C9 to Address [100H, 101H, 102H, 103H], CSEL = 0; [108H, 109H, 10aH, 10bH], CSEL = 1; [110H, 111H, 112H, and 113H], CSEL = 2, respectively. h(n) EVEN-TAP DECIMATING INA0-9 A C0 C1 FIR A A EVEN-TAP DECIMATING B B INB0-9 M U X OUT9-27 C2 C3 C4 C5 C6 C7 C8 C9 C11C11 C10 C10 24-TAPS C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 x(n) FIR B 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 FIGURE 15. EVEN-TAP DECIMATING FILTER, 24-TAP DEC = 3 15 8 7 6 5 4 3 2 FIGURE 16. DATA/COEFFICIENT ALIGNMENT FOR 24-TAP DECIMATE BY 3 FIR FILTER 1 0 HSP43168 2 1 0 5 4 3 8 7 6 20 19 18 4 3 8 7 6 11 21 20 19 18 17 16 15 14 13 14 13 12 17 16 15 + + + + C5 + + + + C1 C2 10 9 12 22 21 1 0 5 11 10 9 C8 C11 C4 C7 C10 CSEL = 1 CSEL = 0 ACCUMULATOR ACCUMULATOR (X1+X22)C1+(X4X19)C4+(X7+X16)C7+(X10+X13)C10 +(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 (X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 FIGURE 17A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED FORWARD STAGE 0 5 4 3 8 7 6 11 10 FIGURE 17B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS CLOCKED INTO THE FEED FORWARD STAGE 9 12 13 5 4 3 23 22 21 20 19 18 17 + C0 + + C3 8 7 6 11 10 9 16 15 14 14 13 12 + C6 C9 24 + CSEL = 2 ACCEN ASSERTED AND ACTIVE ACCUMULATOR 23 22 21 C2 20 19 18 + C5 17 16 15 + C8 + C11 CSEL = 0 TXFR ASSERTED AND ACTIVE ACCUMULATOR (X0+X23)C0+(X3+X20)C3+(X6+X17)C6+(X9+X14)C9 +(X1+X22)C1+(X4+X19)C4+(X7+X16)C7+(X10+X13)C10 +(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 (X5+X24)C0+(X8+X21)C5+(X11+X18)C8+(X14+X15)C11 FIGURE 17C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 17D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 17. DATA FLOW DIAGRAMS FOR 24-TAP DECIMATED BY 3 FIR FILTER 0 1 2 4 3 21 5 22 23 CLK INA0-9 0 1 2 3 4 CSEL0-4 0 1 2 0 1 5 2 21 22 23 0 1 2 Example 5. Odd-Tap Decimating Symmetric Filter This example highlights the use of the HSP43168 as two independent, 23-tap, symmetric, decimate by 3 filters. In this example, the operational differences in the control signals and data reversal structure may be compared to the previously discussed even-tap decimating filter. Figure 19 shows two FIR cells. The data flow in this example uses only one of the FIR cells. ACCEN FWRD † HSP43168 ODD-TAP DECIMATING RVRS † INA0-9 SHIFTEN † A FIR A A ODD-TAP DECIMATING TXFR B B INB0-9 †Tied low. FIGURE 18. CONTROL SIGNAL TIMING FOR 24-TAP DECIMATE X3 FILTER 16 M U X OUT9-27 FIR B FIGURE 19. USING HSP43168 AS TWO INDEPENDENT FILTERS HSP43168 As in the 24-tap example, an output is required every third CLK which allows 3 CLKs for computation. On each CLK, one of three sets of coefficients are used to calculate the filter taps. Since this is an odd length filter, the center coefficient must be scaled by 1/2 to compensate for the summation of the same data sample from the forward and backward shifting decimation paths. The Block Diagrams in Figure 20 show the data flow, and the accumulator output for the data coefficient alignment is shown in Figure 21. Proper data and coefficient alignment is achieved by asserting TXFR once every three CLKs to switch the LIFOs which are being read and written. In the odd-tap mode, TXFR is internally delayed by one clock cycle with respect to ACCEN so that the convolutional sum will be computed correctly. For odd length filters, data prior to the last register in the forward decimation path is routed to the feedback circuitry. As a result, TXFR should be asserted one cycle prior to the input data samples which align with the center tap. The timing relationship between the CSEL0-5, ACCEN, and TXFR are shown in Figure 22. 2 1 6 3 2 1 6 5 4 9 8 7 20 19 18 17 16 15 14 13 12 13 21 20 19 22 21 + + + + C5 + 15 14 13 + + C4 C7 C10 CSEL = 1 CSEL = 0 C11/2 C8 18 17 16 + C1 C2 11 10 8 7 12 5 4 9 12 11 10 ACCUMULATOR ACCUMULATOR (X2+X22)C1+(X5+X19)C4+(X8+X16)C7+(X11+X13)C10 +(X3+X21)C2+(X6+X18)C5+(X9+X15)C8+(X12+X12)C11/2 (X3+X21)C2+(X6+X18)C5+(X9+X15)C8+(X12+X12)C11/2 FIGURE 20A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED FORWARD STAGE TXFR TAKES AFFECT ON THIS CLOCK CYCLE 1 6 5 7 12 11 4 9 8 FIGURE 20B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS CLOCKED INTO THE FEED FORWARD STAGE 10 6 5 4 9 8 7 12 11 10 23 22 21 20 19 18 17 16 15 15 14 13 13 14 23 22 21 20 + C0 19 18 17 + C3 16 15 14 + C6 + C9 ACCUMULATOR 24 + CSEL = 2 ACCEN ASSERTED AND ACTIVE C2 + C5 + C8 + C11/2 CSEL = 0 ACCUMULATOR TXFR ASSERTED (X1+X23)C0+(X4+X20)C3+(X7+X17)C6+(X14+X10)C9 +(X2+X22)C1+(X5+X19)C4+(X8+X16)C7+(X11+X13)C10 +(X3+X21)C2+(X6+X18)C5+(X9+X15)C8+(X12+X12)C11/2 FIGURE 20C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED FORWARD STAGE (X6+X24)C2+(X9+X21)C5+(X12+X18)C8+(X15+X15)C11/2 FIGURE 20D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS CLOCKED INTO THE FEED FORWARD STAGE TXFR TAKES AFFECT ON THIS CLOCK CYCLE FIGURE 20. DATA FLOW DIAGRAMS FOR 23-TAP DECIMATE BY 3 SYMMETRIC FILTER 17 HSP43168 h(n) C0 C1 C2 C3 C6 C4 C5 C7 C11 C10 C10C9 C9 C8 C8 Example 6. Dual Decimation Example 23-TAPS C7 C6 C5 C4 C3 C2 C1 C0 x(n) The purpose of this example is to give an overview of one of the more complex applications of the HSP43168. The input is two data streams (A) and (B) samples. Figure 23 shows the upper level block diagram of the system being implemented. The decimation rate was set to N. N-1 is loaded into the decimation factor in Control Word 000H. FS 2FS /(N+1) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIGURE 21. DATA/COEFFICIENT ALIGNMENT FOR 23-TAP DECIMATE BY 3 SYMMETRIC FILTER B3, B2, B1, B0 INB0-9 A3, A2, A1, A0 HSP43168 INA0-9 DECIMATE BY N 0 1 2 4 3 20 5 21 22 CLK INA0-9 0 1 2 3 CSEL0-4 0 1 2 0 4 1 5 2 21 22 23 0 1 2 ACCEN FWRD † RVRS † SHIFTEN † TXFR †Tied low. FIGURE 22. CONTROL SIGNAL TIMING FOR 23-TAP SYMMETRIC FILTER To operate in this mode, the Dual is configured by writing 112H to Address 000H via the microprocessor interface, CIN0-9, A0-8, and WR. Data reversal must be enabled (see Table 2). The 12 unique coefficients for this example are stored as three sets of coefficients for either FIR cell. For FIR A, the coefficients are loaded into the Coefficient Bank by writing [C2, C5, C8, (C11)/ 2], CSEL = 0; [C1, C4, C7, C10], CSEL = 1; [C0, C3, C6, and C9], CSEL = 2; to address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H, 111H, 112H, and 113H, respectively. 18 OUT9-27 BOUT1 AOUT1 BOUT0 AOUT0 FIGURE 23. MULTIPLEXED DECIMATION BLOCK DIAGRAM To demonstrate the muxed decimation, lets suppose that the application requires filter A to be configured as an even-decimate-by-3 filter and filter B to be configured as a odd-decimate-by-3 filter. The output data is made of the two decimated data streams multiplexed together and has a data rate equal to 2 times the input sampling rate divided by the decimation factor. Figure 24 shows the data/coefficient alignment for FIR A and FIR B. To operate in this mode, Control Word 000H must be written with a 0x152. Data reversal must be enabled by setting bit 4 of Control Word 001H = 0. The filter set selected by CSEL0-4 = 0 should be loaded by writing C2, C5, C8, C11, D2, D5, D8, and (D11)/ 2 into 100H, 101H, 102H, 103H, 104H, 105H, 106H, and 107H. The filter set selected by CSEL0-4 = 1 should be loaded by writing C1, C4, C7, C10, D1, D4, D7, and D10 into 108H, 109H, 10aH, 10bH, 10cH, 10dH, 10eH, and 10fH. The filter set selected by CSEL0-4 = 2 should be loaded by writing C0, C3, C6, C9, D0, D3, D6, and D9 into 110H, 111H, 112H, 113H, 114H, 115H, 116H, and 117H. HSP43168 h2(n) D3 D1 D2 D0 D6 D4 D5 D7 D8 D11 D9 D10 D10 D9 23-TAPS FIRB D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 25 shows the Timing Diagram required to obtained the multiplexed/decimated output. The output of the two filters are provided at by selecting the odd-decimation filter first, then the even-decimation second using MUX0-1. Figure 26 shows the Data Flow Diagram for the multiplexed decimation example. 0 B(n) 1 2 4 3 20 5 21 22 CLK 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 h1(n) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C11 C11 C10 C10 C9 24-TAPS FIRA C8 C7 C6 C5 C4 C3 C2 INA0-9 0 1 2 3 CSEL0-4 0 1 2 0 4 5 1 2 20 21 22 2 0 1 ACCEN C1 C0 11 MUX0-1 10 11 11 10 11 A(n) TXFR 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIGURE 25. TIMING DIAGRAM FOR MULTIPLEXED DECIMATION EXAMPLE FIGURE 24. DATA/COEFFICIENT ALIGNMENT FOR MULTIPLEXED DECIMATION EXAMPLE FIR B FIR B 3 2 1 6 5 4 9 8 7 20 19 18 17 16 15 14 13 12 2 1 6 13 12 11 10 B DATA STREAM 21 20 19 22 21 + + + + D5 + 15 14 13 + + D4 D7 D10 CSEL = 1 CSEL = 0 D11/2 D8 18 17 16 + D1 D2 11 10 8 7 12 5 4 9 ACCUMULATOR ACCUMULATOR (X2+X22)D1+(X5+X19)D4+(X8+X16)D7+(X11+X13)D10 +(X3+X21)D2+(X6+X18)D5+(X9+X15)D8+(X12+X12)D11/2 (X3+X21)D2+(X6+X18)D5+(X9+X15)D8+(X12+X12)D11/2 FIR A A DATA STREAM 2 1 0 21 20 19 18 8 7 6 1 0 5 11 10 9 10 9 7 6 11 4 3 8 12 + C2 5 4 3 FIR A + C5 22 14 13 12 17 16 15 + C8 + C11 21 20 19 + CSEL = 0 C1 18 17 16 + C4 15 14 13 + C7 + C10 CSEL = 1 ACCUMULATOR ACCUMULATOR (X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 (X1+X22)C1+(X4X19)C4+(X7+X16)C7+(X10+X13)C10 +(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 FIGURE 26A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED FORWARD STAGE 19 FIGURE 26B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS CLOCKED INTO THE FEED FORWARD STAGE HSP43168 FIR B 1 6 5 4 9 8 7 12 11 FIR B 10 6 5 4 9 8 7 12 11 10 23 22 21 20 19 18 17 16 15 15 14 13 13 14 23 22 21 20 + D0 19 18 17 + D3 24 16 15 14 + D6 D9 ACCUMULATOR + + CSEL = 2 D2 + D5 OUTPUT OF B IS SENT TO OUT9-27 + D8 + D11/2 CSEL = 0 ACCUMULATOR (X6+X24)D2+(X9+X21)D5+(X12+X18)D8+(X15+X15)D11/2 (X1+X23)D0+(X4+X20)D3+(X7+X17)D6+(X14+X10)D9 +(X2+X22)D1+(X5+X19)D4+(X8+X16)D7+(X11+X13)D10 +(X3+X21)D2+(X6+X18)D5+(X9+X15)D8+(X12+X12)D11/2 FIR A 0 5 4 3 8 7 6 11 10 FIR A 9 5 4 3 8 7 6 11 10 9 12 13 23 22 21 20 + C0 19 18 17 + C3 16 15 14 + C6 14 13 12 24 + C9 23 22 21 + CSEL = 2 C2 20 19 18 + C5 17 16 15 + C8 + C11 CSEL = 0 OUTPUT OF A IS SENT TO OUT9-27 ACCUMULATOR ACCUMULATOR (X0+X23)C0+(X3+X20)C3+(X6+X17)C6+(X9+X14)C9 +(X1+X22)C1+(X4+X19)C4+(X7+X16)C7+(X10+X13)C10 +(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11 (X5+X24)C0+(X8+X21)C5+(X11+X18)C8+(X14+X15)C11 FIGURE 26C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 26D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 26. DATA FLOW DIAGRAM FOR MULTIPLEXED DECIMATION EXAMPLE 20 HSP43168 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CPGA Package . . . . . . . . . . . . . . . . . . 35 6 MQFP Package . . . . . . . . . . . . . . . . . . 33.0 N/A PLCC Package. . . . . . . . . . . . . . . . . . . 23.0 N/A Maximum Junction Temperature CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC MQFP and PLCC Packages. . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (MQFP and PLCC - Leads Tips Only) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5% Temperature Range, Commercial . . . . . . . . . . . . . . . . . 0oC to 70oC Temperature Range, Industrial. . . . . . . . . . . . . . . . . . . .-40oC to 85o Die Characteristics Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V Number of Transistors or Gates . . . . . . . . . . . . . . . . . . . . . . . . 32529 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current ICCOP VCC = Max CLK Frequency 33MHz Notes 3, 4, 5 - 363 mA Standby Power Supply Current ICCSB VCC = Max, Outputs Not Loaded - 500 µA Input Leakage Current II VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current IO VCC = Max, Input = 0V or VCC -10 10 µA Logical One Input Voltage VIH VCC = Max 2.0 - V Logical Zero Input Voltage VIL VCC = Min - 0.8 V Logical One Output Voltage VOH IOH = -400µA, VCC = Min 2.6 - V Logical Zero Output Voltage VOL IOL = 2mA, VCC = Min - 0.4 V Clock Input High VIHC VCC = Max 3.0 - V Clock Input Low VILC VCC = Min - 0.8 V Input Capacitance CIN CLK Frequency 1MHz All measurements referenced to GND. TA = 25oC, Note 2 - 12 pF - 12 pF Output Capacitance COUT NOTES: 2. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 3. Power Supply current is proportional to operating frequency. Typical rating for ICCOP is 11mA/MHz. 4. Output load per test load circuit and CL = 40pF. 5. Maximum junction temperature must be considered when operating part at high clock frequencies. 21 HSP43168 AC Electrical Specifications VCC = +4.75V to +5.25V, TA = 0oC to 70oC Commercial, TA = -40oC to 85oC Industrial (Note 6) PARAMETER SYMBOL NOTES -33 (33MHz) -40 (40.8MHz) -45 (45MHz) MIN MAX MIN MAX MIN MAX UNITS CLK Period tCP 30 - 24.5 - 22 - ns CLK High tCH 12 - 10 - 8 - ns CLK Low tCL 12 - 10 - 8 - ns WR Period tWP 30 - 24.5 - 22 - ns WR High tWH 12 - 10 - 10 - ns WR Low tWL 12 - 10 - 10 - ns Setup Time A0-8 to WR Going Low tAWS 10 - 8 - 8 - ns Hold Time A0-8 from WR Going High tAWH 0 - 0 - 0 - ns Setup Time CIN0-9 to WR Going High tCWS 12 - 11 - 10 - ns Hold Time CIN0-9 from WR Going High tCWH 1 - 1 - 1 - ns Setup Time WR Low to CLK Low tWLCL Note 7 5 - 4 - 3 - ns Setup Time CIN0-9 to CLK Low tCVCL Note 7 7 - 7 - 7 - ns Setup Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9, ACCEN, MUX0-1 to CLK Going High tECS 15 - 13 - 12 - ns Hold Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9, ACCEN, MUX0-1 to CLK Going High tECH 0 - 0 - 0 - ns CLK to Output Delay OUT0-27 tDO - 14 - 13 - 12 ns Output Enable Time tOE - 12 - 12 - 12 ns Output Disable Time tOD Note 8 - 12 - 12 - 12 ns Output Rise, Fall Time tRF Note 8 - 6 - 6 - 6 ns NOTES: 6. AC tests performed with CL = 40pF, IOL = 2mA, and IOH = -400µA. Input reference level CLK = 2.0V. Input reference level for all other inputs is 1.5V. Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V, VILC = 0V. 7. Setup time requirement for loading of data on CIN0-9 to guarantee recognition on the following clock. 8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. AC Test Load Circuit DUT S1 CL (NOTE) SWITCH S1 OPEN FOR ICCSB AND ICCOP IOH ± 1.5V EQUIVALENT CIRCUIT NOTE: Test head capacitance. 22 IOL HSP43168 Waveforms tCP tCH tCL CLK tECS CSEL0 - 4, MUX0 - 1 tECH SHFTEN, FWRD RVRS, TXFR INA0 - 9, INB0 - 9, ACCEN tDO OUT0 - 27 tWLCL tWP tWH tWL WR tAWH tAWS A0 - 8 tCWS tCWH CIN0 - 9 tCVCL 1.5V OEL, OEH 1.5V tOE OUT0 - 27 HIGH IMPEDANCE tOD 1.7V 1.3V HIGH IMPEDANCE FIGURE 27. OUTPUT ENABLE, DISABLE TIMING 2.0V 0.8V tRF 2.0V 0.8V tRF FIGURE 28. OUTPUT RISE AND FALL TIMES 23 HSP43168 Metric Plastic Quad Flatpack Packages (MQFP) Q100.14x20 (JEDEC MS-022GC-1 ISSUE B) D 100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 -D- INCHES -A- -B- E E1 e PIN 1 SEATING A PLANE -H- 0.076 0.003 -C- 12o-16o 0.40 0.016 MIN 0.20 M C A-B S 0.008 0o MIN A2 A1 0o-7o L 24 MIN MAX MIN MAX NOTES A - 0.134 - 3.40 - A1 0.010 - 0.25 - - A2 0.101 0.113 2.57 2.87 - b 0.009 0.015 0.22 0.38 6 b1 0.009 0.013 0.22 0.33 - D 0.908 0.918 23.08 23.32 3 D1 0.782 0.792 19.88 20.12 4, 5 E 0.673 0.681 17.10 17.30 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.029 0.040 0.73 1.03 - N 100 100 7 e 0.026 BSC 0.65 BSC - ND 30 30 - NE 20 20 Rev. 1 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. b 2. All dimensions and tolerances per ANSI Y14.5M-1982. b1 BASE METAL WITH PLATING SYMBOL D S 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 0.13/0.17 0.005/0.007 12o-16o MILLIMETERS 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.23 0.005/0.009 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. HSP43168 Ceramic Pin Grid Array Packages (CPGA) S1 G84.A MIL-STD-1835 CMGA3-P84C (P-AC) –A– D 84 LEAD CERAMIC PIN GRID ARRAY PACKAGE INCHES D1 –B– S E1 E MIN MAX MIN MAX A 0.215 0.345 5.46 8.76 - 0.070 0.145 1.78 3.68 3 b 0.016 0.0215 0.41 0.55 8 b1 0.016 0.020 0.41 0.51 - b2 0.042 0.058 1.07 1.47 4 C - 0.080 - 2.03 - D 1.140 1.180 29.97 - E INDEX CORNER SEE NOTE 9 1.140 0.100 BSC 2.54 BSC 6 k 0.008 REF 0.20 REF - L 0.120 0.140 3.05 3.56 - Q 0.040 0.060 1.02 1.52 5 N 0.000 BSC 0.003 SEATING PLANE AT STANDOFF k A1 L b2 e Q SECTION A-A b A A Ø0.030 M C A M B M Ø0.010 M C L A1 Q 25 0.00 BSC - 0.08 121 - 11 - 10 - - 121 2 11 1 Rev. 1 6/28/95 b 0.008 C B - e S B 29.97 - S1 –C– 28.96 - 25.4 BSC b1 SECTION B-B 1.180 25.4 BSC 1.000 BSC M A 28.96 1.000 BSC E1 S SEE NOTE 7 NOTES A1 D1 C MILLIMETERS SYMBOL NOTES: 1. “M” represents the maximum pin matrix size. 2. “N” represents the maximum allowable number of pins. Number of pins and location of pins within the matrix is shown on the pinout listing in this data sheet. 3. Dimension “A1” includes the package body and Lid for both cavity-up and cavity-down configurations. This package is cavity up. Dimension “A1” does not include heatsinks or other attached features. 4. Standoffs are intrinsic and shall be located on the pin matrix diagonals. The seating plane is defined by the standoffs at dimensions Q. 5. Dimension “Q” applies to cavity-up configurations only. 6. All pins shall be on the 0.100 inch grid. 7. Datum C is the plane of pin to package interface for both cavity up and down configurations. 8. Pin diameter includes solder dip or custom finishes. Pin tips shall have a radius or chamfer. 9. Corner shape (chamfer, notch, radius, etc.) may vary from that shown on the drawing. The index corner shall be clearly unique. 10. Dimension “S” is measured with respect to datums A and B. 11. Dimensioning and tolerancing per ANSI Y14.5M-1982. 12. Controlling dimension: INCH. HSP43168 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N84.1.15 (JEDEC MS-018AF ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” A1 A D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN 84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 1.185 1.195 30.10 30.35 - D1 1.150 1.158 29.21 29.41 3 D2 0.541 0.569 13.75 14.45 4, 5 E 1.185 1.195 30.10 30.35 - E1 1.150 1.158 29.21 29.41 3 E2 0.541 0.569 13.75 14.45 4, 5 N 84 84 6 Rev. 2 11/97 SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 26 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029