INTERSIL HSP43168GM

HSP43168/883
TM
Data Sheet
May 1999
FN3177.3
Dual FIR Filter
Features
The HSP43168/883 Dual FIR Filter consists of two
independent 8-tap FIR filters. Each filter supports
decimation from 1 to 16 and provides on-board storage for
32 sets of coefficients. The Block Diagram shows two FIR
cells each fed by a separate coefficient bank and one of two
separate inputs. The outputs of the FIR cells are either
summed or multiplexed by the MUX/Adder. The compute
power in the FIR Cells can be configured to provide
quadrature filtering, complex filtering, 2-D convolution, 1D/2-D correlations, and interpolating/decimating filters.
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Two Independent 8-Tap FIR Filters Configurable as a
Single 16-Tap FIR
• 10-Bit Data and Coefficients
• On-Board Storage for 32 Programmable
Coefficient Sets
• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or
10 x 20-Bit Data and Coefficients
The FIR cells take advantage of symmetry in FIR
coefficients by pre-adding data samples prior to
multiplication. This allows an 8-tap FIR to be implemented
using only 4 multipliers per filter cell. These cells can be
configured as either a single 16-tap FIR filter or dual 8-tap
FIR filters. Asymmetric filtering is also supported.
• Programmable Decimation to 16
• Programmable Rounding on Output
• Standard Microprocessor Interface
• 33MHz, 25.6MHz Versions
Decimation of up to 16 is provided to boost the effective number
of filter taps from 2 to 16 times. Further, the Decimation
Registers provide the delay necessary for fractional data
conversion and 2-D filtering with kernels to 16 x 16.
Applications
The flexibility of the dual is further enhanced by 32 sets of
user programmable coefficients. Coefficient selection may
be changed asynchronously from clock to clock. The ability
to toggle between coefficient sets further simplifies
applications such as polyphase or adaptive filtering.
• Image Processing
• Quadrature, Complex Filtering
• Correlation
• PolyPhase Filtering
• Adaptive Filtering
Ordering Information
The HSP43168 is a low power fully static design
implemented in an advanced CMOS process. The
configuration of the device is controlled through a standard
microprocessor interface.
PART NUMBER
TEMP.
RANGE ( oC)
PACKAGE
PKG.
NO.
HSP43168GM-25/883
-55 to 125
84 Ld PGA
G84.A
HSP43168GM-33/883
-55 to 125
84 Ld PGA
G84.A
Block Diagram
10
CIN0 - 9
A0 - 8
WR
CSEL0 - 4
CONTROL /
CONFIGURATION
9
COEFFICIENT
BANK A
COEFFICIENT
BANK B
10
INA0 - 9
INB0 - 9/
OUT0 - 8
FIR CELL A
FIR CELL B
MUX
MUX
10
MUX /
ADDER
9
19
OUT9 - 27
OEL
OEH
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HSP43168/883
Pinouts
84 PIN PGA
TOP VIEW
11
10
9
8
7
6
OUT15 OUT14 OUT12 OUT10 OUT11
5
4
3
2
1
INB1
INB4
INB5
INB6
INB9
L
GND
INB7
INB8
INA1
K
INA0
INA2
J
INA3
INA4
H
L
GND
K
OUT18
J
OUT19 OUT17
H
OUT21 OUT20
G
OUT24 OUT23 OUT25
INA7
INA5
INA6
G
F
OUT27 OUT22 OUT26
INA8
INA9
VCC
F
CIN2
CIN1
CIN0
E
GND
CIN3
D
CIN6
CIN4
C
CIN7
CIN5
B
VCC
OUT16 OUT13
E
OEH
GND
D
VCC
ACCEN
C
TXFR
FWRD
B
SHFT
EN
MUX0 MUX1
A
RVRS
WR
11
10
VCC
INB0
INB2
OUT9
OEL
INB3
CLK
A5
A6
CSEL0
A0
A3
A2
VCC
GND
A1
A4
A7
A8
9
8
7
6
5
CSEL2 CIN9
CSEL1 CSEL3 CSEL4 CIN8
4
3
2
1
4
3
2
1
'A1'
A PIN
ID
84 PIN PGA
BOTTOM VIEW
11
10
9
8
7
6
5
A
RVRS
WR
GND
A1
A4
A7
A8
B
SHFT
EN
MUX0 MUX1
A0
A3
A2
VCC
C
TXFR FWRD
A5
A6
CSEL0
CSEL1 CSEL3 CSEL4 CIN8
A PIN 'A1'
ID
CIN7
CIN5
B
CIN6
CIN4
C
GND
CIN3
D
CIN2
CIN1
CIN0
E
OUT27 OUT22 OUT26
INA8
INA9
VCC
F
G OUT24 OUT23 OUT25
INA7
INA5
INA6
G
INA3
INA4
H
INA0
INA2
J
D
VCC
ACCEN
E
OEH
GND
F
H
OUT21 OUT20
J
OUT19 OUT17
K
OUT18
L
GND
11
2
VCC
CLK
OUT16 OUT13
OUT9
OEL
INB3
VCC
INB0
INB2
GND
INB7
INB8
INA1
K
INB1
INB4
INB5
INB6
INB9
L
5
4
3
2
1
OUT15 OUT14 OUT12 OUT10 OUT11
10
CSEL2 CIN9
9
8
7
6
HSP43168/883
Pin Description
NAME
PIN
NUMBER
VCC
B5, D11, K10, K7, F1
VCC: +5V power supply pin.
GND
A9, E10, L11, K4, D2
Ground.
CIN0-9
E1-3, D1, C1-2, B1-3,
A1
I
Control/Coefficient Data Bus. Processor interface for loading control data and coefficients.
CIN0 is the LSB.
A0-8
A5-8, B6-8, C6-7
I
Control/Coefficient Address Bus. Processor interface for addressing control and Coefficient
Registers. A0 is the LSB.
WR
A10
I
Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on
the rising edge of WR.
CSEL0-4
A2-4, B4, C5
I
Coefficient Select. This input determines which of the 32 coefficient sets are to be used by
FIR A and B. This input is registered and CSEL0 is the LSB.
INA0-9
K1, J1-2, H1-2, G1-3,
F2-3
I
Input to FIR A. INA0 is the LSB.
INB0-9
L1-5, K2-3, K5-6, J5
I/O
OUT9-27
F9-11, G9-11, H10-11,
J10-11, J7, K11, K8-9,
L6-10
O
19 MSB’s of Output Bus. Data format is either unsigned or two’s complement depending on
configuration. OUT27 is the MSB.
SHFTEN
B11
I
Shift Enable. This active low input enables shifting of data through the Decimation Registers.
FWRD
C10
I
Forward ALU Input Enable. When active low, data from the forward decimation path is input
to the ALU’s through the “a” input. When high, the “a” inputs to the ALUs are zeroed.
RVRS
A11
I
Reverse ALU Input Enable. When active low, data from the reverse decimation path is input
to the ALU’s through the “b” input. When high, the “b” inputs to the ALUs are zeroed.
TXFR
C11
I
Data Transfer Control. This active low input switches the LIFO being read into the reverse
decimation path with the LIFO being written from the forward decimation path (see Figure 1).
MUX0-1
B9-10
I
Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 3.0
lists the various configurations.
CLK
E9
I
Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR)
and the output enables (OEL, OEH) are registered by the rising edge of CLK.
OEL
J6
I
Output Enable Low. This tristate control enables the LSB’s of the output bus to
INB1-9 when OEL is low.
OEH
E11
I
Output Enable High. This tristate control enables OUT9-27 when OEH is low.
ACCEN
D10
I
Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator.
A low on this input latches the FIR Accumulator contents into the Output Holding Registers
while zeroing the feedback path in the accumulator.
3
TYPE
DESCRIPTION
Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output,
INB1-9 is the LSB’s of the output bus.
HSP43168/883
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . .300oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to 125oC
θJA (oC/W)
θJC(oC/W)
Ceramic PGA Package . . . . . . . . . . . .
33.5
7.5
Maximum Package Power Dissipation at 125oC
Ceramic PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.49 W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32529 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER
SYMBOL
CONDITIONS
LIMITS
GROUP A
SUB-GROUPS
TEMPERATURE (oC)
MIN
MAX
UNITS
Logical One Input
Voltage
VIH
VCC = 5.5V
1, 2, 3
-55 ≤ TA ≤ 125
2.2
-
V
Logical Zero Input
Voltage
VIL
VCC = 4.5V
1, 2, 3
-55 ≤ TA ≤ 125
-
0.8
V
Logical One Input
Voltage Clock
VIHC
VCC = 5.5V
1, 2, 3
-55 ≤ TA ≤ 125
3.0
-
V
Logical Zero Input
Voltage Clock
VILC
VCC = 4.5V
1, 2, 3
-55 ≤ TA ≤ 125
-
0.8
V
Output HIGH Voltage
VOH
IOH = -400µA
VCC= 4.5V (Note 1)
1, 2, 3
-55 ≤ TA ≤ 125
2.6
-
V
Output LOW Voltage
VOL
IOL = +2.0mA
VCC= 4.5V (Note 1)
1, 2, 3
-55 ≤ TA ≤ 125
-
0.4
V
Input Leakage Current
II
VIN = VCC or GND
VCC = 5.5V
1, 2, 3
-55 ≤ TA ≤ 125
-10
+10
µA
Output Leakage Current
IO
VIN = VCC or GND
VCC = 5.5V
1, 2, 3
-55 ≤ TA ≤ 125
-10
+10
µA
Standby Power Supply
Current
ICCSB
VIN = VCC or GND
VCC = 5.5V,
Outputs Open
1, 2, 3
-55 ≤ TA ≤ 125
-
500
µA
Operating Power Supply
Current
ICCOP
f = 25.6MHz, VIN =
VCC or GND, VCC =
5.5V (Note 2)
1, 2, 3
-55 ≤ TA ≤ 125
-
281.6
mA
7, 8
-55 ≤ TA ≤ 125
-
-
-
Functional Test
FT
(Note 3)
NOTES:
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current is proportional to frequency, typical rating is 11mA/MHz.
4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.4V, VIH (all other inputs) = 2.6V, V IL = 0.4V, VOH ≥ 1.5V, and VOL ≤ 1.5V.
4
HSP43168/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 5)
CONDITIONS
(-33MHz)
(-25MHz)
GROUP A
SUBGROUPS
TEMPERATURE (oC)
MIN
MAX
MIN
MAX
UNITS
CLK Period
TCP
9, 10, 11
-55 ≤ TA ≤ 125
30
-
39
-
ns
CLK High
TCH
9, 10, 11
-55 ≤ TA ≤ 125
12
-
15
-
ns
CLK Low
TCL
9, 10, 11
-55 ≤ TA ≤ 125
12
-
15
-
ns
WR Period
TWP
9, 10, 11
-55 ≤ TA ≤ 125
30
-
39
-
ns
WR High
TWH
9, 10, 11
-55 ≤ TA ≤ 125
12
-
15
-
ns
WR Low
TWL
9, 10, 11
-55 ≤ TA ≤ 125
12
-
15
-
ns
Set-up Time;
A0-8 to WR Low
TAWS
9, 10, 11
-55 ≤ TA ≤ 125
10
-
10
-
ns
Hold Time;
A0-8 to WR High
TAWH
9, 10, 11
-55 ≤ TA ≤ 125
1
-
1
-
ns
Set-up Time;
CIN0-9 to WR High
TCWS
9, 10, 11
-55 ≤ TA ≤ 125
12
-
15
-
ns
Hold Time;
CIN0-9 to WR High
TCWH
9, 10, 11
-55 ≤ TA ≤ 125
1.5
-
1.5
-
ns
Set-up Time;
WR Low to CLK Low
TWLCL
Note 7
9, 10, 11
-55 ≤ TA ≤ 125
5
-
8
-
ns
Set-up Time;
CIN0-9 to CLK Low
TCVCL
Note 7
9, 10, 11
-55 ≤ TA ≤ 125
8
-
8
-
ns
Set-up Time;
CSEL0-5, SHFTEN,
FWRD, RVRS,
TXFR, MUX0-1 to
CLK High
TECS
9, 10, 11
-55 ≤ TA ≤ 125
15
-
17
-
ns
Hold Time;
CSEL0-5, SHFTEN,
FWRD, RVRS,
TXFR, MUX0-1 to
CLK High
TECH
9, 10, 11
-55 ≤ TA ≤ 125
0
-
0
-
ns
CLK to Output Delay
OUT0-27
TDO
9, 10, 11
-55 ≤ TA ≤ 125
-
15
-
17
ns
Output Enable Time
TOE
9, 10, 11
-55 ≤ TA ≤ 125
-
12
-
12
ns
Note 6
NOTES:
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 3.0V and 0V; timing reference levels (CLK)
2.0V; all others 1.5V. VCC = 4.5V and 5.5V. Output load per test load circuit with CL = 40 pF. Output transition is measured at VOH Š > 1.5V and
V OL < 1.5V.
6. Transition is measured at ±200mV from steady state voltage, Output loading per test load circuit, CL = 40pF.
7. Set-up time requirements for loading of data on CIN0-9 to guarantee recognition on the following clock.
5
HSP43168/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
(-33MHz)
PARAMETER
Input Capacitance
SYMBOL
CIN
Output Capacitance
COUT
Output Disable Time
TOD
CONDITIONS
VCC = Open,
f = 1 MHz, All measurements are referenced to
device GND.
(-25MHz)
NOTES
TEMPERATURE (oC)
MIN
MAX
MIN
MAX
UNITS
1
TA = 25
-
12
-
12
pF
1
TA = 25
-
12
-
12
pF
1, 2
-55 ≤ TA ≤ 125
-
12
-
12
ns
Output Rise Time
tR
From 0.8V to 2.0V
1, 2
-55 ≤ TA ≤ 125
-
8
-
8
ns
Output Fall Time
tF
From 2.0V to 0.8V
1, 2
-55 ≤ TA ≤ 125
-
8
-
8
ns
NOTES:
8. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after
major process and/or design changes.
9. Loading is as specified in the test load circuit with CL = 40pF.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
-
PDA
100%
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
-
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Samples/5005
1, 7, 9
Group A
Groups C and D
AC Test Load Circuit
S1
DUT
*CL
IOH
±
1.5V
* INCLUDES STRAY
AND JIG
CAPACITANCE
EQUIVALENT CIRCUIT
SWITCH S1 OPEN FOR ICCSB AND ICCOP TEST
6
IOL
HSP43168/883
Waveforms
tCP
tCH
tCL
CLK
tECS
tECH
CSEL0-4, MUX0-1
SHFTEN, FWRD,
RVRS, TXFR,
INA0-9, INB0-9
tDO
OUT0-27
tWLCL
tWP
tWH
tWL
WR
tAWS
tAWH
A0-8
tCWS
tCWH
CIN0-15
tCVCL
1.5V
OEL, OEH
1.5V
tOD
tOE
1.7V
OUT0-27
HIGH
IMPEDANCE
1.3V
HIGH
IMPEDANCE
OUTPUT ENABLE, DISABLE TIMING
2.0V
2.0V
0.8V
0.8V
tRF
tRF
OUTPUT RISE AND FALL TIMES
7
HSP43168/883
Burn-In Circuit
84 PIN PGA
BOTTOM VIEW
11
10
9
8
7
6
5
A
RVRS
WR
GND
A1
A4
A7
A8
B
SHFT
MUX0 MUX1
EN
A0
A3
A2
VCC
C
TXFR FWRD
A5
A6
CSEL0
D
VCC
ACCEN
E
OEH
GND
4
3
2
1
CSEL1 CSEL3 CSEL4 CIN8
A
CSEL2 CIN9
CLK
CIN7
CIN5
B
CIN6
CIN4
C
GND
CIN3
D
CIN2
CIN1
CIN0
E
F
OUT27 OUT22 OUT26
INA8
INA9
VCC
F
G
OUT24 OUT23 OUT25
INA7
INA5
INA6
G
H
OUT21 OUT20
INA3
INA4
H
J
OUT19 OUT17
INA0
INA2
J
K
OUT18
L
OEL
INB3
INB0
INB2
GND
INB7
INB8
INA1
K
GND OUT15 OUT14 OUT12 OUT10 OUT11 INB1
INB4
INB5
INB6
INB9
L
4
3
2
1
11
VCC
OUT9
OUT16 OUT13 VCC
10
9
8
7
6
5
PIN 'A1'
ID
NOTES:
1. VCC/2 (2.7V ±10%) used for outputs only.
2. 47KΩ (±20%) resistor connected to all pins except VCC and GND.
3. V CC = 5.5 ±0.5V.
4. 0.1µf (Min) capacitor between VCC and GND per position.
8
5. F0 = 100KHz ±10%, F1 = F0/2, F2 = F1/2. . . , F16 = F15/2,
40 to 60% duty cycle.
6. Input voltage limits:
VIL = 0.8V Max, VIH = 4.5 ±10%.
HSP43168/883
PGA PIN
PIN NAME
PGA PIN
BURN-IN SIGNAL
PIN NAME
BURN-IN SIGNAL
A1
CIN8
F9
F9
SUM26
VCC/2
A2
CSEL4
F12
F10
SUM22
VCC/2
A3
CSEL3
F11
F11
SUM27
VCC/2
INA6
F7
A4
CSEL1
F9
G1
A5
A8
F12
G2
INA5
F6
A6
A7
F10
G3
INA7
F8
A7
A4
F11
G9
SUM25
VCC/2
A8
A1
F12
G10
SUM23
VCC/2
A9
GND
GND
G11
SUM24
VCC/2
A10
WRB
F6
H1
INA4
F5
A11
RVRS
F12
H2
INA3
F4
SUM20
VCC/2
B1
CIN5
F8
H10
B2
CIN7
F10
H11
SUM21
VCC/2
B3
CIN9
F10
J1
INA2
F3
B4
CSEL2
F10
J2
INA0
F1
B5
VCC
VCC
J5
INB3
F4
B6
A2
F11
J6
OELB
F13
B7
A3
F10
J7
SUM9
VCC/2
B8
A0
F13
J10
SUM17
VCC/2
SUM19
VCC/2
B9
MUX1
F13
J11
B10
MUX0
F12
K1
INA1
F2
B11
SHFTEN
F14
K2
INB8
F9
C1
CIN4
F7
K3
INB7
F8
C2
CIN6
F9
K4
GND
GND
C5
CSEL0
F8
K5
INB2
F3
C6
A6
F11
K6
INB0
F1
C7
A5
F12
K7
VCC
VCC
SUM13
VCC/2
C10
FWRD
F13
K8
C11
TXFR
F11
K9
SUM16
VCC/2
D1
CIN3
F10
K10
VCC
VCC
D2
GND
GND
K11
SUM18
VCC/2
D10
ACCEN
F13
L1
INB9
F10
D11
VCC
VCC
L2
INB6
F7
E1
CIN0
F7
L3
INB5
F6
E2
CIN1
F8
L4
INB4
F5
INB1
F2
E3
CIN2
F9
L5
E9
CLK
F0
L6
SUM11
VCC/2
E10
GND
GND
L7
SUM10
VCC/2
E11
OEHB
F14
L8
SUM12
VCC/2
F1
VCC
VCC
L9
SUM14
VCC/2
F2
INA9
F10
L10
SUM15
VCC/2
F3
INA8
F9
L11
GND
GND
9
HSP43168/883
Die Characteristics
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ
DIE DIMENSIONS:
314 x 348 x 19 ± 1mils
WORST CASE CURRENT DENSITY:
METALLIZATION:
1.93 x 105 A/cm2
Type: Si-Al or Si-Al-Cu
Thickness: 8kÅ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
7585 Irvine Center Drive
Suite 100
Irvine, CA 92618
TEL: (949) 341-7000
FAX: (949) 341-7123
Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7946
10
EUROPE
Intersil Europe Sarl
Ave. William Graisse, 3
1006 Lausanne
Switzerland
TEL: +41 21 6140560
FAX: +41 21 6140579
ASIA
Intersil Corporation
Unit 1804 18/F Guangdong Water Building
83 Austin Road
TST, Kowloon Hong Kong
TEL: +852 2723 6339
FAX: +852 2730 1433