EL1056A, EL1056 UCT ROD CEMENT t P E EPLA ter a OLET OBS NDED R port Cen /tsc E p M Su com ECOM echnical .intersil. w NO R T Data Sheet March 1993, Rev. A w r ct ou L or w conta -INTERSI 1-888 ® Monolithic High-Speed Pin Driver Features The EL1056 is designed to drive highquality test signals into close or terminated loads. It has a dispersion of 250ps or less — whether due to signal size or direction of edge. It can output a very wide 24V output span, encompassing all logic families as well as analog levels. The EL1056 is fabricated in Elantec's oxide isolated process, which eliminates the possibility of latch-up and provides a very durable circuit. • Wide ±12V output levels The output can be turned off in two ways; the OE pins allow the output to be put in a high-impedance state which makes the output look like a large resistance in parallel with 3pF, even for back-driven signals with as much as 2.5V/µs slew rate. The E pins put the output in an even higher impedance state, guaranteed to 150nA leakage in the EL1056A. This allows accurate measurements on the bus without disconnecting the EL1056 with a relay. The EL1056 incorporates an output current sense which can warn the system controller that excessive output current is flowing. The trip point is set by two external resistors. Pinout FN7035 • 250ps dispersion • 3ns delay times • 1V/ns slew rate—adjustable • Low overshoot and aberrations in 50Ω systems • Three-state output • Power-down mode reduces output leakage to nanoamperes • Overcurrent sense flag available to protect internal output devices • Buffered analog inputs • Differential logic inputs are compatible with ECL, TTL, and CMOS Applications • Memory testers • ASIC testers • Functional board testers EL1056A, EL1056 (24-PIN THERMAL SOL PACKAGE) TOP VIEW • Analog/digital incoming component verifiers • Logic emulators Ordering Information PART NUMBER TEMP. RANGE PACKAGE PKG. NO. EL1056CM 0°C to +75°C 24-Pin Thermal SOL MDP0027 EL1056ACM 0°C to +75°C 24-Pin Thermal SOL MDP0027 *and Heat-spreader 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL1056A, EL1056 Absolute Maximum Ratings (TA = 25°C) VS VB+ BISR VSR Shunt+ ShuntData, Data OE, OE Voltage between V+ and V- . . . . . . . . . . . . . . . . . .+33V Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -18V Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . VINH to V+ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . V- to VINL Input Current . . . . . . . . . . . . . . . . . . . . . . . 0mA to 3mA Input Voltage, Power-Down Mode . . . . . . . -0.3V to +6V Input Voltage . . . . . . . . . . . . . . . . . . . . . (B+) -5V to B+ Input Voltage . . . . . . . . . . . . . . . . . . . . . . B- to (B-) +5V Input Voltages . . . . . . . . . . . . . . . . . . . . . . . V- to V+ or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6V Differential Input Voltages . . . . . . . . . . . . . . . . . . . . . . . V- to V+ or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6V Differential E, E Sense VINH VINL IOUT TJ TA TST PD Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±6V Differential Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ Input Voltage . . . . . . . . . . . . . . . . . . . . . . .VINL -0.3V to B+ Input Voltage . . . . . . . . . . . . . . . . . . . . . . B- to VINH +0.3V Output Current. . . . . . . . . . . . . . . . . . . . . -60mA to +60mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C Operating Ambient Temperature Range . . . .-0°C to +75°C Storage Temperature . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation (TA = 25°C) (See Curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1W CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA. DC Electrical Specifications TA = 25°C, V+ = B+ =15V, V- = B- = -10V, Rshunt+ = Rshunt- = 6.5Ω, no load. Data, E, and OE from -1.6V to -0.8V. ISR = 800µA. VINH = 5V, VINL = -1.6V PARAMETER DESCRIPTION MIN TYP MAX UNITS IS (V+) + (B+), (V-) + (B-) Supply Currents 52 60 mA IS, dis (V+) + (B+), (V-) + (B-) Supply Currents, Disabled 17 25 mA IVINH -20 -3 20 µA IVINL -20 2 20 µA IDATA -30 -15 30 µA IOE OE Input Current -30 -14 30 µA IE E Input Current -20 7 20 µA VSR Voltage at ISR Pin 0 20 40 mV 4 7 mA 160 200 250 mV 1 1.5 2 mA 50 100 mV mV 0 0 % % Ishunt+, IshuntVshunt+, Vshunt- Sense Threshold at Shunts ISENSE Sense Output Currents VOS Output Offset, Data High, VINH = 0V, VINL = -1.6V Data Low, VINL = 0V, VINH = 5V -50 -100 Eg Gain Error Data High, VINH from 0V to 5V, VINL = -1.6V, No Load Data Low, VINH = 5V, VINL from -5V to 0V, No Load -1.5 -1.5 NL Gain Nonlinearity Data High, VINH from 0V to 10V, VINL = -1.6V, No Load Data Low, VINH = 5V, VINL from -10V to 0V, No Load 0.04 0.06 % % PSRR Power Supply Rejection Ratio of VOUT with Respect to B+, B-, Shunt+, or Shunt- Potential 2.2 mV/V RO, en Output Resistance, Enabled, Il = ±20mA RO, dis Output Resistance, Output Disabled, VO = -1.6V to -5V, EL1056 EL1056A IO, dis IO, off -0.6 -0.6 4.5 6 20K 100K 100K 200K Output Current, Output, Disabled, VO = 0V -20 5 Output Leakage, E Low, (Shut-Down), VO = 0V, EL1056 EL1056A -20 -150 2 7.5 Ω Ω 20 µA 20 150 µA nA EL1056A, EL1056 AC Electrical Specifications TA = 25°C, V+ = B+ = +15V, V- = B- = -10V, Rshunt+ = Rshunt- = 6.5Ω. RL = 500Ω. 50Ω + 22pF snubber included at output. Data E, and OE from -1.6V to -0.8V. ISR = 800µA. ECL swing is defined by VINH = 0.8V and VINL = -1.6V, CMOS swing defined by VINH = 5V and VINL = 0V. Propagation delay is measured at 0.4V movement of output. PARAMETER DESCRIPTION TPD Propagation Delay, CMOS Swing Dis Propagation Delay Dispersion Due to Output Edge Direction From ECL to CMOS Swings Due to Repetition Rate MIN TYP MAX UNITS 1.0 3.0 4.5 ns 250 250 80 450 450 ps ps ps 1 1.2 V/ns 3 10 % SR Output Slew Rate, CMOS Swing, 20%–80% 0.8 SRSYM Slew Rate Symmetry TR Output Rise Time, ECL Swing, 20%–80% 2.2 OS Output Overshoot CMOS Swing ECL Swing (ISR = 350µA) 190 65 500 mV mV TDIS Output Disable Delay Time 4.7 6.5 ns TEN Output Enable Delay Time 6.0 8.5 ns CO, dis Output Capacitance in Disable TOFF ns 3 pF Power-Down Delay Time 0.5 µs TON Power-On Delay Time 90 ns CO, off Output Capacitance in Power-Down 50 pF TSENSE Comparator Delay Time — Switching ON Switching OFF 1.5 0.4 µs µs 3 EL1056A, EL1056 Block Diagram 4 EL1056A, EL1056 Typical Performance Curves 10V, CMOS, TTL, and ECL Outputs into 550Ω Load CMOS Output at ISR = 100µA, 200µA, 400µA, and 1000µA Propagation Delay vs ISR 5 CMOS and ECL Outputs As Seen at the End of an Unterminated Cable, Backmatched at Driver Output Slewrate vs ISR (Two Samples) Output Slewrate vs Die Temperature EL1056A, EL1056 Typical Performance Curves (Continued) Propagation Delay Change with Die Temperature Output Edge Dispersion vs Temperature Minimum Output Pulse Width 6 Change in Propagation Delay with Power Supply Headroom Edge Dispersion vs ISR Output Offset vs ISR EL1056A, EL1056 Typical Performance Curves (Continued) Three-State Turn-off Waveforms Three-State Turn-on Waveforms Power-Down Disable Waveforms Power-Down Enable Waveforms Supply Current vs ISR 7 Total Supply Current vs Supply Voltage EL1056A, EL1056 Typical Performance Curves (Continued) Mounted Thermal Resistance of Package vs Airflow Speed Package Power Dissipation vs Ambient Temperature Sense Comparator Delay vs Overdrive EL1056 USED IN CMOS AND TTL SYSTEMS Applications Information Functional Description The EL1056 is a fully integrated pin driver for automatic test systems. Pin drivers are essentially pulse generators whose high and low levels can be externally programmed and accurately switched in time, as well as incorporating an output switch to disconnect the driver from a measurement bus. Additionally, the EL1056 has programmable slewrate. Control Voltage Inputs The analog level inputs are named VINH and VINL, and the output replicates them as controlled by logic inputs. The analog inputs are buffered and have bandwidths of 35MHz 8 and slewrates of 25V/µs. For full slewrate, 4V of headroom should be given to the inputs, that is VINH should be 4V less than V+ or B+, and VINL should be 4V more positive than Vor B-. At lower slewrates (ISR = 500µA or less), 3V of headroom will suffice. Insufficient headroom causes distorted output waveforms or delay errors in output transitions. VINH may be lower in voltage than VINL, but the output will not follow the control logic correctly. Furthermore, VINH should be 200mV more positive than VINL (the minimum output amplitude) for accurate switching. EL1056A, EL1056 Logic Inputs The logic inputs are all differential types, with both NPN and PNP transistors connected to each terminal. They are optimized for differential ECL drive, which optimizes + to edge delay time matching. Larger logic levels can introduce feedthrough glitches into the output waveform. For CMOS input logic levels, an ECL output waveform will show feedthrough when the input risetime is shorter than 8ns, differential or single-ended. CMOS output swings show less aberration, and the EL1056 can tolerate a 4ns single-ended risetime or 2ns risetime for differential inputs. Attenuating CMOS or TTL inputs to 1VPP will eliminate all logic feedthrough as shown in Figure 1. NPN will occur within the driver. A signal diode or zener can be used to clamp the ISR input for positive input voltages if the voltage on the ISR resistor is potentially greater than 6V when the driver is in power-down mode. Output Stage–Three-State Mode In three-state mode (OE low) the output transistors have their emitter-base junctions reverse-biased by a diode voltage. This turn-off voltage is in fact provided by an internal buffer whose input is connected to the output pin (see Figure 3). Transistors Q1–Q4 form the output buffer in normal mode. The three-state mode buffer Q5–Q8 replicates externally impressed voltages from the output pin onto the internal schottky switch node. They also turn off Q1–Q4 by a reverse diode voltage between bases and emitters, effectively bootstrapping the internal voltages, so that no transistor's base-emitter junction is reverse-biased by a damaging potential. Another benefit is that the capacitance seen at the output in three-state mode is reduced. Because the three-state buffer's input is connected to the output terminal, the output is quite “alive” during three-state. For instance, the input bias current of the buffer is seen as the three-state “leakage”, and its variation with applied voltage becomes three-state input impedance. The three-state input current is like a current source, and it can drag an output to unpredictable voltages. It is not a danger to connect a three-stated output that has drifted to, say, -6V to a logic pin of a device to be tested. The threestate output current will simply comply with whatever voltage the connected part normally establishes. FIGURE 1. ALTERNATE LOGIC INTERFACE Slewrate Control The slewrate is controlled by the ISR input. This is a current input and scales the output slewrate by a nominal 1.25V/ns/mA. The slewrate maintains calibration and symmetry to at least as slow as 0.2V/ns. The practical upper end of ISR is 1mA, and supply current increases with increasing ISR. The three-state input impedance is also quite active over frequency. The output can oscillate when presented with resonant or inductive impedances. To prevent this, a snubber should be connected from output to ground, consisting of a resistor in series with a small capacitor. The snubber can also reduce the reflections of the coaxial line when driven from the far end, since the line appears to have an open termination during three-state. Typical values for the resistor are 50Ω to 75Ω, and 12pF to 22pF for the series capacitor. The effect of the snubber is to “de-Q” resonances at the output. The ISR control can be used to adjust individual pin drivers to a system standard, by adjusting the value of its series resistor. Slewrate can also be slowed to reduce output ringing and crosstalk. With ECL output swings, there is not enough voltage excursion to incur slewrate delays to 50% logic threshold. The risetime, delays, and dispersions do not degrade with reasonably reduced ISR, and overshoot will reduce markedly. An ISR of 350µA produces a very good ECL output, and driver dissipation is also reduced. The ISR pin is connected to the emitter of a PNP transistor whose base is biased a diode below ground (see Figure 2). Thus, the ISR input looks like a low impedance for positive input currents, and is biased close to ground. A protection diode absorbs negative currents, and the input PNP will not conduct. In power-down mode, the PNP releases its current sink and the external circuit must not present more than 6V to the disabled ISR input, or emitter-base damage to the 9 FIGURE 2. ISR PIN CIRCUITRY EL1056A, EL1056 FIGURE 3. OUTPUT STAGE CIRCUIT IN THREE-STATE MODE Output Stage–Normal Mode Capacitive loads can cause the output stage to ring. Little ringing occurs for loads less than 25pF, but substantial ringing for more than 40pF. Terminated transmission lines cause no ringing, and actually suppress it as a snubber does. A terminated line draws heavy DC current, however, and greatly raises dissipation. Driving a back-terminated line also causes little ringing and does not cause DC dissipation. The series matching resistor between the EL1056 output and a back-terminated line also serves to isolate the driver from capacitive loads and shortcircuits. The slewrate of the driver slows by about 10% when 10 driving a 50Ω back-matched line, as seen at the end of the line. The snubber can be on either side of the back-match resistor. When placed on the line side it creates a highfrequency termination for the line when the driver is threestated, but it slows the output small-signal risetime by about 10% (although not slewrate). When placed on the driver side of the backmatch resistor, no speed reduction occurs in normal mode but the cable is more poorly terminated in three-state. EL1056A, EL1056 The transient currents that occur when driving capacitive or back-matched loads can be very high, approaching 100mA. The driver is capable of outputting a peak of 140mA, but long-term load currents must be limited to 60mA. Shortcircuits can rapidly destroy the EL1056, although the part will survive for 20ms periods. If there is the possibility of output load fault the overcurrent sense circuitry should be used to signal alarm to the controlling system, which should ultimately activate the three-state mode to relieve the output stage. Driving large static currents also raises internal dissipation and should be part of the thermal budget. The collectors of the output transistors are connected to the Shunt terminals, and the output stage drivers' collectors are connected to the B+ and B- terminals (see Figure 4). The Shunt lines can have transient currents as high as 120mA and are separated from the V+ and V- terminals to keep switching noise out of the control and logic circuitry. A bypass capacitor should be connected to the B+ and Bterminals. FIGURE 4. OUTPUT STAGE IN NORMAL MODE 11 EL1056A, EL1056 Overcurrent Protection Power-Down The sense comparators are available to alert the test system's controller that the driver is outputting excessive current. Shunt resistors are connected from B+ to Shunt+ and B- to Shunt-. When the internal comparators sense more than a nominal 200mV drop on the shunts, they cause a 1.5mA current to be sunk from the Sense terminal. The comparators are of “slow attack, fast decay” design, so that transient load currents will not trigger a sense output; only a sustained over-current will. The EL1056 incorporates a power-down feature that drastically reduces power consumption of an unused driver and also drops the output leakage current to nanoamperes (“A” grade only). The output is not a low capacitance in this mode, however, and transients driven from the cable can momentarily turn on the output transistors. Power-down is intended to allow the switching of accurate DC meters onto the bus without having to relay out the driver's leakage current. It takes about 40µs for the output leakage to sag to nanoamperes, but this is still much faster than relays or voltmeters. The sense resistors must not be inductive, and the skin resistance of long, narrow connections between Shunt and B+ or B- can cause transient voltages that produce output overshoot (but not ringing). The Sense output is simply a switched current source connected to V-. It can be used to interface to CMOS, TTL, or ECL inputs. For CMOS and TTL, it can be connected to a pull-up resistor to +5V of 10K value. This establishes a logic high value, and a clamp diode (internal to TTL) establishes a low level of -0.6V. For ECL, a gate should be available to provide a static logic high level. An 820Ω pull-up resistor is wired to that output. The logic low will be more negative than is usual for ECL, but this will cause no problem. In all cases, multiple Sense outputs may be connected together from many drivers to effect a wired-or function. A further protection scheme is to provide a series resistor from B+ to V+ and B- to V-. The resistor serves to limit the output fault current by allowing B+ and B- voltages to sag under heavy load. This also reduces the dissipation on the output transistors for valid loads. Because B+ and B- are separately bypassed, these voltages will sustain under transient loads and dynamics will not be affected. Output Accuracy The accuracy of the output voltage depends on several factors. The first is the gain error from VINH or VINL to the output, unloaded. The gain error is nominally -0.6%, and has a few tenths of a percent variation between parts. The second is supply rejection. If the B+, B-, Shunt+, or Shuntvoltages are different from those used by Elantec to test the part, there will be about 2.2mV systematic shift in output offset per volt of supply variation. The V+ and V- supplies have much less influence on output error. Finally, there is a random VOS error as specified in the data table. Power-down is controlled by the E and E differential inputs. There is no problem with logic amplitude or slewrate, and input resistor networks are not needed. Supply and Input Bypassing The V+, B+, V-, and B- leads should be bypassed very closely with 0.1µF capacitors, preferably chip type. There should be a wide ground plane between bypasses, and this can be the heatsink copper. It is wise to also have a 4.7µF tantalum bypass capacitor within a couple of inches to the driver. The logic inputs are active device bases, and can oscillate if presented with inductive lines. A local resistor of 1000Ω or less to ground will suffice in de-Q'ing any resonance. A 100pF or larger capacitor can also serve as a bypass. Thermal Considerations The package of the EL1056 includes two fused leads on each side which are connected to the internal die mounting metal. Heat generated in the die flows through the mounting pad to the fused leads, and then to the circuit-board copper, achieving a thermal resistance to air around 40°/W. Characterization curves show the thermal resistance versus airflow rate. Consult the EL1056 Demonstration Board literature for a suggested board pattern. Note that thicker layers of copper than we used improves the thermal resistance further, to a limit of 22°C/W for an “infinite heatsink” directly soldered to the fused leads. As a practical limit, the die temperature should be kept to 125°C rather than the allowable 150°C to retain optimum timing accuracies. Of course, the finite output impedance of the EL1056 will cause additional output error when the driver is loaded. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12