TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 COMPLETE DDR AND DDR2 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE FEATURES • • DESCRIPTION Synchronous Buck Controller (VDDQ) – Wide-Input Voltage Range: 3.0-V to 28-V – D–CAP™ Mode with 100-ns Load Step Response – Current Mode Option Supports Ceramic Output Capacitors – Supports Soft-Off in S4/S5 States – Current Sensing from RDS(on) or Resistor – 2.5-V (DDR), 1.8-V (DDR2) or Adjustable Output (1.5-V to 3.0-V) – Equipped with Powergood, Overvoltage Protection and Undervoltage Protection 3-A LDO (VTT), Buffered Reference (VREF) – Capable to Sink and Source 3 A – LDO Input Available to Optimize Power Losses – Requires only 20-µF Ceramic Output Capacitor – Buffered Low Noise 10-mA Output – Accuracy ±20 mV for both VREF and VTT – Supports High-Z in S3 and Soft-Off in S4/S5 – Thermal Shutdown TYPICAL APPLICATION (DDR2) VTT 0.9 V 2A C3 Ceramic 2 × 10 µF C4 Ceramic 0.033 µF VREF 0.9 V 10 mA GND APPLICATIONS • • TPS51116PWP 1 VLDOIN DDR/DDR2 Memory Power Supplies SSTL-2 SSTL-18 and HSTL Termination C1 Ceramic VIN C5 Ceramic 2 × 10 µF VBST 20 L1 1 µH 0.1 µF 2 VTT GND The TPS51116 provides a complete power supply for both DDR/SSTL-2 and DDR2/SSTL-18 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The TPS51116 offers the lowest total solution cost in systems where space is at a premium. The TPS51116 synchronous controller runs fixed 400kHz pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The TPS51116 supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The TPS51116 has all of the protection features including thermal shutdown and is in a 20-pin HTSSOP PowerPAD™ package. DRVH 19 3 VTTGND LL 18 4 VTTSNS DRVL 17 5 GND PGND 16 C8 SP−CAP 2 × 150 µF VDDQ 1.8 V 10 A R1 6 MODE CS 15 7 VTTREF V5IN 14 5V_IN R2 8 COMP PGOOD 13 9 VDDQSNS S5 12 PGOOD S5 10 VDDQSET S3 11 S3 C2 Ceramic 4.7 µF UDG−04058 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA PLASTIC HTTSOP PowerPAD (PWP) (1) -40°C to 85°C TPS51116PWP The PWP package is also available taped and reeled. Add an R suffix to the device type (TPS51116PWPR) ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range unless otherwise noted TPS51116 VIN Input voltage range VBST -0.3 to 36 VBST wrt LL -0.3 to 6 CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET -0.3 to 6 V PGND, VTTGND -0.3 to 0.3 DRVH -1.0 to 36 LL -1.0 to 30 VOUT Output voltage range TA Operating ambient temperature range -40 to 85 Tstg Storage temperature -55 to 150 COMP, DRVL, PGOOD, VTT, VTTREF (1) UNITS V -0.3 to 6 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. DISSIPATION RATINGS PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING 20-pin PWP 2.53 W 25.3 mW/°C 1.01 W RECOMMENDED OPERATING CONDITIONS Supply voltage, V5IN Voltage range Operating free-air temperature, TA 2 MIN MAX UNIT V 4.75 5.25 VBST, DRVH -0.1 34 LL -0.6 28 VLDOIN, VTT, VTTSNS, VDDQSNS -0.1 3.6 VTTREF -0.1 1.8 PGND, VTTGND -0.1 0.1 S3, S5, MODE, VDDQSET, CS, COMP, PGOOD, DRVL -0.1 5.25 -40 85 V °C TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IV5IN1 Supply current 1, V5IN TA = 25°C, No load, VS3 = VS5 = 5 V, COMP connected to capacitor 0.8 2 IV5IN2 Supply current 2, V5IN TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, COMP connected to capacitor 300 600 IV5IN3 Supply current 3, V5IN TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, VCOMP = 5 V 240 500 IV5INSDN Shutdown current, V5IN TA = 25°C, No load, VS3 = VS5 = 0 V 0.1 1.0 IVLDOIN1 Supply current 1, VLDOIN TA = 25°C, No load, VS3 = VS5 = 5 V 1 10 IVLDOIN2 Supply current 2, VLDOIN TA = 25°C, No load, VS3 = 5 V, VS5 = 0 V, 0.1 10 IVLDOINSDN Standby current, VLDOIN TA = 25°C, No load, VS3 = VS5 = 0 V 0.1 1.0 mA µA VTTREF OUTPUT VVTTREF VVTTREFTOL Output voltage, VTTREF Output voltage tolerance VVDDQSNS/2 V -10 mA < IVTTREF < 10 mA, VVDDQSNS = 2.5 V, Tolerance to VVDDQSNS/2 -20 20 -10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.8 V, Tolerance to VVDDQSNS/2 -18 18 -20 -40 -80 20 40 80 VVTTREFSRC Source current VVDDQSNS = 2.5 V, VVTTREF = 0 V VVTTREFSNK Sink current VVDDQSNS = 2.5 V, VVTTREF = 2.5 V mV mA VTT OUTPUT VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V 1.25 VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V 0.9 VVTTSNS Output voltage, VTT VVTTTOL25 VS3 = VS5 = 5 V, IVTT = 0 A VTT output voltage tolerance VS3 = VS5 = 5 V, |IVTT| = 0 A < 1.5 A to VTTREF VS3 = VS5 = 5 V, |IVTT| = 0 A < 3 A VS3 = VS5 = 5 V, IVTT = 0 A VVTTTOL18 IVTTTOCLSRC VTT output voltage tolerance VS3 = VS5 = 5 V, |IVTT| = 0 A < 1 A to VTTREF VS3 = VS5 = 5 V, |IVTT| = 0 A < 2 A Source current limit, VTT V -20 20 -30 30 -40 40 -20 20 -30 30 -40 40 VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.19 V, PGOOD = HI 3.0 3.8 6.0 VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V 1.5 2.2 3.0 VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.31 V, PGOOD = HI 3.0 3.6 6.0 2.2 3.0 IVTTTOCLSNK Sink current limit, VTT VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ 1.5 IVTTLK Leakage current, VTT VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 -10 IVTTBIAS Input bias current, VTTSNS VS3 = 5 V, VVTTSNS = VVDDQSNS /2 -1 IVTTSNSLK Leakage current, VTTSNS VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 -1 IVTTDisch Discharge current, VTT TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V, VVTT = 0.5 V 10 17 TA = 25°C, VVDDQSET = 0 V, No load 2.465 2.500 2.535 0°C ≤ TA≤ 85°C, VVDDQSET = 0 V, No load (1) 2.457 2.500 2.543 mV A 10 -0.1 1 µA 1 mA VDDQ OUTPUT -40°C ≤ TA≤ 85°C, VVDDQSET = 0 V, No load VVDDQ Output voltage, VDDQ (1) 2.440 2.500 2.550 TA = 25°C, VVDDQSET = 5 V, No load (1) 1.776 1.800 1.824 0°C ≤ TA≤ 85°C, VVDDQSET = 5V, No load (1) 1.769 1.800 1.831 -40°C ≤ TA≤ 85°C, VVDDQSET = 5V, No load (1) 1.764 1.800 1.836 -40°C ≤ TA≤ 85°C, Adjustable mode, No load (1) (1) 1.5 V 3.0 Ensured by design. Not production tested. 3 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C, Adjustable mode VVDDQSET VDDQSET regulation voltage 0°C ≤ TA≤ 85°C, Adjustable mode -40°C ≤ TA≤ 85°C, Adjustable mode RVDDQSNS MIN TYP MAX 742.5 750.0 757.5 740.2 750.0 759.8 738.0 750.0 762.0 VVDDQSET = 0 V 215 Input impedance, VDDQSNS VVDDQSET = 5 V 180 Adjustable mode UNIT mV kΩ 460 VVDDQSET = 0.78 V, COMP = Open -0.04 VVDDQSET = 0.78 V, COMP = 5 V -0.06 IVDDQSET Input current, VDDQSET IVDDQDisch Discharge current, VDDQ VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, VMODE = 0 V IVDDOINDisch Discharge current, VLDOIN VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, VMODE = 0.5 V 10 µA 40 mA 700 TRANSCONDUCTANCE AMPLIFIER gm Gain TA = 25°C 240 300 360 ICOMPSNK COMP maximum sink current VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCOMP = 1.28 V 13 ICOMPSRC COMP maximum source cur- VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, rent VVDDQSNS = 2.3 V, VCOMP = 1.28 V -13 VCOMPHI COMP high clamp voltage VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCS = 0 V 1.31 1.34 1.37 VCOMPLO COMP low clamp voltage VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCS = 0 V 1.18 1.21 1.24 µS µA V DUTY CONTROL TON Operating on-time VIN = 12 V, VVDDQSET = 0 V 520 TON0 Startup on-time VIN = 12 V, VVDDQSNS = 0 V 125 (2) TON(min) Minimum on-time TA = 25°C TOFF(min) Minimum off-time TA = 25°C (2) ns 100 350 OUTPUT DRIVERS RDRVH RDRVL TD DRVH resistance DRVL resistance Dead time Source, IDRVH = -100 mA Sink, IDRVH = 100 mA Source, IDRVL = -100 mA Sink, IDRVL = 100 mA LL-low to DRVL-on (2) 3 6 0.9 3 3 6 0.9 3 10 DRVL-off to DRVH-on (2) Ω ns 20 INTERNAL BST DIODE VFBST IVBSTLK (2) 4 Forward voltage VV5IN-VBST , IF = 10 mA, TA = 25°C VBST leakage current VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V, TA = 25°C Ensured by design. Not production tested. 0.7 0.8 0.9 V 0.1 1.0 µA TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VPGND-CS , PGOOD = HI, VCS < 0.5 V 50 60 70 VPGND-CS , PGOOD = LO, VCS < 0.5 V 20 30 40 TA = 25°C, VCS > 4.5 V, PGOOD = HI 9 10 11 TA = 25°C, VCS > 4.5 V, PGOOD = LO 4 5 6 UNIT PROTECTIONS VOCL Current limit threshold ITRIP Current sense sink current TCITRIP TRIP current temperature co- RDS(on) sense scheme, On the basis efficient of TA = 25°C (3) VOCL(off) Overcurrent protection COMP offset VR(trip) Current limit threshold setting VV5IN-CS (3) range (VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV, VCS > 4.5 V 4500 -5 0 mV µA ppm/°C 5 mV 30 150 POWERGOOD COMPARATOR VTVDDQPG VDDQ powergood threshold PG in from lower 93% 95% 97% PG in from higher 103% 105% 107% PG hysteresis 5% IPG(max) PGOOD sink current VVTT = 0 V, VPGOOD = 0.5 V 2.5 7.5 TPG(del) PGOOD delay time Delay for PG in 80 130 200 mA Wake up 3.7 4.0 4.3 Hysteresis 0.2 0.3 0.4 No discharge 4.7 µs UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD VUVV5IN VTHMODE V5IN UVLO threshold voltage MODE threshold Non-tracking discharge 0.1 2.5 V output 0.08 0.15 0.25 1.8 V output 3.5 4.0 4.5 2.2 VTHVDDQSET VDDQSET threshold voltage VIH High-level input voltage S3, S5 VIL Low-level input voltage S3, S5 VIHYST Hysteresis voltage S3, S5 VINLEAK Logic input leakage current S3, S5, MODE -1 1 VINVDDQSET Input leakage/ bias current VDDQSET -1 1 V 0.3 0.2 µA UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP VDDQ OVP trip threshold voltage TOVPDEL VDDQ OVP propagation delay (3) VUVP Output UVP trip threshold TUVPDEL Output UVP propagation delay (3) TUVPEN Output UVP enable delay (3) OVP detect Hysteresis 110% 115% 120% 5% 1.5 UVP detect 70% Hysteresis 10% 32 µs cycle 1007 THERMAL SHUTDOWN TSDN (3) Thermal SDN threshold (3) Shutdown temperature Hysteresis 160 10 °C Ensured by design. Not production tested. 5 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 DEVICE INFORMATION PWP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 VLDOIN VTT VTTGND VTTSNS GND MODE VTTREF COMP VDDQSNS VDDQSET 20 19 18 17 16 15 14 13 12 11 VBST DRVH LL DRVL PGND CS V5IN PGOOD S5 S3 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. COMP 8 I/O Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable gm amplifier and use D-CAP™ mode. CS 15 I/O Current sense comparator input (-) for resistor current sense scheme. Or over current trip voltage setting input for RDS(on) current sense scheme if connected to V5IN through the voltage setting resistor. DRVH 19 O Switching (top) MOSFET gate drive output. DRVL 17 O Rectifying (bottom) MOSFET gate drive output. GND 5 - Signal ground. Connect to minus terminal of the VTT LDO output capacitor. LL 18 I/O Switching (top) MOSFET gate driver return. Current sense comparator input (-) for RDS(on) current sense. MODE 6 I Discharge mode setting pin. See VDDQ and VTT Discharge Control section. PGND 16 - Ground for rectifying (bottom) MOSFET gate driver. Also current sense comparator input (+). PGOOD 13 O Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the target range. S3 11 I S3 signal input. S5 12 I S5 signal input. V5IN 14 I 5-V power supply input for internal circuits. VBST 20 I/O VDDQSET 10 I VDDQSNS 9 I/O VLDOIN 1 I Power supply for the VTT LDO. VTT 2 O Power output for the VTT LDO. VTTGND 3 - Power ground output for the VTT LDO. VTTREF 7 O VTTREF buffered reference output. VTTSNS 4 I Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor. 6 Switching (top) MOSFET driver bootstrap voltage input. VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section. VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for VDDQ output if VDDQSET pin is connected to V5IN or GND. TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 FUNCTIONAL BLOCK DIAGRAM 7 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 DETAILED DESCRIPTION The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a 10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin HTSSOP package. Each of these rails generates VDDQ, VTTREF and VTT that required with DDR/DDR2 memory systems. The switch mode power supply (SMPS) portion employs external N-channel MOSFETs to support high current for DDR/DDR2 memory’s VDD/VDDQ. The output voltage is preset and selectable from 2.5 V or 1.8 V. User defined output voltage is also possible and can be adjustable from 1.5 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS runs an adaptive on-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiency down to several mA. Current sensing scheme uses either RDS(on) of the external rectifying MOSFET for a low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying MOSFET for more accurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate one-half VDDQ for the 10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT LDO can source and sink up to 3-A peak current with only 20-µF (two 10 µF in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2 within ±20 mV. VTT output tracks VTTREF within ±20 mV at no load condition while ±40 mV at full load. The LDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin. This helps reducing power dissipation in sourcing phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2 specifications at S3/S5 sleep state (see Table 2). The part has two options of output discharge function when both VTT and VDDQ are disabled. The tracking discharge mode discharges VDDQ and VTT outputs through the internal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking discharge mode discharges outputs using internal discharge MOSFETs which are connected to VDDQSNS and VTT. The current capability of these discharge FETs are limited and discharge occurs more slowly than the tracking discharge. These discharge functions can be disabled by selecting non-discharge mode. VDDQ SMPS, Dual PWM Operation Modes The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ mode uses internal compensation circuit and is suitable for low external component count configuration with an appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as ceramic or specialty polymer capacitors. These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN, TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage is monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section). At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by VIN and VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (see PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedback information indicates insufficient output voltage and inductor current information indicates below the over current limit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current. In the current mode control scheme, the transconductance amplifier generates a target current level corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and when the inductor current signal comes lower than the target current level, the comparator provides SET signal to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support various types of output MOSFETs and capacitors. In the D-CAP™ mode, the transconductance amplifier is disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides SET signal to initiate the next ON state. 8 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 DETAILED DESCRIPTION (continued) VDDQ SMPS, Light Load Condition TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of VOUTripple or load regulation. Detail operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1: (V V OUT) V OUT 1 I OUT(LL) IN 2Lf V IN (1) where • f is the PWM switching frequency (400 kHz) Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is 40 kHz at IOUT(LL)/10 and 4 kHz at IOUT(LL)/100. Low-Side Driver The low-side driver is designed to drive high-current, low-RDS(on), N-channel MOSFET(s). The drive capability is represented by its internal resistance, which are 3 Ω for V5IN to DRVL and 0.9 Ω for DRVL to PGND. A dead-time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average drive current is equal to the gate charge at VGS = 5 V times switching frequency. This gate drive current as well as the high-side gate drive current times 5 V makes the driving power which needs to be dissipated from TPS51116 package. High-Side Driver The high-side driver is designed to drive high-current, low-RDS(on) N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBST and LL pins. The drive capability is represented by its internal resistance, which are 3 Ω for VBST to DRVH and 0.9 Ω for DRVH to LL. Current Sensing Scheme In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor sensing and MOSFET RDS(on) sensing. For resistor sensing scheme, an appropriate current sensing resistor should be connected between the source terminal of the bottom MOSFET and PGND. CS pin is connected to the MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin. For RDS(on) sensing scheme, CS pin should be connected to V5IN through the trip voltage setting resistor, RTRIP. In this scheme, CS terminal sinks 10-µA ITRIP current and the trip level is set to the voltage across the RTRIP. The inductor current is monitored by the voltage between PGND pin and LL pin so that LL pin should be connected to the drain terminal of the bottom MOSFET. ITRIP has 4500ppm/°C temperature slope to compensate the temperature dependency of the RDS(on). In either scheme, PGND is used as the positive current sensing node so that PGND should be connected to the proper current sensing device, i.e. the sense resistor or the source terminal of the bottom MOSFET. 9 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 DETAILED DESCRIPTION (continued) PWM Frequency and Adaptive On-Time Control TPS51116 employs adaptive on-time control scheme and does not have a dedicated oscillator on board. However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio is kept as VOUT/VIN technically with the same cycle time. Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output becomes 750 mV or larger. VDDQ Output Voltage Selection TPS51116 can be used for both of DDR (VVDDQ = 2.5 V) and DDR2 (VVDDQ = 1.8 V) power supply and adjustable output voltage (1.5 V < VVDDQ < 3 V) by connecting VDDQSET pin as shown in Table 1. Table 1. VDDQSET and Output Voltages VDDQSET VDDQ (V) VTTREF and VTT GND 2.5 VVDDQSNS/2 NOTE DDR V5IN 1.8 VVDDQSNS/2 DDR2 FB Resistors Adjustable VVDDQSNS/2 1.5 V < VVDDQ < 3 V VTT Linear Regulator and VTTREF TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to keep tracking the VTTREF within ±40 mV at all conditions including fast load transient. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 µF. It is recommended to attach two 10-µF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output capacitor is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input to achieve loop stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-µF ceramic capacitor for stable operation. Outputs Management by S3, S5 Control In the DDR/DDR2 memory applications, it is important to keep VDDQ always higher than VTT/VTTREF including both start-up and shutdown. TPS51116 provides this management by simply connecting both S3 and S5 terminals to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All of VDDQ, VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and VTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT output is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the three outputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin (see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2) Table 2. S3 and S5 Control 10 STATE S3 S5 VDDQ VTTREF S0 HI HI On On VTT On S3 LO HI On On Off (Hi-Z) S4/S5 LO LO Off (Discharge) Off (Discharge) Off (Discharge) TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 DETAILED DESCRIPTION (continued) Soft-Start and Powergood The soft start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. At the starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent threshold is set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target, the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85 µs. The overcurrent threshold is released to nominal value at the end of this period. The powergood signal waits another 45 µs after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of the target voltage), then turns off powergood open-drain MOSFET. The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changed in two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergood threshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with low and constant current that gives linear ramp up of the output. When the output comes up to the good state, the overcurrent limit level is released to normal value (3.8 A). TPS51116 has an independent counter for each output, but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT powergood externally. See Figure 1. 100% 87% 80% VVDDQ VOCL VPGOOD VS5 85 µs 45 µs UDG−04066 Figure 1. VDDQ Soft-Start and Powergood Timing Soft-start duration, TVDDQSS, TVTTSS are functions of output capacitances. 2 C VDDQ V VDDQ 0.8 T VDDQSS 85 s I VDDQOCP (2) where IVDDQOCP is the current limit value for VDDQ switcher calculated by Equation 5. C VVTT T VTTSS VTT I VTTOCL (3) where, IVTTOCL = 2.2 A (typ). In each of the two previous calculations, no load current during start-up are assumed. Note that both switchers and the LDO do not start up with full load condition. VDDQ and VTT Discharge Control TPS51116 discharges VDDQ, VTTREF and VTT outputs during S3 and S5 are both low. There are two different discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3. 11 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 DETAILED DESCRIPTION (continued) Table 3. Discharge Selection MODE DISCHARGE MODE V5IN No discharge VDDQ Tracking discharge S4/GND Non-tracking discharge When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistors and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can handle up to 3 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off and the operation mode is changed to the non-tracking-discharge mode. When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which are connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly. Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In case of non-tracking mode, TPS51116 does not discharge output charge at all. Current Protection for VDDQ The SMPS has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller keeps the OFF state during the inductor current is larger than the over current trip level. The trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme section). For resistor sensing scheme, the trip level, VTRIP, is fixed value of 60 mV. For RDS(on) sensing scheme, CS terminal sinks 10 µA and the trip level is set to the voltage across this RTRIP resistor. V TRIP (mV) RTRIP (k) 10 (A) (4) As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load current at over current threshold, IOCP, can be calculated as shown in Equation 5. V IN V OUT V OUT V I V 1 I OCP TRIP RIPPLE TRIP 2 RDS(on) R DS(on) 2 L f V IN (5) In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. If the output voltage becomes less than Powergood level, the VTRIP is cut into half and the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and shutdown. Current Protection for VTT The LDO has an internally fixed constant over current limiting of 3.8 A while operating at normal condition. This trip point is reduced to 2.2 A before the output voltage comes within ±5% of the target voltage or goes outside of ±10% of the target voltage. Overvoltage and Undervoltage Protection for VDDQ TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON. Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off the top MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116 latches OFF both top and bottom MOSFETs. This function is enabled after 1007 cycles of SMPS operation to ensure startup. 12 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 DETAILED DESCRIPTION (continued) V5IN Undervoltage Lockout (UVLO) Protection TPS51116 has V5IN undervoltage lock out protection (UVLO). When the V5IN voltage is lower than UVLO threshold voltage, SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection. V5IN Input Capacitor Add a ceramic capacitor with a value between 1.0 µF and 4.7 µF placed close to the V5IN pin to stabilize 5 V from any parasitic impedance from the supply. Thermal Shutdown TPS51116 monitors the temperature of itself. If the temperature exceeds the threshold value, 160°C (typ), SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection and the operation is resumed when the device is cooled down by about 10°C. 13 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION Loop Compensation and External Parts Selection Current Mode Operation A buck converter using TPS51116 current mode operation can be partitioned into three portions, a voltage divider, an error amplifier and a switching modulator. By linearizing the switching modulator, we can derive the transfer function of the whole system. Since current mode scheme directly controls the inductor current, the modulator can be linearized as shown in Figure 2. Figure 2. Linearizing the Modulator Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal model. As a result, a modulated current source including the power inductor can be modeled as a current source with its transconductance of 1/RS and the output capacitor represent the modulator portion. This simplified model is applicable in the frequency space up to approximately a half of the switching frequency. One note is, although the inductance has no influence to small signal model, it has influence to the large signal model as it limits slew rate of the current source. This means the buck converter’s load transient response, one of the large signal behaviors, can be improved by using smaller inductance without affecting the loop stability. Total open loop transfer function of the whole system is given by Equation 6. H(s) H 1(s) H 2(s) H 3(s) (6) Assuming RL>>ESR, RO>>RC and CC>>CC2, each transfer function of the three blocks is shown starting with Equation 7. R2 H 1(s) (R2 R1) (7) H 2(s) gm H 3(s) R O 1 s CC RC 1 s C C R O 1 s C C2 R C (1 s CO ESR) 1 s C O RL RL RS There are three poles and two zeros in H(s). Each pole and zero is given by the following five equations. 14 (8) (9) TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) P1 1 CC RO (10) 1 P2 CO RL (11) 1 P3 CC2 RC (12) Z1 Z2 1 CC RC (13) 1 CO ESR (14) Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f0. However, the f0 should be kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f0 is given by Equation 15. gm RC gm R C R1 f0 1 1 0.75 2 R1 R2 C O RS 2 VOUT C O R S (15) Based on small signal analysis above, the external components can be selected by following manner. 1. Choose the inductor. The inductance value should be determined to give the ripple current of approximately 1/4 to 1/3 of maximum output current. L 1 I IND(ripple) f VIN(max) VOUT VOUT VIN(max) 3 I OUT(max) f V IN(max) V OUT V OUT V IN(max) (16) The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as shown in Equation 17. I IND(peak) VIN(max) VOUT V OUT V TRIP 1 RDS(on) L f VIN(max) (17) 2. Choose rectifying (bottom) MOSFET. When RDS(on) sensing scheme is selected, the rectifying MOSFET’s on-resistance is used as this RS so that lower RDS(on) does not always promise better performance. In order to clearly detect inductor current, minimum RS recommended is to give 15 mV or larger ripple voltage with the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side of the RDS(on) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency more at high-load conditions. When using external resistor current sensing, there is no restriction for low RDS(on). However, the current sensing resistance RS itself affects the efficiency 3. Choose output capacitor(s). In cases of organic semiconductor capacitors (OS-CON) or specialty polymer capacitors (SP-CAP), ESR to achieve required ripple value at stable state or transient load conditions determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. The peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESR times the load current step for a fast transient load response. In case of ceramic capacitor(s), usually ESR is small enough to meet ripple requirement. On the other hand, transient undershoot and overshoot driven by output capacitance becomes the key factor to determine the capacitor(s). 4. Determine f0 and calculate RC using Equation 18. Note that higher RC shows faster transient response in cost of unstableness. If the transient response is not enough even with high RC value, try increasing the out put capacitance. Recommended f0 is fOSC/4. Then RC can be derived by Equation 19. 15 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) V OUT CO gm RS 0.75 R C 2.8 V OUT C O [F] R S [m] R C 2 f 0 (18) (19) 5. Calculate CC2. Purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. In case of ceramic capacitor(s) is used, no need for CC2. 1 1 z2 p3 CO ESR C C2 RC (20) C C2 CO ESR RC (21) 6. Calculate CC. The purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it causes phase delay, another zero to cancel this effect at f0 frequency is need. This zero, ωz1, is determined by Cc and Rc. Recommended ωz1 is 10 times lower to the f0 frequency. f 1 f z1 0 10 2 C C R C (22) 7. When using adjustable mode, determine the value of R1 and R2. Recommended R2 value is from 100 kΩ to 300 kΩ. Determine R1 using Equation 23. V 0.75 R1 OUT R2 0.75 (23) D-CAP™ Mode Operation A buck converter system using D-CAP™ Mode can be simplified as below. Figure 3. Linearizing the Modulator The VDDQSNS voltage is compare with internal reference voltage after divider resistors. The PWM comparator determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency. 16 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) f0 f 1 SW 3 2 ESR CO (24) As f0 is determined solely by the output capacitor’s characteristics, loop stability of D-CAP™ mode is determined by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have CO in the order of several 100 µF and ESR in range of 10 mΩ. These makes f0 in the order of 100 kHz or less and the loop is then stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode. Although D-CAP™ mode provides many advantages such as ease-of-use, minimum external components configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient amount of feedback signal needs to be provided by external circuit to reduce jitter level. The required signal level is approximately 15 mV at comparing point. This gives VRIPPLE = (VOUT/0.75) x 15 (mV) at the output node. The output capacitor’s ESR should meet this requirement. The external components selection is much simple in D-CAP™ mode. 1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the Current Mode Operation section. 2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in Equation 25. V 0.015 ESR OUT VOUT 60 [m] I RIPPLE 0.75 I OUT(max) (25) Thermal Design Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and sink directions generate power dissipation from the part. In the source phase, potential difference between VLDOIN and VTT times VTT current becomes the power dissipation, WDSRC. W DSRC VVLDOIN VVTT I VTT (26) In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be decreased. For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, WDSNK, is calculated by Equation 27: W DSNK VVTT I VTT (27) Since this device does not sink AND source the current at the same time and IVTT varies rapidly with time, actual power dissipation need to be considered for thermal design is an average of above value. Another power consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN supply can be estimated as 1.5 mA or less at normal operational conditions. These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the package is calculated by Equation 28, T J(max) T A(max) W PKG JA (28) where • TJ(max) is 125°C • TA(max) is the maximum ambient temperature in the system • θJA is the thermal resistance from the silicon junction to the ambient 17 TPS51116 SLUS609A – MAY 2004 – REVISED JUNE 2004 www.ti.com APPLICATION INFORMATION (continued) This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhanced PowerPAD™ package that has exposed die pad underneath the body. For improved thermal performance, this die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat sink/spread. The typical thermal resistance, 39.6°C/W, is achieved based on a 6.5 mm × 3.4 mm thermal land with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number. Further information about PowerPAD™ and its recommended board layout is described in (SLMA002). This document is available at <www.ti.com>. Layout Considerations Certain points must be considered before designing a layout using the TPS51116. • PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFET and high-voltage side of the inductor, should be as short and wide as possible. • Consider adding a small snubber circuit, consists of 3 Ω and 1 nF, between LL and PGND in case a high-frequency surge is observed on the LL voltage waveform. • All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltage switching nodes such as LL, DRVL or DRVH nodes to avoid coupling. • VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wide connection. • The output capacitor for VTT should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL of the trace. • VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and the output capacitor(s). • Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 mΩ. • VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines. • Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding common impedance to the high current path of the VTT source/sink current. • GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point. • In order to effectively remove heat from the package, prepare thermal land and solder to the package’s thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading. Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath the package. 18 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) Figure 4. D-CAP™ Mode Table 4. D-CAP™ Mode Schematic Components SYMBOL SPECIFICATION MANUFACTURER R1 5.1 kΩ - PART NUMBER R2 100 kΩ - R3 (100 ×VVDDQ - 75) kΩ - R4 75 kΩ - M1 30 V, 13 mΩ International Rectifier IRF7821 M2 30 V, 5 mΩ International Rectifier IRF7832 19 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 Figure 5. Current Mode Table 5. Current Mode 20 SYMBOL SPECIFICATION MANUFACTURER PART NUMBER R0 6 mΩ, 1% Vishay WSL-2521 0.006 R2 100 kΩ - - M0 30 V, 13 mΩ International Rectifier IRF7821 M1 30 V, 5 mΩ International Rectifier IRF7832 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS V5IN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 2.0 1.0 1.8 0.9 IV5IN1 − V5IN Shutdown Current − µA IV5IN1 − V5IN Supply Current − mA V5IN SUPPLY CURRENT vs JUNCTION TEMPERATURE 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.2 0 −50 0 50 100 0 −50 150 TJ − Junction Temperature − °C 50 100 Figure 6. Figure 7. V5IN SUPPLY CURRENT vs LOAD CURRENT VLDOIN SUPPLY CURRENT vs TEMPERATURE 10 150 1.0 DDR2 VVTT = 0.9 V 0.9 IVLDOIN − VLDOIN Supply Current − µA 9 IV5IN − V5IN Supply Current − mA 0 TJ − Junction Temperature − °C 8 7 6 5 4 3 2 1 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 −2 −1 0 1 2 0 −50 0 50 100 IVTT − VTT Current − A TJ − Junction Temperature − °C Figure 8. Figure 9. 150 21 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) CS CURRENT vs JUNCTION TEMPERATURE VDDQ DISCHARGE CURRENT vs JUNCTION TEMPERATURE 16 14 PGOOD = HI ITRIP − CS Current − µA 12 10 8 6 PGOOD = LO 4 IDISCH − VDDQ Discharge Current − mA 80 2 0 −50 40 30 20 10 −50 Figure 10. Figure 11. VTT DISCHARGE CURRENT vs JUNCTION TEMPERATURE OVERVOLTAGE AND UNDERVOLTAGE THRESHOLD vs JUNCTION TEMPERATURE 100 150 150 140 VTRIP − OVP/UVP Trip Threshold − % IDISCH − VTT Discharge Current − mA 50 0 50 100 TJ − Junction Temperature − °C 50 25 20 15 0 50 100 TJ − Junction Temperature − °C Figure 12. 22 60 TJ − Junction Temperature − °C 0 30 10 −50 70 150 120 VOVP 100 80 VUVP 60 −50 0 50 100 TJ − Junction Temperature − °C Figure 13. 150 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs INPUT VOLTAGE SWITCHING FREQUENCY vs OUTPUT CURRENT 430 450 D-CAP Mode IVDDQ = 7 A DDR2 400 fSW − Switching Frequency − kHz fSW − Switching Frequency − kHz 420 410 400 DDR2 390 DDR 380 350 DDR 300 250 200 150 100 50 370 D−CAP Mode VIN = 12 V 0 4 8 12 16 20 24 28 0 Figure 15. VDDQ OUTPUT VOLTAGE vs OUTPUT CURRENT (DDR) VDDQ OUTPUT VOLTAGE vs INPUT VOLTAGE (DDR2) 1.820 1.820 1.815 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 2 4 6 8 IVDDQ − VDDQ Output Current − A Figure 16. 10 D−CAP Mode 1.810 IVDDQ = 0 A 1.805 1.800 1.795 IVDDQ = 10 A 1.790 1.785 D−CAP Mode VIN = 12 V 0 2 4 6 8 IVDDQ − VDDQ Output Current − A Figure 14. VVDDQ − VDDQ Output Voltage − V VVDDQ − VDDQ Output Voltage − V VIN − Input Voltage − V 1.780 10 4 8 12 16 20 24 30 VIN − Input Voltage − V Figure 17. 23 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) VTT OUTPUT VOLTAGE vs OUTPUT CURRENT (DDR) VTT OUTPUT VOLTAGE vs OUTPUT CURRENT (DDR2) 0.94 1.30 0.93 1.28 VVTT − VTT Output Voltage − V VVTT − VTT Output Voltage − V 1.29 1.27 1.26 VVLDOIN = 2.5 V 1.25 1.24 1.23 0.92 0.91 VVLDOIN = 1.8 V 0.90 0.89 VVLDOIN = 1.5 V 0.88 1.22 0.86 1.20 −5 −4 −3 −2 −1 0 1 2 3 IVTT − VTT Output Current − A 4 −3 5 VTTREF OUTPUT VOLTAGE vs OUTPUT CURRENT (DDR) VTTREF OUTPUT VOLTAGE vs OUTPUT CURRENT (DDR2) 0.904 1.251 2 3 DDR2 0.903 VVTTREF − VTTREF Voltage − V VVTTREF − VTTREF Voltage − V −1 0 1 IVTT − VTT Output Current − A Figure 19. DDR 1.250 1.249 1.248 1.247 1.246 1.245 1.244 −10 −2 Figure 18. 1.252 0.902 0.901 0.900 0.899 0.898 0.897 −5 0 5 IVTTREF − VTTREF Current − A Figure 20. 24 VVLDOIN = 1.2 V 0.87 VVLDOIN = 1.8 V 1.21 10 0.896 −10 −5 0 5 IVTTREF − VTTREF Current − A Figure 21. 10 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) VDDQ EFFICIENCY (DDR) vs VDDQ CURRENT VDDQ EFFICIENCY (DDR2) vs VDDQ CURRENT 100 100 VVDDQ = 2.5 V VIN = 8 V VVDDQ = 1.8 V 90 90 VIN = 12 V Efficiency − % Efficiency − % VIN = 8 V 80 VIN = 20 V 70 80 VIN = 12 V VIN = 20 V 70 60 60 50 0.001 0.01 0.1 1 IVDDQ − VDDQ Current − A 10 Figure 22. 50 0.001 0.01 0.1 IVDDQ − VDDQ Current − A 1 10 Figure 23. VVDDQ (50 mV/div) VVDDQ (50 mV/div) IVDDQ (2 A/div) IIND (5 A/div) VVTTREF (10 mV/div) VVTT (10 mV/div) IVDDQ (5 A/div) t − Time − 2 µs/div Figure 24. Ripple Waveforms - Heavy Load Condition t − Time − 20 µs/div Figure 25. VDDQ Load Transient Response 25 TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) VVDDQ (50 mV/div) VVTT (20 mV/div) S5 VDDQ VVTTREF (20 mV/div) VTTREF IVTT (2 A/div) PGOOD IVDDQ = IVTTREF = 0 A t − Time − 100 µs/div t − Time − 20 µs/div Figure 26. VTT Load Transient Response Figure 27. VDDQ, VTT, and VTTREF Start-Up Waveforms VDDQ VDDQ VTTREF VTTREF VTT VTT S5 S5 IVDDQ = IVTT = IVTTREF = 0 A t − Time − 200 µs/div Figure 28. Soft-Start Waveforms Tracking Discharge 26 IVDDQ = IVTT = IVTTREF = 0 A t − Time − 1 ms/div Figure 29. Soft-Stop Waveforms Non-Tracking Discharge TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) VDDQ BODE PLOT (CURRENT MODE) GAIN AND PHASE vs FREQUENCY VTT BODE PLOT, SOURCE (DDR2) GAIN AND PHASE vs FREQUENCY 180 80 135 60 40 90 40 90 20 45 20 45 0 0 0 0 60 180 Phase Gain Gain − dB Phase − 135 −45 −45 −20 −40 −90 −40 −90 −60 −135 −60 −135 −20 Gain IVDDQ = 7 A −180 10 M 1M 100 k −80 10 k IVTT = −1 A 1M 100 k f − Frequency − Hz −180 10 M f − Frequency − Hz Figure 30. Figure 31. VTT BODE PLOT, SINK (DDR2) GAIN AND PHASE vs FREQUENCY 80 180 60 135 40 Phase 20 90 45 0 Gain 0 −20 −45 −40 −90 Phase − ° −80 10 k Gain − dB ITRIP − CS Current − µA Phase Phase − 80 −135 −60 IVTT = 1 A −80 10 k 100 k 1M −180 10 M f − Frequency − Hz Figure 32. 27 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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