RT8036 One Step Down DC/DC Converter and Four Linear Regulators with Individual On/Off Control General Description Features The RT8036 is an integrated power management unit which integrates one 600mA high efficiency step down DC/DC converter and four low dropout voltage regulators with 300mA current capability for each regulator. z The RT8036 is optimized for sub block power requirement solution. The individual on/off control for each device can provide flexibility for different power on sequence. Four linear regulators provide high PSRR output and are suitable for both analog and digital power. The RT8036 is available in the WQFN-20L 3x3 package that is suitable for portable device. z z z z Four Low Noise LDOs for Up to 300mA One High Efficiency Synchronous Buck Up to 600mA Output Individual On/Off Control for Each Output Small 20-Lead WQFN Package RoHS Compliant and Halogen Free Applications z z Smart Handheld device Cellular phone Pin Configurations (TOP VIEW) Package Type QW : WQFN-20L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Output Voltage : A : Buck : 1V LDO1/2/3/4 : 1V/2.6V/3V/3.3V B : Buck : 1.2V LDO1/2/3/4 : 1.8V/2.8V/2.8V/2.8V C : Buck : 1.3V LDO1/2/3/4 : 1.8V/2.8V/2.8V/2.8V D : Buck : 1.3V LDO1/2/3/4 : 1.8V/2.8V/2.8V/3.0V E : Buck : 1.3V LDO1/2/3/4 : 1.8V/2.8V/2.8V/3.3V Note : Richtek products are : ` 20 19 18 17 16 VINL1 ENL1 ENL2 VINB LX 1 15 2 14 GND 3 4 21 5 13 12 11 6 7 8 VOUTL3 VOUTL4 AGND ENL4 ENL3 9 10 PGND ENB PGND VOUTB PGND RT8036 VOUTL2 VOUTL1 NC AGND VINL2 Ordering Information WQFN-20L 3x3 Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. DS8036-02 April 2011 www.richtek.com 1 RT8036 Typical Application Circuit VINB VINL1 VINL2 Chip Enable 4 VINB CINB 4.7µF RT8036 LX 5 VINL1 VOUTB 9 VOUTL1 19 VINL2 VOUTL2 ENL1 ENL2 ENL3 ENL4 ENB 13, 17 AGND VOUTL3 1 CINL1 1µF 16 CINL2 1µF 2 3 11 12 7 L 2.2µH COUTB 10µF COUTL1 1µF 20 COUTL2 1µF 15 COUTL3 1µF VOUTL4 14 COUTL4 1µF PGND 6, 8, 10 VOUTB VOUT1 VOUT2 VOUT3 VOUT4 Functional Pin Description Pin No. Pin Name Pin Function 1 VINL1 Supply Input for LDO1 and LDO2. 2 ENL1 Chip Enable for LDO1 (Active High). 3 ENL2 Chip Enable for LDO2 (Active High). 4 VINB Supply Input for Buck Converter. 5 LX Power Switching Output. PGND Power Ground. 7 ENB Chip Enable for Buck Converter (Active High). 9 VOUTB Feedback Input of Buck Converter. 11 ENL3 Chip Enable for LDO3 (Active High). 12 ENL4 Chip Enable for LDO4 (Active High). 13, 17 AGND Analog Ground. 14 VOUTL4 LDO4 Output. 15 VOUTL3 LDO3 Output. 16 VINL2 Supply Input for LDO3 and LDO4. 18 NC No Internal Connection. 19 VOUTL1 LDO1 Output. 20 VOUTL2 LDO2 Output. 6, 8, 10 21 (Exposed Pad) GND www.richtek.com 2 Ground. The exposed pad must be soldered to a large PCB and connected to AGND for maximum power dissipation. DS8036-02 April 2011 RT8036 Function Block Diagram VINB ENB OSC & Shutdown Control Slope Compensation VOUTB R S1 Current Sense Control Logic EA RC V REF Current Limit Detector Driver LX PWM Comparator Mux COMP Current Source Controller UVLO &Power Good Detector ENL1 EA R S2 PGND Shutdown and Logic Control V REF Current Detector MOS Driver VINL1 VOUTL1 Current Limit and Thermal Protection ENL2 Shutdown and Logic Control V REF EA MOS Driver AGND VOUTL2 Current Limit and Thermal Protection ENL3 Shutdown and Logic Control V REF EA MOS Driver VINL2 VOUTL3 Current Limit and Thermal Protection ENL4 Shutdown and Logic Control V REF EA MOS Driver VOUTL4 Current Limit and Thermal Protection DS8036-02 April 2011 www.richtek.com 3 RT8036 Absolute Maximum Ratings z z z z z z z z z z (Note 1) Buck Supply Input Voltage, VINB ------------------------------------------------------------------------ENB, VOUTB Voltage --------------------------------------------------------------------------------------LDO1, LDO2 Supply Input Voltage, VINL1, VINL2 -----------------------------------------------------ENL1 to ENL4, VOUT1 to VOUT4 Voltage ------------------------------------------------------------Power Dissipation, PD @ TA = 25°C −0.3V to 6.5V −0.3V to VINB −0.3V to 6V −0.3V to 6V WQFN−20L 3x3 ----------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN−20L 3x3, θJA ----------------------------------------------------------------------------------------WQFN−20L 3x3, θJC ----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) --------------------------------------------------------------------------------MM (Machine Mode) ----------------------------------------------------------------------------------------- 1.471W Recommended Operating Conditions z z z 68°C/W 7.5°C/W 260°C 150°C −65°C to 165°C 2kV 200V (Note 4) Supply Voltage, VINB, VINL1, VINL2 ------------------------------------------------------------------------ 2.5V to 5.5V Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VINB = 3.6V, VINLx = VOUTLx + 0.7V, VENLx = VINLx, CINB = 4.7μF, COUTB = 10μF, CINLx = COUTLx = 1μF, L = 2.2μH, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 2.5 -- 5.5 V Buck Converter Input Voltage Range VINB Quiescent Current IQB IOUTB = 0mA, -- 40 60 μA Shutdown Current ISHDNB -- 0.1 0.9 μA Output Voltage Accuracy ΔV OUTB −3 -- 3 % VOUTB Pin Input Current IOUTB ENB = GND VINB = VOUTB + ΔV to 5.5V VIN > 2.5V which ever is larger. (Note 5) VOUTB = V INB −50 -- 50 nA RDS(ON) of P-MOSFET RDS(ON)_P IOUTB = 200mA, V INB = 3.6V 0.1 0.28 0.6 Ω IOUTB = 200mA, V INB = 2.5V 0.1 0.38 0.6 Ω R DS(ON) of N-MOSFET RDS(ON)_N IOUTB = 200mA, V INB = 3.6V 0.1 0.25 0.55 Ω IOUTB = 200mA, V INB = 2.5V 0.1 0.35 0.55 Ω P-Channel Current Limit ENB High-Level Input Voltage ENB Low-Level Input Voltage Under Voltage Lock Out ILIM_P VINB = 2.5V to 5.5V 600 1800 2500 mA VENB_H VINB = 2.5V to 5.5V 1.5 -- VINB V VENB_L VINB = 2.5V to 5.5V -- -- 0.4 V -- 1.8 -- V UVLO To be continued www.richtek.com 4 DS8036-02 April 2011 RT8036 Parameter Under Voltage Lockout Hysteresis Oscillator Frequency Thermal Shutdown Temperature Maximal Duty Cycle Symbol Test Conditions UVLO_Hys fOSC VINB = 3.6V, IOUTB = 100mA TSDB LX Leakage Current VINB = 3.6V, V LX = 0V or VLX = 3.6V Min Typ Max Unit 0.05 0.1 0.35 V -- 1.5 -- MHz -- 160 -- °C 100 -- -- % 1 -- 100 μA 2.5 -- 5.5 V LDO LDO Input Voltage VINL = 2.5V to 5.5V Quiescent Current IQL VENL > 1.5V -- 50 80 μA Shutdown Current Dropout Voltage (Note 5) VOUTL Accuracy Line Regulation IQL_SD VENL < 0.4V -- 0.1 0.8 μA VDROP IOUTL = 300mA -- 330 500 mV ΔV ΔVLINE IOUTL = 1mA VIN = 2.5V to 5.5V −3 0 -0.02 3 0.2 % %/V Load Regulation ΔVLOAD 1mA < IOUTL < 300mA 0 0.1 0.6 % Current Limit ILIM RLOAD = 1Ω 330 430 600 mA VIHL VINL = 2.5V to 5.5V, Power On 1.5 -- -- V VILL VINL = 2.5V to 5.5V, Shutdown -- -- 0.4 V -- 100 -- ppm/°C -- 20 -- Ω -- 170 -- °C -- 30 -- °C f = 100Hz, ILOAD = 10mA -- 65 -- f = 1kHz, ILOAD = 10mA -- 60 -- f = 10kHz, ILOAD = 10mA -- 50 -- f = 100Hz, ILOAD = 150mA -- 65 -- f = 1kHz, ILOAD = 150mA -- 50 -- f = 10kHz, ILOAD = 150mA -- 50 -- ENL Threshold Output Voltage TC VOUTL Discharge Resistance in Shutdown Thermal Shutdown TSDL Thermal Shutdown ΔT SDL Hysteresis PSRR VINL = VOUTL + 1V COUTL = 2.2μF ILOAD = 50mA PSRR VIN = 5V, EN1 = EN2 = GND dB Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. ΔV = IOUT x RDS(ON)_P DS8036-02 April 2011 www.richtek.com 5 RT8036 Typical Operating Characteristics For Buck Efficiency vs. Output Current Output Voltage vs. Output Current 100 1.220 90 1.218 VINB = 3.6V 1.216 VINB = 5V 70 Output Voltage (V) Efficiency (%) 80 60 50 40 30 VINB = 3.6V 1.214 1.212 VINB = 5V 1.210 1.208 1.206 1.204 20 10 1.202 VOUTB = 1.2V, COUT = 10uF, L = 2.2H 0 0.001 0.01 0.1 1.200 0 1 0.1 0.2 0.3 0.6 0.7 0.8 0.9 1 UVLO Threshold vs. Temperature Output Voltage vs. Temperature 1.25 2.1 1.24 2.0 1.23 1.22 Input Voltage (V) Output Voltage (V) 0.5 Output Current (A) Output Current (A) 1.21 1.20 1.19 1.18 1.17 Rising 1.9 1.8 1.7 Falling 1.6 1.5 1.4 1.16 VINB = 3.6V, IOUTB = 0A 1.15 -40 -25 -10 5 20 35 50 65 80 VOUTB = 1.2V, IOUTB = 0A 1.3 -40 -25 -10 95 110 125 5 EN Threshold vs. Input Voltage 1.5 1.5 1.4 1.4 1.3 1.3 EN Voltage (V) 1.6 1.2 1.1 Rising 0.9 0.8 Falling 1.0 0.8 0.6 VOUTB = 1.2V, IOUTB = 0A 2.8 3.1 3.4 3.7 4 4.3 4.6 Input Voltage (V) www.richtek.com 6 80 95 110 125 4.9 5.2 5.5 Rising 0.9 0.6 2.5 65 1.1 0.7 0.4 50 1.2 0.7 0.5 35 EN Threshold vs. Temperature 1.6 1.0 20 Temperature (°C) Temperature (°C) EN Voltage (V) 0.4 Falling 0.5 VINB = 3.6V, VOUTB = 1.2V, IOUTB = 0A 0.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) DS8036-02 April 2011 RT8036 Frequency vs. Temperature 1.60 1.55 1.55 1.50 1.50 Frequency (MHz) Frequency (MHz) Frequency vs. Input Voltage 1.60 1.45 1.40 1.35 1.30 1.25 VIN = 3.6V, VOUT = 1.2V, IOUTB = 300mA 1.20 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 1.45 1.40 1.35 1.30 1.25 1.20 5.5 VINB = 3.6V, VOUTB = 1.2V, IOUTB = 300mA -40 -25 -10 5 Input Voltage (V) 35 50 65 80 95 110 125 Temperature (°C) Current Limit vs. Input Voltage Current Limit vs. Temperature 2.2 2.2 2.1 2.1 2.0 2.0 Output Current (A) Output Current (A) 20 1.9 1.8 1.7 1.6 1.5 1.4 VINB = 3.6V 1.9 VINB = 5V 1.8 1.7 VINB = 3.3V 1.6 1.5 1.4 1.3 VOUTB = 1.2V 1.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 1.3 5.5 -40 -25 -10 Input Voltage (V) 20 35 50 65 80 95 110 125 Output Ripple Voltage VINB = 3.6V, VOUTB = 1.2V, IOUTB = 1A VINB = 5V, VOUTB = 1.2V, IOUTB = 1A VOUTB (10mV/Div) VOUTB (10mV/Div) VLX (5V/Div) VLX (5V/Div) DS8036-02 April 2011 5 Temperature (°C) Output Ripple Voltage Time (500ns/Div) VOUTB = 1.2V 1.2 Time (500ns/Div) www.richtek.com 7 RT8036 Power On from EN Power On from EN VINB = 3.6V, VOUTB = 1.2V, IOUTB = 10mA VINB = 3.6V, VOUTB = 1.2V, IOUTB = 1A VENB (2V/Div) VENB (2V/Div) VOUTB (1V/Div) VOUTB (1V/Div) I INB (500mA/Div) I INB (500mA/Div) Time (100μs/Div) Time (100μs/Div) Power On from VIN Power Off from EN VENB = 3.6V, VOUTB = 1.2V, IOUTB = 1A VINB = 3.6V, VOUTB = 1.2V, IOUTB = 1A VENB (2V/Div) VINB (2V/Div) VOUTB (1V/Div) VOUTB (1V/Div) I INB (500mA/Div) I INB (500mA/Div) Time (250μs/Div) Time (100μs/Div) Load Transient Response Load Transient Response VINB = 3.6V, VOUTB = 1.2V IOUTB = 50mA to 1A VINB = 3.6V, VOUTB = 1.2V IOUTB = 50mA to 0.5A VOUTB (50mV/Div) VOUTB (50mV/Div) IOUTB (500mA/Div) IOUTB (500mA/Div) Time (50μs/Div) www.richtek.com 8 Time (50μs/Div) DS8036-02 April 2011 RT8036 Load Transient Response Load Transient Response VINB = 5V, VOUTB = 1.2V IOUTB = 50mA to 1A VINB = 5V, VOUTB = 1.2V IOUTB = 50mA to 0.5A VOUTB (50mV/Div) VOUTB (50mV/Div) IOUTB (500mA/Div) IOUTB (500mA/Div) Time (50μs/Div) DS8036-02 April 2011 Time (50μs/Div) www.richtek.com 9 RT8036 For LDO LDO2 Output Voltage vs. Temperature 3.00 1.95 2.95 1.90 2.90 Output Voltage (V) Output Voltage (V) LDO1 Output Voltage vs. Temperature 2.00 1.85 1.80 1.75 1.70 1.65 2.85 2.80 2.75 2.70 2.65 VINL1 = 4.3V, No Load 1.60 -40 -25 -10 5 20 35 50 65 80 VINL1 = 4.3V, No Load 2.60 95 110 125 -40 -25 -10 5 Temperature (°C) 35 50 65 80 95 110 125 Temperature (°C) Quiescent Current vs. Temperature LDO2 Dropout Voltage vs. Load Current 450 60 400 50 Dropout Voltage (mV) Quiescent Current (uA) 20 40 30 20 10 350 300 25°C 250 200 125°C 150 -40°C 100 50 VINL1 = 4.3V 0 -40 -25 -10 5 20 35 50 65 80 VOUTL2 = 2.8V 0 0 95 110 125 Temperature (°C) 50 75 100 125 150 175 200 Load Current (mA) Line Transient Response VINL1 4.8 (V) 25 Line Transient Response VINL1 4.8 (V) 3.8 3.8 VOUTL1 (20mV/Div) VOUTL1 (20mV/Div) VOUTL2 (20mV/Div) VOUTL2 (20mV/Div) VOUTL1 = 1.8V, VOUTL2 = 2.8V, IOUTL1 = IOUTL2 = 1mA VOUTL1 = 1.8V, VOUTL2 = 2.8V, IOUTL1 = IOUTL2 = 10mA Time (100μs/Div) Time (100μs/Div) www.richtek.com 10 DS8036-02 April 2011 RT8036 Line Transient Response VINL1 4.8 (V) Line Transient Response 4.8 VINL1 (V) 3.8 3.8 VOUTL1 (20mV/Div) VOUTL1 (10mV/Div) VOUTL2 (20mV/Div) VOUTL2 (10mV/Div) VOUTL1 = 1.8V, VOUTL2 = 2.8V, IOUTL1 = IOUTL2 = 100mA VOUTL1 = 1.8V, VOUTL2 = 2.8V, IOUTL1 = IOUTL2 = 50mA Time (100μs/Div) Time (100μs/Div) Load Transient Response Load Transient Response VINL1 = 4.3V, VOUTL1 = 1.8V, VOUTL2 = 2.8V VINL1 = 4.3V, VOUTL1 = 1.8V, VOUTL2 = 2.8V IOUT (50mA/Div) IOUT (100mA/Div) VOUTL1 (20mV/Div) VOUTL1 (20mV/Div) VOUTL2 (20mV/Div) VOUTL 2 (20mV/Div) IOUTL1 = IOUTL2 = 10mA to 100mA IOUTL1 = IOUTL2 = 10mA to 50mA Time (250μs/Div) Time (250μs/Div) Power On from ENL1 Power Off from ENL1 VINL1 = 5V, VOUTL1 = 1.8V, VOUTL2 = 2.8V, IOUTL1 = IOUTL2 = 50mA ENL1 (5V/Div) ENL1 (5V/Div) VOUTL1 (1V/Div) VOUTL1 (1V/Div) VOUTL2 (1V/Div) VOUTL2 (1V/Div) Time (25μs/Div) DS8036-02 April 2011 VINL1 = 5V, VOUTL1 = 1.8V, VOUTL2 = 2.8V, IOUTL1 = IOUTL2 = 50mA Time (25μs/Div) www.richtek.com 11 RT8036 Noise Noise VINL1 = VENL1 = 5V, No Load VOUTL1 (100μV/Div) VINL2 = VENL2 = 5V, IOUTL2 = 50mA VOUTL2 (100μV/Div) Time (10ms/Div) VOUTL1 PSRR 10 0 0 -10 -10 -20 -20 -30 -40 IOUTL1 = 10mA -50 IOUTL1 = 150mA -60 VOUTL2 PSRR 10 -70 PSRR (dB) PSRR(dB) Time (10ms/Div) -30 IOUTL2 = 10mA -40 -50 IOUTL2 = 150mA -60 -70 -80 -80 VINL1 = VENL1 = 4.3V ±50mV, VOUTL1 = 1.8V, IOUTL1 = 50mA -90 -100 10 100 1000 10000 Frequency (Hz) www.richtek.com 12 100000 1000000 VINL2 = VENL2 = 4.3V ±50mV, VOUTL2 = 2.8V, IOUTL2 = 50mA -90 -100 10 100 1000 10000 100000 1000000 Frequency (Hz) DS8036-02 April 2011 RT8036 Application Information The RT8036 is an integrated power management IC including one Buck converter and four linear regulators. The RT8036 features a fixed output voltage to eliminate the need of external feedback resistors and simplify the PCB layout. The RT8036 fix the output voltage by internal resistor and keep the output voltage between -3% to 3%. Please refer to the ordering information for detailed output voltage setting. Buck Enable Control Pull the ENB pin (>1.5V) to turn on the buck converter and to pull low the ENB pin (<0.4V) to turn off the buck converter. Soft-Start The RT8036 has a soft-start to control the output voltage rise time and limit the current surge at the startup. The soft-start will begin while EN rises above high threshold. Buck Current Limiting A current limit feature allows the RT8036 to protect itself and external components during overload conditions. In operating mode, the inductor peak current under 600mA is normally used. The current limit prevents the loss of current control seen in some products when the output voltage is pulled low in serious overload conditions. Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current, ΔI L, increases with higher V INB and decreases with higher inductance. ⎤ ⎡V ⎤ ⎡ V ΔIL = ⎢ OUT ⎥ × ⎢1 − OUT ⎥ VIN ⎦ ⎣ f ×L ⎦ ⎣ Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔIL = 0.4 (IMAX). The largest ripple current occurs at the highest VINB. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : DS8036-02 April 2011 ⎡ VOUT ⎤ ⎡ VOUT ⎤ L=⎢ ⎥ × ⎢1 − ⎥ ⎣⎢ f × ΔIL(MAX) ⎦⎥ ⎣⎢ VIN(MAX) ⎦⎥ Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. CINB and COUTB Selection The input capacitance, C INB, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : IRMS = IOUTB(MAX) VOUTB VINB VINB −1 VOUTB www.richtek.com 13 RT8036 This formula has a maximum at VINB = 2VOUTB, where I RMS = I OUTB/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUTB is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUTB, is determined by : ⎡ ⎤ 1 ΔVOUT ≤ ΔIL ⎢ESR + ⎥ 8fCOUT ⎦ ⎣ The output ripple is highest at maximum input voltage since DIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long www.richtek.com 14 wires, a load step at the output can induce ringing at the input, VINB. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VINB large enough to damage the part. LDO Capacitor Selection Like any low-dropout regulator, the external capacitors used with the RT8036 must be carefully selected for regulator stability and performance. Using a capacitor whose value is >1μF on the RT8036 input and the amount of capacitance can be increased without limit. The input capacitor must be located at a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs application. The RT8036 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1μF with ESR is > 20mΩ on the RT8036 output ensures stability. The RT8036 still works well with output capacitor of other types due to the wide stable ESR range. Figure 1. shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the output pin of the RT8036 and returned to a clean analog ground. LDO Enable The LDO of RT8036 goes into shutdown mode when the ENL1, ENL2, ENL3 and ENL4 pin is in a logic low condition. During this condition, the pass transistor, error amplifier, and bandgap are turned off, reducing the supply current to be lower than 1μA. The ENL1, ENL2, ENL3 and ENL4 pin can be directly tied to VINL1 and VINL2 to keep the part on. DS8036-02 April 2011 RT8036 resistance θJA is 68°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : Region of Stable C OUT ESR (Ω) 100 10 Unstable Range 1 PD(MAX) = (125°C − 25°C) / (68°C/W) =1.471W for WQFN-20L 3x3 packages Stable Range 0.1 0.01 Simulation Verify VINL = 5V, CINL = COUTLx = 1uF/X7R 0.001 0 50 100 150 200 250 300 Load Current (mA) The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA . For RT8036 packages, the Figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. Figure 1. Stable Region of Output Capacitor ESR 1.6 Maximum Power Dissipation (W) LDO Current limit The RT8036 contains an independent current limiter, which monitors and controls the pass transistor's gate voltage, limiting the output current to 460mA (typ.). The output can be shorted to ground indefinitely without damaging the part. Thermal Shutdown Protection As the die temperature reaches a certain thermal shutdown threshold, the chip will enter protection mode. The power MOSFET will turn-off during protection mode to prevent abnormal operation. PD(MAX) = (TJ(MAX) − TA) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8036, The maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-20L 3x3 packages, the thermal DS8036-02 April 2011 1.2 1.0 WQFN-20L 3x3 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 2. Derating Curves for RT8036 Packages Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : Four Layers PCB 1.4 Layout Consideration The RT8036 is an integrated power management unit which integrates one 1A high efficiency step down DC/DC converter and four low dropout voltage regulators with 300mA current capability for each regulator. Careful PCB layout is necessary. For best performance, place all peripheral components as close to the IC as possible. A short connection is highly recommended. The following guidelines should be strictly followed when designing a PCB layout for the RT8036. ` Input capacitor should be placed close to IC and connected to ground plane. The trace of input in the PCB should be placed far away from the sensitive devices or shielded by the ground. www.richtek.com 15 RT8036 ` The GND should be connected to a strong ground plane for heat sinking and noise protection. ` The inductor should be placed close to LX pin and connected to output capacitor. The trace of input in the PCB should be placed far away from the sensitive devices or shielded by the ground. ` Output capacitor should be placed close to inductor and connected to ground plane to reduce noise coupling. Output capacitor should be placed close to VOUT and connected to ground plane to reduce noise coupling. GND COUT2 Battery CINB VOUTL2 VOUTL1 NC AGND VINL2 Input capacitor should be placed close to VIN and connected to ground plane. The trace of VIN in the PCB should be placed far away the sensitive devices or shielded by the ground. CINL1 20 19 18 17 16 VINL1 1 15 VOUTL3 ENL1 ENL2 2 14 VINB 4 12 VOUTL4 AGND COUT4 ENL4 LX 5 11 ENL3 GND 3 13 21 7 8 9 10 PGND ENB PGND VOUTB PGND 6 The inductor (L) should be placed close to LX and connected to Cout to reduce noise. CINL2 COUT1 Input capacitor should be placed close to VIN and connected to ground plane. The trace of VIN in the PCB should be placed far away the sensitive devices or shielded by the ground. COUT3 Output capacitor should be placed close to V OUT and connected to ground plane to reduce noise coupling. VOUTB GND Figure 3. PCB Layout Guide www.richtek.com 16 DS8036-02 April 2011 RT8036 Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 2.950 3.050 0.116 0.120 D2 1.650 1.750 0.065 0.069 E 2.950 3.050 0.116 0.120 E2 1.650 1.750 0.065 0.069 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 20L QFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8036-02 April 2011 www.richtek.com 17