FBGA-SS A JCET Company Fine Pitch Ball Grid Array - Side by Side HIGHLIGHTS •Array molded, cost effective, space-saving package solution •Available in 1.40mm (LFBGA), 1.20mm (TFBGA), 1.00mm (VFBGA), 0.80mm (WFBGA), 0.65mm (UFBGA) maximum thickness and 0.50mm (XFBGA) maximum thickness •Laminate substrate-based package which enables 1, 2, 3 and 4 layers of routing flexibility DESCRIPTION FEATURES • Thin, lightweight, space-saving package • Flexible body sizes range from 3 x 3mm to 23 x 23mm with square or rectangular body size options • 2 to 4 die in a single package • 0.40, 0.50, 0.65, 0.75, 0.80, 1.00mm ball pitch • Eutectic & Pb free solder balls • Green package available • Multiple routing layers and dedicated ground/power planes available for improved electrical performance • BT laminate materials (1, 2, 3 and 4 metal layers) • JEDEC standard compliant APPLICATIONS The Fine Pitch Ball Grid Array (FBGA) is a laminate substrate-based chip scale package with plastic overmolded encapsulation and an array of fine pitch solder ball terminals. FBGA’s reduced outline and thickness and higher density options make it an ideal advanced technology packaging solution for high performance and/or portable applications. For higher I/O requirements, STATS ChipPAC offers FBGA packages with 2 to 4 die in a side-by-side configuration. STATS ChipPAC’s FBGA-SS is available in a broad range of JEDEC standard body sizes with LFBGA (<1.70mm [typically <1.40mm]), TFBGA (<1.20mm), VFBGA (<1.00mm), WFBGA (<0.80mm), UFBGA (0.65mm max.) and XFBGA (0.50mm max.) thickness. The use of the latest materials and advanced assembly infrastructure produce a reliable and cost effective package. Lead free and halogen free compatible material sets are available. • Microprocessors/Controllers • Wireless RF • Analog • ASIC • Memory • Simple PLDs • Others www.cj-elec.com BGA technology was first introduced as a solution for the increasingly high lead counts required for advanced semiconductors used in applications such as portable computers and wireless telecommunications. Today BGA packages are used for high performance applications with high I/O connections and high thermal and electrical requirements. The characteristics of BGA packages make them suitable for a wide variety of devices used in computing platforms, networking, hand-held consumer products, wireless communications devices, video cameras, home electronic devices and game consoles. www.statschippac.com FBGA-SS A JCET Company Fine Pitch Ball Grid Array - Side by Side SPECIFICATIONS Die Thickness Gold Wire Pd/Cu Wire Ag Wire Mold Cap Thickness Marking Packing Options RELIABILITY Moisture Sensitivity Level Temperature Cycling High Temp Storage Temperature/Humidity Test Unbiased HAST 50-300µm (3-12mils) 15-30µm (0.6/0.8/0.9/1.0/1.2mils) diameter 15-25µm (0.6/0.7/0.8/1.0mils) diameter 18-25µm (0.7/0.8/1.0mils) diameter 0.25 - 1.22mm Laser JEDEC tray/tape and reel JEDEC Level 2A, 260°C Reflow Condition C (–55°C to 125°C), 1000 cycles 150°C, 1000 hrs 85°C/85% RH, 1000 hrs 110°C/85% RH/2 atm, 264 hrs THERMAL PERFORMANCE, θja (°C/W) Thermal performance is highly dependent on package size, die size, substrate layers and thickness, and solder ball configuration. Simulation for specific applications should be performed to obtain maximum accuracy. Package LFBGA-SS Body Size (mm) 11 x 11 (2L) 15 x 15 (4L) Pin Count 144 208 Die Size (mm) 4.5 x 4.5 10.2 x 10.2 Thermal Performance θja(ºC/W) 34.1 19.4 Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-9) under natural convection as defined in JESD51-2. ELECTRICAL PERFORMANCE Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire. Conductor Component Wire Net (2L) Length (mm) 2 2 - 7 Resistance (mOhms) 120 34 -119 Inductance (nH) 1.65 1.30 - 4.55 4 - 9 154 - 239 2 120 Net (4L) 2 - 7 Total (4L) 4 - 9 Total (2L) Wire Inductance Mutual (nH) 0.45 - 0.85 0.26 - 2.28 Capacitance (pF) 0.10 0.25 - 0.95 Capacitance Mutual (pF) 0.01 - 0.02 0.06 - 0.42 2.95 - 6.20 0.71 - 3.13 0.35 - 1.05 0.07 - 0.44 1.65 0.45 - 0.85 0.10 0.01 - 0.02 34 - 119 0.90 - 3.15 0.18 - 1.58 0.35 - 1.10 0.06 - 0.42 154 - 239 2.55 - 4.80 0.63 - 2.43 0.45 - 1.20 0.07 - 0.44 Note: Net = Total Trace Length + Via + Solder Ball. CROSS-SECTION PACKAGE CONFIGURATIONS Body Sizes (mm) Ball Count Ball Pitch (mm) 3x3 to 23x23 with square or rectangular body size options; Common body sizes: 5x10, 7x9, 8x10, 8x11, 8x12, 8x14, 10x12, 10x14, 13x13, 15x15, 16x16, 17x17 40 to 450 0.40 to 1.0 Die 2 to 4 Typ. Pkg. Thickness LFBGA: TFBGA: VFBGA: WFBGA: 1.70mm (1.40mm max. typical) 1.20mm max 1.00mm max 0.80mm max Two die copper wire configuration shown in example above. Corporate Office Global Offices 10 Ang Mo Kio St. 65, #04-08/09 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-32-340-3114 SWITZERLAND 41-21-8047-200 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Pte. Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2016. STATS ChipPAC Pte. Ltd. All rights reserved. Apr 2016