PBGA-MD Plastic Ball Grid Array - Multi-Die HIGHLIGHTS • Strip molded, cost-effective, high I/O, multi-die packaging solution • Enables space efficient side by side and stacked die packaging options • Wide range of pre-existing body sizes • Available in eutectic and Pb-free versions FEATURES • Full in-house package and substrate design capability • Full in-house electrical, thermal and mechanical simulation and measurement capability • Multiple metal layer options for signal, power and ground planes for improved electrical performance • Flexible body sizes ranging from 15mm x 15mm to 40mm x 40mm • Accommodates both side by side and/or stacked die configurations • Multiple chip design and optional passive / discrete components available (SiP) • 0.65, 0.80, 1.00, 1.27mm and 1.5mm ball pitch with greater than 1000 I/O available • Perimeter or full ball array • SnPb and Pb-free balls available • Pb-free and green material set options • JEDEC standard compliant APPLICATIONS • ASIC • DSPs and Memory • Gate Arrays • Microprocessors/Controllers/Graphics • PC chipsets • Other advanced applications involving package level integration of memory and logic devices www.statschippac.com DESCRIPTION STATS ChipPAC’s Plastic Ball Grid Array - Multi-Die (PBGA-MD) packages utilize laminate substrates and are available in a variety of standard JEDEC body sizes and ball counts to meet a wide range of customer requirements. This package provides a cost-effective advanced packaging solution and is a direct extension of our single die product offerings to multi-die configurations. STATS ChipPAC’s PBGA-MD offerings support either side by side and/or stacked die configurations. Advanced design and simulation capabilities are used in these multi-die packaging applications for maximum electrical and thermal performance. STATS ChipPAC combines state of the art processing and equipment with proven material sets to achieve enhanced yield, reliability and performance. Green and lead-free material sets are available for all PBGA-MD package types. PBGA-MD Plastic Ball Grid Array - Multi-Die SPECIFICATIONS Die Thickness Gold Wire Pd/Cu Wire Bond Pad Pitch Mold Cap Thickness Marking Packing Options RELIABILITY Moisture Sensitivity Level Temperature Cycling High Temperature Storage Pressure Cooker Test Liquid Thermal Shock Unbiased HAST 150-381µm (6-15mils) 15-30µm (0.6/0.7/0.8/0.9/1.0/1.1/1.2mils) diameter 15-30µm (0.6/0.7/0.8/1.0mils) diameter 45µm inline or 25/50µm staggered capable 0.7~1.17mm Laser JEDEC tray/tape and reel JEDEC Level 3 -65°C/150°C, 1000 cycles (typical) 150°C, 1000 hrs (typical) 121°C, 100%RH, 2 atm, 168 hrs (Condition B) -55°C/125°C, 1000 cycles 130°C/85% RH/2 atm, 96 hrs THERMAL PERFORMANCE The thermal performance of each die in the package is influenced by other die in the package. Thermal performance is highly dependent on package size, die size, substrate layers and thickness, and solder ball configuration. Simulation for specific applications should be performed. ELECTRICAL PERFORMANCE Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire. onductor C Length Component (mm) Wire 2 Net (2L) 2 - 7 Total (2L) Wire 2 Net (4L) 2 - 7 Total (4L) Resistance (mOhms) 120 34 - 119 154 - 239 120 34 - 119 154 - 239 Inductance (nH) 1.65 1.3 - 4.55 2.95 - 6.2 1.65 0.9 - 3.15 2.55 - 4.80 Inductance Mutual (nH) 0.45 - 0.85 0.26 - 2.28 0.71 - 3.13 0.45 - 0.85 0.18 - 1.58 0.63 - 2.43 Capacitance (pF) 0.1 0.25 - 0.95 0.35 - 1.05 0.1 0.35 - 1.1 0.45 - 1.2 Capacitance Mutual (pF) 0.01 - 0.02 0.06 - 0.42 0.07 - 0.44 0.01 - 0.02 0.06 - 0.42 0.07 - 0.44 Note: Net = Total Trace Length + Via + Solder Ball. CROSS-SECTION PACKAGE CONFIGURATIONS PBGA-MD Package Size (mm) Ball Count 15 x 15 74, 121, 160, 176, 196 17 x 17 17.2 x 17.2 208, 256 512 19 x 19 225, 233, 260, 324, 484 23 x 23 169, 192, 196, 208, 217, 225, 241, 304, 316, 324, 340, 360, 376, 388, 484 27 x 27 225, 256, 272, 292, 300, 316, 320, 324, 336, 352, 384, 388, 392, 400, 484, 484, 512, 625, 672 31 x 31 329, 353, 360, 385, 421, 433, 560, 604, 608, 676, 692, 701 35 x 35 312, 352, 363, 385, 388, 420, 452, 454, 456, 468, 492, 496, 512, 516, 544, 548, 564, 580, 680, 700, 740, 788 37.5 x 37.5 435, 625, 784, 840 40 x 40 503, 596, 600, 900, 928, 1253 Corporate Office Global Offices 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-31-639-8915 TAIWAN 886-3-593-6565 SWITZERLAND 41-21-8047-200 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2014. STATS ChipPAC Ltd. All rights reserved. December 2014