FLGA Fine Pitch Land Grid Array HIGHLIGHTS •Array molded, cost effective, space-saving packaging solution •Available in 2.45mm (LFLGA), 1.20mm (TFLGA), 1.00mm (VFLGA) and 0.80mm (WFLGA) maximum thickness •Thinner than FBGA •Exposed thermal/mechanical lands available •Laminate substrate based enabling 2 and 4 layers of routing flexibility FEATURES • Low profile • Flexible body sizes range from 4 x 4mm to 13 x 13mm • Flip chip and discrete passive options (SiP) • Minimum 0.50mm pitch (array and peripheral land pads) • Flexible land pattern arrangement • Pb-free and halogen-free compatible materials available • JEDEC standard compliant APPLICATIONS • Handheld devices • Wireless RF • Analog • ASIC • Memory • Simple PLDs www.statschippac.com DESCRIPTION STATS ChipPAC’s FLGA is a laminate substrate based package with plastic overmolded encapsulation. Unlike a standard FBGA, second level interconnect is achieved on the LGA by connecting “lands” on the package directly onto the PCB through solder re-flow. The elimination of solder balls brings better electrical performance and lower package profile without using the more expensive thinner BT core material. It also offers the flexibility of land pattern arrangement in the form of signal lands or heat spreader/ground pads to suit the thermal and electrical requirements of various devices. The FLGA package’s reduced outline and thickness make it an ideal advanced technology packaging solution for high performance and/or portable applications. STATS ChipPAC’s FLGA is available in a broad range of JEDEC standard body sizes including LFLGA (<2.45mm), TFLGA (<1.20mm), VFLGA (<1.00mm) and WFLGA (<0.80mm) package thickness. FLGA Fine Pitch Land Grid Array SPECIFICATIONS Die Thickness Gold Wire Pd/Cu Wire Ag Wire Mold Cap Thickness Marking Packing Options RELIABILITY Moisture Sensitivity Level Temperature Cycling 50-300µm (3-12mils) 15-30µm (0.6/0.8/0.9/1.0/1.2mils) diameter 15-25µm (0.6/0.7/0.8/1.0mils) diameter 18-25µm (0.7/0.8/1.0mils) diameter 0.25 - 1.22mm Laser JEDEC tray/tape and reel High Temp Storage Pressure Cooker Test Temperature/Humidity Test Unbiased HAST JEDEC Level 2A, 260°C Reflow Condition C (–65°C to 150°C), 1000 cycles 150°C, 1000 hrs 121°C/100%RH/2atm, 168 hrs 85°C/85% RH, 1000 hrs 130°C/85% RH/2 atm, 96 hrs THERMAL PERFORMANCE, θja (°C/W) Thermal performance is highly dependent on package size, die size, substrate layers and thickness, and land configuration. Simulation for specific applications should be performed to obtain maximum accuracy. Package VFLGA Body Size (mm) 9 x 9 (4L) Pin Count 112 Die Size 4.1 x 4.1 PCB Vias 16 Thermal Performance θja(ºC/W) 36.1 Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-9) under natural convection as defined in JESD51-2. ELECTRICAL PERFORMANCE Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire. Conductor Component Wire Net (2L) Total (2L) Wire Length (mm) 2 2 - 7 Resistance (mOhms) 120 25 -110 Inductance (nH) 1.65 1.10 - 4.35 Inductance Mutual (nH) 0.45 - 0.85 0.25 - 2.27 Capacitance (pF) 0.10 0.20 - 0.90 Capacitance Mutual (pF) 0.01 - 0.02 0.05 - 0.41 4 - 0 145 - 230 2.75 - 6.00 0.70 - 3.12 0.30 - 1.00 0.06 - 0.43 2 120 1.65 0.45 - 0.85 0.10 0.01 - 0.02 Net (4L) 2 - 7 25 - 110 0.70 - 2.95 0.17 - 1.57 0.30 - 1.05 0.05 - 0.41 Total (4L) 4 - 9 145 - 230 2.35 - 4.60 0.62 - 2.42 0.40 - 1.15 0.06 - 0.43 Note: Net = Total Trace Length + Via CROSS-SECTION PACKAGE CONFIGURATIONS FLGA Corporate Office Global Offices Body Sizes (mm) Terminal Count Terminal Pitch (mm) 4 x 4 to 13 x 13 8 to 200 0.50 to 0.80 Typical Package Thickness LFLGA: 2.45mm max. TFLGA: 1.20mm VFLGA: 1.00mm max. WFLGA: 0.80mm max. 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-31-639-8915 TAIWAN 886-3-593-6565 SWITZERLAND 41-21-8047-200 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2014. STATS ChipPAC Ltd. All rights reserved. December 2014