ISL97650 ® Data Sheet November 28, 2006 4-Channel Integrated LCD Supply Features The ISL97650 represents a high power, integrated LCD supply IC targeted at large panel LCD displays. The ISL97650 integrates a high power, 2.6A boost converter for AVDD generation, an integrated VON charge pump, a VOFF charge pump driver, VON slicing circuitry and a buck regulator with 2A switch for logic generation. • 4V to 14V input supply The ISL97650 has been designed for ease of layout and low BOM cost. Supply sequencing is integrated for both AVDD -> VOFF -> VON and AVDD/VOFF -> VON sequences. The TFT power sequence uses a separate enable to the logic buck regulator for maximum flexibility. Peak efficiencies are >90% for both the boost and buck while operating from a 4V to 14V input supply. The current mode buck offers superior line and load regulation. Available in the 36 Ld QFN package, the ISL97650 is specified for ambient operation over the -40°C to +105°C temperature range. FN9198.3 • AVDD boost up to 20V, with integrated 2.8A FET • Integrated VON charge pump, up to 35V out • VOFF charge pump driver, down to -18V • VLOGIC buck down to 1.2V, with integrated 2A FET • Automatic start-up sequencing - AVDD -> VOFF -> VON or AVDD/VOFF -> VON - Independent logic enable • VON slicing • Thermally enhanced 6x6 Thin QFN package • Pb-free plus anneal available (RoHS compliant) Applications • LCD monitors (15”+) Pinout • LCD-TVs (up to 40”) • Notebook displays (up to 16”) 28 VDC1 29 CDEL • Industrial/medical LCD displays 30 ENL 31 DELB 32 CM1 33 VIN 34 FBB 35 EN 36 VDC2 ISL97650 (36 LD TQFN) TOP VIEW Ordering Information LX1 1 27 AGND1 LX2 2 26 PGND1 CB 3 25 PGND2 LXL 4 24 VINL THERMAL PAD NC 5 23 NOUT VSUP 6 22 PGND3 1 PART MARKING TAPE & REEL PACKAGE PKG. (Pb-Free) DWG. # ISL97650ARTZ-T ISL97650ARTZ 13” (4k pcs) 36 Ld 6x6 Thin QFN L36.6x6 ISL97650ARTZ-TK ISL97650ARTZ 13” (1k pcs) 36 Ld 6x6 Thin QFN L36.6x6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. NC 18 C2+ 17 C2- 16 C1+ 15 19 FBP C1- 14 CTL 9 POUT 13 20 VREF COM 12 CM2 8 DRN 11 21 FBN AGND2 10 FBL 7 PART NUMBER (Note) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97650 Absolute Maximum Ratings (TA = +25°C) Thermal Information Maximum Pin Voltages, all pins except below . . . . . . . . . . . . . . 6.5V LX1, LX2, VSUP, NOUT, DELB, C2- . . . . . . . . . . . . . . . . . . . .24V C1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V VIN1, VINL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V DRN, COM, POUT, C1+, C2+ . . . . . . . . . . . . . . . . . . . . . . . . .36V CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21V Thermal Resistance Recommended Operating Conditions Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4V to 14V Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . . . . +20V VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . +15V to +32V VOFF Output Range, VOFF . . . . . . . . . . . . . . . . . . . . . . . -15V to -5V Logic Output Voltage Range, VLOGIC . . . . . . . . . . . . +1.5V to +3.3V Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10µF Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH-10µH Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . . . 2x22µF Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH-10µH Operating Ambient Temperature Range . . . . . . . . -40°C to +105°C Operating Junction Temperature . . . . . . . . . . . . . . -40°C to +125°C θJA (°C/W) θJC (°C/W) 6x6 QFN Package (Notes 1, 2) . . . . . . 30 2.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Power Dissipation TA ≤ +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3W TA = +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8W TA = +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3W TA = +100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8W CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may trigger the shutdown of the device even before +150°C, since this number is specified as typical. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +105°C, unless otherwise stated. DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY PINS VIN Supply Voltage (VIN1) 4 12 14 V VINL Logic Supply Voltage 4 12 14 V VSUP Charge Pumps and VON Slice Positive Supply 4 20 V IVIN Quiescent Current into VIN IINL Logic Supply Current Enabled, No switching 3 5 mA Disabled 25 50 µA 0.25 2 mA 1 25 µA 1 mA 1 10 µA 3.85 4 V Enabled, No switching Disabled ISUP VSUP Supply Current Enabled, No Switching and VPout = VSUP Disabled VLOR Undervoltage Lockout Threshold VDC rising VLOF Undervoltage Lockout Threshold VDC falling 3.3 3.45 VREF Reference Voltage TA = +25°C 1.18 1.205 1.225 V 1.177 1.205 1.228 V 1020 1200 1380 kHz 20 25 % FOSC Oscillator Frequency V AVDD BOOST DMIN Minimum Duty Cycle DMAX Maximum Duty Cycle 2 84 % FN9198.3 November 28, 2006 ISL97650 Electrical Specifications PARAMETER VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +105°C, unless otherwise stated. (Continued) DESCRIPTION CONDITIONS VBOOST Boost Output Range IBOOST Boost Switch Current Current limit EFFBOOST Peak Efficiency See graphs and component recommendations rDS(ON) Switch On Resistance ΔVBOOST/ΔVIN Line Regulation ΔVBOOST/ΔIOUT VFBB MIN TYP 1.25 *VIN 2.6 3.2 MAX UNIT 20 V 3.8 A 90+ % 160 300 mΩ 5V < VIN < 13V 0.4 1.0 %/V Load Regulation 100mA < Iload < 200mA 0.1 0.5 % Boost Feedback Voltage TA = +25°C 1.192 1.205 1.218 V 1.188 1.205 1.222 V 1.5 % ACCBOOST AVDD Output Accuracy TA = +25°C tss Soft-Start Period for AVDD CDEL = 220nF VBUCK Buck Output Voltage Output current = 0.5A 1.5 IBUCK Buck Switch Current Current limit 2.0 EFFBUCK Peak Efficiency See graphs and component recommendations RDS-ONBK Switch On Resistance ΔVBUCK/ΔVIN Line Regulation ΔVBUCK/ΔIOUT VFBL -1.5 9.6 ms VLOGIC BUCK 2.4 5.5 V 2.9 A 92 % 200 400 mΩ 5V < VIN < 13V 0.1 1.0 %/V Load Regulation 100mA < Iload < 500mA 0.2 1 % FBL Regulation Voltage TA = +25°C 1.176 1.2 1.224 V 1.174 1.2 1.226 V 2 % ACCLOGIC VLOGIC Output Accuracy TA = +25°C tssL Soft-Start Period for V(Logic) C(VREF) = 220nF (Note - no soft-start if EN asserted HIGH before ENB) -2 0.5 ms NEGATIVE (VOFF) CHARGE PUMP VOFF VOFF Output Voltage Range 2X Charge Pump ILoad_NCP_min External Load Driving Capability VSUP > 5V Ron(NOUT)H High-Side Driver ON Resistance at NOUT I(NOUT) = +60mA 10 Ω Ron(NOUT)L Low-Side Driver ON Resistance at NOUT I(NOUT) = -60mA 5 Ω Ipu(NOUT)lim Pull-Up Current Limit in NOUT V(NOUT) = 0V to V(SUP)-0.5V Ipd(NOUT)lim Pull-Down Current Limit in NOUT V(NOUT) = 0.36V to V(VSUP) I(NOUT)leak Leakage Current in NOUT V(FBN) < 0 or EN = LOW VFBN FBN Regulation Voltage TA = +25°C ACCN VOFF Output Accuracy D_NCP_max Max Duty Cycle of the Negative Charge Pump Rpd(FBN)off Pull-Down Resistance, Not Active 3 IOFF = 1mA, TA = +25°C -VSUP +1.4V 0 30 60 mA 270 -200 -5 mA -60 mA 5 µA 0.173 0.203 0.233 V 0.171 0.203 0.235 V +3 % -3 50 I(FBN) = 500µA V 1.5 3.3 % 5.5 kΩ FN9198.3 November 28, 2006 ISL97650 Electrical Specifications PARAMETER VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +105°C, unless otherwise stated. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 34 V POSITIVE (VON) CHARGE PUMP VON VON Output Voltage Range 2X or 3X Charge Pump VSUP+ 2V ILoad_PCP_min External Load Driving Capability VON = 25V (2X Charge Pump) 20 mA VON = 34V (3X Charge Pump) 20 mA 17 Ω 30 Ω 7 Ω Ron(VSUP_SW) ON Resistance of VSUP Input Switch I(switch) = +40mA Ron(C1/2-)H High-Side Driver ON Resistance at C1- and C2- I(C1/2-) = +40mA Ron(C1/2-)L Low-Side Driver ON Resistance at C1- and C2- I(C1/2-) = -40mA Ipu(VSUP_SW) Pull-Up Current Limit in VSUP Input Switch V(C2+) = 0V to V(SUP) - 0.4V - V(diode) 40 100 mA Ipu(C1/2-) Pull-Up Current Limit in C1- and C2- V(C1/2-) = 0V to V(VSUP) - 0.4V 40 100 mA Ipd(C1/2-) Pull-Down Current Limit in C1- and C2- V(C1/2-) = 0.2V to V(VSUP) I(POUT)leak Leakage Current in POUT EN = LOW -5 VFBP FBP Regulation Voltage TA = +25°C 1.176 1.172 10 4 -100 -40 mA 5 µA 1.2 1.224 V 1.2 1.228 V +2 % ACCP VON Output Accuracy D_PCP_max Max Duty Cycle of the Positive Charge Pump 50 V(diode) Internal Schottky Diode Forward Voltage I(diode) = +40mA 700 ION = 1mA, TA = +25°C -2 % 800 mV ENABLE INPUTS VHI-EN Enable “HIGH” VLO_EN Enable “LOW” IEN_pd Enable Pin Pull-Down Current VHI-ENL Logic Enable “HIGH” VLO-ENL Logic Enable “LOW” IENL_pd Logic Enable Pin Pull-Down Current 2.2 V VEN > VLO_EN 0.8 V 25 µA 2.2 V VENL > VLO_ENL 0.8 V 25 µA VON SLICE POSITIVE SUPPLY = V(POUT) I(POUT)_slice VON Slice Current from POUT Supply CTL = VDD, sequence complete 200 400 µA CTL = AGND, sequence complete 100 150 µA RON(POUT-COM) ON Resistance between POUT - COM CTL = VDD, sequence complete 5 10 Ω RON(DRN-COM) ON Resistance between DRN - COM CTL = ACGND, sequence complete 30 60 Ω RON_COM ON Resistance between COM and PGND3 500 1500 Ω VLO CTL Input LOW Voltage 0.8 V VHI CTL Input HIGH Voltage 200 2.2 V FAULT DETECTION THRESHOLDS T_off Thermal Shut-Down (latched and reset by power cycle or EN cycle) Temperature rising 150 °C Vth_AVDD(FBB) AVDD Boost Short Detection V(FBB) falling less than 0.9 V V(FBL) falling less than 0.9 V Vth_VLOGIC(FBL) VLOGIC Buck Short Detection 4 FN9198.3 November 28, 2006 ISL97650 Electrical Specifications PARAMETER VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +105°C, unless otherwise stated. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT Vth_POUT(FBP) POUT Charge Pump Short Detection V(FBP) falling less than 0.9 V Vth_NOUT(FBN) NOUT Charge Pump Short Detection V(FBN) rising more than 0.4 V TFD Fault Delay Time to Chip Turns Off 52 ms 80 ms START-UP SEQUENCING tSTART-UP Enable to AVDD Start Time IDELB_ON DELB Pull-Down Current or Resistance VDELB > 0.9V when Enabled by the Start-Up Sequence VDELB < 0.9V CDEL = 220nF 36 50 70 µA 1.00 1.326 1.75 kΩ 500 nA 220 nF IDELB_OFF DELB Pull-Down Current or Resistance VDELB < 20V when Disabled CDEL Sequence Timing and Fault Time Out Capacitor tVOFF AVDD to VOFF CDEL = 220nF 9 ms tVON VOFF to VON Delay CDEL = 220nF 20 ms tVON-SLICE VON to VON-SLICE Delay CDEL = 220nF 17 ms 10 Typical Performance Curves 100 0.12 VIN = 5V VIN = 12V 0.1 LOAD REGULATION (%) EFFICIENCY (%) 80 VIN = 5V 60 40 20 VIN = 12V 0.08 0.06 0.04 0.02 0 0 0 500 1000 0 1500 500 IO (mA) 1000 1500 2000 IO (mA) FIGURE 2. BOOST LOAD REGULATION FIGURE 1. BOOST EFFICIENCY 100 0 VIN = 5V LOAD REGULATION (%) EFFICIENCY (%) 80 VIN = 12V 60 40 20 0 -0.5 VIN = 5V VIN = 12V -1.0 -1.5 -2.0 0 500 1000 1500 IO (mA) FIGURE 3. BUCK EFFICIENCY 5 2000 0 500 1000 1500 2000 IO (mA) FIGURE 4. BUCK LOAD REGULATION FN9198.3 November 28, 2006 ISL97650 0 0 -0.1 -0.05 VON LOAD REGULATION (%) VOFF LOAD REGULATION (%) Typical Performance Curves (Continued) -0.2 -0.3 -0.4 VOFF = -8V -0.5 -0.6 -0.7 -0.1 -0.15 VON = 25V -0.2 -0.25 -0.3 -0.35 0 10 20 30 40 50 IOFF (mA) 60 70 FIGURE 5. VOFF LOAD REGULATION vs IOFF Ch1=LX(boost)(5V/DIV) Ch2=Io(Boost)(10mA/DIV) 200ns/DIV FIGURE 7. BOOST DISCONTINUOUS MODE 80 0 10 20 30 40 50 60 ION (mA) FIGURE 6. VON LOAD REGULATION vs ION Ch1=LX(boost)(5V/DIV) Ch2=Io(Boost)(10mA/DIV) 200ns/DIV FIGURE 8. THRESHOLD OF BOOST FROM DC TO CC MODE Ch1=LX(buck)(5V/DIV) Ch2=Io(Buck)(10mA/DIV) Ch1=LX(buck)(5V/DIV) Ch2=Io(Buck)(10mA/DIV) 400ns/DIV FIGURE 9. BUCK DISCONTINUOUS MODE 6 400ns/DIV FIGURE 10. THRESHOLD OF BUCK FROM DC TO CC MODE FN9198.3 November 28, 2006 ISL97650 Typical Performance Curves (Continued) Ch1 = VIN Ch2 = LX, Ch3 = AVDD, Ch4 = IINDUCTOR Ch1 = AVDD(VBOOST)(100mV/DIV) Ch2 = Io(Boost)(100mA/DIV) 1ms/DIV FIGURE 11. BOOST CONVERTER PULSE-SKIPPING MODE WAVEFORM Ch1 = VLOGIC(VBUCK)(10mV/DIV) Ch2 = Io(Buck)(100mA/DIV) FIGURE 12. TRANSIENT RESPONSE OF BOOST Ch1 = CDLY, Ch2 = VREF, Ch3 = VLOGIC, Ch4 = VON R1 = AVDD, R2 = AVDD_DELAY, R3 = VOFF 1ms/DIV FIGURE 13. TRANSIENT RESPONSE OF BUCK 7 FIGURE 14. START-UP SEQUENCE FN9198.3 November 28, 2006 ISL97650 Pin Descriptions PIN NUMBER PIN NAME 1 LX1 Internal boost switch connection 2 LX2 Internal boost switch connection 3 CB Logic buck, boost strap pin 4 LXL Buck converter output 5, 18 NC No connect. Connect to die pad and GND for improved thermal efficiency. 6 VSUP 7 FBL Logic buck feedback pin 8 CM2 Buck compensation network pin 9 CTL Input control for VON slice output 10 AGND2 11 DRN Lower reference voltage for VON slice output 12 COM VON slice output: when CTL = 1, COM is connected to SRC through a 5Ω resistor; when CTL = 0, COM is connected to DRN through a 30Ω resistor 13 POUT Positive charge pump out 14 C1- Charge pump capacitor 1, negative connection 15 C1+ Charge pump capacitor 1, positive connection 16 C2- Charge pump capacitor 2, negative connection 17 C2+ Charge pump capacitor 2, positive connection 19 FBP Positive charge pump feedback pin 20 VREF 21 FBN 22 PGND3 23 NOUT 24 VINL 25, 26 PGND2, 1 27 AGND1 28 VDC1 Internal supply decoupling capacitor 29 CDEL Delay capacitor for start up sequencing, soft-start and fault detection timers 30 ENL 31 DELB Open drain NFET output to drive optional AVDD delay PFET 32 CM1 Boost compensation network pin 33 VIN Input voltage pin 34 FBB Boost feedback pin 35 EN Enable for boost, charge pumps and VON slice (independent of ENL) 36 VDC2 Exposed Die Plate N/A 8 DESCRIPTION Positive supply for charge pumps Signal GND pin Reference voltage Negative charge pump feedback pin Power ground for VOFF, VON and VON slice Negative charge pump output Logic buck supply voltage Boost power grounds Signal ground pin Buck enable for VLOGIC output Internal supply decoupling capacitor Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See the section on "Layout Recommendations" for PCB layout thermal considerations. FN9198.3 November 28, 2006 ISL97650 Block Diagram VREF SAWTOOTH GENERATOR CM1 GM AMPLIFIER SLOPE COMPENSATION + FBB VREF ∑ UVLO COMPARATOR LX1 LX2 BUFFER CONTROL LOGIC + RSENSE PGND1 PGND2 CURRENT AMPLIFIER 0.75 VREF 1.2MHz OSCILLATOR VDC1 VIN1, VIN2 CURRENT LIMIT COMPARATOR REGULATOR REFERENCE BIAS EN AND CDEL CURRENT LIMIT THRESHOLD SEQUENCE CONTROLLER ENL DELB VDC2 VIN2 REGULATOR CB VSUP LXL NOUT CONTROL LOGIC CURRENT LIMIT COMPARATOR + FBN BUFFER CURRENT AMPLIFIER GM AMPLIFIER FBL VREF SLOPE COMPENSATION CURRENT LIMIT THRESHOLD UVLO COMPARATOR + ∑ + 0.2V CM2 SAWTOOTH GENERATOR + 0.4V UVLO COMPARATOR 0.75 VREF + + 0.75 VREF FBP SUP + VREF POUT SUP C1- 9 C1+ POUT C2+ C2- DRIV CTL COM FN9198.3 November 28, 2006 ISL97650 Typical Application Diagram VIN 6.8µF R18 4.7Ω 15V R3 55k C2 20µF C3 R1 4.7nF 10k PGND1 BOOST LX2 R16* FBB R5 DELB EN CDEL C6 0.22µF BIAS & SEQUENCE CONTROL R20 VDC1 VOFF CP VDC2 FBN 5k C11 220nF C20 820p C19 100p R6 40k NOUT C18 0.47µF R7 328k D2 C12 POUT C1VON CP C2+ C2- D3 R9 DRN C22 2.2nF R12 VON SLICE C15 0.1µF CTL COM +25V VON C14 470nF 50k VDC2 C17 0.47µF C13 470nF VSUP C21 100p R8 983k FBP -8V VOFF 220nF C1+ C18* 500kΩ PGND3 VREF C18 0.47µF C8 220nF C5 1µF LX1 CM1 PGND2 C7 220nF R4 300kΩ C4 OPEN VIN C1 2.2µF AVDD_DELAY AVDD D1 L1 R10 68k R11 1k VON SLICE R13 100kΩ VINL TO GATE DRIVER IC CB C10 10µF C9 4.7nF R2 C16 1µF CM2 BUCK 10k LXL D4 ENL FBL AGND L2 6.8µH 3.3V VLOGIC R14 2k C17 20µF R15 1.2k *Open component positions 10 FN9198.3 November 28, 2006 ISL97650 Applications Information The ISL97650 provides a complete power solution for TFT LCD applications. The system consists of one boost converter to generate AVDD voltage for column drivers, one buck converter to provide voltage to logic circuit in the LCD panel, one integrated VON charge pump and one VOFF linear-regulator controller to provide the voltage to row drivers. This part also integrates VON-slice circuit which can help to optimize the picture quality. With the high output current capability, this part is ideal for big screen LCD TV and monitor panel application. The integrated boost converter and buck converter operate at 1.2MHz which can allow to use multilayer ceramic capacitors and low profile inductor which result in low cost, compact and reliable system. The logic output voltage is independently enabled to give flexibility to the system designers. Boost Converter The boost converter is a current mode PWM converter operating at a fixed frequency of 1.2MHz. It can operate in both discontinuous conduction mode (DCM) at light load and continuous mode (CCM). In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by: V boost 1 ------------------ = ------------1–D V IN (EQ. 1) Where D is the duty cycle of the switching MOSFET. The boost converter uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60kΩ is recommended. The boost converter output voltage is determined by the following equation: R3 + R5 A VDD = --------------------- × V FBB R5 (EQ. 2) The current through the MOSFET is limited to 2.6Apeak. This restricts the maximum output current (average) based on the following equation: ΔI L V IN I OMAX = ⎛ I LMT – --------⎞ × --------⎝ ⎠ 2 VO Where ΔIL is peak to peak inductor ripple current, and is set by: V IN D ΔI L = --------- × ----L fS (EQ. 4) where fs is the switching frequency(1.2MHz). The following table gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fs and IOMAX): TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION VIN (V) VO (V) L (µH) fs (MHz) IOMAX (mA) 5 9 6.8 1.2 1138 5 12 6.8 1.2 777 4 15 6.8 1.2 560 12 15 6.8 1.2 1345 12 18 6.8 1.2 998 The minimum duty cycle of the ISL97650 is 25%. When the operating duty cycle is lower than the minimum duty cycle, the part will not switch in some cycles randomly, which will cause some LX pulses to be skipped. In this case, LX pulses are not consistent any more, but the output voltage (AVDD) is still regulated by the ratio of R3 and R5. This relationship is given by Equation 2. Because some LX pulses are skipped, the ripple current in the inductor will become bigger. Under the worst case, the ripple current will be from 0 to the threshold of the current limit. In turn, the bigger ripple current will increase the output voltage ripple. Hence, it will need more output capacitors to keep the output ripple at the same level. When the input voltage equals, or is larger than, the output voltage, the boost converter will stop switching. The boost converter is not regulated any more, but the part will still be on and other channels are still regulated. The typical waveforms of pulse-skipping mode are shown in the "Typical Performance Curves" section. Boost Converter Input Capacitor An input capacitor is used to suppress the voltage ripple injected into the boost converter. The ceramic capacitor with capacitance larger than 10µF is recommended. The voltage rating of input capacitor should be larger than the maximum input voltage. Some capacitors are recommended in Table 2 for input capacitor. TABLE 2. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/25V 1210 TDK C3225X7R1E106M 10µF/25V 1210 Murata GRM32DR61E106K (EQ. 3) 11 FN9198.3 November 28, 2006 ISL97650 Boost Inductor The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Values of 3.3µH to 10µH are to match the internal slope compensation. The inductor must be able to handle the following average and peak current: IO I LAVG = ------------1–D (EQ. 5) ΔI L I LPK = I LAVG + -------2 (EQ. 6) Some inductors are recommended in Table 3. TABLE 3. BOOST INDUCTOR RECOMMENDATION INDUCTOR 6.8µH/ 3APEAK DIMENSIONS (mm) VENDOR 7.3x6.8x3.2 TDK Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across then increases. COUT in the equation above assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts. The following table shows some selections of output capacitors. TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/25V 1210 TDK C3225X7R1E106M 10µF/25V 1210 Murata GRM32DR61E106K PART NUMBER RLF7030T-6R8N3R0 6.8µH/ 2.9APEAK 7.6X7.6X3.0 Sumida 5.2µH/ 4.55APEAK 10x10.1x3.8 Cooper CD1-5R2 Bussmann CDR7D28MNNP-6R8NC Rectifier Diode (Boost Converter) A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output voltage. The rectifier diode must meet the output current and peak inductor current requirements. The following table is some recommendations for boost converter diode. TABLE 4. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION DIODE VR/IAVG RATING PACKAGE SS23 30V/2A SMB Fairchild Semiconductor SL23 30V/2A SMB Vishay Semiconductor VENDOR Output Capacitor The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor. V O – V IN IO 1 V RIPPLE = I LPK × ESR + ------------------------ × ---------------- × ---V C f O capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. OUT s PI Loop Compensation (Boost Converter) The boost converter of ISL97650 can be compensated by a RC network connected from CM1 pin to ground. C3 = 4.7nF and R1 = 10k RC network is used in the demo board. A higher resistor value can be used to lower the transient overshoot - however, this may be at the expense of stability to the loop. The stability can be examined by repeatedly changing the load between 100mA and a max level that is likely to be used in the system being used. The AVDD voltage should be examined with an oscilloscope set to AC 100mV/div and the amount of ringing observed when the load current changes. Reduce excessive ringing by reducing the value of the resistor in series with the CM1 pin capacitor. Boost Converter Feedback Resistors and Capacitor An RC network across feedback resistor R5 may be required to optimize boost stability when AVDD voltage is set to less than 12V. This network reduces the internal voltage feedback used by the IC. This RC network sets a pole in the control loop. This pole is set to approximately fp = 10kHz for COUT = 10µF and fp = 4kHz for COUT = 30µF. Alternatively, adding a small capacitor (20-100pF) in parallel with R5 (i.e. R16 = short) may help to reduce AVDD noise and improve regulation, particularly if high value feedback resistors are used. 1 1 –1 R16 = ⎛ ⎛ --------------------------⎞ – -------- ⎞ ⎝ ⎝ 0.1 × R5 ⎠ R3 ⎠ (EQ. 8) 1 C18 = ------------------------------------------------------( 2 × 3.142 × fp × R5 ) (EQ. 9) (EQ. 7) For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output 12 FN9198.3 November 28, 2006 ISL97650 Cascaded MOSFET Application Feedback Resistors An 20V N-channel MOSFET is integrated in the boost regulator. For the applications where the output voltage is greater than 20V, an external cascaded MOSFET is needed as shown in Figure 15. The voltage rating of the external MOSFET should be greater than AVDD. The buck converter output voltage is determined by the following equation: VIN AVDD LX1, LX2 FBB INTERSIL ISL97650 R 14 + R 15 V LOGIC = --------------------------- × V FBL R 15 (EQ. 13) Where R14 and R15 are the feedback resistors of buck converter to set the output voltage Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 1kΩ is recommended. Buck Converter Input Capacitor The capacitor should support the maximum AC RMS current which happens when D = 0.5 and maximum output current. I acrms ( C IN ) = FIGURE 15. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS Buck Converter The buck converter is the step down converter, which supplies the current to the logic circuit of the LCD system. The ISL97650 integrates an 20V N-channel MOSFET to save cost and reduce external component count. In the continuous current mode, the relationship between input voltage and output voltage is as following: V LOGIC ---------------------- = D V IN (EQ. 10) Where D is the duty cycle of the switching MOSFET. Because D is always less than 1, the output voltage of buck converter is lower than input voltage. The peak current limit of buck converter is set to 2A, which restricts the maximum output current (average) based on the following equation: I OMAX = 2A – ΔI pp (EQ. 11) Where ΔIpp is the ripple current in the buck inductor as the following equation, V LOGIC ΔI pp = ---------------------- ⋅ ( 1 – D ) L ⋅ fs (EQ. 12) Where L is the buck inductor, fs is the switching frequency (1.2MHz). 13 D ⋅ ( 1 – D ) ⋅ IO (EQ. 14) Where Io is the output current of the buck converter. The following table shows some recommendations for input capacitor. TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/16V 1206 TDK C3216X7R1C106M 10µF/10V 0805 Murata GRM21BR61A106K 22µF/16V 1210 Murata C3225X7R1C226M Buck Inductor An 3.3µH-10µH inductor is the good choice for the buck converter. Besides the inductance, the DC resistance and the saturation current are also the factor needed to be considered when choosing buck inductor. Low DC resistance can help maintain high efficiency, and the saturation current rating should be 2A. Here are some recommendations for buck inductor. TABLE 7. BUCK INDUCTOR RECOMMENDATION INDUCTOR DIMENSIONS (mm) VENDOR PART NUMBER 4.7µH/ 2.7APEAK 5.7x5.0x4.7 Murata LQH55DN4R7M01K 6.8µH/ 3APEAK 7.3x6.8x3.2 TDK RLF7030T-6R8M2R8 10µH/ 2.4APEAK 12.95x9.4x3.0 Coilcraft DO3308P-103 FN9198.3 November 28, 2006 ISL97650 Rectifier Diode (Buck Converter) A Schottky diode is recommended due to fast recovery and low forward voltage. The reverse voltage rating should be higher than the maximum input voltage. The peak current rating is 2A, and the average current should be as the following equation: I avg = ( 1 – D )*I o (EQ. 15) Where Io is the output current of buck converter. The following table shows some diode recommended. TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION DIODE VR/IAVG RATING PACKAGE PMEG2020EJ 20V/2A SOD323F Philips Semiconductors SS22 20V/2A SMB Fairchild Semiconductor VENDOR Output Capacitor (Buck Converter) Four 10µF or two 22µF ceramic capacitors are recommended for this part. The overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer. TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/6.3V 0805 TDK C2012X5R0J106M 10µF/6.3V 0805 Murata GRM21BR60J106K 22µF/6.3V 1210 TDK C3216X5R0J226M 100µF/6.3V 1206 Murata GRM31CR60J107M PI Loop Compensation (Buck Converter) The buck converter of ISL97650 can be compensated by a RC network connected from CM2 pin to ground. C9 = 4.7nF and R2 = 2k RC network is used in the demo board. The larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. The stability can be optimized in a similar manner to that described in the section on "PI Loop Compensation (Boost Converter)”. Bootstrap Capacitor (C16) This capacitor is used to provide the supply to the high driver circuitry for the buck MOSFET. The bootstrap supply is formed by an internal diode and capacitor combination. A 1µF is recommended for ISL97650. A low value capacitor can lead to overcharging and in turn damage the part. If the load is too light, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. In this case, if VIN-VBUCK < 1.5V, the internal MOSFET pull-up device may be unable to turn-on until VLOGIC falls. Hence, there is a minimum load requirement in this case. The 14 minimum load can be adjusted by the feedback resistors to FBL. The bootstrap capacitor can only be charged when the higher side MOSFET is off. If the load is too light which can not make the on time of the low side diode be sufficient to replenish the boot strap capacitor, the MOSFET can’t turn on. Hence there is minimum load requirement to charge the bootstrap capacitor properly. Charge Pump Controllers (VON and VOFF) The ISL97650 includes 2 independent charge pumps (see charge pump block and connection diagram). The negative charge pump inverters the VSUP voltage and provides a regulated negative output voltage. The positive charge pump doubles or triples the VSUP voltage and provided a regulated positive output voltage. The regulation of both the negative and positive charge pumps is generated by internal comparator that senses the output voltage and compares it with the internal reference. The pumps use pulse width modulation to adjust the pump period, depending on the load present. The pumps can provide 30mA for VOFF and 20mA for VON. Positive Charge Pump Design Consideration The positive charge pump integrates all the diodes (D1, D2 and D3 shown in the “Block Diagram” on page 9) required for x2 (VSUP doubler) and x3 (VSUP Tripler) modes of operation. During the chip start-up sequence the mode of operation is automatically detected when the charge pump is enabled. With both C7 and C8 present, the x3 mode of operation is detected. With C7 present, C8 open and with C1+ shorted to C2+, the x2 mode of operation will be detected. Due to the internal switches to VSUP (M1, M2 and M3), POUT is independent of the voltage on VSUP until the charge pump is enabled. This is important for TFT applications where the negative charge pump output voltage (VOFF) and AVDD supplies need to be established before POUT. The maximum POUT charge pump current can be estimated from the following equations assuming a 50% switching duty: I MAX ( 2x ) ∼ min of 50mA or 2 • V SUP – 2 • V DIODE ( 2 • I MAX ) – V ( V ON ) ---------------------------------------------------------------------------------------------------------------------- • 0.95A ( 2 • ( 2 • R ONH + R ONL ) ) I MAX ( 3x ) ∼ min of 50mA or 3 • V SUP – 3 • V DIODE ( 2 • I MAX ) – V ( V ON ) ---------------------------------------------------------------------------------------------------------------------- • 0.95V ( 2 • ( 3 • R ONH + 2 • R ONL ) ) (EQ. 16) Note: VDIODE (2 • IMAX) is the on-chip diode voltage as a function of IMAX and VDIODE (40mA) < 0.7V. FN9198.3 November 28, 2006 ISL97650 External Connections and Components VSUP x2 Mode x3 Mode Both M2 C1C7 M4 C1+ VSUP M1 Control D3 D2 D1 1.2MHz POUT C14 0.9V VSUP Error C2+ M3 VREF C8 C2- FB C21 R8 M5 FBP C22 R9 FIGURE 16. VON FUNCTION DIAGRAM In voltage doubler configuration, the maximum VON is as given by the following equation: V ON_MAX(2x) = 2 • ( V SUP – V DIODE ) – 2 • I OUT • ( 2 • R ONH + R ONL ) (EQ. 17) For Voltage Tripler: VON_MAX(3x) = 3 • ( V SUP – V DIODE ) – 2 • I OUT • ( 3 • R ONH + 2 • RONL ) (EQ. 18) VON output voltage is determined by the following equation: R 8⎞ ⎛ V ON = V FBP • ⎜ 1 + -------⎟ R ⎝ 9⎠ (EQ. 19) Negative Charge Pump Design Consideration The negative charge pump consists of an internal switcher M1, M2 which drives external steering diodes D2 and D3 via a pump capacitor (C12) to generate the negative VOFF supply. An internal comparator (A1) senses the feedback voltage on FBN and turns on M1 for a period up to half a CLK period to maintain V(FBN) in regulated operation at 0.2V. External feedback resistor R6 is referenced to VREF. Faults on VOFF which cause VFBN to rise to more than 0.4V, are detected by comparator (A2) and cause the fault detection system to start a fault ramp on CDLY pin which will cause the chip to power down if present for more than the time TFD (see "Electrical Specification" section and also Figure “VON FUNCTION DIAGRAM” on page 15). 15 FN9198.3 November 28, 2006 ISL97650 VREF A2 C19 100pF VSUP VDD FAULT 0.4V FBN C20 820pF R6 40k A1 R7 328k 0.2V 1.2MHz STOP M2 CLK NOUT C12 220nF D2 VOFF (-8V) D3 PWM CONTROL EN C13 470nF M1 PGND FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM The maximum VOFF output voltage of a single stage charge pump is: V OFF_MAX ( 2x ) = – V SUP + V DIODE + 2 • I OUT • ( R ON ( NOUT )H + R ON ( NOUT )L ) (EQ. 20) R6 and R7 in the Typical Application Diagram determine VOFF output voltage. R7 R7 V OFF = V FBN • ⎛ 1 + --------⎞ – V REF • ⎛ --------⎞ ⎝ R6⎠ ⎝ R6⎠ (EQ. 21) Improving Charge Pump Noise Immunity Depending on PCB layout and environment, noise pick-up at the FBP and FBN inputs, which may degrade load regulation performance, can be reduced by the inclusion of capacitors across the feedback resistors (e.g. in the Application Diagram, C21 and C22 for the positive charge pump). Set R6 • C20 = R7 • C19 with C19 ~ 100pF. VON Slice Circuit The VON Slice Circuit functions as a three way multiplexer, switching the voltage on COM between ground, DRN and SRC, under control of the start-up sequence and the CTL pin. During the start-up sequence, COM is held at ground via an NDMOS FET, with ~1k impedance. Once the start-up sequence has completed, CTL is enabled and acts as a multiplexer control such that if CTL is low, COM connects to DRN through a 30Ω internal MOSFET, and if CTL is high, COM connects to POUT internally via a 5Ω MOSFET. 16 The slew rate of start-up of the switch control circuit is mainly restricted by the load capacitance at COM pin as following equation: Vg ΔV -------- = -----------------------------------( R i || R L ) × C L Δt (EQ. 22) Where Vg is the supply voltage applied to DRN or voltage at POUT, which range is from 0V to 36V. Ri is the resistance between COM and DRN or POUT including the internal MOSFET rDS(On), the trace resistance and the resistor inserted, RL is the load resistance of switch control circuit, and CL is the load capacitance of switch control circuit. In the Typical Application Circuit, R10, R11 and C15 give the bias to DRN based on the following equation: V ON ⋅ R 11 +AVDD ⋅ R 10 V DRN = --------------------------------------------------------------R 10 + R 11 (EQ. 23) And R12 can be adjusted to adjust the slew rate. FN9198.3 November 28, 2006 CHIP DISABLED FAULT DETECTED VON SOFT-START VOFF, DELB ON VREF, VLOGIC ON AVDD SOFT-START ISL97650 VCDLY VIN EN VREF VBOOST tSTART-UP tSS VLOGIC VOFF tVOFF DELAYED VBOOST tVON VON VON SLICE tVON-SLICE START-UP SEQUENCE TIMED BY CDLY NOTE: Not to scale NORMAL OPERATION FAULT PRESENT FIGURE 18. START-UP SEQUENCE Start-Up Sequence Figure 18 shows a detailed start up sequence waveform. For a successful power up, there should be 6 peaks at VCDLY. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. When the input voltage is higher than 3.85V, VREF turns on, as well as VLOGIC if the ENL is high. an internal current source starts to charge CCDLY to an upper threshold using a 17 fast ramp followed by a slow ramp. During the initial slow ramp, the device checks whether there is a fault condition. If no fault is found, CCDLY is discharged after the first peak and VREF turns on. Initially the boost is not enabled so AVDD rises to VINVDIODE through the output diode. Hence, there is a step at AVDD during this part of the start-up sequence. If this step is not desirable, an external PMOS FET can be used to delay FN9198.3 November 28, 2006 ISL97650 the output until the boost is enabled internally. The delayed output appears at AVDD. AVDD soft-starts at the beginning of the third ramp. The soft start ramp depends on the value of the CDLY capacitor. For CDLY of 220nF, the soft-start time is ~9.6ms. VOFF turns on at the start of the fourth peak. At the same time, DELB gate goes low to turn on the external PMOS to generate a delayed AVDD output. VON is enabled at the beginning of the sixth ramp. Once the start-up sequence is complete, the voltage on the CDLY capacitor remains at 1.15V until either a fault is detected or the EN pin is disabled. If a fault is detected, the voltage on CDLY rises to 2.4V at which point the chip is disabled until the power is cycled or enable is toggled. AVDD_delay Generation Using DELB DELB pin is an open drain internal N-FET output used to drive an external optional P-FET to provide a delayed AVDD supply which also has no initial pedistal voltage (see Figure 14 and compare the AVDD and AVDD_delayed curves). When the part is enabled, the N-FET is held off until CDLY reaches the 4th peak in the start-up sequence. During this period, the voltage potential of the source and gate of the external P-FET (M0 in application diagram) should be almost the same due to the presence of the resistor (R4) across the source and gate, hence M0 will be off. Please note that the maximum leakage of DELB in this period is 500nA. To avoid any mis-trigger, the maximum value of R4 should be less than: V GS ( th )_min(M0) R 4_max < -------------------------------------------500nA (EQ. 24) Where VGS(th)_min(M0) is the minimum value of gate threshold voltage of M0. After CDLY reaches the 4th peak, the internal N-FET is turned-on and produces an initial current output of IDELB_ON1 (~50µA). This current allows the user to control the turn-on inrush current into the AVDD_delay supply capacitors by a suitable choice of C4. This capacitor can provide extra delay and also filter out any noise coupled into the gate of M0, avoiding spurious turn-on, however, C4 must not be so large that it prevents DELB reaching 0.6V by the end of the start-up sequence on CDLY, else a fault time-out ramp on CDLY will start. A value of 22nF is typically required for C4. The 0.6V threshold is used by the chip's fault detection system and if V(DELB) is still above 0.6V at the end of the power sequencing then a fault time-out ramp will be initiated on CDLY. If the maximum VGS voltage of M0 is less than the AVDD voltage being used, then a resistor may be inserted between the DELB pin and the gate of M0 such that it's potential divider action with R4 ensures the gate/source stays below VGS(M0)max. This additional resistor allows much larger values of C4 to be used, and hence longer AVDD delay, without affecting the fault protection on DELB. Component Selection for Start-up Sequencing and Fault Protection The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 22nF to 1µF and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. The CDEL capacitor is typically 220nF and has a usable range from 47nF minimum to several microfarads - only limited by the leakage in the capacitor reaching µA levels. CDEL should be at least 1/5 of the value of CREF (see above). Note, with 220nF on CDEL, the fault time-out will be typically 50ms. and the use of a larger/smaller value will vary this time proportionally (e.g. 1µF will give a fault time-out period of typically 230ms). Fault Sequencing The ISL97650 has advanced overall fault detection systems including Over Current Protection (OCP) for both boost and buck converters, Under Voltage Lockout Protection (UVLP) and Over-Temperature Protection. Once the peak current flowing through the switching MOSFET of the boost and buck converters triggers the current limit threshold, the PWM comparator will disable the output, cycle by cycle, until the current is back to normal. The ISL97650 detects each feedback voltage of AVDD, VON, VOFF and VLOGIC. If any of the VON, VOFF or AVDD feedback is lower than the fault threshold, then a timed fault ramp will appear on CDEL. If it completes, then VON, VOFF and AVDD will shut down, but VLOGIC will stay on. If VLOGIC feedback is lower than fault threshold, then all channels will switch off, and VIN or Enable needs recycling to turn them on again. An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point of +150°C, the device will shut down. Operation with die temperatures between +125°C and +150°C can be tolerated for short periods of time, however, in order to maximize the operating life of the IC, it is recommended that the effective continuous operating junction temperature of the die should not exceed +125°C. When the voltage at DELB falls below ~0.6V it's current is increased to IDELB_ON2 (~1.4mA) to firmly pull the DELB voltage to ground. 18 FN9198.3 November 28, 2006 ISL97650 Layout Recommendation The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VDC bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. Minimize feedback input track lengths to avoid switching noise pick-up. A demo board is available to illustrate the proper layout implementation. 19 FN9198.3 November 28, 2006 ISL97650 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) L36.6x6 2X 0.15 C A D A 36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C) D/2 MILLIMETERS 2X 6 INDEX AREA N 0.15 C B 1 2 3 SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - 0.30 5, 8 4.05 7, 8 A3 E/2 b E D D2 B TOP VIEW 0.20 REF 0.18 6.00 BSC 3.80 C 0.08 C SEATING PLANE A3 SIDE VIEW A1 - E 6.00 BSC - 5.75 BSC 9 3.80 e / / 0.10 C 3.95 E1 E2 A 0.25 3.95 4.05 0.50 BSC 7, 8 - k 0.20 - - - L 0.45 0.55 0.65 8 N 36 2 Nd 9 3 Ne 9 3 Rev. 2 04/06 NX b 5 0.10 M C A B D2 NX k D2 2 (DATUM B) 8 7 N (DATUM A) 6 INDEX AREA E2 E2/2 3 2 1 NX L N 7 (Ne-1)Xe REF. 8 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. e 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 SECTION "C-C" All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN9198.3 November 28, 2006