EL7584 ® Data Sheet February 4, 2005 4-Channel DC/DC Converter Features The EL7584 is a 4-channel DC/DC converter IC which is designed primarily for use in TFT-LCD applications. The boost converter has 2V to 14V input capability and provides 5V to 17V output, which powers the column drivers and provides up to 370mA @ 15V. A pair of charge pump control circuits provide outputs to allow the external generation of VON and VOFF supplies at 5V to 40V and 0V to -40V, respectively, each at up to 60mA for VBOOST = 15V. The VCOM buffer provides up to 50mA continuous output current from 2V to 13V. • TFT-LCD display supply - Boost regulator - VCOM buffer - VON charge pump - VOFF charge pump The EL7584 features adjustable switching frequency and onchip power sequence to simplify start-up operation. A separate input is available to externally increase the default delay of the positive charge pump. An over-temperature feature is provided to allow the IC to be automatically protected from excessive power dissipation. The EL7584 is available in a 24-pin TSSOP package and is specified for operation over the full -40°C to +85°C temperature range. FN7317.2 • 2V to 14V VIN supply • 5V < VBOOST < 17V • 2V < VCOM < 13V • 5V < VON < 40V • -40V < VOFF < 0V • VBOOST = 15V @ 370mA • High frequency, small inductor DC/DC boost circuit • Over 90% efficient DC/DC boost converter capability • Built-in power-up sequence with adjustable VON delay • Adjustable frequency • Adjustable soft-start Pinout • Adjustable outputs EL7584 (24-PIN TSSOP) TOP VIEW • Over-temperature protection • Small parts count SS 1 24 VSSB • Pb-free available (RoHS compliant) FBB 2 23 ROSC Applications EN 3 22 VREF • TFT-LCD panels VDDB 4 21 PGND • PDAs LX1 5 20 PGND Ordering Information LX2 6 19 VSSP VSSN 7 18 DRVP DRVN 8 VDDN 9 PART NUMBER PACKAGE TAPE & REEL PKG. DWG. # EL7584IR 24-Pin TSSOP - MDP0044 17 VDDP EL7584IR-T7 24-Pin TSSOP 7” MDP0044 16 FBP EL7584IR-T13 24-Pin TSSOP 13” MDP0044 FBN 10 15 VSSC EL7584IRZ (See Note) 24-Pin TSSOP (Pb-free) - MDP0044 DP 11 14 VCOM EL7584IRZ-T7 (See Note) 24-Pin TSSOP (Pb-free) 7” MDP0044 INC 12 13 VDDC EL7584IRZ24-Pin TSSOP T13 (See Note) (Pb-free) 13” MDP0044 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL7584 Absolute Maximum Ratings (TA = 25°C) LX Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V VDDB, VDDP, VDDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V VDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Maximum Continuous VBOOST Output Current. . . . . . . . . . . 800mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VIN = 3.3V, VBOOST = 12V, ROSC = 62kΩ, TA = 25°C, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT DC/DC BOOST CONVERTER IQ1_B Quiescent Current - Shut-down EN = 0V 0.8 10 µA IQ2_B Quiescent Current - Switching EN = VDDB 4.8 8 mA V(FBB) Feedback Voltage 1.275 1.300 1.325 V VREF Reference Voltage 1.260 1.310 1.360 V VROSC Oscillator Set Voltage 1.260 1.325 1.390 V I(FBB) Feedback Input Bias Current VDDB Boost Converter Supply Range 2 DMAX Maximum Duty Cycle 85 I(LX)MAX Peak Internal FET Current RDS-ON Switch On Resistance at VBOOST = 10V, I(LX) total = 350mA ILEAK-SWITCH Switch Leakage Current I(LX) total VBOOST Output Range VBOOST > VIN + VDIODE ∆VBOOST/∆VIN Line Regulation 2.7V < VIN < 13.2V, VBOOST = 15V 0.1 % ∆VBOOST/∆IO1 Load Regulation 50mA < IO1 < 250mA 0.5 % FOSC-RANGE Frequency Range ROSC range = 240kΩ to 60kΩ 200 FOSC1 Switching Frequency ROSC = 62kΩ 900 0.1 µA 17 V 92 % 1.75 A 0.22 Ω 5 1000 1 µA 17 V 1200 kHz 1100 kHz 15 V VCOM BUFFER VDDC Supply Voltage Range IQ1, VDDC VDDC Disable Current VDDC = 12V, EN = 0V 5.5 20 µA IQ2, VDDC VDDC Enable Current VDDC = 12V, VEN = VDDB, no load 1.7 5 mA VCOM-offset Accuracy of VCOM Output Voltage 2V < VCOM < (VDDC - 2V) -10 +10 mV I(INC) VCOM Input Bias Currents Current magnitude -0.1 0.1 µA RO(VCOM) VCOM Output Impedance VDDC = VBOOST = 12V, VCOM = 6V with -100mA < ILOAD < 100mA CLOAD for VCOM > 0.47µF, MLCC ICOM(max) Output Current Limit PSRR Supply Voltage Rejection VINC = VDDC/2, 9V < VDDC < 15V CMRR Common Mode Voltage Rejection VDDC = 12V, 2V < VINC < 10V 2 6 0.01 0.25 Ω 150 mA 60 102 dB 60 93 dB FN7317.2 February 4, 2005 EL7584 Electrical Specifications PARAMETER VIN = 3.3V, VBOOST = 12V, ROSC = 62kΩ, TA = 25°C, Unless Otherwise Specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT POSITIVE REGULATED CHARGE PUMP (VON) Most positive VON output depends on the magnitude of the VDDP input voltage (normally connected to VBOOST) and the external component configuration (doubler or tripler) VDDP Supply Input for Positive Charge Pump Usually connected to VBOOST output IQ1(VDDP) Quiescent Current - Shut-down EN = 0V IQ2(VDDP) Quiescent Current - Switching EN = VDDB IDP1 Disable Charge Current EN = 0V, DP = 0V IDP2 Enable Discharge Current EN = VDDB, DP = 5V V(FBP) Feedback Reference Voltage I(FBP) Feedback Input Bias Current I(DRVP) RMS DRVP Output Current 5 17 V 11.5 20 µA 2.3 5 mA 1.5 1.9 2.5 mA 100 200 300 nA 1.245 1.310 1.375 V VDDP = 12V VDDP = 6V ILR_VON Load Regulation 5mA < IL < 15mA FPUMP Charge Pump Frequency Frequency set by ROSC - see boost section 0.1 µA 60 mA 15 -0.5 mA 0.03 0.5 %/mA 0.5*FOSC NEGATIVE REGULATED CHARGE PUMP (VOFF) Most negative VOFF output depends on the magnitude of the VDDN input voltage (normally connected to VBOOST) and the external component configuration (doubler or tripler) VDDN Supply Input for Negative Charge Pump Usually connected to VBOOST output 5 IQ1(VDDN) Quiescent Current - Shut-down ENBN = 0V IQ2(VDDN) Quiescent Current - Switching ENBN = VDDB V(FBN) Feedback Reference Voltage I(FBN) Feedback Input Bias Current Magnitude of input bias 0.1 µA I(DRVN) RMS DRVN Output Current VDDN = 12V 60 mA -80 VDDN = 6V ILR_VOFF Load Regulation -15mA < IL < -5mA FPUMP Charge Pump Frequency Frequency set by ROSC - see boost section 17 V 4.5 20 µA 2.3 5 mA 0 +80 mV 15 -0.5 mA 0.03 0.5 %/mA 0.5*FOSC ENABLE CONTROL LOGIC VHI-EN Enable Input High Threshold VLO-EN Enable Input Low Threshold I(EN) Enable Input Bias Current 1.6 VEN = 5V V 3.7 0.5 V 7.5 µA OVER-TEMPERATURE PROTECTION TOT Over-temperature Threshold 130 °C THYS Over-temperature Hysteresis 40 °C 3 FN7317.2 February 4, 2005 EL7584 Pin Descriptions I = Input, O = Output, S = Supply PIN NUMBER PIN NAME PIN TYPE PIN FUNCTION 1 SS I Soft-Start input: a capacitor determines the current limit ramp time. 2 FBB I Voltage feedback input determines the value of VBOOST. 3 EN I Starts internal power sequencing of VBOOST, VOFF, VCOM and VON outputs (See Applications Information) ; active HIGH input. 4 VDDB P Positive supply for VBOOST DC/DC controller. 5 LX1 O Boost inductor saturating MOSFET #1. 6 LX2 O Boost inductor saturating MOSFET #2. 7 VSSN* P Ground return for VOFF regulator. 8 DRVN O Pump capacitor driver for VOFF regulator. 9 VDDN P Positive supply for VOFF regulator. 10 FBN I Voltage feedback input determines the value of VOFF. 11 DP I An external capacitor increases VON power up delay time. 12 INC I VCOM Buffer input. 13 VDDC P Positive supply for VCOM Buffer. 14 VCOM O VCOM Buffer output. 15 VSSC* P Ground return for VCOM Buffer. 16 FBP I Voltage feedback input determines the value of VON. 17 VDDP P Positive supply for VON regulator. 18 DRVP O Pump capacitor driver for VON regulator. 19 VSSP* P Ground return for VON regulator. 20 PGND* P Ground return for MOSFET #1. 21 PGND* P Ground return for MOSFET #2. 22 VREF O Voltage reference for VOFF feedback . 23 ROSC I An external resistor sets the DC/DC switching frequency. 24 VSSB* P Ground return for VBOOST DC/DC controller. NOTE: *VSSB, VSSC, VSSN, VSSP, and PGND (2) are shorted internally to the device substrate. 4 FN7317.2 February 4, 2005 EL7584 Typical Performance Curves 95 95 90 15V EFFICIENCY (%) EFFICIENCY (%) 9V 80 9V 90 5V 85 12V 75 70 65 12V 85 15V 80 75 70 60 65 VIN=3.3V FREQ=1MHz 55 VIN=5V FREQ=1MHz 60 50 0 100 200 300 400 500 600 700 800 0 100 200 300 FIGURE 1. EFFICIENCY vs IOUT 600 700 800 FIGURE 2. EFFICIENCY vs IOUT 95 95 90 90 5V 85 9V 12V 15V 80 EFFICIENCY (%) EFFICIENCY (%) 500 IOUT (mA) IOUT (mA) 75 70 65 12V 15V 85 9V 80 75 70 65 VIN=3.3V FREQ=700kHz 60 VIN=5V FREQ=700kHz 60 0 100 200 300 400 500 600 700 800 0 100 200 IOUT (mA) 300 400 500 600 700 800 IOUT (mA) FIGURE 3. EFFICIENCY vs IOUT FIGURE 4. EFFICIENCY vs IOUT 1.27 970 ROSC = 61.9kΩ 969 1.265 968 VOLTAGE (V) FREQUENCY (kHz) 400 967 966 965 1.26 1.255 964 963 962 3 3.5 4 4.5 5 VDDB (V) FIGURE 5. FS vs VDDB 5 5.5 6 1.25 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 6. VREF vs TEMPERATURE FN7317.2 February 4, 2005 EL7584 Typical Performance Curves (Continued) 1.5 f=675kHz, VIN=5.0V 1.5 1.0 LOAD REGULATION (%) LOAD REGULATION (%) 1.0 f=675kHz, VIN=3.3V 0.5 0.0 -0.5 -1.0 18V -1.5 0 100 200 300 15V 12V 0.0 -0.5 15V -1.0 18V 9V 12V 700 600 0 100 200 300 f=1MHz, VIN=5.0V 1.5 1.0 500 600 700 800 f=1MHz, VIN=3.3V 1.0 LOAD REGULATION (%) LOAD REGULATION (%) 400 FIGURE 8. LOAD REGULATION vs IOUT FIGURE 7. LOAD REGULATION vs IOUT 0.5 0.0 -0.5 -1.0 18V 9V 12V 0 100 200 300 500 400 0.5 0.0 -0.5 15V 12V -1.0 9V 18V 15V -1.5 600 5V -1.5 700 0 100 200 300 400 500 600 700 800 IOUT (mA) IOUT (mA) FIGURE 9. LOAD REGULATION vs IOUT FIGURE 10. LOAD REGULATION vs IOUT 6.5 20 19 VDDN = 15V 6 VDDP = 15V VDDN = 12V 5.5 18 VDDP = 12V VOFF (-V) VON (V) 5V IOUT (mA) IOUT (mA) 1.5 9V -1.5 500 400 0.5 17 5 16 4.5 15 4 3.5 14 0 10 20 30 40 50 ILOAD (mA) FIGURE 11. VON vs ION 6 60 70 80 0 10 20 30 40 50 60 70 80 ILOAD (mA) FIGURE 12. VOFF vs IOFF FN7317.2 February 4, 2005 EL7584 Typical Performance Curves (Continued) 1400 f(MHz)=1/(0.0118 ROSC+0.378) 6 SWITCHING PERIOD (µs) FREQUENCY (kHz) 1200 1000 800 600 400 200 SWITCHING PERIOD(µs)=0.0118 ROSC+0.378) 5 4 3 2 1 0 0 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 ROSC (kΩ) 100K & 0.1µF DELAY NETWORK ON ENP, CSS=0.1µF 5V/DIV VBOOST 5V/DIV 10V/DIV VON VON VOFF 200ms/DIV FIGURE 15. POWER-DOWN VIN=3.3V, VOUT=11.3V, IOUT=50mA FIGURE 17. LX WAVEFORM - DISCONTINUOUS MODE 7 450 100K & 0.1µF DELAY NETWORK ON ENP, CSS=0.1µF VBOOST 2V/DIV 400 FIGURE 14. FS vs ROSC FIGURE 13. FS vs ROSC 10V/DIV 350 ROSC (kΩ) 2V/DIV VOFF 1ms/DIV FIGURE 16. POWER-UP VIN=3.3V, VOUT=11.3V, IOUT=250mA FIGURE 18. LX WAVEFORM - CONTINUOUS MODE FN7317.2 February 4, 2005 EL7584 Typical Performance Curves (Continued) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 0.8 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 1.176W TS SO θ JA P2 =8 4 5° C/ W 1 0.8 0.6 0.4 0.2 781mW 0.7 0.6 θ JA 0.5 0.4 TS SO P2 =1 4 28 °C /W 0.3 0.2 0.1 0 0 0 25 75 85 50 100 0 125 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Functional Block Diagram VOUT 10µH R2 R1 13kΩ VIN 110kΩ 49Ω 10µF 10µF 0.1µF FBB VDDB LX MAX_DUTY ROSC R3 62kΩ REFERENCE GENERATOR VREF VRAMP PWM LOGIC PWM COMPARATOR 0.22Ω EN 12µA + START-UP OSCILLATOR ILOUT VSSB 7.2K 160mΩ SS PGND 0.1µF 8 FN7317.2 February 4, 2005 EL7584 Applications Information Steady-State Operation The EL7584 is high efficiency multiple output power solution designed specifically for thin-film transistor (TFT) liquid crystal display (LCD) applications. The device contains one high current boost converter and two low power charge pumps (VON and VOFF). When the output reaches the preset voltage, the regulator operates at steady state. Depending on the input/output condition and component, the inductor operates at either continuous-conduction mode or discontinuous-conduction mode. The boost converter contains an integrated N-channel MOSFET to minimize the number of external components. The converter output voltage can be set from 5V to 18V with external resistors. The VON and VOFF charge pumps are independently regulated to positive and negative voltages using external resistors. Output voltages as high as 40V can be achieved with additional capacitors and diodes. In the continuous-conduction mode, the inductor current is a triangular waveform and LX voltage a pulse waveform. In the discontinuous-conduction mode, the inductor current is completely ‘dried-out’ before the MOSFET is turned on again. The input voltage source, the inductor, and the MOSFET and output diode parasitic capacitors forms a resonant circuit. Oscillation will occur in this period. This oscillation is normal and will not affect the regulation. Boost Converter The boost converter operates in constant frequency pulsewidth-modulation (PWM) mode. Quiescent current for the EL7584 is only 5mA when enabled, and since only the low side MOSFET is used, switch drive current is minimized. 90% efficiency is achieved in most common application operating conditions. A functional block diagram with typical circuit configuration is shown on previous page. Regulation is performed by the PWM comparator which regulates the output voltage by comparing a divided output voltage with an internal reference voltage. The PWM comparator outputs its result to the PWM logic. The PWM logic switches the MOSFET on and off through the gate drive circuit. Its switching frequency is external adjustable with a resistor from timing control pin (ROSC) to ground. The boost converter has 200kHz to 1.2MHz operating frequency range. At very low load, the MOSFET will skip pulse sometimes. This is normal. Current Limit The MOSFET is current limited to <1.75Amps (nominal). This restricts the maximum output current IOMAX based on the following formula: V IN I OMAX = I LMT – ∆L ------- × -------- VO 2 where: • ∆IL is the inductor peak-to-peak current ripple and is decided by: V IN D ∆I L = --------- × ------L FS Start-Up • D is the MOSFET turn-on radio and is decided by: After VDDB reaches a threshold of about 2V, the power MOSFET is controlled by the start-up oscillator, which generates fixed duty-ratio of 0.5 - 0.7 at a frequency of several hundred kilohertz. This will boost the output voltage, providing the initial output current load is not too great (<250mA). V O - V IN D = ----------------------VO • FS is the switching frequency. When VDDB reaches about 3.7V, the PWM comparator takes over the control. The duty ratio will be decided by the multiple-input direct summing comparator, Max_Duty signal (about 90% duty-ratio), and the Current Limit Comparator, whichever is the smallest. The soft-start is provided by the current limit comparator. As the internal 12µA current source charges the external softstart capacitor, the peak MOSFET current is limited by the voltage on the capacitor. This in turn controls the rising rate of output voltage. The regulator goes through the start-up sequence as well after the EN signal is pulled to HI. 9 FN7317.2 February 4, 2005 EL7584 The following table gives typical values: (Margins are considered 10%, 3%, 20%, 10%, and 15% on VIN, VO, L, FS, and ILMT, respectively) TABLE 1. MAXIMUM CONTINUOUS OUTPUT CURRENT VIN (V) VO (V) L (µH) FS (kHz) IOMAX (mA) 3.3 9 10 1000 430 3.3 12 10 1000 320 3.3 15 10 1000 250 5 9 10 1000 650 5 12 10 1000 470 5 15 10 1000 370 12 18 10 1000 830 Component Considerations Input Capacitor It is recommended that CIN is larger than 10µF. Theoretically, the input capacitor has ripple current of ∆IL. Due to high-frequency noise in the circuit, the input current ripple may exceed the theoretical value. Larger capacitor will reduce the ripple further. Boost Inductor The inductor has peak and average current decided by: ∆I I LPK = I LAVG + --------L 2 Schottky Diode Speed, forward voltage drop, and reverse current are the three most critical specifications for selecting the Schottky diode. The entire output current flows through the diode, so the diode average current is the same as the average load current and the peak current is the same as the inductor peak current. When selecting the diode, one must consider the forward voltage drop at the peak diode current. On the Elantec demo board, MBRM120 is selected. Its forward voltage drop is 450mV at 1A forward current. Output Capacitor The EL7584 is specially compensated to be stable with capacitors which have a worst-case minimum value of 10µF at the particular VOUT being set. Output ripple voltage requirements also determine the minimum value and the type of capacitors. Output ripple voltage consists of two components - the voltage drop caused by the switching current though the ESR of the output capacitor and the charging and discharging of the output capacitor: I OUT V OUT - V IN V RIPPLE = I LPK × ESR + ------------------------------- × -----------------------------C × FS V OUT OUT For low ESR ceramic capacitors, the output ripple is dominated by the charging/discharging of the output capacitor. In addition to the voltage rating, the output capacitor should also be able to handle the RMS current is given by: IO I LAVG = ------------1-D The inductor should be chosen to be able to handle this current. Furthermore, due to the fixed internal compensation, it is recommended that maximum inductance of 10µH and 15µH to be used in the 5V and 12V or higher output voltage, respectively. The output diode has average current of IO, and peak current the same as the inductor's peak current. Schottky diode is recommended and it should be able to handle those currents. Feedback Resistor Network An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 200kΩ is recommended. The boost converter output voltage is determined by the following relationship: I CORMS = 2 ∆I L 1 ( 1 - D ) × D + ------------------- × ------ × I LAVG 2 12 I LAVG Positive and Negative Charge Pump (VON and VOFF) The EL7584 contains two independent charge pumps (see charge pump block and connection diagram.) The negative charge pump inverts the VDDN supply voltage and provides a regulated negative output voltage. The positive charge pump doubles the VDDP supply voltage and provides a regulated positive output voltage. The regulation of both the negative and positive charge pumps is generated by the internal comparator that senses the output voltage and compares it with and internal reference. The switching frequency of the charge pump is set to ½ the boost converter switching frequency. The pumps use pulse width modulation to adjust the pump period, depending on the load present. The pumps are shortcircuit protected to 180mA at 12V supply and can provide 15mA to 60mA for 6V to 12V supply. R1 + R2 V BOOST = --------------------- × V FBB R1 where VFBB is 1.300V. 10 FN7317.2 February 4, 2005 EL7584 Single Stage Charge Pump VDDN 5V TO 17V VDDP 5V TO 17V 0.1µF 0.1µF CCPP RONP RONP DRVN OSC DRVP CCPN VOFF RONN COUT2 RONN 3.3µF R21 FBN V COUT1ON VSSP VSSN 2.2µF FBP + + - R12 + - VFBP R11 RON IS 30 - 40Ω FOR VDD 6V TO 12V R22 VREF Positive Charge Pump Design Considerations A single stage charge pump is shown above. The maximum VON output voltage is determined by the following equation: 1 1 V ON ( max ) ≤ 2 × V DDCPP - I OUT × 2 × ( R ONN + R ONP ) - 2 × V DIODE - I OUT × -------------------------------------------- - I OUT × -----------------------------------------------0.5 × F × C 0.5 × F × C S CPP S OUT1 where: • RONN and RONP resistance values depend on the VDDP voltage levels. For 12V supply, RON is typically 33Ω. For 6V supply, RON is typically 45Ω. If additional stage is required, the LX switching signal is recommended to drive the additional charge pump diodes. The drive impedance at the LX switching is typically 150mΩ. The figure below illustrates an implementation for two-stage positive charge pump circuit. 11 FN7317.2 February 4, 2005 EL7584 Two-Stage Positive Charge Pump Circuit VDDP VBOOST (5V-17V) VLX RONP CCPP DRNP VON CCPP RONN COUT1 COUT1 VSSP R12 + FBP 1.265V + - R11 The maximum VON output voltage for N+1 stage charge pump is: 1 V ON ( max ) ≤ 2 × V DDP - I OUT × 2 × ( R ONN + R ONP ) - 2 × V DIODE - I OUT × -------------------------------------------- - I OUT × 0.5 × F × C S CPP 1 1 1 ------------------------------------------------ + N × V LX ( max ) - N × 2 × V DIODE + I OUT × -------------------------------------------- + I OUT × ------------------------------------------------ 0.5 × F S × C OUT1 0.5 × F S × C CPP 0.5 × F S × C OUT1 R11 and R12 set the VON output voltage: R 11 + R 12 V ON = V FBP × --------------------------R 11 where VFBP is 1.310V. Negative Charge Pump Design Considerations The criteria for the negative charge pump is similar to the positive charge pump. For a single stage charge pump, the maximum VOFF output voltage is: 1 1 V OFF ( max ) ≥ I OUT × 2 × ( R ONN + R ONP ) + 2 × V DIODE - IOUT × -------------------------------------------- - I OUT × ------------------------------------------------ - V DDN 0.5 × F × C 0.5 × F × C S CPN S OUT2 Similar to positive charge pump, if additional stage is required, the LX switching signal is recommended to drive the additional charge pump diodes. The figure on the next page shows a two stage negative charge pump circuit. 12 FN7317.2 February 4, 2005 EL7584 Two-Stage Negative Charge Pump Circuit VDDN 5V-17V VLX RONP CCPN DRVN RONN CCPN VOFF COUT2 COUT2 VSSN + - R21 FBN R22 VREF The maximum VOFF output voltage for N+1 stage charge pump is: 1 1 V OFF ( max ) ≥ I OUT × 2 × ( R ONN + R ONP ) + 2 × V DIODE - I OUT × -------------------------------------------- - I OUT × ------------------------------------------------ 0.5 × F × C 0.5 × F × C S CPN 1 1 V DDN - N × V LX ( max ) + N × 2 × V DIODE + I OUT × -------------------------------------------- + I OUT × ------------------------------------------------ 0.5 × F S × C CPN 0.5 × F S × C OUT2 S OUT2 R21 and R22 determine VOFF output voltage: R 21 V OFF = -V REF × ---------R 22 where VREF is 1.310V. The VCOM Buffer The VCOM buffer is designed to control the voltage on the back plane of an LCD display. This plane is capacitively coupled to the pixel drive voltage which alternately cycles positive and negative at the line rate for the display. Thus the amplifier must be capable of sourcing and sinking capacitive pulses of current, which can occasionally be quite large (a few 100mA for typical applications). The use of the VCOM Buffer is illustrated in Figure 21. Here, a voltage, corresponding to the mid-DAC potential, is generated by a resistive divider and buffered by the amplifier. The amplifier's stability is designed to be dominated by the load capacitance, thus for very short duration pulses (< 1µs) the output capacitor supplies the current. For longer pulses the VCOM buffer supplies the current. By virtue of its high transconductance which progressively increases as more current is drawn, it can maintain regulation within 5mV as currents up to 50mA are drawn, while consuming only 1.5mA of quiescent current. If VBOOST exceeds 15V, VDDC must be protected from overvoltage by including a zener diode between VBOOST and VDDC. VBOOST 0.1µF R32 INC R31 + VDDC - V SSC VCOM VCOM 1µF CERAMIC LOW ESR FIGURE 21. VCOM USED AS A VOLTAGE BUFFER As with any high performance buffer, there are several design issues that must be considered when using the part. These are summarized below. Good Decoupling of Power Supplies This is essential for this component and 1µF ceramic low ESR decoupling capacitors are recommended. These should be placed close to the pins. Choice of Output Capacitor A 1µF ceramic capacitor with low ESR (X5R or X7R type) is recommended for this amplifier. This capacitor determines the stability of the amplifier. Reducing it will make the amplifier less stable, and should be avoided. With a 1µF capacitor, the unity gain bandwidth of the amplifier is close to 13 FN7317.2 February 4, 2005 EL7584 500kHz when reasonable currents are being drawn. (For lower load currents, the gain and hence bandwidth progressively decreases.) This means the active transconductance is: 2π × 1µF × 500kHz = 3.14S This high transconductance indicates why it is important to have a low ESR capacitor. If: • ESR * 3.14 > 1 then the capacitor will not force the gain to roll off below unity, and subsequent poles can affect stability. The recommended capacitor has an ESR of 10mΩ, but to this must be added the resistance of the board trace between the capacitor and the VCOM pin, where the sense connection is made internally - therefore this should be kept short. Also ground resistance between the capacitor and the base of R2 must be kept to a minimum. These constraints should be considered when laying out the PCB. If the capacitor is increased above 1µF, stability is generally improved and short pulses of current will cause a smaller “perturbation” on the VCOM voltage. The speed of response of the amplifier is however degraded as its bandwidth is decreased. At capacitor values around 10µF, a subtle interaction with internal DC gain boost circuitry will decrease the phase margin and may give rise to some overshoot in the response. The amplifier will remain stable, though. Response to High Current Spikes The VCOM amplifier's output current is limited to 180mA. This limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. It does not necessarily prevent a large temperature rise if the current is maintained. (In this case the whole chip may be shut down by the thermal trip to protect functionality.) If the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. This will happen on the µs time scale in practical systems and for pulses 2 or 3 times the current limit, the VCOM voltage will have settled again before the next line is processed. Power-Up Sequencing With the components shown in the application diagram the on-chip power-up sequencing operates as follows. When the EN pin is taken to logic 1, the following sequence is followed by on-chip functions: and the current capability of these negative charge pumps (which is rising as VBOOST and hence VDDN rises.) 2. When VBOOST reaches a voltage such that V(FBB)> 1.13V and VOFF first reaches its required regulation voltage, the VCOM regulator is enabled and VCOM rises at a rate determined by the VCOM load capacitor, the load on VCOM, and the current limit of the VCOM amplifier. 3. When VCOM rises to within 100mV of V(INC), an internal delay circuit triggers and, for VDDP = 12V, a default delay of approximately 3.5ms is introduced before the positive charge pump is then enabled. This delay can be increased externally by connecting a capacitor between DP and VSSP. A 1nF capacitor will typically increase the delay before VON becomes enabled to 80ms. The enabled states of the on-chip functions become independent of VBOOST, VOFF, VCOM, and VON once each is triggered. The chip may be reset by forcing EN to logic 0 and allowing sufficient time for the various supplies to discharge sufficiently before taking EN to 1 again. Over-Temperature Protection An internal temperature sensor continuously monitors the die temperature. In the event that die temperature exceeds the thermal trip point, the device will shut down and disable itself. The upper and lower trip points are typically set to 130°C and 90°C respectively. PCB Layout Guidelines Careful layout is critical in the successful operation of the application. The following layout guidelines are recommended to achieve optimum performance. 1. VREF and VDDB bypass capacitors should be placed next to the pins. 2. Place the boost converter diode and inductor close to the LX pins. 3. Place the boost converter output capacitor close to the PGND pins. 4. Locate feedback dividers close to their respected feedback pins to avoid switching noise coupling into the high impedance node. 5. Place the charge pump feedback resistor network after the diode and output capacitor node to avoid switching noise. 6. All low-side feedback resistors should be connected directly to VSSB. VSSB should be connected to the power ground at one point only. A demo board is available to illustrate the proper layout implementation. 1. The boost circuit and negative charge pumps are enabled. VBOOST rises at a rate set by the boost load capacitor, the external load, and the boost’s current limit (controlled by the SS pin input.) Similarly, VOFF falls in voltage determined by the load capacitor, the VOFF load, 14 FN7317.2 February 4, 2005 EL7584 Typical Application Circuit C7 R2 110kΩ R1 13kΩ R4 49.9Ω C5 VBOOST (12V@ 350mA) + 22µF VIN GND C6 0.1µF VSSB 24 2 FBB ROSC 23 3 EN VREF 22 4 VDDB PGND 21 5 LX PGND 20 6 LX VSSP 19 + 7 VSSN DRVP 18 8 DRVN VDDP 17 9 VDDN FBP 16 R3 61.9kΩ C8 1nF *D1 L1 C1 10µF 1 SS 0.1µF 10µH C12 0.1µF C11 0.1µF VOFF -6V C21 R21 154kΩ C26 3.3µF 0.1µF **D21 ***C20 1nF 10 FBN VSSC 15 11 DP VCOM 14 12 INC VDDC 13 VCOM REFERENCE VON 18V **D11 C22 0.1µF C31 1µF C13 2.2µF R12 51kΩ R11 3.9kΩ VCOM C32 0.1µF C33 R22 33.2kΩ * MBRM120LT3 ** BAT54S *** C20 is optional if extended VON delay is required 15 FN7317.2 February 4, 2005 EL7584 Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7317.2 February 4, 2005