INTERSIL ISL98604

6-Channel Integrated LCD Supply
ISL98604
Features
The ISL98604 is a high power, fully programmable 6-Channel
output control IC targeted at large panel LCD displays. The
ISL98604 integrates a high power, boost converter and delay
switch for AVDD generation, one VIO asynchronous buck
regulator, two synchronous buck regulators for HAVDD and
VCORE supply generation, and linear regulator controllers for VON
and VOFF charge pumps.
• 8V to 16.5V input supply
• AVDD boost up to 19.0V, with integrated 4.0APEAK FET
• HAVDD synchronous buck for 8V with 1APEAK FET
• Overvoltage protection (OVP)
• Internal AVDD delay FET
• Dual linear regulator controllers for VON and VOFF
Operating at 750kHz, the AVDD boost converter features a 4.0A
boost FET and 6-bit resolution programmable from 12.7V to
19.0V. The delay switch is also integrated for power sequence.
• VON temperature compensation
• VIO buck with integrated 2APEAK FET
• VCORE synchronous buck with integrated 1APEAK FET
The asynchronous buck converter for VIO supply features an
integrated 2A FET. It also operates at 750kHz internal clock and
compensation features.
• Internal feedback and compensation
• Programmable output control with IIC
• Programmable sequencing with IIC
The two synchronous bucks are integrated with controller,
upper, and lower side switches for HAVDD and VCORE
generation with internal compensation. The HAVDD and
VCORE outputs are both programmable ranging from 6.4V to
9.55V and 0.9V to 2.4V, respectively.
• UVLO and OTP protection
• Thermally enhanced 5x5 Thin QFN package
• Pb-free (RoHS compliant)
Applications
Dual linear regulator controllers are provided to allow generation
of accurate VON and VOFF voltages in conjunction with external
charge pumps and bipolar power transistors. VON output voltage
can be compensated adoptively by temperature sensing.
• LCD TV
All output voltages are programmed through IIC and stored in
EEPROM. Alternative factory set voltages are available for
ISL98604; please contact Consumer Product Marketing via email
at [email protected].
Pin Configuration
PGND4
VIO
PHASE2
NC
SWB1
SWB2
NC
PVIN2
PVIN1
NC
ISL98604
(40 LD 5x5 TQFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
EN 1
30 VCORE
TCOMP 2
29 SDA
VDC 3
28 SCL
AGND 4
27 A0
AVIN 5
26 PG
THERMAL
PAD
PVIN3 6
25 NC
24 DRVN
NC 7
PHASE1 8
23 NC
HAVDD 9
22 FBN
21 FBP
PGND3 10
1
NC
DRVP
SWO
SWIN
SW1
SW2
PGND1
PGND2
SS
December 17, 2012
FN7687.0
COMP
11 12 13 14 15 16 17 18 19 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners
ISL98604
Typical Application Circuit
L1
4.7µH
VIN: 12V
8V~16.5V
C1
10µF
C4
10µF
SS34
LX D1
AVDD: 16V
12.7V~19.0V
C02
20µF
C04
10µF
C03
20µF
BOOST
VIO BUCK
PVIN1
PVIN2
SW1
SW2
SWIN
L2
6.8µH
VIO: 3.3V
3.0V~3.7V
SWB1
SWO
R01
SWB2
C11
20µF
AVDD
COMP
5.6kΩ
D11
SS33
VIO
PGND1
C01
15nF
PGND2
C63
1µF
BAT54S
LX
D61 0Ω
R64
C64
0.1µF
SS
C05
47nF
VCORE BUCK
VON C.P.
R63
700Ω
DRVP
VCORE: 1.8V, 0.9V~2.4V
Q1
VCORE
VON:
HT: 26V
7V~32V
LT: 28V, 19V~34V
fmmt3906
C65
10µF
PHASE2
L3
2.2µF
C21
10µF
FBP
VDC
PGND4
R61
10kΩ
ASYNC MODE
TDK NTC 1068 E TYPE 10kΩ
NTC
TCOMP
R62
10kΩ
HAVDD BUCK
VIN
C2
10µF
HAVDD: 8.0V
6.4V~9.55V
VOFF C.P.
R53
0Ω
C53
0.22µF
PVIN3
HAVDD
MMBT3904
PHASE1
L4
6.8µH
C31
4.7µF
SWB1
Q2
D52
D51
C52 BAT54S
100nF
DRVN
R54
PGND3
VOFF:
5V, -8.1V~1.8V
C51
4.7µF
700Ω
FBN
ASYNC MODE
VIO
VIO
VIO
R42
10kΩ
INTERFACE/SEQUENCE
R44
100kΩ
R43
100kΩ
PG
SCL
PC
SDA
AVIN
A0
PGOOD
VIN
C3
10µF
C40
1µF
EN
VDC
AGND
2
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December 17, 2012
ISL98604
Block Diagram
AGND
COMP
VIO
SWO
SW1
FOSC
750kHz
PVIN1
FOSC
750kHz
S
Q
REF
PVIN2
SW2
R
PGND1
SLOPE
COMPENSATION
S
Q
PGND2
R
SWB1
SWIN
SWB2
DELAY
FET
SWO
PGOOD
MONITORING
PG
VON
LINEAR
REGULATOR
CONTROL
EN
SS
2
I C INTERFACE
AND
SEQUENCE
CONTROL
SCL
SCA
DRVP
FBP
EEPROM
TCOMP
REF
4.5V
REGULATOR
VOFF
LINEAR
REGULATOR
CONTROL
A0
VDC
DRVN
FBN
AVIN
HAVDD
VCORE
PVIN3
VIO
FOSC
3MHz
S
Q
Q R
REF
REF
FOSC
1MHz
S
Q
R Q
PHASE1
PHASE2
AVIN
PGND4
AVIN
PGND3
3
FN7687.0
December 17, 2012
ISL98604
Pin Descriptions
PIN #
SYMBOL
DESCRIPTION
1
EN
2
TCOMP
3
VDC
4
AGND
Analog ground pin.
5
AVIN
Internal regulator supply pin; connect to external 10µF capacitor close to the pin.
6
PVIN3
HAVDD buck power input pin; connect to external 10µF capacitor close to the pin.
7, 19,
23, 25,
34, 37,
40
NC
8
PHASE1
HAVDD buck switch node; connect an inductor to the pin for synchronous mode, or connect a inductor and a Schottky diode
to the pin for asynchronous mode.
9
HAVDD
HAVDD buck output feedback input pin.
10
PGND3
HAVDD buck Power ground.
11
SS
12
COMP
13, 14
PGND2, 1
15, 16
SW2, 1
17
SWIN
AVDD delay FET input, connect a 10µF capacitor close to the pin.
18
SWO
AVDD delay FET output, connect a 22µF capacitors close to the pin.
20
DRVP
Positive charge pump LDO transistor driver, connect the base of an external PNP bipolar to the pin.
21
FBP
Positive charge pump output feedback input pin.
22
FBN
Negative charge pump output feedback input pin.
24
DRVN
26
PG
Power good output.
27
A0
IIC slave address select pin.
28
SCL
IIC clock pin.
29
SDA
IIC data pin.
30
VCORE
VCORE buck output feedback input pin.
31
PGND4
VCORE buck power ground.
32
PHASE2
VCORE buck switch node, connect an inductor to the pin for synchronous mode, or connect a inductor and a Schottky diode
to the pin for asynchronous mode.
33
VIO
35, 36
SWB1, 2
VIO asynchronous buck switch node connection.
38, 39
PVIN2, 1
VIO buck and VCORE buck power input pin; connect to external 10µF capacitor close to the pin.
-
PAD
IC enable pin; pull high to enable all the outputs.
Temperature compensation input, connect NTC resistor in the resistor ladder from VDC to GND to set the curve of VON vs
temperature.
Internal linear regulator output, connected to external 1µF capacitor close to the pin.
Not connected.
AVDD boost and HAVDD buck soft-start timing capacitor connection for step-up.
AVDD boost compensation pin; connect a 5.6kΩ resistor and 15nF capacitor in series to the pin.
AVDD boost power ground.
AVDD boost switch node connection.
Negative charge pump LDO transistor driver, connect the base of an external NPN bipolar to the pin.
VIO buck output feedback input pin.
Thermal Pad.
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December 17, 2012
ISL98604
Ordering Information
PART NUMBER
(Notes 2, 3, 4)
ISL98604IRTZ
(Note 1)
AVDD HAVDD VIO VCORE
BOOST BUCK BUCK BUCK
(V)
(V)
(V)
(V)
PART
MARKING
ISL9860 4IRZ
16
8.0
3.3
1.0
VON
LT
(V)
VON
HT
(V)
VOFF
(V)
DLY1
(ms)
DLY2
(ms)
DLY3
(ms)
28
26
-5
10
30
30
TEMP
RANGE PACKAGE
(°C)
(Pb-free)
PKG.
DWG. #
-40 to 40 Ld
L40.5x5D
+85 5x5 TQFN
ISL98604IRTZ-EVZ Evaluation Board
NOTES:
1. For availability and lead time of devices with voltage and power-on timing combinations not listed in the table, please contact Intersil Marketing via
email at [email protected].
2. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL98604. For more information on MSL please see techbrief TB363.
5
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ISL98604
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Test Circuits and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HAVDD Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIO Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCORE Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VON Linear-Regulator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VOFF Linear-Regulator Controller and Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of the Linear Regulator Base-Emitter Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VON/VOFF Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VON Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
16
17
18
19
19
19
19
20
20
25
25
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
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December 17, 2012
ISL98604
Absolute Maximum Ratings
Thermal Information
(TA = +25°C)
DRVP to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +45V
FBP to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V
FBN to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -10V
SW1, SW2, SWI, and SWO . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
PVIN1, PVIN2, AVIN, SWB1, SWB2, PHASE1, PHASE2, HAVDD, and EN to
AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18.6V
DRVN, VDC, VCORE, SS, PGOOD, SCL, SDA, and A0
to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
Voltage between AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5V
All other pins to GND, AGND and PGND . . . . . . . . . . . . . . . . -0.5V to +5.5V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . 750V
Latch Up (Tested per JESD-78B; Class II, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
5x5 TQFN Package (Notes 5, 6) . . . . . . . . .
32
2.4
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 16.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40°C to +85°C, unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
8
12
MAX
(Note 7) UNITS
SUPPLY PINS
PVIN +SUP
Supply Voltage
IVIN +SUP
Supply Current when Disabled
EN = 0V
IVIN +SUP
Supply Current when Enabled
EN = VDC, no loading on all channels
IEN
Enable Input Bias Current
EN = 0
EN = VDC
VLDO
Internal LDO Output Voltage
16.5
V
1.25
mA
8
mA
0.01
0.1
µA
10
15
µA
4.5
V
AVDD BOOST
VAVDD
Output Voltage Range
ACCAVDD
Output Voltage Accuracy
AVDD = 16V, ILOAD = 100mA
-2
ISWPL_AVDD
Switch Peak Current Limit
Boost Peak Current limit
3.5
EFFAVDD
Peak Efficiency
ISWLK_AVDD
Switch Leakage Current
rDS(ON)_AVDD
Switch ON-Resistance
TA = +25°C, ISW = 500mA
0.125
DVAVDD/DVIN
Line Regulation
9.5V < PVIN < 13.5V,
ILOAD = 200mA,
0.08
%
DVAVDD/DIOUT
Load Regulation
100mA < ILOAD < 500mA
0.5
%
DMAX_AVDD
Maximum Duty Cycle
FOSC = 750kHz
87
%
DMIN_AVDD
Minimum Duty Cycle
FOSC = 750kHz
FOSC_AVDD
Oscillator Frequency
Internal OSC
1.14*VIN
16
4
19.0
V
2
%
4.5
A
93
82
675
%
22
µA
0.19
Ω
12
16
%
750
825
kHz
0.15
0.24
Ω
AVDD DELAY SWITCH
rDS(ON)_DLY
Switch ON-Resistance
7
FN7687.0
December 17, 2012
ISL98604
Electrical Specifications
VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40°C to +85°C, unless otherwise noted. (Continued)
SYMBOL
PARAMETER
ISWPL_DLY
Switch Peak Current Limit
FET timeout
Delay FET Fault Timeout
ISWPL_Immed
Switch High Current Limit, Immediate Shut Down
Once Triggered
ISWLK_ DLY
Leakage Current When Disabled
TEST CONDITIONS
MIN
(Note 7)
TYP
2.3
3.1
ISWO > IDLY
VIN = 16.5V, VSWIN = 19V, VSWO = 0V,
EN = 0V
MAX
(Note 7) UNITS
3.8
A
1
ms
6.0
A
5
20
µA
8
9.55
V
1.6
%
HAVDD SYNC BUCK
VHAVDD
Output Voltage Range
Internal feedback
6.4
ACCHAVDD
Output voltage accuracy
HAVDD = 8V
-1.6
ISWPL_HAVDD
Switching Peak Current Limit
ISWRL_HAVDD
Lower Switch Reverse Current Limit
EFFHAVDD
Peak Efficiency
1
0.65
A
0.9
1.15
93
rDS(ON)_U_HAVDD Upper Switch ON-Resistance
TA = +25°C , ISW = 500mA
0.3
0.37
rDS(ON)_L_HAVDD Lower Switch ON-Resistance
TA = +25°C , ISW = 500mA
0.3
0.37
IFB_HAVDD
Feedback Input Current
DVHAVDD/DVIN
Line Regulation
A
%
Ω
Ω
11
µA
9.5V < PVIN < 13.5V, ILOAD = 200mA
0.3
%
0.3
DVHAVDD/DIOUT
Load Regulation
200mA < ILOAD < 1000mA
ISWLK_HAVDD
Switch Leakage Current
TA = +25°C
DMAX_HAVDD
Maximum Duty Cycle
FOSC = 750kHz
DMIN_HAVDD
Minimum Duty Cycle
FOSC = 750kHz
FOSC_HAVDD
Oscillator Frequency
Internal OSC
VIO
Output Voltage Range
Internal feedback
ACCVIO
Output Voltage Accuracy
VIO = 3.3V
IVIO
Output Current
Internal feedback
ISWPL_VIO
Switch Peak Current Limit
Current limit
EFFVIO
Peak Efficiency
See graphs and “Applications Information”
on page 15 for component
recommendations
rDS(ON)_VIO
Switch On-Resistance
TA = +25°C, ISW = 500mA
DVVIO/DVIN
Line Regulation
9.5V < PVIN < 13.5V, ILOAD = 200mA
0.3
DVVIO/DIOUT
Load Regulation
200mA < ILOAD < 1000mA
0.3
IFB_VIO
Feedback Input Current
ISWLK_VIO
Switch Leakage Current
TA = +25°C
5
85
90
675
750
3.0
3.3
%
20
µA
%
15
%
825
kHz
VIO BUCK
DMAX_VIO
Maximum Duty Cycle
FOSC = 750kHz
DMIN_VIO
Minimum Duty Cycle
FOSC = 750kHz
FOSC_VIO
Oscillator Frequency
Internal OSC
VCORE
Output Voltage Range
ACCVCORE
Output Voltage Accuracy
-2.25
3.7
V
2.25
%
0.7
A
86
%
2
A
0.200
85
0.300
Ω
%
%
2.5
100
nA
5
20
µA
86
%
10
15.5
%
675
750
825
kHz
Internal feedback
0.9
1.0
2.4
V
VCORE = 1.0V
-2.5
2.5
%
VCORE BUCK
8
FN7687.0
December 17, 2012
ISL98604
Electrical Specifications
VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40°C to +85°C, unless otherwise noted. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
ICORE
Output Current
ISWPL_VCORE
Switch Peak Current Limit
Current limit
EFFVCORE
Peak Efficiency
See graphs and “Applications Information”
on page 15 for component
recommendations
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
0.5
A
1
A
86
%
rDS(ON)_U_VCORE Upper Switch ON-Resistance
TA = +25°C , ISW = 500mA
0.18
Ω
rDS(ON)_L_VCORE Lower Switch ON-Resistance
TA = +25°C , ISW = 500mA
0.18
Ω
DVVCORE/DVIN
Line Regulation of VCORE Buck
9.5V < PVIN < 13.5V, ILOAD = 200mA
0.1
%
DVVCORE/DIOUT
Load Regulation of VCORE Buck
200mA < ILOAD < 500mA
0.3
%
IFB_VCORE
Feedback Input Current
VVCORE = 1.8V
5
µA
ISWLK_VCORE
Switch leakage current
DMAX_VCORE
Maximum Duty Cycle
FOSC = 3MHz
DMIN_VCORE
Minimum Duty Cycle
FOSC = 3MHz
FOSC_VCORE
Oscillator Frequency
Internal OSC
VVON
Output Voltage Range
Low temperature
ACCVON
Output Voltage Accuracy
DVON/DIOUT
Load Regulation
IDRVP = 60µA to 120µA with MMBT3906
PNP, related resistors are shown in the
application circuit
0.64
%
DVON/DVIN
Line Regulation
IDRVP = 100µA, VIN = 9.5V to 14V
0.5
%
IDRVP
Positive Source Current (Max)
VFBP = 1.15V, VDRVN = 10V
ILEAK_DRVP
DRVP Off Leakage Current
VFBP = 1.40V, VDRVN = 30V
3
85
10
µA
90
%
8
%
1.32
1.50
1.68
MHz
19
28
34
V
High temperature
17
26
VON = 28V
-2.1
VON LDO
3
VTCOMP_HYST
Hysteresis Voltage in Temp. Compensation
VREF = 1.265V
V
%
6
0.1
VTCOMP_TH (NOTE Threshold Voltage in Temp. Compensation
2)
32
2.1
mA
10
µA
1.265
V
20
mV
VOFF LDO
VVOFF
Output Voltage Range
ACCVOFF
Output Voltage Accuracy
VOFF = -5V
IFBN
LDO Input Bias Current
VFBN = -5V
11
µA
DVOFF/DIOUT
Load Regulation
IDRVN = 60µA to 120µA with MMBT3904
NPN, related resistors are shown in the
application circuit, IOUT = 200mA
2.7
%
IDRVN
Negative Source Current
VFBN = 0.6V, VDRVN = -10V
5
mA
ILEAK_DRVN
DRVN Off Leakage Current
VFBN = 0.5V, VDRVN = -6V
Logic “HIGH”
SCL, SDA, A0
1.85
V
EN
1.6
V
-8.1
-5
-3.75
3
0.1
-1.8
V
3.75
%
10
µA
LOGIC INPUTS
VHI
VLO
Logic “LOW”
SCL, SDA, A0
EN
9
0.85
V
0.675
V
FN7687.0
December 17, 2012
ISL98604
Electrical Specifications
VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40°C to +85°C, unless otherwise noted. (Continued)
SYMBOL
ILG_PD
PARAMETER
Logic Pin Pull-Down Current
TEST CONDITIONS
MIN
(Note 7)
TYP
VLG > VLO
MAX
(Note 7) UNITS
25
µA
400
kHz
I2C
fSCL (Note 8)
SCL Frequency
tiN (Note 8)
Pulse Width Suppression Time at SDA and SCL
Inputs
Any pulse narrower than max spec is
suppressed
50
ns
tAA (Note 8)
SCL Falling Edge to SDA Output Data Valid
SCL falling edge crossing 30% of VO_LDO,
until SDA exits the 30% to 70% of VO_LDO
window
900
ns
tBUF (Note 8)
Time the Bus Must Be Free before the Start of a New SDA crossing 70% of VO_LDO during a STOP
Transmission
condition, to SDA crossing 70% of VO_LDO
during the following START condition
1300
ns
tLOW (Note 8)
Clock LOW Time
Measured at the 30% of VO_LDO crossing
1300
ns
tHIGH (Note 8)
Clock HIGH Time
Measured at the 70% of VO_LDO crossing
600
ns
tSU:STA (Note 8)
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VO_LDO
600
ns
tHD:STA (Note 8)
START Condition Hold Time
SDA falling edge crossing 30% of VO_LDO to
SCL falling edge crossing 70% of VO_LDO
600
ns
tSU:DAT (Note 8)
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge cross 30% of VCC
100
ns
tHD:DAT (Note 8)
Input Data Hold Time
From SCL falling edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0
tSU:STO (Note 8)
Stop Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge cross 30% of VCC
600
ns
tHD:ST0 (Note 8)
Stop Condition Hold Time
From SDA rising edge to SCL falling edge.
Both crossing 70% of VCC
600
ns
tDH (Note 8)
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0
ns
tR (Note 8)
SDA and SCL Rise Time
Depend on Load
tSU:A (Note 8)
nWR Condition Setup Time
From nWR rising/falling edge crossing
70/30% of VCC, to SDA falling edge cross
30% of VCC (START)
600
ns
tHD:A (Note 8)
nWR Data Hold Time
From SDA rising edge crossing 70% of VCC
(STOP) to nWR rising/falling edge crossing
70/30% of VCC window
800
ns
tF (Note 8)
SDA and SCL Fall Time
Cb (Note 8)
I2C Bus Capacitive Load
CSDA (Note 8)
Capacitance on SDA
CSCL (Note 8)
Capacitance on SCL
tWP (Note 8)
Non-volatile Write Cycle Time
900
1000
300
400
nWR = 0
nWR = 1
ns
ns
ns
pF
5
pF
5
pF
5
12
pF
20
ms
EEPROM
tEEPROM
EEPROM Programming Time
TA = +25°C
90
ms
REEPROM
EEPROM Memory Retention
TA = +25°C
88
kHrs
10
FN7687.0
December 17, 2012
ISL98604
Electrical Specifications
VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40°C to +85°C, unless otherwise noted. (Continued)
SYMBOL
CEEPROM
PARAMETER
EEPROM Read/Write Cycles
TEST CONDITIONS
MIN
(Note 7)
TA = +25°C
TYP
MAX
(Note 7) UNITS
1
kCyc
20.5
V
FAULT DETECTION THRESHOLD
OVP
Overvoltage Protection Off Threshold to Shutdown IC
VUVLO
Undervoltage Lock Out Threshold
PVIN rising
7.2
PVIN falling
6.0
TOFF
Thermal Shutdown All Channels
Temperature rising
7.5
7.9
6.3
6.6
140
V
V
°C
START-UP AND SOFT-START
ISS_AVDD
Soft-Start Current
CSS = 47nF
6
µA
tSS_HAVDD
Boost and HAVDD Buck Soft-Start Time
CSS = 47nF
10
ms
tSS_VON
Positive Charge Pump Soft-Start Period
6.4
ms
tSS_VOFF
Negative Charge Pump Soft-Start Period
tSS_VOFF = -1.6*VOFF-15
tDLY1
Delay Time from VIO to /RST Start
From 90% of VIO
0
10
ms
tDLY2
Delay Time from VOFF to AVDD Start
From 90% of VOFF
0
30
ms
tDLY3
Delay Time from AVDD to VON Start
From 90% of AVDD
0
30
ms
1.6
9
ms
POWER GOOD BLOCK
VPGOOD
PGOOD Output Low Voltage
IPGOOD = 1mA
IPGLEAK
PGOOD Leakage Current
VPGOOD = 3V
0.007
0.025
V
0.05
µA
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and
are not production tested.
8. Limits established by design or characterization but not production tested.
11
FN7687.0
December 17, 2012
ISL98604
Typical Performance Curves
95
0.04
VIN = 12V
94
0.02
LOAD REGULATION (%)
EFFICIENCY (%)
93
92
91
90
89
88
87
VIN = 12V
86
L = RLF7030T-4R7M3R4
85
D = SS34
0.2
0.4
0.6
0.8
1.0
-0.02
-0.04
-0.06
-0.08
84
0
0.00
-0.10
0.1
1.2
0.3
0.5
I_AVDD (A)
0.7
0.9
1.1
I_AVDD (A)
FIGURE 1. AVDD BOOST EFFICIENCY
FIGURE 2. AVDD BOOST LOAD REGULATION
0.01
IAVDD = 200mA
AVDD RIPPLE (500mV/DIV)
LINE REGULATION (%)
0.01
0.00
-0.01
-0.01
IAVDD (100mA/DIV)
-0.02
-0.02
-0.03
9
10
11
12
13
14
VIN (V)
VIN = 12V
FIGURE 3. AVDD BOOST LINE REGULATION
FIGURE 4. AVDD BOOST TRANSIENT RESPONSE
0.04
100
VIN = 12V
90
0.02
LOAD REGULATION (%)
EFFICIENCY (%)
80
70
60
50
40
30
20
VIN = 12V
10
L = RLF7030T-6R8M2R8
0
0
0.1
0.2
0.3
0.4
0.5
-0.02
-0.04
-0.06
-0.08
0.6
I_HAVDD (A)
FIGURE 5. HAVDDBUCK EFFICIENCY
12
0.00
0.7
0.8
-0.10
0.2
0.4
0.6
0.8
I_HAVDD (A)
FIGURE 6. HAVDD BUCK REGULATION
FN7687.0
December 17, 2012
ISL98604
Typical Performance Curves (Continued)
0.10
HAVDD RIPPLE (50mV/DIV)
LINE REGULATION (%)
IHAVDD = 200mA
0.05
0.00
IHAVDD (100mA/DIV)
-0.05
-0.10
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
VIN (V)
FIGURE 7. HAVDD BUCK LINE REGULATION
FIGURE 8. HAVDD BUCK TRANSIENT RESPONSE
90
0.05
VIN = 12V
LOAD REGULATION (%)
EFFICIENCY (%)
85
80
75
70
VIN = 12V
65
0.00
-0.05
-0.10
L = RLF7030T-6R8M2R8
D = SS33
60
0
0.5
1.0
1.5
2.0
-0.15
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
I_VIO (A)
I_VIO (A)
FIGURE 10. VIO BUCK LOAD REGULATION
FIGURE 9. VIO BUCK EFFICIENCY
0.04
LINE REGULATION (%)
0.03
IVIO = 200mA
VIO RIPPLE (50mV/DIV)
0.03
0.02
0.02
IVIO (100mA/DIV)
0.01
0.01
0.00
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
VIN = 12V
VIN (V)
FIGURE 11. VIO BUCK LINE REGULATION
13
FIGURE 12. VIO BUCK TRANSIENT RESPONSE
FN7687.0
December 17, 2012
ISL98604
Test Circuits and Waveforms
95
0.04
VIN = 12V
93
0.02
LOAD REGULATION (%)
EFFICIENCY (%)
91
89
87
85
83
81
79
VIN = 12V
77
0.00
-0.02
-0.04
-0.06
-0.08
L = RLF7030T-2R2M5R4
75
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-0.10
0.2
0.8
0.3
0.4
0.5
0.6
0.7
0.8
I_VCORE (A)
I_VCORE (A)
FIGURE 13. VCORE BUCK EFFICIENCY
FIGURE 14. VCORE BUCK LOAD REGULATION
0.01
IVCORE = 200mA
LINE REGULATION (%)
0.01
VCORE RIPPLE (50mV/DIV)
0.01
0.01
0.00
IVCORE (100mA/DIV)
0.00
0.00
0.00
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
VIN = 12V
13.5
VIN (V)
FIGURE 16. VCORE BUCK TRANSIENT RESPONSE
FIGURE 15. VCORE BUCK LINE REGULATION
0.10
0.04
VIN = 12V
IVON = 20mA
0.02
LINE REGULATION (%)
LOAD REGULATION (%)
0.05
0.00
-0.05
-0.10
-0.15
-0.20
0.00
-0.02
-0.04
-0.06
-0.08
-0.25
-0.30
0
0.01
0.02
0.03
0.04
I_VON (A)
FIGURE 17. VON LOAD REGULATION
14
0.05
-0.10
9.5
10.5
11.5
12.5
13.5
VIN (V)
FIGURE 18. VON LINE REGULATION
FN7687.0
December 17, 2012
ISL98604
Test Circuits and Waveforms (Continued)
0.10
0.18
VIN = 12V
LINE REGULATION (%)
LOAD REGULATION (%)
IVOFF = 20mA
0.16
0.00
-0.10
-0.20
-0.30
-0.40
0.14
0.12
0.10
0.08
0.06
0.04
0.02
-0.50
0
0.01
0.02
0.03
0.04
0.05
0.00
9.5
10.5
11.5
I_VOFF (A)
13.5
FIGURE 20. VOFF LINE REGULATION
FIGURE 19. VOFF LOAD REGULATION
Applications Information
The ISL98604 provides a complete power solution for TFT LCD
applications. The system consists of one boost converter to
generate AVDD voltage for column drivers, one asynchronous
buck converter to provide voltage to logic circuit in the LCD panel,
two synchronous bucks for core voltage and HAVDD, LDO
controllers for VON and VOFF charge pump outputs, and AVDD
delay FET. With the high output current capability, this part is
ideal for LCD TV and monitor panel application.
Boost Converter
OPERATION
The AVDD boost converter is a current mode PWM converter
operating at a fixed switching frequency (750kHz). It can operate
in both discontinuous conduction mode (DCM) at light loads and
continuous mode (CCM). In continuous current mode, current
flows continuously in the inductor during the entire switching
cycle in steady state operation. The voltage conversion ratio in
continuous current mode is given by Equation 1:
V boost
1
------------------ = ------------1–D
V IN
12.5
VIN (V)
V IN D
ΔI L = --------- × ----L
fS
(EQ. 3)
ISL98604 uses internal feedback resistor divider to divide the
output voltage down to the nominal reference voltage. The boost
converter output voltage is programmable through I2C control,
which will be described in more detail in section “I2C Control” on
page 20.
INPUT CAPACITOR
An input capacitor is used to suppress the voltage ripple injected
into the boost converter. A ceramic capacitor with low ESR should be
chosen to minimize the ripple. The voltage rating of input capacitor
should be larger than the maximum input voltage. Some capacitors
are recommended in Table 1.
TABLE 1. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/25V
1206
TDK
C3216X7R1E106K
22µF/25V
1206
Murata
GRM31CR61E226KE15L
(EQ. 1)
BOOST INDUCTOR
The boost converter uses a summing amplifier architecture for
voltage feedback, current feedback, and slope compensation. A
comparator looks at the peak inductor current cycle-by-cycle and
terminates the PWM cycle if the current limit is triggered. Since
this comparison is cycle based, the PWM output will be released
after the peak current goes below the current limit threshold.
The boost inductor is a critical part which influences the output
voltage ripple, transient response, and efficiency. The selection
of inductor should be based on its maximum current (ISAT)
characteristics, power dissipation (DCR) and size. Values of
3.3µH to 10µH are recommended to match the internal slope
compensation as well as to maintain a good transient response
performance. The inductor must be able to handle the average
and peak currents shown in Equations 4 and 5:
The current through the MOSFET is limited to 4A peak. This restricts
the maximum output current (average) based on Equation 2:
IO
I LAVG = -----------------------------( 1 – D )xEff
(EQ. 4)
ΔI L
V IN
I OMAX = ⎛ I LMT – --------⎞ × --------⎝
2 ⎠ VO
ΔI L
I LPK = I LAVG + -------2
(EQ. 5)
where D is the duty cycle of the switching MOSFET.
(EQ. 2)
Where DIL is peak to peak inductor ripple current, and is set by
Equation 3. fs is the switching frequency (750kHz).
15
Where Eff is the efficiency of the boost converter; 90% can be used
in calculation as approximation.
FN7687.0
December 17, 2012
ISL98604
COMPENSATION
Some inductors are recommended in Table 2.
TABLE 2. BOOST INDUCTOR RECOMMENDATION
DIMENSIONS
(mm)
VENDOR
INDUCTANCE
DCR (mΩ)
4.7µH/
3.4APEAK
31
4.7µH/
4.5APEAK
44.1
4.0x4.0x3.1 Coilcraft XAL4030-472MEB
4.3µH/
11.2
12.9x12.9x4 SUMIDA CDEP12D38NP-4R3M
7.3x6.8x3.2 TDK
PART NUMBER
RLF7030T-4R7M3R4
6.4APEAK
The boost converter of ISL98604 can be compensated by a RC
network connected from the COMP pin to ground. The resistance
sets the high -frequency integrator gain for fast transient
response and the capacitance sets the integrator zero to ensure
loop stability. On the demo board 5.6k and 15nF RC network is
used. Stability can be examined by repeatedly changing the load
between 100mA and a max level that is likely to be used in the
application. The AVDD voltage should be examined with an
oscilloscope set to AC and observe the amount of ringing when
the load current changes.
SOFT-START
RECTIFIER DIODE
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of their
fast recovery time and low forward voltage. The reverse voltage
rating of this diode must be higher than the maximum output
voltage. Also the average/peak current rating of the selected
Schottky diode must meet the output current and peak inductor
current requirements. Table 3 shows some recommendations for
boost converter diodes.
TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION
DIODE
VR/IAVG
RATING
PACKAGE
VENDOR
SS34
40V/3A
DO-214
Fairchild
PMEG3030
30V/3A
SOD128
NXP
OUTPUT CAPACITOR
The output capacitors smooths the output voltage and supplies
load current directly during the conduction phase of the power
switch. Output ripple voltage consists of two components: the
voltage drop due to the inductor ripple current flowing through
the ESR of output capacitor, and the charging and discharging of
the output capacitor.
IO
V O – V IN
1
V RIPPLE = I LPK × ESR + ------------------------ × ---------------- × ---C OUT f s
VO
(EQ. 6)
The conservation of charge principle also indicates that, during
the boost switch Off period, the output capacitor is charged with
the inductor ripple current, minus a relatively small output
current in boost topology. As a result, the user must select an
output capacitor with low ESR and adequate input ripple current
capability.
Table 4 shows some recommendations of output capacitors.
Note: Capacitors have a voltage coefficient that makes their effective
capacitance drop as the voltage across them increases. COUT in
Equation 6 assumes the effective value of the capacitor at a
particular voltage and not the manufacturer's stated value,
measured at 0V.
TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/50V
1206
TDK
C3216X5R1H106K
22µF/25V
1210
Murata
GRM32ER71E226KE15L
16
The soft-start is provided by an internal current source to charge
the external soft-start capacitor. The ISL98604 ramps up the
current limit from 0A up to the full value, as the voltage at the SS
pin ramps up from 0.8V. Hence, the soft-start time is 2.9ms
when the soft-start capacitor is 22nF, 6.3ms for 47nF and
13.3ms for 100nF.
AVDD DELAY SWITCH
ISL98604 integrates a disconnect switch for the AVDD boost
output to disconnect VIN from AVDD when the EN input is low or
when DLY2 is not completed. When EN is taken high and DLY2
timing is finished, the integrated FET is turned on to connect
power to the display. The AVDD delay switch circuitry constantly
monitors both the current flowing through the switch and the
voltage at SWOUT. The delay switch has two current limits: a low
current limit and a high current limit. If the current flowing
through delay switch is higher than the delay switch low current
limit, the IC faults out after 1ms; if the delay switch high current
limit is reached, the IC faults out immediately.
HAVDD Synchronous Buck Converter
OPERATION
HAVDD synchronous buck converter is a step down converter with
a fixed switching frequency (750kHz) supplying voltage bias for
gamma buffer in the LCD system. The ISL98604 integrates two
MOSFETs to reduce external component count, save cost, and
improve efficiency. In continuous current mode, the relationship
between input voltage and output voltage is as shown in Equation 7:
HVDD
------------------ = D
V IN
(EQ. 7)
where D is the duty cycle of the upper switching MOSFET.
Because D is always less than 1, the output voltage of the HAVDD
buck converter is lower than the input voltage.
The peak current limit of HAVDD buck converter is set to 0.9A,
which restricts the maximum output current based on
Equation 8:
ΔI P-P
I HAVDDMAX = 0.9 – --------------2
(EQ. 8)
Where ΔIP-P is the ripple current in the buck inductor as shown in
Equation 9:
HAVDD
ΔI P-P = ---------------------- ⋅ ( 1 – D )
L ⋅ fs
(EQ. 9)
FN7687.0
December 17, 2012
ISL98604
Where L is the buck inductance, fs is the switching frequency of
HADD buck inductor (750kHz).
ISL98604 uses internal feedback resistor divider to divide the
output HAVDD voltage down to the nominal reference voltage. The
HAVDD voltage is programmable through I2C control, which will be
described in more detail in section “I2C Control” on page 20.
INPUT CAPACITOR
Selection of input capacitance is important for input voltage
ripple. A ceramic capacitor should be used because of its small
ESR. Another important criteria when selecting input capacitor is
that it should be able to support the maximum AC RMS current
which occurs at D = 0.5 and maximum output current.
I ACRMS =
D ⋅ ( 1 – D ) ⋅ I HAVDD
(EQ. 10)
Where IHAVDD is the output current of the buck converter. Table 5
shows recommendations for input capacitors.
TABLE 5. HAVDD BUCK CONVERTER INPUT CAPACITOR
RECOMMENDATION
capacitor is recommended (see Table 7).
TABLE 7. HAVDD BUCK OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
SIZE
VENDOR
PART NUMBER
22µF/16V
0805
TDK
C2012X5R1C226K
10µF/25V
0805
TDK
C2012X5R1E106M
VIO Buck Converter
OPERATION
VIO buck converter is an asynchronous step down converter with
a fixed switching frequency (750kHz) supplying power to the logic
circuit of the LCD system. In continuous current mode, the
relationship between input voltage and output voltage, is as shown
in Equation 11.
VIO
----------- = D
V IN
(EQ. 11)
where D is the duty cycle of the switching MOSFET.
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/25V
1206
TDK
C3216X7R1E106K
22µF/25V
1206
Murata
GRM31CR61E226KE15L
The peak current limit of VIO buck converter is set to 2A, which
restricts the maximum output current based on Equation 12:
ΔI P-P
I VIOMAX = 2 – --------------2
(EQ. 12)
Where ΔIP-P is the ripple current in the buck inductor as shown in
Equation 13:
HAVDD BUCK INDUCTOR
The inductance is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. Increasing the inductance reduces the ripple
current and voltage. However, the large inductance values reduce
the converter’s response time to load transients. Taking all the
factors into consideration, a 3.3µH to 10µH inductor range is
recommended for the HAVDD buck converter. Besides the
inductance, the DC resistance and the saturation current are also
factors that need to be considered when choosing a buck
inductor. Low DC resistance can help maintain high efficiency.
Saturation current rating should be higher than the peak inductor
current in the application. Table 5 shows some
recommendations for the HAVDD buck inductor.
TABLE 6. HAVDD BUCK INDUCTOR RECOMMENDATION
(EQ. 13)
Where L is the buck inductance, fs is the switching frequency of VIO
buck inductor.
ISL98604 uses internal feedback resistor divider to divide the
output VIO voltage down to the nominal reference voltage. The VIO
voltage is programmable through I2C control, which will be
described in more detail in section “I2C Control” on page 20.
INPUT CAPACITOR
Selection of input capacitance is important for input voltage ripple.
A ceramic capacitor should be used because of its small ESR.
Another important criteria when selecting input capacitor is that it
should be able to support the maximum AC RMS current, which
occurs at D = 0.5 and maximum output current.
DCR
(mΩ)
DIMENSIONS
(mm)
VENDOR
6.8µH/
3.6APEAK
74.1
4.0x4.0x3.1
Coilcraft
XAL4030682MEB
I ACRMS =
6.8µH/
2.8APEAK
45
7.3x6.8x3.2
TDK
RLF7030T6R8M2R8
Where IVIO is the output current of the VIO buck converter. Table 8
shows recommendations for input capacitors.
INDUCTANCE
PART
NUMBER
VIO
ΔI P-P = ------------ ⋅ ( 1 – D )
L ⋅ fs
D ⋅ ( 1 – D ) ⋅ I VIO
(EQ. 14)
TABLE 8. VIO BUCK CONVERTER INPUT CAPACITOR RECOMMENDATION
OUTPUT CAPACITOR
The output ripple and transient response typically drives the
selection of an output capacitor. A 10µF or a 22µF ceramic
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/25V
1206
TDK
C3216X7R1E106K
22µF/25V
1206
Murata
GRM31CR61E226KE15L
VIO BUCK INDUCTOR
The inductance is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
17
FN7687.0
December 17, 2012
ISL98604
load transient. Increasing the inductance reduces the ripple
current and voltage. However, the large inductance values reduce
the converter’s response time to load transients. Taking all the
factors into consideration, a 3.3µH to 10µH inductor range is
recommended for the VIO buck converter. Besides the
inductance, the DC resistance and the saturation current are also
factors that need to be considered when choosing a buck
inductor. Low DC resistance can help maintain high efficiency.
Saturation current rating should be higher than the peak inductor
current in the application. Table 9 shows some
recommendations for the VIO buck inductor.
TABLE 9. VIO BUCK INDUCTOR RECOMMENDATION
DCR
(mΩ)
DIMENSIONS
(mm)
VENDOR
6.8µH/
3.6APEAK
74.1
4.0x4.0x3.1
Coilcraft
XAL4030682MEB
6.8µH/
2.8APEAK
45
7.3x6.8x3.2
TDK
RLF7030T6R8M2R8
INDUCTANCE
PART
NUMBER
VIO BUCK DIODE
A Schottky diode is recommended for its fast recovery time and
low forward voltage. The reverse voltage rating should be higher
than the maximum input voltage. The peak current rating should
be higher than the current limit of the VIO switch, and the
average current rating should be higher than the value given by
Equation 15.
I AVG = ( 1 – D )*I VIO
(EQ. 15)
Where IVIO is the output current of the VIO buck converter. Table 10
shows diode recommendations..
TABLE 10. VIO BUCK DIODE RECOMMENDATION
DIODE
VR/IAVG
RATING
PACKAGE
VENDOR
PMEG2020EJ
20V/2A
SOD323F
NXP Semiconductors
SS22
20V/2A
SMB
Fairchild Semiconductor
VCORE
----------------------- = D
V IN
(EQ. 16)
where D is the duty cycle of the upper MOSFET and VIN of the
VCORE buck converter is the output voltage of the VIO buck
converter.
The peak current limit of the VCORE buck converter is set to 1A,
which restricts the maximum output current based on
Equation 17:
ΔI P-P
I VCOREMAX = 1 – --------------2
(EQ. 17)
Where ΔIP-P is the ripple current in the buck inductor, as shown in
Equation 18:
VCORE
ΔI P-P = ----------------------- ⋅ ( 1 – D )
L ⋅ fs
(EQ. 18)
Where L is the buck inductance and fs is the switching frequency of
the VCORE buck inductor.
The ISL98604 uses internal feedback resistor divider to divide the
output VCORE voltage down to the nominal reference voltage. The
VCORE voltage is programmable through I2C control, which will be
described in more detail in section “I2C Control” on page 20.
INPUT CAPACITOR
The input of the VCORE buck converter is internally connected to
the output of VIO buck converter. Therefore, the output
capacitors of the VIO buck converter also plays the role of input
capacitor of the VCORE buck converter. Please refer to the
“Output Capacitor” section of the “VIO Buck Converter” on
page 17 for selection of input capacitors for the VCORE buck
converter.
VCORE BUCK INDUCTOR
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/10V
0805
TDK
C2012X7R1A106K
The inductance is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. Increasing the inductance reduces the ripple
current and voltage. However, the large inductance values reduce
the converter’s response time to load transients. Besides the
inductance, the DC resistance and the saturation current are also
factors that need to be considered when choosing a buck
inductor. Low DC resistance can help maintain high efficiency.
Saturation current rating should be higher than the peak inductor
current in the application. Taking all the factors into
consideration, 2.2µH inductors as shown in Table 12 are
recommended for the VCORE buck inductor.
10µF/10V
0805
Murata
GRM21BR71A106KE51L
TABLE 12. VCORE BUCK INDUCTOR RECOMMENDATION
22µF/10V
0805
TDK
C2012X5R1A226M
OUTPUT CAPACITOR
The output ripple and transient response typically drives the
selection of output capacitor. 10µF or 22µF ceramic capacitors
(Table 11) are recommended.
.
current mode, the relationship between input voltage and output
voltage is as shown in Equation 16.
TABLE 11. VIO BUCK OUTPUT CAPACITOR RECOMMENDATION
VCORE Buck Converter
OPERATION
VCORE buck converter is a synchronous step-down converter with
a fixed switching frequency (1.5MHz) to generate voltage and
supply current to the core circuit of the LCD system. In continuous
18
DCR
(mΩ)
DIMENSIONS
(mm)
VENDOR
2.2µH/
1.26APEAK
55
3.0x2.5x1.2
TDK
VLF302512M
T-2R2M
2.2µH/
5.6APEAK
35.2
4.0x4.0x2.1
Coilcraft
XAL4020222ME
INDUCTANCE
PART
NUMBER
FN7687.0
December 17, 2012
ISL98604
TABLE 12. VCORE BUCK INDUCTOR RECOMMENDATION
INDUCTANCE
2.2µH/
5.5APEAK
DCR
(mΩ)
DIMENSIONS
(mm)
VENDOR
12
7.3x6.8x3.2
TDK
PART
NUMBER
RLF7030T2R2M5R4
OUTPUT CAPACITOR
The output ripple and transient response typically drives the
selection of output capacitor. 10µF or 22µF ceramic capacitors
(Table 13) are recommended.
TABLE 13. VIO BUCK OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
SIZE
VENDOR
PART NUMBER
10µF/6.3V
0603
MURATA
GRM188R60J106ME47D
10µF/6.3V
0402
TDK
C1005X5R0J106M
22µF/6.3V
0603
TDK
C1608X5R0J226M
VON Linear-Regulator Controller
The ISL98604 includes two independent linear-regulator controllers
for positive output voltage (VON) and negative voltage (VOFF). The
VON and VOFF linear-regulator controller subcircuit is shown in the
“Typical Application Circuit” on page 2.
The VON power supply is used to power the positive supply of the row
driver in the LCD panel. It consists of an external charge pump
powered from the switching node (LX) of the boost converter,
followed by a low dropout linear regulator (LDO_ON). The LDO_ON
regulator uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz) transconductance
amplifier capable of 5mA output current, which is sufficient for up to
50mA or more output current under the low dropout condition
(forced beta of 10). Typical VON voltage supported by ISL98604 is
programmable from +19V to +34V through I2C control, which will be
described in more detail in section “I2C Control” on page 20.
VOFF Linear-Regulator Controller and Charge
Pump
The VOFF power supply is used to power the negative supply of the
row driver in the LCD panel. It consists of an external diode-capacitor
charge pump powered from the switching node of the VIO buck
converter, followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the pass
element. The onboard LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 5mA output current, which is
sufficient for up to 50mA or more output current under the low
dropout condition (forced beta of 10). Typical VOFF voltage
supported by ISL98604 is programmable from -8.1V to -1.8V
through I2C control, which will be described in more detail in section
“I2C Control” on page 20.
Calculation of the Linear Regulator
Base-Emitter Resistors
For the pass transistor of the linear regulator, DC current gain (Hfe)
and unity gain frequency (fT) are usually specified in the datasheet.
The pass transistor adds a pole to the loop transfer function at
fp = fT/Hfe. Therefore, in order to maintain phase margin at low
frequency, the best choice for a pass device is often a high
19
frequency, low gain switching transistor. Further improvement can
be obtained by adding a base-emitter resistor RBE, which increases
the pole frequency to: fp = fT * (1 + Hfe * re/RBE)/Hfe, where
re = KT/qIc. Therefore, choose the lowest value RBE in the design as
long as there is still enough base current (IB) to support the
maximum output current (IC).
For example, the VON linear regulator. If a Fairchild MMBT3906 PNP
transistor is used as the external pass transistor (Q7 in the
application diagram), then for a maximum VON operating
requirement of 50mA, the data sheet indicates Hfe_min = 60. The
base-emitter saturation voltage is: Vbe_max = 0.7V.
For the ISL98604, the minimum drive current is:
I_DRVP_min = 3mA.
The minimum base-emitter resistor, RBP, can now be calculated as
Equation 19:
RBP_min = VBE_max ⁄ (I_DRVP_min - Ic/Hfe_min =
(EQ. 19)
( ( 0.7V ) ⁄ ( 3mA – ( 50mA ) ⁄ 60 ) ) = 325Ω
This is the minimum value that can be used so, we now choose a
convenient value greater than this minimum value (e.g., 400W).
Larger values may be used to reduce quiescent current, however,
regulation may be adversely affected by supply noise if RBP is made
too high in value.
VON/VOFF Charge Pump
Single or multiple stages of charge pumps are needed to generate
output voltage higher than VBOOST and negative voltage. The charge
pumps can be driven by switching node of the boost converter and
VIO buck converter, as shown in “Typical Application Circuit” on
page 2.
The number of the charge pump stages can be calculated using
Equations 20 and 21.
VOFF HEADROOM = N × V IN – 2 × N × V d – VOFF > 0
(EQ. 20)
VON HEADROOM = ( N + 1 ) × AVDD – N × V d – VON > 0
(EQ. 21)
Where N is the number of the charge pump stages, Vd is the
forward voltage drop of one Schottky diode used in the charge
pumps. Vd is varied with forward current and ambient
temperature, so it should be the maximum value in the diode
datasheet according to max forward current and lowest
temperature in the application condition.
Once the number of the charge pump stages is determined, the
relationship between output voltages and the maximum current
that the charge pump can deliver can be calculated using
Equations 22 and 23 as follows:
V OFF = N × ( – VIN + 2 × V d + I VOFF ⁄ ( Freq × C fly ) )
(EQ. 22)
V ON = AVDD + N × ( AVDD – 2 × V d – I VON ⁄ ( Freq × C fly ) )
(EQ. 23)
Where Freq is the switching frequency of the AVDD boost, C_fly is
the flying capacitance (C64, C53 in the application diagram).
IVON and IVOFF are the loadings of VON and VOFF.
FN7687.0
December 17, 2012
ISL98604
CHARGE PUMP OUTPUT CAPACITORS
A ceramic capacitor with low ESR is recommended. With ceramic
capacitors, the output ripple voltage is dominated by the
capacitance value. The capacitance value can be chosen by
Equation 24:
I OUT
C OUT ≥ -----------------------------------------------------2 × V RIPPLE × f OSC
(EQ. 24)
For VON charge pump, fOSC is the switching frequency of boost
converter; for VOFF charge pump, fOSC is the switching frequency of
VIO buck converter.
VON Temperature Compensation
The ISL98604 can output two levels of VON voltages depending
on the temperature. A voltage divider which consists of two
resistors (R61 and R62) and a thermistor, as shown in the
application diagram connected to TCOMP pin is used to
determine the VON voltage.
Figure 21 shows that the VON voltage will be VON_LT when the
TCOMP voltage is above the compensation threshold voltage. If
the TCOMP voltage is below the compensation threshold voltage,
the VON voltage will be VON_HT. There is a 20mV hysteresis
between the threshold when TCOMP voltage rises and the
threshold when TCOMP voltage falls. R61, R62, and thermistor
values are selected to set the VON voltage at desired
temperature. VON_LT and VON_HT are programmable through
I2C control, which will be described in more detail in section “I2C
Control” on page 20.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
TABLE 14. I2C INTERFACE SPECIFICATION
PARAMETER
MIN
TYP
MAX
UNITS
SDA and SCL Rise Time
1000
ns
SDA and SCL Fall Time
300
ns
I2C Bus Capacitive Load
400
pF
PROTOCOL CONVENTIONS
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 22). On
power-up, the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH.
ISL98604 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 22). All I2C interface must be
terminated by a STOP condition, which is a LOW to HIGH
transition of SDA while SCL is high (see Figure 22). An ACK
(Acknowledge) is a software convention used to indicate a
successful data transfer. The transmitting device, either master or
slave, releases the SDA bus after transmitting eight bits. During the
ninth clock cycle, the receiver pulls the SDA line LOW to
acknowledge the reception of the eight bits of data (see Figure 23).
WRITE OPERATION
FBP
VON_LT
VDC
R61
VON (V)
TCOMP
NTC
R62
VON_HT
To write into a DAC register (DR), it requires a START condition
from the Master, followed by 7-bit device address (010000A0),
R/W bit (=0 when writing), a valid DAC register address Byte
(01h-09h), a data byte, and a STOP condition. After each of the
three bytes, the ISL98604 responds with an ACK. At this time, if
the data byte is to be written only to volatile registers, the device
enters its standby state.
Example: Writing 21h to register address 01h (HAVDD)
TEMPERATURE WHEN TCOMP VOLTAGE
> VTCOMP_TH = 1.265V
TEMPERATURE (°C)
TEMPERATURE HYSTERESIS RESULTED FROM VTCOMP_HYST = 20mV
FIGURE 21. VON TEMPERATURE COMPENSATION
I2C Control
The ISL98604 supports all rail outputs with fully programmable I2C
control. The programmed output values can be stored into EEPROM
during the operation and read out.
The I2C protocol defines any device that sends data on to the bus
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, ISL98604 operates as a slave device in all
applications. The fall and rise time of SDA and SCL signal should
be in the range listed in Table 14. The capacitive load on the I2C
bus is also specified in Table 14.
20
To write data in the DAC registers into EEPROM, it requires a
START condition from the Master, followed by 7-bit device
address, R/W bit (=0 when writing), Control Register (CR)
address byte (FFh), a data byte of 80h to write data in DRs to
EEPROM and a STOP condition. After each of the three bytes,
ISL98604 responds with an ACK. If the Data Byte is to be written
to EEPROM, ISL98604 begins its internal write cycle, which takes
25ms to finish. During the internal EEPROM write cycle, the
device ignores transitions at the SDA and SCL pins and the SDA
output is at high impedance state. When the internal EEPROM
write cycle is completed, the ISL98604 enters its standby state.
Example: Writing current data in DRs into EEPROM.
READ OPERATION
To read from the DAC register (DR), it first requires to write 00
into the Control Register (CR) (FFh) to specify that the data is
read from DR. Then it sends desired DR address to be read
(00h-09h). Finally, it reads data from DR, which requires a START
condition from Master, followed by 7-bit device address
(010000A0), R/W bit (= 1 when reading); the second byte
FN7687.0
December 17, 2012
ISL98604
contains the data read from the specified DR. Note that the
Master will not acknowledge this byte. Finally, the last Master
sends STOP condition.
Example: Reading data from DR address 06h (VOFF).
To read from EEPROM first, it first requires to write 01 into the
Control Register (CR) (FFh) to specify that the data is read from
EEPROM. Then it sends the desired DR address to be read
(00h-09h). Finally, it reads data from DR, which requires a START
condition from Master, followed by 7-bit device address
(010000A0), R/W bit (=1 when reading); the second byte
contains the data read from EEPROM. Note that the Master will
not acknowledge this byte. Finally, the last Master sends STOP
condition.
Example: Reading data from EEPROM address 06h (VOFF).
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 22. VALID DATA CHANGES, START, AND STOP CONDITION
SCL FROM
MASTER
1
8
SDA OUTPUT FROM
TRANSMITTER
9
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 23. ACKNOWLEDGE RESPONSE FROM RECEIVER
21
FN7687.0
December 17, 2012
ISL98604
REGISTER MAP AND REGISTER VALUES
TABLE 16. DATA FORMAT OF DAC REGISTER AND EEPROM
Table 15 shows the address of the DAC registers and their default
values. Table 16 shows the data format of each register. Table 17
shows the parameters corresponding to different register values.
TABLE 15. MEMORY MAP OF DAC REGISTER AND EEPROM
AVDD (Default Data: 21h)
MSB
R
REGISTER
ADDRESS
AVDD
00h
6-bit Non-volatile
21h
HAVDD
01h
6-bit Non-volatile
20h
MSB
R
R
VCORE
03h
4-bit Non-volatile
01h
VON_LT
04h
4-bit Non-volatile
09h
MSB
R
4-bit Non-volatile
09h
VOFF
06h
6-bit Non-volatile
20h
DLY1
07h
3-bit Non-volatile
01h
MSB
R
3-bit Non-volatile
03h
CR
FFh
Volatile
00h
1
0
0
0
0
R
0
1
0
0
0
1
0
0
1
0
0
0
0
0
R
0
0
R
0
1
R
0
1
1
R
R
0
R
R
1
LSB
R
05h
09h
1
VCORE (Default Data: 01h)
VON_HT
DLY3
0
LSB
R
03h
03h
0
VIO (Default Data: 03h)
3-bit Non-volatile
3-bit Non-volatile
0
LSB
R
02h
08h
0
MSB
VIO
DLY2
1
HAVDD (Default Data: 20h)
DATA
(VOLATILE/
NON-VOLATILE)
FACTORY DEFAULT
(POWER-UP)
LSB
R
R
R
1
VON_LT (Default Data: 09h)
LSB
R
R
R
1
VON_HT (Default Data: 09h)
MSB
R
LSB
R
R
R
1
VOFF (Default Data: 20h)
MSB
R
LSB
R
1
0
0
DLY1 (Default Data: 01h)
MSB
R
LSB
R
R
R
1
DLY2 (Default Data: 03h)
MSB
R
LSB
R
R
R
1
DLY3 (Default Data: 03h)
MSB
R
LSB
R
R
R
Control Register (Default Data: 00h)
MSB
Write
EEPROM
Data
LSB
R
R
R
R
Read EEPROM
or DR data
R: Reserved
<Contol Register Data>
0h: Read DAC register data only
01h: ead EEPROM data only
80h Write all DAC Register data to EEPROM
22
FN7687.0
December 17, 2012
ISL98604
TABLE 17. PARAMETER VALUES CORRESPONDING TO REGISTER VALUES
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
STEP
HEX
AVDD
(V)
HAVDD
(V)
VIO
(V)
VCORE
(V)
VON_LT
(V)
VON_HT
(V)
VOFF
(V)
DLY1
(ms)
DLY2
(ms)
DLY3
(ms)
0
00h
12.7
6.40
3.0
0.9
19
17
-1.8
0
0
0
1
01h
12.8
6.45
3.1
1.0
20
18
-1.9
10
10
10
2
02h
12.9
6.50
3.2
1.1
21
19
-2.0
20
20
20
3
03h
13.0
6.55
3.3
1.2
22
20
-2.1
30
30
30
4
04h
13.1
6.60
3.4
1.3
23
21
-2.2
40
40
40
5
05h
13.2
6.65
3.5
1.4
24
22
-2.3
50
50
50
6
06h
13.3
6.70
3.6
1.5
25
23
-2.4
60
60
60
7
07h
13.4
6.75
3.7
1.6
26
24
-2.5
70
70
70
8
08h
13.5
6.80
1.7
27
25
-2.6
9
09h
13.6
6.85
1.8
28
26
-2.7
10
0Ah
13.7
6.90
1.9
29
27
-2.8
11
0Bh
13.8
6.95
2.0
30
28
-2.9
12
0Ch
13.9
7.00
2.1
31
29
-3.0
13
0Dh
14.0
7.05
2.2
32
30
-3.1
14
0Eh
14.1
7.10
2.3
33
31
-3.2
15
0Fh
14.2
7.15
2.4
34
32
-3.3
16
10h
14.3
7.20
-3.4
17
11h
14.4
7.25
-3.5
18
12h
14.5
7.30
-3.6
19
13h
14.6
7.35
-3.7
20
14h
14.7
7.40
-3.8
21
15h
14.8
7.45
-3.9
22
16h
14.9
7.50
-4.0
23
17h
15.0
7.55
-4.1
24
18h
15.1
7.60
-4.2
25
19h
15.2
7.65
-4.3
26
1Ah
15.3
7.70
-4.4
27
1Bh
15.4
7.75
-4.5
28
1Ch
15.5
7.80
-4.6
29
1Dh
15.6
7.85
-4.7
30
1Eh
15.7
7.90
-4.8
31
1Fh
15.8
7.95
-4.9
32
20h
15.9
8.00
-5.0
33
21h
16.0
8.05
-5.1
34
22h
16.1
8.10
-5.2
35
23h
16.2
8.15
-5.3
36
24h
16.3
8.20
-5.4
37
25h
16.4
8.25
-5.5
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FN7687.0
December 17, 2012
ISL98604
TABLE 17. PARAMETER VALUES CORRESPONDING TO REGISTER VALUES (Continued)
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
VIO
(V)
VCORE
(V)
VON_LT
(V)
VON_HT
(V)
VOFF
(V)
DLY1
(ms)
DLY2
(ms)
DLY3
(ms)
STEP
HEX
AVDD
(V)
HAVDD
(V)
38
26h
16.5
8.30
-5.6
39
27h
16.6
8.35
-5.7
40
28h
16.7
8.40
-5.8
41
29h
16.8
8.45
-5.9
42
2Ah
16.9
8.50
-6.0
43
2Bh
17.0
8.55
-6.1
44
2Ch
17.1
8.60
-6.2
45
2Dh
17.2
8.65
-6.3
46
2Eh
17.3
8.70
-6.4
47
2Fh
17.4
8.75
-6.5
48
30h
17.5
8.80
-6.6
49
31h
17.6
8.85
-6.7
50
32h
17.7
8.90
-6.8
51
33h
17.8
8.95
-6.9
52
34h
17.9
9.00
-7.0
53
35h
18.0
9.05
-7.1
54
36h
18.1
9.10
-7.2
55
37h
18.2
9.15
-7.3
56
38h
18.3
9.20
-7.4
57
39h
18.4
9.25
-7.5
58
3Ah
18.5
9.30
-7.6
59
3Bh
18.6
9.35
-7.7
60
3Ch
18.7
9.40
-7.8
61
3Dh
18.8
9.45
-7.9
62
3Eh
18.9
9.50
-8.0
63
3Fh
19.0
9.55
-8.1
NOTE: Shaded numbers are the factory default at power-up.
PROTECTIONS
The ISL98604 integrates overcurrent protection (OCP), overvoltage
protection (OVP), and over-temperature protection (OTP). The
protection threshold and the reaction of the chip are listed in
Table 18.
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FN7687.0
December 17, 2012
ISL98604
TABLE 18. ISL98604 PROTECTION TABLE
CONTINUED FAUTL TIME
TO SHUTDOWN
CHIP REACTION
RE-ENABLE
MECHANISM
Switch peak current
higher than 4A
NA
Terminate PWM
NA
IDS current higher than
3.1A during operation
1ms
Shut down whole IC
Power Cycle
IDS current higher than
6A at start-up and
normal operation
Immediately
Shut down whole IC
Power Cycle
HAVDD
Switch peak current
higher than 1A or lower
switch peak current
higher than 0.9A
NA
Terminate PWM
NA
VIO
Switch peak current
higher than 2A
NA
Terminate PWM
NA
VCORE
Switch peak current
higher than 1A
NA
Terminate PWM
NA
OVP
AVDD
Higher than 20.5V on
SWI pin
Immediately
Shut down whole IC
Power Cycle
OTP
Junction Temp
Temperature higher
than +140°C
Immediately
Shut down whole IC
Power Cycle
CATEGORY
CHANNEL
TRIP LEVEL (TYP)
OCP
AVDD
AVDD delay FET
Start-Up Sequence
When VIN rising exceeds UVLO and EN is high, VIO and VCORE
start-up. When VIO and VCORE reach 90% of the their target
values, after a delay time of DLY1, PGOOD rises up and VOFF
soft-starts; when VOFF reaches 90% of its target value, after a
delay time of DLY2, AVDD and HAVDD start to rise up. The
soft-start time of AVDD and HAVDD depends on the capacitance
on the soft-start pin. When AVDD and HAVDD reach 90% of their
target values, after a delay time of DLY3, VON starts to rise up.
DLY1, DLY2 and DLY3 are programmable through I2C control,
which is described in section “I2C Control” on page 20. The detailed
start-up sequence is shown in Figure 24.
Layout Recommendation
PCB layout is critical especially at high switching frequency. The
device's performance, including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout.
6. The exposed die plate, on the underside of the package,
should be soldered to an equivalent area of metal on the PCB.
This contact area should have multiple via connections to the
back of the PCB as well as connections to intermediate PCB
layers, if available, to maximize thermal dissipation away
from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track and
ground plane area connected to the exposed die plate should
be maximized and spread out as far as possible from the IC.
The bottom and top PCB areas especially should be
maximized to allow thermal dissipation to the surrounding air.
8. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
There are some general guidelines for layout:
1. Place the external power components (the input capacitors,
output capacitors, boost inductor and output diodes, etc.) in
close proximity to the device. Traces to these components
should be kept as short and wide as possible to minimize
parasitic inductance and resistance.
2. Place VDC and VREF bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from the LX
node as possible.
5. The power ground (PGND) and signal ground (SGND) pins
should be connected at the ISL98604 exposed die plate area.
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FN7687.0
December 17, 2012
ISL98604
U V LO
UVLO
V IN
VLO
VHI
VDC
EN
V IO
90%
VCORE
DLY1
PGOOD
VOFF
90%
90%
50%
DLY2
AVDD
50%
HAVDD
DLY3
VON
NOTES:
9. VIO and VCORE start when EN is enabled and 90% rising point will occur at the same time.
The timing gap between VIO and VCORE at 90% rising point will be less than 3ms.
10. PGOOD and VOFF will be triggered after VIO and VCORE rise and not before delay time DLY1.
11. AVDD and HAVDD start-up after delay time DLY2. Both are synchronized at 50% rising point.
12. VON will be triggered after AVDD and HAVDD rise and not before delay time DLY3.
FIGURE 24. ISL98604 START-UP SEQUENCE
26
FN7687.0
December 17, 2012
ISL98604
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
December 17, 2012
FN7687.0
CHANGE
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
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our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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27
FN7687.0
December 17, 2012
ISL98604
Package Outline Drawing
L40.5x5D
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/10
4X 3.60
5.00
36X 0.40
A B
6
PIN #1 INDEX AREA
5.00
3.65
6
PIN 1
INDEX AREA
(4X)
0.15
40X 0.4± 0.1
TOP VIEW
b
BOTTOM VIEW
0.20
0.10 M
C A B
4
PACKAGE OUTLINE
0.40
SEE DETAIL "X"
0.750
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
0.050
3.65
5.00
SIDE VIEW
(36X 0.40)
(40X 0.20)
5
C 0.2 REF
(40X 0.60)
0.00 MIN
0.05 MAX
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.27mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220WHHE-1
either a mold or mark feature.
28
FN7687.0
December 17, 2012