ISL97652 ® December 21, 2006 • AVDD boost up to 19.5V (OVP threshold), with integrated 2.8APEAK FET • Overvoltage protection (OVP) • 2A integrated AVDD delay FET, with short circuit protection • Dual charge pump controllers for VON and VOFF • VLOGIC buck with integrated 2.5APEAK FET • VON slicing • Dual high speed VCOM amplifiers • 650kHz/1.3MHz switching frequency • Integrated sequencing The asynchronous buck converter features an integrated 2.5A FET. It also operates from the 650kHz or 1.3MHz internal clock and features separate enable and soft-start control. • UVLO and OTP protection The dual charge pump controllers used for VON and VOFF generation uses the full FOSC switching frequency to allow the use of small output components for board space efficiency. VON is further processed through an integrated VON-SLICE circuit for reduced flicker. Applications • Pb-free plus anneal available (RoHS compliant) • LCD-TVs (up to 40”) • Industrial/medical LCD displays Pinout Ordering Information 37 SW1 38 SW2 34 PGND1 48 Ld 7x7 QFN L48.7x7 VFLK 5 13” 48 Ld 7x7 QFN L48.7x7 (4k pcs) VDPM 6 1 31 VC 30 SS RE 7 VGHM 8 29 DLY2 SWB2 24 25 PVIN1 SWB1 23 26 PVIN2 DRVP 12 CBOOT 22 27 VDC GND 11 FBB 21 28 FREQ FBP 10 VCB 20 VGH 9 SSB 19 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 32 EN2 THERMAL PAD DLY1 18 13” 48 Ld 7x7 QFN L48.7x7 (1k pcs) 33 EN1 CE 4 REF 17 - PACKAGE (Pb-Free) FBN 16 ISL97652IRZ ISL97652IRZ-TK ISL97652IRZ 43 AVIN VGL 3 TAPE & REEL ISL97652IRZ 44 NEG2 35 PGND2 PKG. DWG. # PART MARKING AGND 15 ISL97652IRZ-T 36 PGND3 OUT1 2 SUP 13 ISL97652IRZ POS1 1 DRVN 14 PART NUMBER (Note) 45 POS2 48 NEG1 Available in the 48 Ld 7mmx7mm QFN package, the ISL97652 is specified for ambient operation over the -40°C to +85°C temperature range. 46 OUT2 ISL97652 (48 LD QFN) TOP VIEW 47 OGND The integrated amplifiers feature high slew-rate and high output current capability. They are permanently enabled when AVIN is present. • Thermally enhanced 7x7 QFN package 39 SWI Operating at 650kHz or 1.3MHz, the AVDD boost converter features a 2.8A boost FET. A short circuit protected AVDD delay switch is integrated to provide sequencing of the AVDD output. Feedback is taken from the far side of the delay FET for improved regulation and an OVP circuit protects output side components. The boost features programmable soft-start. • 8V to 15V input supply 40 SUI The ISL97652 represents a high power, integrated LCD supply IC targeted at large panel LCD displays. The ISL97652 integrates a high power, boost converter for AVDD generation, delay switch, regulated VON and VOFF charge pumps, VON slicing circuitry, a buck regulator for logic supply generation and dual high power VCOM amplifiers. Features 41 FB 4-Channel Integrated LCD Supply with Dual VCOM Amplifiers FN9287.0 42 SWO Data Sheet CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97652 Absolute Maximum Ratings (TA = +25°C) Thermal Information Maximum Pin Voltages, All Pins Except Below . . . . . . . -0.3 to 6.5V SW, SUP, DRVP, DRVN, SUI, SWO, AVIN, POS1, NEG1, OUT1, POS2, NEG2, OUT2, VGL . . . . . . . . . . . . . . . . . . -0.3 to 22V SWI,SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 24V SUI . . . . . . . . . . . . . . . . . . . . . . . V(SWI) - 6.5V to V(SWI) +0.3V PVIN, SWB, VFLK, VDPM, EN1, EN2, FREQ . . . . . -0.3 to 15.5V VGH, VGHM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 36V Thermal Resistance Recommended Operating Conditions θJA (°C/W) θJC (°C/W) 7x7 QFN Package (Notes 1, 2) . . . . . . 26 1.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Power Dissipation TA ≤ +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.7W TA = +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0W TA = +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4W Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 15V Boost Output Voltage, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . +15V VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . +15V to +32V VOFF Output Range, VOFF . . . . . . . . . . . . . . . . . . . . . . . -15V to -5V Logic Output Voltage Range, VLOGIC . . . . . . . . . . . . +1.5V to +3.3V Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10µF Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH-10µH Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . . . 2x22µF Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH-10µH Operating Ambient Temperature Range . . . . . . . . . -40°C to +85°C Operating Junction Temperature Range . . . . . . . . -40°C to +125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may trigger the shutdown of the device even before +150°C, since this number is specified as typical. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +85°C, unless otherwise stated. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT 12 15 V SUPPLY PINS PVIN Supply Voltage 8 VSUP Charge Pumps Positive Supply 8 20 V VGH VON-SLICE Positive Supply 8 30 V AVIN Op-AmpV Positive Supply 4.5 20 V PIVIN Quiescent Current into PVIN 3 6 mA 0.5 5 µA 0.5 mA Disabled 5 µA 7 mA Enabled, no switching Disabled ISUP VSUP Supply Current Enabled, no switching and VPOUT = VSUP IAVIN AVIN Supply Current For AVIN range VREF Reference Voltage TA = +25°C FOSC Oscillator Frequency for Buck, Boost, VON and VOFF Functions 1.252 1.265 1.278 V 1.240 1.265 1.290 V FREQ = VIN 1100 1300 1500 kHz FREQ = GND 550 650 750 kHz 2.8 AVDD BOOST IBOOST Boost Switch Peak Current Boost Peak Current limit EFFBOOST Peak Efficiency See graphs and component recommendations 2 A 91 % FN9287.0 December 21, 2006 ISL97652 Electrical Specifications PARAMETER VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +85°C, unless otherwise stated. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 125 200 mΩ rDS(ON) Switch On Resistance ΔVBOOST/ΔVIN Line Regulation Vin = 8V to 12V at Iload=200mA, see “Typical Performance Curves” on page 6 0.08 % ΔVBOOST/ΔIOUT Load Regulation 100mA to 500mA, see “Typical Performance Curves” on page 6 0.5 % VFB Boost Feedback Voltage TA = +25°C Dmax_boost Dmin_boost Boost Maximum Duty Cycle Boost Minimum Duty Cycle 1.252 1.265 1.278 V 1.240 1.265 1.290 V FOSC = 650kHz 90 % FOSC = 1.3MHz 85 % FOSC = 650kHz 10 % FOSC = 1.3MHz 20 % AVDD DELAY SWITCH RPD RDS(ON) SWIMAX Maximum SWI Voltage 21 IdelayFET Delay FET RMS Current Limit 1.5 FETtimeout Delay FET Fault Timeout Ipull-Down Pull-down Current Applied to FET Gate and SUI VGATE SUI Voltage When Switch is Fully Switched On SWILEAK SWI Leakage Current When Disabled VDSOK Drain Source Voltage When Boost is Enabled SWI =16.5V 15.7 V VDSHYS Hysteresis on VDSOK Spec SWI =16.5V 1.4 V IBUCK Buck Switch Current Current limit EFFBUCK Peak Efficiency See graphs and component recommendations RDS(ON) BK Switch On Resistance ΔVBUCK/ΔVIN Line Regulation Vin = 8V to 12V at Iload = 200mA, see “Typical Performance Curves” on page 6 0.05 % ΔVBUCK/ΔIOUT Load Regulation 200mA to 1000mA, see “Typical Performance Curves” on page 6 0.1 % VFBB FBL Regulation Voltage TA = +25°C 180 I(SWO) > IdelayFET 240 mΩ V 2 A 100 µs 65 µA V(SWI) - 5 V VIN = 15V, SWI = 21V, SWO = 0V, EN1 = EN2 = 0V 1 µA VLOGIC BUCK Dmax_buck Dmin_buck Buck Maximum Duty Cycle Buck Minimum Duty Cycle 2.5 A 85 170 % 250 mΩ 1.252 1.265 1.278 V 1.240 1.265 1.290 V FOSC = 650kHz 90 % FOSC = 1.3MHz 85 % FOSC = 650kHz 10 % FOSC = 1.3MHz 20 % NEGATIVE (VOFF) CHARGE PUMP VOFF VOFF Output Voltage Range 1X Charge Pump ILoad_NCP_min External Load Driving Capability VSUP >5V 3 VSUP + 1.4V 30 0 V mA FN9287.0 December 21, 2006 ISL97652 Electrical Specifications VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +85°C, unless otherwise stated. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT Ron(DRVN)H High-Side Driver ON Resistance at DRVN I(DRVN) = +60mA 11 Ω RON(DRVN)L Low-Side Driver ON Resistance at DRVN I(DRVN) = -60mA 10 Ω Ipu(DRVN)lim Pull-Up Current Limit in DRVN V(DRVN) = 0V to V(SUP)-0.5V Ipd(DRVN)lim Pull-Down Current Limit in DRVN V(DRVN) = 0.36V to V(VSUP) I(DRVN)leak Leakage Current in DRVN V(FBN) < 0 or EN1 = LOW VFBN FBN Regulation Voltage TA = +25°C D_NCP_max Max Duty Cycle of the Negative Charge Pump Rpd(FBN)off Pull-Down Resistance, Not Active 60 270 -200 -2 mA -60 mA 2 µA 0.48 0.5 0.52 V 0.47 0.5 0.53 V 50 I(FBN) = 500µA 2.5 3.5 % 4.5 kΩ 34 V POSITIVE (VON) CHARGE PUMP VON VON Output Voltage Range ILoad_PCP_min External Load Driving Capability Ron(DRVP)H High-Side Driver ON Resistance at DRVP I(DRVP) = +60mA 11 Ω Ron(DRVP)L Low-Side Driver ON Resistance at DRVP I(DRVP) = -60mA 10 Ω Ipu(DRVP)lim Pull-Up Current Limit in DRVP V(DRVP) = 0V to V(SUP)-0.5V Ipd(DRVP)lim Pull-Down Current Limit in DRVP V(DRVP) = 0.36V to V(VSUP) I(DRVP)leak Leakage Current in DRVP VFBP > VREF or EN1 or EN2 = low VFBP FBP Regulation Voltage TA = +25°C D_PCP_max 2X or 3X charge pump VSUP + 2V 30 60 mA 270 -200 -2 mA -60 mA 2 µA 1.225 1.25 1.275 V 1.22 1.25 1.28 V Max Duty Cycle of the Positive Charge Pump 50 % LOGIC INPUTS VHI Logic “HIGH” EN1, EN2, VFLK, VDPM 2.0 V VLO Logic “LOW” EN1, EN2, VFLK, VDPM 0.8 V IL_pd Logic Pin Pull-Down Current VLOGIC > VLO 25 µA 30 V VON SLICE VGH VGH Voltage 8 IVGH VGH Input Current VFLK = 0, RE=33K 300 µA VFLK = 5V, RE=33K 40 µA VGL VGL Voltage 3 IVGL VGL Input Current -2 RONVGH VGH to VGH_M On Resistance TDEL DELAY Time CE = 470pF VGH - 2 V 0.1 2 µA 15 30 Ω 10 µs VCOM AMPLIFIERS Icont Maximum Continuous Current Per Amplifier 50 VSAMP Supply Voltage 4.5 ISAMP Supply Current per amplifier 3 VOS Offset Voltage 3 20 mV IB Noninverting Input Bias Current per amplifier 0 150 nA CMIR Common Mode Input Voltage Range AVIN V 4 0 mA 20 V mA FN9287.0 December 21, 2006 ISL97652 Electrical Specifications PARAMETER VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +85°C, unless otherwise stated. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT CMRR Common-Mode Rejection Ratio 50 70 dB PSRR Power Supply Rejection Ratio 70 85 dB VOH Output Voltage Swing High IOUT(SOURCE) = 5mA AVIN - 50 mV VOH Output Voltage Swing High IOUT(SOURCE) = 50mA AVIN - 450 mV VOL Output Voltage Swing Low IOUT(SINK) = 5mA 50 mV VOL Output Voltage Swing Low IOUT(SINK) = 50mA 450 mV ISC Output Short Circuit Current per amplifier 400 mA SR Slew Rate 50 V/µs BW Gain Bandwidth 30 MHz 300 -3dB gain point FAULT DETECTION THRESHOLDS OVP Overvoltage Protection Threshold AVDD rising OVPHYS Overvoltage Protection Threshold Hysteresis VLOR Undervoltage Lockout Threshold PVIN rising VLOF Undervoltage Lockout Threshold PVIN falling TOFF Thermal Shut-Down TON Vth_AVDD(FB) 18.8 19.5 20 0.8 7.8 7.4 V V 8.0 V 7.6 V Temperature rising 150 °C Reset after Thermal Shut-Down Temperature falling 100 °C AVDD Boost Short Detection V(FBFBB) falling less than 1.14 V Vth_VLOGIC(FBB) VLOGIC Buck Short Detection V(FBB) falling less than 1.14 V Vth_POUT(FBP) POUT Charge Pump Short Detection V(FBP) falling less than 1.14 V Vth_NOUT(FBN) NOUT Charge Pump Short Detection V(FBN) rising more than 0.525 V TFD Fault Delay Time to Chip Turns Off 64 µs START-UP SEQUENCING ISS SS, SSB Current SS, SSB ≤1.5V 6 µA IDLY DLY1, DLY2 Current DLY1, DLY2 <1.5V 6 µA SSTH1 SS, SSB Voltage to Give Max Current Limit 1.27 V SSTH2 SS, SSB Voltage to Enable Fault Checking 2.05 V DELTH1 DEL1, DEL2 Voltage to Give Max Current Limit 1.27 V DELTH2 DEL1, DEL2 Voltage to Enable Fault Checking 2.05 V 5 FN9287.0 December 21, 2006 ISL97652 100 95 95 90 90 85 85 EFFICIENCY (%) EFFICIENCY (%) Typical Performance Curves 13V VIN TO 14V VOUT 8V VIN TO 14V VOUT 80 12V VIN TO 14V VOUT 75 70 75 65 55 0 500 1000 1500 50 2000 0 500 IOUT (mA) 1500 FIGURE 2. BOOST EFFICIENCY @ 1.3MHz 0.20 BOOST LOAD REGULATION (%) 0.20 12V VIN TO 14V VOUT 0.15 0.10 0.05 0.00 -0.05 13V VIN TO 14V VOUT -0.10 8V VIN TO 14V VOUT -0.15 1000 IOUT (mA) FIGURE 1. BOOST EFFICIENCY @ 650kHz BOOST LOAD REGULATION (%) 13V VIN TO 14V VOUT 12V VIN TO 14V VOUT 70 60 65 60 8V VIN TO 14V VOUT 80 0 500 1000 1500 2000 8V VIN TO 14V VOUT 0.15 0.10 0.05 0.00 13V VIN TO 14V VOUT -0.05 12V VIN TO 14V VOUT -0.10 0 500 1000 1500 2000 IOUT (mA) IOUT (mA) FIGURE 4. BOOST LOAD REGULATION @ 1.3MHz FIGURE 3. BOOST LOAD REGULATION @ 650kHz BOOST LINE REGULATION (%) 0.09 CH3 = IOUT 0.08 0.07 0.06 0.05 0.04 fs = 1.3MHz 0.03 fs = 650kHz 0.02 0.01 0.00 CH4 = AVDD (AC COUPLED) 8 9 10 11 12 13 14 15 16 VIN (V) FIGURE 5. BOOST LINE REGULATION 6 FIGURE 6. BOOST TRANSIENT RESPONSE @ 650kHz FN9287.0 December 21, 2006 ISL97652 Typical Performance Curves (Continued) 100 90 BUCK EFFICIENCY (%) CH3 = IOUT 80 8V VIN TO 3.3V VOUT 70 60 13V VIN TO 3.3V VOUT 12V VIN TO 3.3V VOUT 50 40 30 20 10 CH4 = AVDD (AC COUPLED) 0 0 500 1000 1500 2000 IOUT (mA) FIGURE 7. BOOST TRANSIENT RESPONSE @ 1.3MHz FIGURE 8. BUCK EFFICIENCY @ 650kHz 0 BUCK LOAD REGULATION (%) 90 BUCK EFFICIENCY (%) 85 80 75 8V VIN TO 3.3V VOUT 12V VIN TO 3.3V VOUT 70 65 60 13V VIN TO 3.3V VOUT 55 50 8V VIN TO 3.3V VOUT -0.05 -0.1 -0.15 -0.2 12V VIN TO 3.3V VOUT -0.25 -0.3 13V VIN TO 3.3V VOUT -0.35 0 500 1000 1500 2000 2500 0 500 IOUT (mA) 1000 1500 IOUT (mA) 2000 2500 FIGURE 10. BUCK LOAD REGULATION @ 650kHz FIGURE 9. BUCK EFFICIENCY @ 1.3MHz BUCK LOAD REGULATION (%) 0 -0.05 CH3 = IOUT 8V VIN TO 3.3V VOUT -0.1 -0.15 -0.2 12V VIN TO 3.3V VOUT -0.25 -0.3 13V VIN TO 3.3V VOUT -0.35 -0.4 0 500 1000 1500 2000 2500 CH4 = VLOGIC (AC COUPLED) IOUT (mA) FIGURE 11. BUCK LOAD REGULATION @ 1.3MHz 7 FIGURE 12. BUCK TRANSIENT RESPONSE @ 650kHz FN9287.0 December 21, 2006 ISL97652 Typical Performance Curves (Continued) 0 VON LOAD REGULATION (%) CH3 = IOUT -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 CH4 = VLOGIC (AC COUPLED) -1 0 FIGURE 13. BUCK TRANSIENT RESPONSE @ 1.3MHz 10 20 30 40 IOUT (mA) 50 60 70 FIGURE 14. VON LOAD REGULATION VOFF LOAD REGULATION (%) 0.2 CH3 = VFLK 0.15 0.1 0.05 0 -0.05 CH4 = Vgh_M -0.1 -0.15 -0.2 0 5 10 15 20 IOUT (mA) 25 FIGURE 15. VOFF LOAD REGULATION 30 35 FIGURE 16. GPM WAVEFORM + INPUT SIGNAL OUTPUT SIGNAL FIGURE 17. VCOM RISING SLEW RATE 8 FN9287.0 December 21, 2006 ISL97652 Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 POS1 Op-amp 1 non-inverting input 2 OUT1 Op-amp 1 output 3 VGL 4 CE 5 VFLK GPM control pin 6 VDPM GPM enable pin 7 RE 8 VGHM 9 VGH GPM higher supply pin 10 FBP Positive charge pump feedback voltage 11 GND Positive and negative charge pump Ground connection 12 DRVP Positive charge pump driver output pin GPM lower supply pin GPM delay pin GPM output voltage slope adjust pin GPM output voltage 13 SUP 14 DRVN Negative charge pump driver output pin Positive and negative charge pump supply 15 AGND Device analog Ground 16 FBN Negative charge pump feedback voltage 17 REF Reference voltage for all internal functions and external VOFF feedback 18 DLY1 Buck and negative charge pump delay pin 19 SSB Buck soft-start pin 20 VCB Buck compensation pin 21 FBB Buck feedback voltage 22 CBOOT 23, 24 SWB1, SWB2 Buck FET source connection Buck boot-strap capacitor 25, 26 PVIN1, PVIN2 Input supply 27 VDC 28 FREQ 29 DLY2 30 SS Internal regulated 5V supply - attach external decoupling capacitor Switching frequency select pin Boost and positive charge pump delay pin Boost soft-start pin 31 VC Boost compensation pin 32 EN2 Boost and positive charge pump enable 33 EN1 34 PGND1 Buck and negative charge pump enable 35, 36 PGND2, PGND3 37, 38 SW1, SW2 39 SWI 40 SUI AVDD start-up in-rush control 41 FB Boost feedback voltage 42 SWO Device power GND Boost FET source connection Boost FET drain connection AVDD delay switch source connection AVDD delay switch drain connection 43 AVIN VCOM amplifier positive supply pin 44 NEG2 Op-amp 2 inverting input 45 POS2 Op-amp 2 non-inverting input 46 OUT2 Op-amp 2 output 47 OGND Op-amp ground 48 NEG1 Op-amp 1 inverting input 9 FN9287.0 December 21, 2006 ISL97652 Block Diagram SSB VCB FBB FB VC FREQ SS CBOOT + PVIN1 SW1 REF F/F + OSC Q F/F PVIN2 S SW2 S - OSC SLOPE COMPENSATION Q R ∑ + R + + - BOOST CONVERTER ∑ PGND2 SWB1 PGND3 FOSC SUI SWB2 BUCK CONVERTER SWI GATE CONTROL PGND1 SWO UVLO AND THERMAL PROTECTION AVIN POS1 NEG1 AVIN + - POS2 + - NEG2 OGND OUT2 OUT1 DLY1 DLY2 REF BIAS AND EN1 SEQUENCE EN2 CONTROL SUP PVIN2 FOSC 5V VOFF CHARGE PUMP CONTROL DRVN REGULATOR GND + - VDC 0.5V FBN SUP RE CE VON FOSC SLICE CIRCUIT VDPM VON CHARGE PUMP CONTROL DRVP + - VGH VGHM VGHL VFLK 10 1.265V FBP AGND FN9287.0 December 21, 2006 ISL97652 Typical Application Diagram L1 VIN CIN 6.8µH 100nF 3 x 10µF FREQ VIN CVIN 0.1µF PVIN1 PVIN2 SUP REF CREF 220nF R5 40.2k C2* VMAIN D1 COUT 3x R1 10µF 1x100nF 226k SW1 SW2 FB VGL SWI SUI R6 453k D4 C3* VOFF AVDD * 4.7µF 10k DLY1 DLY2 D3 CE POS1 C12 4 x 10µF R2 20k R4 * RC SS DRVN COFF R9 100k R3 0 CSUI 0.1µF VC CN 0.1µF * CAVDD SWO FBN AVDD C11 CE 10nF CD2 0.1µF CSS 0.1µF CD1 0.1µF CC 4.7nF NEG1 R10 100k COMMON BACK-PLANE OUT1 RE POS2 VGHM NEG2 COMMON BACK-PLANE AVDD TCON BIAS C21 * R11 340 CBOOT SWB1 SWB2 DRVP VFLK VDPM EN2 FBB SSB R12 200 R7 232k CON 4.7µF FBP PGND3 PGND2 PGND1 D5 C22 * C4* AVIN CAVIN 0.1µF 470nF L2 CB RE 10k VON VGH OUT2 6.8µH CB 2x10µF GATE DRIVER SUPPLY C5* R8 10k D7 CP 0.1µF D6 AVDD VCB VDC GND OGND AGND EN1 CSSB 0.1µF 10k RCB 4.7nF CCB CDC 4.7µF *Optional components. NOTE: Separate PGND and SGND planes must be used, see PCB layout procedure section. Applications Information Boost Converter The ISL97652 provides a complete power solution for TFT LCD applications. The system consists of one boost converter to generate AVDD voltage for column drivers, one buck converter to provide voltage to logic circuit in the LCD panel, integrated VON and VOFF charge pump controllers, AVDD delay FET, VON-SLICE and dual high speed VCOM amplifiers. With the high output current capability, this part is ideal for big screen LCD TV and monitor panel application. The boost converter is a current mode PWM converter operating at either 650kHz or 1.3MHz. 650kHz operation allows operation down to lower duty cycles. It can operate in both discontinuous conduction mode (DCM) at light load or when operating duty cycle is lower than the minimum duty cycle and continuous mode (CCM). In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by: The integrated boost converter and buck converter operate at either 650kHz or 1.3MHz which allow the use of multilayer ceramic capacitors and low profile inductor which result in low cost, compact and reliable system. V BOOST 1 ------------------------ = ------------1–D V IN (EQ. 1) Where D is the duty cycle of the switching MOSFET. 11 FN9287.0 December 21, 2006 ISL97652 The boost converter uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60kΩ is recommended. The boost converter output voltage is determined by the following equation: R1 + R2 V BOOST = --------------------- × V FB R2 (EQ. 2) The current through the MOSFET is limited to 2.8Apeak. This restricts the maximum output current (average) based on the following equation: ΔI L V IN I OMAX = ⎛ I LMT – --------⎞ × --------⎝ 2 ⎠ VO (EQ. 3) Where ΔIL is peak to peak inductor ripple current, and is set by: V IN D ΔI L = --------- × ----L fS (EQ. 4) where fs is the switching frequency The following table gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX): TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION VIN (V) VO (V) L (µH) fs (MHz) IOMAX (mA) 12 15 6.8 0.65 1890 12 15 6.8 1.3 1955 12 18 6.8 0.65 1500 12 18 6.8 1.3 1590 8 15 6.8 0.65 1200 8 15 6.8 1.3 1275 8 18 6.8 0.65 950 8 18 6.8 1.3 1050 higher frequency option is selected. The minimum boost duty cycle of the ISL97652 is ~10% for 650kHz and ~20% for 1.3MHz. When the operating duty cycle is lower than the minimum duty cycle, the part will not switch in some cycles randomly, which will cause some LX pulses to be skipped. In this cas, LX pulses are not consistent any more, but the output voltage (AVDD) is still regulated by the ratio of R1 and R2. Because some LX pulses are skipped, the ripple current in the inductor will become bigger. Under the worst case, the ripple current will be from 0 to the threshold of the current limit. In turn, the bigger ripple current will increase the output voltage ripple. Hence, it will need more output capacitors to keep the output ripple at the same level. When the input voltage equals, or is larger than, the output voltage, the boost converter will stop switching. The boost converter is not regulated any more, but the part will still be on and other channels are still regulated. Boost Converter Input Capacitor An input capacitor is used to suppress the voltage ripple injected into the boost converter. A ceramic capacitor with capacitance larger than 10µF is recommended. The voltage rating of input capacitor should be larger than the maximum input voltage. Some capacitors are recommended in Table 2 for input capacitor. TABLE 2. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/25V 1210 TDK C3225X7R1E106M 10µF/25V 1210 Murata GRM32DR61E106K Boost Inductor The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Values of 3.3µH to 10µH should be selected to match the internal slope compensation. The inductor must be able to handle the following average and peak current: IO I LAVG = ------------1–D (EQ. 5) ΔI L I LPK = I LAVG + -------2 (EQ. 6) Some inductors are recommended in Table 3. TABLE 3. BOOST INDUCTOR RECOMMENDATION When operating at the lower frequency option, 650kHz, the potential increase in ripple current in the inductor can be avoided by increasing the inductor by the same factor. This allows the slope compensation in the boost feedback to remain the same as the 1.3MHz case and this will maintain stability of the converter over the widest operating range. Operation at 650kHz allows boost operation down to lower minimum duty cycles, where the output voltage required is closer to the input voltage than can be achieved when the 12 INDUCTOR 6.8µH/ 3APEAK DIMENSIONS (mm) VENDOR 7.3x6.8x3.2 TDK 6.8µH/ 2.9APEAK 7.6X7.6X3.0 Sumida 5.2µH/ 4.55APEAK 10x10.1x3.8 PART NUMBER RLF7030T-6R8N3R0 CDR7D28MNNP-6R8NC Cooper CD1-5R2 Bussmann FN9287.0 December 21, 2006 ISL97652 Rectifier Diode (Boost Converter) A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output voltage. The rectifier diode must meet the output current and peak inductor current requirements. The following table is some recommendations for boost converter diode. TABLE 4. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION examined with an oscilloscope set to AC 100mV/div and the amount of ringing observed when the load current changes. Reduce excessive ringing by reducing the value of the resistor in series with the VC pin capacitor. AVDD Delay Switch The ISL97652 integrates a PMOS disconnect switch for the AVDD boost output to disconnect VIN from AVDD when the EN2 input is not selected. When EN2 is taken high, the PMOS FET is turned on to connect power to the display. The CSUI capacitor provide soft-start control for the connection of this switch. DIODE VR/IAVG RATING PACKAGE SS23 30V/2A SMB Fairchild Semiconductor The operation of the AVDD delay switch is controlled by internal VDSOK and VDSHYS control signals which operate as follows: SL23 30V/2A SMB Vishay Semiconductor During start-up (or during fault conditions): VENDOR VDSOK goes to 1 when V(SWI - SWO) becomes less than ~0.5V. This will turn-on the boost function. Output Capacitor The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor. IO V O – V IN 1 V RIPPLE = I LPK × ESR + ------------------------ × -------------------- × ---f V C O AVDD (EQ. 7) s For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across then increases. COUT in Equation 7 above assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts. The following table shows some selections of output capacitors. TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/25V 1210 TDK C3225X7R1E106M 10µF/25V 1210 Murata GRM32DR61E106K Loop Compensation (Boost Converter) The boost converter of ISL97652 can be compensated by a RC network connected from VC pin to ground. CC = 4.7nF and RC = 10k RC network is used in the demo board. A higher resistor value can be used to lower the transient load change AVDD overshoot - however, this may be at the expense of stability to the loop. The stability can be examined by repeatedly changing the load between 100mA and a max level that is likely to be used in the system being used. The AVDD voltage should be 13 VDSOK goes to 0 when VDS_pfet becomes greater than ~1.1V. This will turn-off the boost function. The threshold voltages have a Vin dependence such that: For Vin1 = 8V: VDSOK goes to 1 occurs at ~0.5V and VDSOK goes to 0 occurs at ~1.1V. For Vin1 =18.5V: VDSOK goes to1 occurs at ~1.13V and VDSOK goes to 0 occurs at ~2.65V. V(SWI - SWO) is the VDS voltage across the internal PFET protection switch. If this voltage exceeds 1.1V for some reason (e.g. under fault conditions or during start-up if VMAIN rises faster than AVDD) the boost is turned-off to allow the AVDD (SWO) potential to catch-up with VMAIN (SWI). VDSHYS is the VDS hysteresis level; Once VDSOK goes to 1 the voltage V(SWI - SWO) then needs to exceed 1.1V for VDSOK goes to 0. During normal operation VDS will be ~Ron_PFET * Iload (~ 0.18x2 = 0.36V for max AVDD load). If a fault develops on AVDD, which causes VDS to exceed 1.1V, then the boost operation is interrupted by the internal VDSOK goes to 0 signal and fault timers will start to operate while the rising/falling character of AVDD is monitored. AVDD Delay Switch Fault Operation When enabled, the gate of the PFET is pulled down with a 30µA current, turning on the FET switch. The speed of this turn-on can be controlled by placing a capacitor from SWI to SUI. In normal operation the gate (and SUI pin) are pulled down to 5V below SWI. The AVDD delay switch circuitry constantly monitors both the current in the switch and the voltage at SWO. If the current exceeds the current limit of 2A, the gate of the FET (and also the SUI pin) will be pulled up to the correct level to limit the current to 2A. In this mode the switch acts like a 2A current source. this current cannot be maintained indefinitely due to the power dissipation on FN9287.0 December 21, 2006 ISL97652 Feedback Resistors chip. Therefore, three separate fault mechanisms are operated. 1. The SWO output range is constantly monitored and expected to rise if the PFET is in current limit. The rate of rise at SWO can be calculated from the current limit and the capacitance on SWO by using the equation dV/dt = Ilimit/Cavdd. The SWO voltage range is split into sections of approximately 0.7V such that every time the output rises by this amount the circuit detects that the voltage is rising. Should the circuit remain in current limit for more than 100µs with no such rise taking place the circuit will fault out. In this scenario, the PFET will immediately switch itself off and the rest of the ISL97652 will later fault out due to the boost voltage at AVDD falling away. 2. As well as monitoring any rise in the voltage at SWO, the circuit also monitors any falls in this level. If the output falls by more than a certain amount while it is in current limit the circuit will fault out immediately. This amount varies from about 1V to about 1.4V depending on the output level before the fall. In this scenario, the PFET will immediately switch itself off and the rest of the ISL97652 will later fault out due to the boost voltage falling away. 3. Once the ISL97652 has successfully sequenced the boost on and the boost soft-start capacitor has charged up, a third fault check is also added. After this point if the PFET enters current limit for greater than the global timeout of 40µs then the chip will fault out. In this scenario the whole chip will be disabled with the PFET immediately switched off. Buck Converter The buck converter is the step down converter, which supplies the current to the logic circuit of the LCD system. The ISL97652 integrates an 20V N-Channel MOSFET to save cost and reduce external component count. In the continuous current mode, the relationship between input voltage and output voltage is as follows: V LOGIC ---------------------- = D V IN (EQ. 8) Where D is the duty cycle of the switching MOSFET. Because D is always less than 1, the output voltage of buck converter is lower than input voltage. The peak current limit of buck converter is set to 2.5A, which restricts the maximum output current (average) based on the following equation: I OMAX = 2.5A – ΔI PP (EQ. 9) Where ΔIPP is the ripple current in the buck inductor as the following equation: V LOGIC ΔI PP = ---------------------- ⋅ ( 1 – D ) L ⋅ fs (EQ. 10) Where L is the buck inductor, fs is the switching frequency. 14 The buck converter output voltage is determined by the following equation: R 11 + R 12 V LOGIC = --------------------------- × V FBB R 12 (EQ. 11) Where R11 and R12 are the feedback resistors of buck converter to set the output voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 1kΩ is recommended. Buck Converter Input Capacitor The capacitor should support the maximum AC RMS current which happens when D = 0.5 and maximum output current. I ACRMS ( C IN ) = (EQ. 12) D ⋅ ( 1 – D ) ⋅ IO Where Io is the output current of the buck converter. The following table shows some recommendations for input capacitor. TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/16V 1206 TDK C3216X7R1C106M 10µF/10V 0805 Murata GRM21BR61A106K 22µF/16V 1210 Murata C3225X7R1C226M Buck Inductor An 3.3µH-10µH inductor is the good choice for the buck converter. Besides the inductance, the DC resistance and the saturation current are also the factor needed to be considered when choosing buck inductor. Low DC resistance can help maintain high efficiency, and the saturation current rating should be 2.5A. Here are some recommendations for buck inductor. TABLE 7. BUCK INDUCTOR RECOMMENDATION INDUCTOR DIMENSIONS (mm) VENDOR PART NUMBER 4.7µH/ 2.7APEAK 5.7x5.0x4.7 Murata LQH55DN4R7M01K 6.8µH/ 3APEAK 7.3x6.8x3.2 TDK RLF7030T-6R8M2R8 10µH/ 2.4APEAK 12.95x9.4x3.0 Coilcraft DO3308P-103 Rectifier Diode (Buck Converter) A Schottky diode is recommended due to fast recovery and low forward voltage. The reverse voltage rating should be higher FN9287.0 December 21, 2006 ISL97652 than the maximum input voltage. The peak current rating is 2A, and the average current should be as the following equation, Regulated Charge Pump Controllers (VON and VOFF) I AVG = ( 1 – D )*I o The ISL97652 includes 2 independent charge pumps (see charge pump block and connection diagram). The negative charge pump inverters the VSUP voltage and provides a regulated negative output voltage. The positive charge pump doubles or triples the VSUP voltage and provided a regulated positive output voltage. The regulation of both the negative and positive charge pumps is generated by internal comparator that senses the output voltage and compares it with the internal reference. (EQ. 13) Where Io is the output current of buck converter. The following table shows some diode recommended. TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION DIODE VR/IAVG RATING PACKAGE PMEG2020EJ 20V/2A SOD323F Philips Semiconductors SS22 20V/2A SMB Fairchild Semiconductor VENDOR The pumps use pulse width modulation to adjust the pump period, depending on the load present. The pumps can provide 30mA for VOFF and 20mA for VON. Output Capacitor (Buck Converter) Positive Charge Pump Design Consideration Four 10µF or two 22µF ceramic capacitors are recommended for this part. The overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer. The positive charge pump can drive multiple stages for 2X/ 3X step up ratios, or higher. Internal switches (M1 and M2) drive external steering diodes via the pump capacitor CP. Figure 18A shows 2X configuration and Figure 18B shows 3X configuration. The output voltage is divided by feedback resistors R7 and R8, which is then compared to the internal reference via comparator A1. The maximum VON charge pump current can be estimated from the following equations assuming a 50% switching duty: TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/6.3V 0805 TDK C2012X5R0J106M 10µF/6.3V 0805 Murata GRM21BR60J106K 22µF/6.3V 1210 TDK C3216X5R0J226M 100µF/6.3V 1206 Murata GRM31CR60J107M PI Loop Compensation (Buck Converter) The buck converter of ISL97652 can be compensated by a RC network connected from VCB pin to ground. CCB = 4.7nF and RCB = 10k RC network is used in the demo board. The larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. I MAX ( 2x ) ∼ min of 50mA or 2 • V SUP – 2 • V DIODE ( 2 • I MAX ) – V ( V ON ) ---------------------------------------------------------------------------------------------------------------------- • 0.95A ( 2 • ( R ONH + R ONL ) ) (EQ. 14) I MAX ( 3x ) ∼ min of 50mA or 3 • V SUP – 4 • V DIODE ( 2 • I MAX ) – V ( V ON ) ---------------------------------------------------------------------------------------------------------------------- • 0.95A 4 • ( R ONH + R ONL ) The stability can be optimized in a similar manner to that described in the section on "PI Loop Compensation (Boost Converter)”. Bootstrap Capacitor (CB) This capacitor is used to provide the supply to the high driver circuitry for the buck MOSFET. The bootstrap supply is formed by an internal diode and capacitor combination. A 470nF is recommended for ISL97652. A low value capacitor can lead to overcharging and in turn damage the part. If the load is too light, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. In this case, if VIN-VBUCK <1.5V, the internal MOSFET pull-up device may be unable to turn-on until VLOGIC falls. Hence, there is a minimum load requirement in this case. The minimum load can be adjusted by the feedback resistors to FBB. 15 FN9287.0 December 21, 2006 ISL97652 A2 C4 100pF VSUP VDC FAULT 1.14V FBP C5 2.2nF R8 10k A1 R7 232k 1.265V FOSC STOP VSUP M2 CP 0.1µF CLK DRVP D6 D7 VON (30V) CON 1µF PWM CONTROL EN M1 GND FIGURE 18A. VON FUNCTION DIAGRAM (VOLTAGE DOUBLER) VSUP CP 0.1µF D6 D7 D6’ D7’ DRVP VON (30V) CON 1µF CP’ 0.1µF CON’ 1µF FIGURE 18B. VOLTAGE TRIPLER FIGURE 18. In voltage doubler configuration, the maximum VON is as given by the following equation: V ON_MAX(2x) = 2 • ( V SUP – V DIODE ) – 2 • I OUT • ( R ONH + R ONL ) (EQ. 15) For Voltage Tripler using additional external diodes and capacitors (Figure 18B): VON_MAX(3x) = 3 • V SUP – 4 • V DIODE – 2 • I OUT • ( R ONH + RONL ) (EQ. 16) VON output voltage is determined by the following equation: R7 V ON = V FBP × ⎛ 1 + --------⎞ ⎝ R8⎠ (EQ. 17) Negative Charge Pump Design Consideration The negative charge pump consists of an internal switcher M1, M2 which drives external steering diodes Dx and Dx via a pump capacitor (CN) to generate the negative VOFF supply. An internal comparator (A1) senses the feedback voltage on FBN and turns on M1 for a period up to half a CLK period to maintain V(FBN) in regulated operation at 0.5V. External feedback resistor R5 is referenced to VREF. 16 FN9287.0 December 21, 2006 ISL97652 VREF A2 C3 100pF VSUP VDC FAULT 0.53V FBN C2 820pF R5 40.2k A1 R6 453k 0.5V FOSC STOP M2 CLK DRVN CN 0.1µF D4 VOFF (-8V) D3 PWM CONTROL EN COFF 1µF M1 GND FIGURE 19. NEGATIVE CHARGE PUMP BLOCK DIAGRAM The maximum VOFF output voltage of a single stage charge pump is: V OFF_MAX ( 2x ) = – V SUP + V DIODE + 2 • I OUT • ( R ON ( NOUT )H + R ON ( NOUT )L ) (EQ. 18) R5 and R6 in the Typical Application Diagram determine VOFF output voltage. (without the boost running) is large enough to satisfy the regulated VOFF supply. R6 R6 V OFF = V FBN • ⎛ 1 + --------⎞ – V REF • ⎛ --------⎞ ⎝ R5⎠ ⎝ R5⎠ Improving Charge Pump Noise Immunity (EQ. 19) Charge Pump Supply The magnitude of the SUP supply will determine the charge pump diode configuration; whether x2 or x3 for the positive charge pump or x1 or x2 for the negative charge pump. An independent charge pump supply pin 13 (SUP) is provided and this may be connected to Vin, Vmain, AVDD or some other suitable supply. Note that if AVDD is chosen for the SUP supply, then a potential fault-like interaction with the supply sequencing and fault checking is present; when EN1 goes high (with EN2 low), fault checking on the VOFF charge pump is started by the voltage ramp on DEL1. If this pin reaches ~1.9V before VOFF is within 90% of it's regulation voltage then the buck converter (Tcon bias) and Voff will be continually re-started. This condition will arise if the SUP supply has not been activated by EN2 going high before DEL1 has reached 1.9V. One solution would be to increase the capacitance on DEL1 to overlap enough in time with the EN2 going high. This does have the disadvantage of lengthening the fault detection time of the VOFF charge pump under true fault conditions and it also lengthens the initial VOFF turn-on time. Another solution would be to supply SUP from Vmain as long as the magnitude of Vmain 17 Depending on PCB layout and environment, noise pick-up at the FBP and FBN inputs, which may degrade load regulation performance, can be reduced by the inclusion of capacitors across the feedback resistors (e.g. in the Application Diagram, C4 and C5 for the positive charge pump). Set R7 • C4 = R8 • C5 with C4 ~ 100pF. VON-SLICE Circuit Operation The Von slice circuit functions as a three way multiplexer, switching VGHM between ground, VGL and VGH (typ 1530V). Voltage selection is provided by digital inputs VDPM (enable) and VFLK (control). HIGH to LOW delay and slew control is provided by external components on pins CE and RE respectively. The block diagram of the VON-SLICE circuit is shown in Figure 3. When VDPM is LOW, the block is disabled and VGHM is grounded. When VDPM is HIGH, VGHM is determined by VFLK; when VFLK goes LOW, there is a delay controlled by the capacitor attached to the CE pin, following which VGHM is driven to VGL, with a slew rate controlled by the resistor attached to the RE pin. Note that VGL is used only as a reference voltage for an amplifier, thus does not have to source or sink a significant DC current. When VFLK goes HIGH, VGHM is FN9287.0 December 21, 2006 ISL97652 external capacitor to VREF. This creates a delay, equal to CE*21300. For example, the delay time is ~10µs for 470pF CE capacitor. At this point, VGHM begins to slew down from VGH to VGL. The slew current is equal to Isl=300/(RE+5kΩ), and the dv/dt slew rate is Isl/Cload. driven HIGH at a rate primarily controlled by the P1 switch resistance (RONVGH) and the external capacitive load. VGHM HIGH to LOW transitions are more complex; take the case where the block is already enabled (VDPM is HIGH). When VFLK is HIGH, pin CE is grounded. On the falling edge of VFLK, a current is passed into pin CE to charge an where Cload is the load capacitance applied to VGHM. VGH VGHM VDPM VGL VGL x248 x248 VREF RE 60µA CE VFLK CONTROL AND TIMING FIGURE 20. VON-SLICE BLOCK DIAGRAM 18 FN9287.0 December 21, 2006 ISL97652 VGH VGHM VGL SLOPE CONTROLLED BY RE AND LOAD CAPACITANCE t 0 VFLK 0 t TCE DELAY TIME CONTROLLED BY CE ~1.94V CE ~1.265V t 0 FIGURE 21. VON-SLICE TIMING WAVEFORM High Performance VCOM Amplifiers The integrated high performance amplifiers are designed to drive the VCOM plane in TFT-LCD displays. Under normal operational conditions, the amplifiers are permanently enabled when the AVIN supply is present. Under fault conditions and with EN1 active, the temperature shut-down (TOFF exceeded) will disable the amplifiers until the temperature drops to TON. Temperature shut-down of the amplifiers is disabled if EN1 is disabled. The amplifiers integrated in to the ISL97652 feature high output current of 50mA minimum and high slew rate of 50V/µs. Both inputs and outputs have rail-to-rail capability. Start-Up Sequence Control The ISL97652 features extensive start-up sequence control options. Two enable pins and two delay control pins are used to set the start-up sequence. The EN1 enable pin controls the buck regulator and negative charge pump controller. When EN1 goes H, the internal 5.3V regulator starts up. Once the regulator output on pin 27 (VDC) exceeds it's UVLO threshold, the REF pin starts to charge up to the normal output level. Once REF is within 15% of it's final value, the buck regulator will start to operate. Note that if VREF moves more than 15% from it's target value, all major functions will be disabled until REF returns to it's normal range. This involves the chip going through the normal start-up sequence from buck start-up onwards, depending on the state of the enable signals EN1, EN2. The soft-start time is set using the capacitor connected to SSB. Once the output reaches 90% the DLY1 capacitor begins to 19 charge. Once the threshold is reached, the negative charge pump will begin. Removing the DLY1 capacitor will cause the negative charge pump to start immediately once the buck regulator reaches 90% of the target value. The delay time and soft-start times are determined using the following equations: V DL1 T DLY1 = C DL1 × -------------I DL1 (EQ. 20) V SSB T SSB = C SSB × --------------I (EQ. 21) SSB The EN2 pin is used to control the boost and positive charge pump circuits.Note that EN2 is ignored until the buck converter has reached 90% of it's target value. When taken high, the internal PFET is turned on to connect the input to the AVDD output. A capacitor connected to SUI provides control over the soft connect to limit inrush current. Next, the boost converter starts to operate. The soft-start time for the boost is set using the capacitor tied to the SS pin. Once the output reaches 90% of the target value, the DLY2 timer starts. Once completed, the positive VON charge pump starts to operate. If CDL2 is not present, the VON charge pump will start immediately once the boost is in regulation. The delay time is determined using the following equation: V DL2 T DLY2 = C DL2 × -------------I (EQ. 22) V SS T SS = C SS × ----------I (EQ. 23) DL2 SS FN9287.0 December 21, 2006 ISL97652 Variations on the start-up sequence can be seen in Figures 22, 23 and 24. The Gate pulse modulator is enabled when both of the following conditions are met: • VDPM is H • VON is over 90% of it's target value. TSSB DLY2 EN1 DLY1 EN2 VTCON TSS VOFF VMAIN VIN - DIODE VIN - 2 x DIODE VMAIN - 2 x DIODE VON VIN - DIODE AVDD FIGURE 22. TIMING DIAGRAM 1 20 FN9287.0 December 21, 2006 ISL97652 TSSB DLY2 EN1 DLY1 EN2 TSS VTCON VOFF VIN - DIODE VMAIN VMAIN - 2 x DIODE VIN - 2 x DIODE VON VIN - DIODE AVDD FIGURE 23. TIMING DIAGRAM 2 21 FN9287.0 December 21, 2006 ISL97652 EN2 DLY2 VDPM VIN - DIODE VIN - DIODE OR VMAIN VMAIN DIODE VON AVDD VFLK VGHM FIGURE 24. TIMING DIAGRAM 3 Switching Frequency Control Fault Detection The ISL97652 can operate at either 650kHz or 1.3MHz depending on the state of the FREQ pin. When connected to GND, 650kHz is selected. When connected to VIN, 1.3MHz is selected. Higher frequencies enable the selection of smaller inductors and capacitors. Lower frequencies allow closer input/output ratios to be supported. The charge pump circuits switch at half the frequency selected. The ISL97652 includes extensive fault handling circuitry, which interacts with the start-up sequence circuitry if a fault is detected. Undervoltage Lockout The integrated undervoltage lockout circuit is designed to power down the TFT-LCD if the input voltage falls below a preset threshold. The ISL97652 will not start if the input voltage is below the UVLO threshold. Over-Temperature Protection An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point of +150°C, the device will shut down. Operation with die temperatures between +125°C and 150°C can be tolerated for short periods of time, however, in order to maximize the operating life of the IC, it is recommended that the effective continuous operating junction temperature of the die should not exceed +125°C. 22 During normal operation, if EN1 goes L, all major functions are disabled immediately, including the 5V regulator. If EN2 goes L, but EN1 remains H, boost, VON and GPM are disabled immediately. When EN1 and/or EN2 return H, the start-up sequence restarts from the appropriate point. If the over-temperature threshold (+150°C nominal) is exceeded, or if VIN drops below the specified lower UVLO limit, all major functions are disabled immediately, excluding the 5.3V regulator. If/when the temperature drops below +100°C, or VIN returns to a level above the upper UVLO threshold the start-up sequence will re-commence by enabling REF. Timed “Faults” The four ramp voltages, SSB, SS, DEL1 and DEL2 all ramp linearly from 0V to approximately 2.7V, where they are soft-clamped. The 2V thresholds of each are used to enable timed fault checking on related blocks. Therefore, external capacitor values should be chosen such that all major FN9287.0 December 21, 2006 ISL97652 outputs are in regulation by the time this threshold is reached. For example, SSB controls step-down regulator fault checking, DEL1 controls VOFF fault checking, SS controls step-up regulator and PFET fault checking, DEL2 controls VON and GPM fault checking. If a fault on any of the major blocks is detected continuously for a predetermined time interval (currently set to 63µs), when fault checking is enabled for that function, the fault latch will be set. This causes all major functions to be disabled immediately, including the 5.3V regulator. Once VDC falls below its internal UVLO limit (typically 3.6V), the FAULT latch is reset. This will initiate an automatic restart. If the fault has been cleared, the restart will be successful; if the fault persists, the FAULT latch will again be set, and the cycle will repeat itself. (Route the following tracks on the PGND (top) metal layer: PGND1,2,3 [a single wide track] to CIN, Cout and CB, D5. SW1,2 [a single wide track] to L1/D1, SWB1,2 [a single wide track] to L2/D5.) Buck, boost and VON circuits have fault thresholds at 90% of target values. Star Ground The VOFF fault threshold is set at 125mV above the 0.5V regulation point. GPM fault detection is designed to detect a short circuit on the output, by monitoring whether VGHM fails to pull up to VGH on two consecutive FOSC clock periods. The AVDD PFET also has fault checking, which will protect the FET in the event of an output short circuit. Note that the VCOM amplifiers are independently biased, and are enabled at all times, except if an over-temperature fault is detected. If this behavior is not desired, then there is an option to power the VCOM amplifiers from AVDD, which will keep them disabled until the boost is enabled. Note also that it is possible to prevent timed fault checking on any or all of the major functions, simply by externally clamping SSB, SS, DEL1 and/or DEL2 to a voltage between 1.3V and 2V. PCB Layout Procedure To ensure the user gets the best chip performance with minimum amount of PCB rework in the development phase, the following PCB layout procedure is strongly recommended. PCB metal layers Reserve the top PCB metal layer for direct power ground (PGND) connections to the supply pins and switching outputs (buck/boost/charge-pumps). The goal is to ensure there are no VIAS in the boost and buck paths to the smoothing capacitors. The top layer may also be used for general routing of non-sensitive tracks as long as this does not compromise the supply track widths which should be as wide as possible. Note that using VIAs in series with smoothing capacitors (even if implemented as multiply parallel VIAs) increases the effective high frequency ESR of the capacitors and WILL cause degraded system operation. 23 Reserve the bottom (or an intermediate layer) for the signal ground plane (SGND) and signal routing. It is recommended that all feedback inputs and any other sensitive tracks are routed to the SGND layer using a VIAs as close to the chip as possible. This prevents unwanted interference pick-up and allows the supply smoothing capacitors to be places as close to the chip as possible. (Route the following tracks on the SGND (bottom or intermediate) metal layer: FB, FBB, FBP, FBN, POS1,2, ) A star ground system is where a number of different grounds (e.g. PGND, SGND°¦) come together at a single location which then becomes the reference ground point for the system as a whole. Star grounding ensures minimum interference between different functions in a system. Practically, it is difficult to achieve an ideal (single location) ground point due to the physical dimensions of the chip, smoothing capacitors and track routing, however, the exposed die plate and the area immediately next to the PGND1,2,3 pins is defined as the star ground for this chip. The negative smoothing capacitor terminals of: Cout, CB and CIN must be located as close as possible to the PGND1,2,3 pins. The smoothing capacitors for VIN, Cout and CB come as a block of three or four capacitors with (usually) one small capacitor whose role is to reduce the total effective ESR of the capacitors. It is recommended that the small capacitor and at least one of the large capacitors from each capacitor block is placed as physically close to the chip PGND pins as possible. The other capacitors from each block can be placed a little further away, if necessary. Exposed Die plate connection The exposed die plate connection to the underside of the chip must directly connect the PGNDs (pins 34,35,36) and AGND (pin 15) with an equivalent area of metal. The other ground pins (amplifier OGND and charge pump GND pins may also be connected to the die plate. The exposed die plate connection must have multiple VIAs (use a 4x4 array) connecting the top metal PGND layer to the bottom SGND metal layer. The bottom SGND metal area around the VIA array should be maximized in order to keep the thermal resistance of the chip and PCB system as low as possible. This will optimise operation at high currents or in high ambient temperature applications. Order of component placement The order of component placement should be as follows. This procedure minimizes the high current PGND and supply track impedance to the chip pins. FN9287.0 December 21, 2006 ISL97652 1). Cout, Cin, CB ®C get these components as close to PGND1,2,3 as possible and use wide tracks on the top PGND layer with no VIAs. 2). L1, D1, L2, D5 ®C get these components as close to the chip pins as possible having observed 1/ and use wide tracks on the top PGND layer with no VIAs. 3). Feedback resistor networks connected to FB, FBB, FBP, FBN, POS1,2 - keep tracks as short as possible, having first observed 1/ and 2/. Routing on the SGND layer should be used. Avoid routing this tracks under switching tracks on the top surface. 4). All other components - keep all switching output tracks (SW1,2, SWB1,2, CBOOT, DRVP, DRVN, VGHM, VFLK) on the PGND layer shielded from adjacent tracks. Evaluation PCB A two layer evaluation PCB is available which follows the above procedure and may be useful as a reference to guide the PCB layout engineer. For example, the smoothing capacitor positive rail to PVin does contain VIAs in series ®C however, a small capacitor has been used directly at the PVin pins which overcomes the ESR objection. 24 FN9287.0 December 21, 2006 ISL97652 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 2X L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C) 0.15 C A MILLIMETERS D A D/2 2X 6 INDEX AREA N 0.15 C B 1 2 3 SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - 0.30 5, 8 4.45 7, 8 4.45 7, 8 A3 b 0.20 REF 0.18 D E/2 D2 E A / / 0.10 C C 0.08 C SEATING PLANE A3 SIDE VIEW A1 4.30 - 7.00 BSC 4.15 e B TOP VIEW - 7.00 BSC 4.15 E E2 0.23 4.30 - 0.50 BSC - k 0.25 - - - L 0.30 0.40 0.50 8 N 48 2 Nd 12 3 Ne 12 3 Rev. 2 5/06 5 NX b 0.10 M C A B D2 7 D2 2 (DATUM B) 8 NX k N (DATUM A) E2 6 INDEX AREA E2/2 (Ne-1)Xe REF. 8 7 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 3 2 1 NX L N e 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 SECTION "C-C" All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 FN9287.0 December 21, 2006