E2C0010-27-Y4
¡ Semiconductor
MSC1163
¡ Semiconductor
This version: Nov.
1997
MSC1163
Previous version: Jul. 1996
40-Bit Anode Driver
GENERAL DESCRIPTION
The MSC1163 is a monolithic IC using the Bi-CMOS process for hybridizing CMOS and bipolar
transistors on the same chip. The logic portion such as the input stage, shift register and latch is
fabricated by CMOS and the output driver requiring a high withstand voltage is fabricated by
bipolar transistors.
Since the 60-pin plastic SSOP package is adopted and the pin configuration allows the circuit
wiring to be formed on the single side PCB, the display unit size can be reduced.
The shift register has a bidirectional configuration; therefore, it is easy to design the circuit wiring
in which devices are arranged so that they are symmetric with respect to the display.
FEATURES
The MSC1163 is designed as a VFD anode driver with emitter-follower output providing 40-bit
active pull-down and built-in 40-bit bidirectional shift register and latch.
• Logic Supply Voltage (VCC) : 5V
• Driver Supply Voltage (VHV) : 65V
• Driver Output Current
IOHVH : –2mA
IOHVL : 2mA
• Built-in 40-bit output with latch
• Built-in 40-bit bidirectional shift register
• Clock frequency: 4MHz
• Package:
60-pin plastic SSOP (SSOP60-P-700-0.65-BK)
(Product name: MSC1163GS-BK)
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¡ Semiconductor
MSC1163
BLOCK DIAGRAM
DIN R/L
LS
CHG
CL
V CC V CC V HV V HV
(1 to 20)(21 to 40)(1 to 20)(21 to 40)
D
HVO1
R-1
40-Bit Bi-directional Shift Register
1
1
HVO2
R-2
2
R-40
40
2
40-Bit Latch
CLK
HVO40
40
Q
DOUT
GND2 GND2
(1 to 20)(21 to 40)
GND1 GND1
(1 to 20) (21 to 40)
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¡ Semiconductor
MSC1163
INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic Portion Input and Output Circuits
Input pin
VCC
VCC
INPUT
GND1
GND2
Output pin
VCC
VCC
DOUT
GND2
GND1
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¡ Semiconductor
MSC1163
Schematic Diagram of Driver Output Circuit
VHV
VHV
HVO
GND 1
GND 1
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¡ Semiconductor
MSC1163
PIN CONFIGURATION (TOP VIEW)
HVO 1
HVO 2
HVO 3
HVO 4
HVO 5
HVO 6
HVO 7
HVO 8
HVO 9
HVO 10
HVO 11
HVO 12
HVO 13
HVO 14
HVO 15
HVO 16
HVO 17
HVO 18
HVO 19
HVO 20
VHV
GND 1
GND 2
CL
NC
LS
NC
R/L
DIN
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HVO 40
HVO 39
HVO 38
HVO 37
HVO 36
HVO 35
HVO 34
HVO 33
HVO 32
HVO 31
HVO 30
HVO 29
HVO 28
HVO 27
HVO 26
HVO 25
HVO 24
HVO 23
HVO 22
HVO 21
VHV
GND 1
GND 2
NC
CHG
NC
CLK
NC
DOUT
VCC
NC : No-connection pin
60-Pin Plastic SSOP
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¡ Semiconductor
MSC1163
PIN DESCRIPTION
Pin
Symbol
Type
1 - 20
41 - 60
21
40
HVO1 HVO40
VHV
O
Driver output pin, applicable to each bit of shift register
—
Power supply pin for driver circuit
Driver GND
22
39
GND 1
—
GND pin for driver circuit. Connect this pin to GND2 near
the mounted IC so that GND1 and GND2 will be at
common level.
Logic GND
23
38
GND 2
—
GND pin for the logic circuit (excluding driver circuit)
GND1 and GND2 are not connected inside of the IC.
Clear Input
24
CL
I
Clear input pin with pull-up resistor. Normally "H" level.
In this condition, the driver outputs "H" or "L" according to
the corresponding latch output level. Setting to "L"
enables the driver output to be fixed at "L" without respect
to latch output.
Latch Strobe Input
26
LS
I
Latch strobe input pin with neither pull-up nor pull-down
resistor. When LS is "H", the output of the shift register
becomes that of the latch circuit. When LS is "L", the latch
circuit holds the contents of the shift register before LS
goes "L".
Shift Direction Control
28
R/L
I
Shift direction control pin with a pull-up resistor.
Normally "H", and in this condition, data of bidirectional
shift register is shifted to the direction of R-40 from R-1.
When this pin is "L", bidirectional shift register shifts data
to the direction of R-1 from R-40.
Data Input
29
DIN
I
Shift register input pin with neither pull-up nor pull-down
resistor. Display data is input in synchronization with
clock. (Positive logic)
Logic Power Supply
30
31
VCC
—
Power supply pin for logic (except driver)
VCC should be 4.5V to 5.5V.
Data Output
32
DOUT
O
Serial output of bidirectional pin shift register. When R/L
is "H", DOUT outputs R-40's output. When R/L is "L",
DOUT outputs R-1's output.
Clock Input
34
CLK
I
Clock input pin with neither pull-up nor pull-down resistor.
Data of shift register is shifted from one stage to the next
at the rising edge of clock.
Test Input
36
CHG
I
Test input pin with a pull-down resistor. Normally "L".
If CL = "H" in this condition, the driver outputs "H" or "L"
according to the corresponding latch output.
If CL = "H", setting CHG to "H" enables the driver output to
be fixed at "H" without respect to latch output.
Function
Driver Output
Driver Power Supply
Description
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¡ Semiconductor
MSC1163
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Note
Logic Supply Voltage
VCC
Applicable to logic supply
voltage pin
–0.3 to +6.5
V
1
Driver Supply Voltage
VHV
Applicable to driver supply
voltage pin
VCC to 70
V
1, 2
Input Voltage
VIN
Applicable to all input
pins
–0.3 to VCC +0.3
V
1
Data Output Voltage
VOD
Applicable to data output
pin
–0.3 to VCC +0.3
V
1
Driver Driving Frequency
Power Dissipation
fDRV
PD
Duty cycle 50% max
Ta £ 25°C
0 to 15
860
kHz
mW
—
—
Package Thermal Resistance
Rj-a
—
145
°C/W
3
Storage Temperature
TSTG
—
–55 to +150
°C
—
Notes: 1) Maximum Supply Voltage with respect to GND
2) Permanent damage may be caused if the voltage is supplied over the rating.
3) Package Thermal Resistance (between junction and atmosphere)
The junction temperature (Tj) given by the equation indicated below should not
exceed 150°C.
Tj=P ¥ Rj–a+Ta (P: Maximum power consumption)
7/13
¡ Semiconductor
MSC1163
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Min.
Max.
Unit
Logic Supply Voltage
VCC
Applicable to logic supply voltage pin
4.5
5.5
V
Driver Supply Voltage
VHV
Applicable to driver supply voltage pin
10
65
V
High Level Input Voltage
VIH
Applicable to all input
pins
VCC=4.5V
3.6
—
V
VCC=5.5V
4.4
—
V
Low Level Input Voltage
VIL
Applicable to all input
pins
VCC=4.5V
—
0.9
V
VCC=5.5V
—
1.1
V
High Level Driver Output
Current
IOHVH
Applicable to all driver output pins
—
–2
mA
Low Level Driver Output
Current
IOHVL
Applicable to all driver output pins
—
2
mA
CLK Frequency
ff
See timing diagram
—
4
MHz
tWCLK
See timing diagram
75
—
ns
Data in Setup Time
tDS
See timing diagram
50
—
ns
Data in Hold Time
tDH
See timing diagram
50
—
ns
LS Pulse Width
tWLS
See timing diagram
80
—
ns
CLK-LS Delay Time
tDCL
See timing diagram
50
—
ns
LS-CLK Delay Time
tDLC
See timing diagram
0
—
ns
LS-CHG Delay Time
tDLCG
See timing diagram
0
—
ms
LS-CL Delay Time
tDLCL
See timing diagram
0
—
ms
CHG Pulse Width
tWCHG
See timing diagram
2
—
ms
CL Pulse Width
tWCL
See timing diagram
2
—
ms
Operating Temperature
Top
—
–40
85
°C
CLK Pulse Width
8/13
¡ Semiconductor
MSC1163
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC=5V±10%, VHV=10V to 65V, Ta=–40°C to +85°C)
Parameter
Symbol
ICC1
Logic Supply Current
ICC2
IHV1
Driver Supply Current
High Level Input Voltage
Condition
No load
VCC=5.5V
IHV2
No load
VCC=5.5V
VIH
—
4.3
6.65
—
0.5
1.0
All driver output: Low
—
—
1
mA
All driver output:
High, Ta=25°C
—
2.45
3.8
mA
VCC=4.5V
3.15
—
—
V
VCC=5.5V
3.85
—
—
V
—
—
1.35
V
VCC=5.5V
—
—
1.65
V
—
—
±1
mA
Ta=25°C
Input Capacitance
CIN
Ta=25°C
Low Level Data Output
Voltage
VODL1
IO=20mA
mA
VCC=4.5V
IIN
IO=–20mA
Unit
—
Input Leakage Current
VODH1
Max.
All input: Low
VIL
High Level Data Output
Voltage
Typ.
All input: High, All
driver output: High, Ta=25°C
Low Level Input Voltage
—
Min.
—
15
—
pF
VCC=4.5V
4.2
—
—
V
VCC=5.5V
5.2
—
—
V
VCC=4.5V
—
—
0.2
V
VCC=5.5V
—
—
0.2
V
VCC=4.5V
3.5
—
—
V
VCC=5.5V
4.5
—
—
V
VCC=4.5V
—
—
1.1
V
VCC=5.5V
—
—
1.1
V
High Level Data Output
Voltage
VODH2
IO=–0.1mA
Low Level Data Output
Voltage
VODL2
IO=0.1mA
High Level Driver Output
Voltage
VOHVH
IOHV=–2mA
VHV–3
—
—
V
Low Level Driver Output
Voltage
VOHVL
IOHV=2mA
—
—
3.0
V
AC Characteristics
(VCC=5V, VHV=65V, Ta=25°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
CLK-DOUT Delay Time
tPD
See timing diagram and test circuit
—
100
150
ns
Delay Time Low to High
tDLH
See timing diagram and test circuit
—
0.3
1
ms
Transit Time Low to High
tTLH
See timing diagram and test circuit
—
3
5
ms
Delay Time High to Low
tDHL
See timing diagram and test circuit
—
0.3
1
ms
Transit Time High to Low
tTHL
See timing diagram and test circuit
—
2
5
ms
9/13
CLOCK
T1/2
tDS tDH
T3/4
T39/40
T1/2
tDS tDH
tWCLK
T3/4
tWCLK
¡ Semiconductor
TIMING DIAGRAM
1/f f
DIN
tWD
tPD
tPD
DOUT
tDCL tWLS
tDLC
LS
tDLCG
CHG
tWCHG
tDLCL
tWCHG
tWCL
tWCL
CL
tDLH
tDLH
tDHL
HVO (1, 2, 39, 40)
tDHL
90%
10%
tDLH
90%
10%
HVO (OTHERS)
tTLH
tTLH
tTHL
tTHL
tTLH
MSC1163
10/13
¡ Semiconductor
MSC1163
Test circuit
20pF
V CC
V HV
HVO1
30kW
HVO2
5.0V
GND1, 2
CL
CHG
R/L
DIN
LS
HVO40
CLK
65V
DOUT
30pF
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¡ Semiconductor
MSC1163
FUNCTIONAL DESCRIPTION
Notes on Use
1. The MSC1163GS is designed as an anode driver of VFD.
The data applied to the data input pin is read into the shift register at the rising edge
of the clock and shifted sequencially to the shift register synchronizing with the
clock.
The shift register output drives the output driver, passing through the latch and the
NOR circuit.
Setting the CL pin to "L" makes all driver outputs go into "L". This function can be
used for setting display blanking.
2. The contents of the shift register are undefined after power is turned on.
Therefore, two or more driver outputs may go into "H" at the same time after poweron.
To avoid this, take the following procedure:
1) Turn on the power of the logic portion while holding the CL pin to "L".
2) Turn on the power of the driver portion.
3) Apply a "L" level signal to the DIN pin and send clock pulses by the specified
number of grids to reset ("L") the entire contents of the shift register.
Function Table
CLK
CL
R/L
DIN
R-1
R-2
R-3
R-4
R-40
DOUT
H
H
H
R1n
R2n
R3n
••••••••
R39n
R39n
H
L
L
R1n
R2n
R3n
R39n
R39n
L
H
R2n
R3n
R4n
R5n
H
R2n
L
L
R2n
R3n
R4n
R5n
L
R2n
CHG
LS
R.X
HVO.X
L
X
X
X
L
H
H
X
X
H
H
L
H
H
H
H
L
H
L
L
H
L
L
X
NC
L : Low Level, H: High Level, X: Don't Care, NC: No Change
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¡ Semiconductor
MSC1163
PACKAGE DIMENSIONS
(Unit : mm)
SSOP60-P-700-0.65-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.21 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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