INTERSIL ISL6740IBZ

ISL6740, ISL6741
®
Data Sheet
July 13, 2007
Flexible Double Ended Voltage and
Current Mode PWM Controllers
FN9111.4
Features
• Precision Duty Cycle and Deadtime Control
The ISL6740, ISL6741 family of adjustable frequency, low
power, pulse width modulating (PWM) voltage mode
(ISL6740) and current mode (ISL6741) controllers is
designed for a wide range of power conversion applications
using half-bridge, full bridge, and push-pull configurations.
These controllers provide an extremely flexible oscillator that
allows precise control of frequency, duty cycle, and
deadtime.
• 95μA Startup Current
• Adjustable Delayed Overcurrent Shutdown and Re-start
(ISL6740)
• Adjustable Short Circuit Shutdown and Re-start
• Adjustable Oscillator Frequency Up to 2MHz
• Bidirectional Synchronization
This advanced BiCMOS design features low operating
current, adjustable switching frequency up to 1MHz,
adjustable soft-start, internal and external over-temperature
protection, fault annunciation, and a bidirectional SYNC
signal that allows the oscillator to be locked to paralleled
units or to an external clock for noise sensitive applications.
• Inhibit Signal
Ordering Information
• Adjustable Input Undervoltage Lockout
PART
NUMBER
• Adjustable Soft-start
• Fault Signal
PACKAGE
-40 to +105
16 Ld SOIC
M16.15
• Tight Tolerance Voltage Reference Over Line, Load, and
Temperature
ISL6740IBZ 6740IBZ
(See Note)
-40 to +105
16 Ld SOIC
(Pb-free)
M16.15
• Pb-Free Plus Anneal Available (RoHS Compliant)
ISL6740IV
-40 to +105
16 Ld TSSOP M16.173
ISL6740IVZ ISL67 40IVZ
(See Note)
-40 to +105
16 Ld TSSOP M16.173
(Pb-free)
ISL6741IB
-40 to +105
16 Ld SOIC
M16.15
• File Server Power
ISL6741IBZ 6741IBZ
(See Note)
-40 to +105
16 Ld SOIC
(Pb-free)
M16.15
• Industrial Power Systems
ISL6741IV
-40 to +105
16 Ld TSSOP M16.173
-40 to +105
16 Ld TSSOP M16.173
(Pb-free)
ISL6740IB
ISL67 40IV
ISL6741IB
ISL67 41IV
ISL6741IVZ ISL67 41IVZ
(See Note)
PKG.
DWG. #
• System Over-Temperature Protection Using a Thermistor
or Sensor
TEMP.
RANGE (°C)
ISL6740IB
PART
MARKING
• Internal Over-Temperature Protection
Add -T suffix to part number for tape and reel packaging
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
x=
CONTROL MODE
0
Voltage Mode
1
Current Mode
Applications
• Telecom and Datacom Power
• Wireless Base Station Power
• DC Transformers and Buss Regulators
Pinout
ISL6740, ISL6741
(16 LD SOIC, 16 LD TSSOP)
TOP VIEW
OUTA 1
16 OUTB
GND 2
15 VREF
SCSET 3
14 VDD
CT 4
13 RTD
SYNC 5
12 RTC
CS 6
11 OTS
VERROR 7
UV 8
1
10 FAULT
9 SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
ISL6740
VDD
SYNC
VREF
VREF
5.00 V
1%
2
+
-
FL
100
Q
OUTA
Q
PWM TOGGLE
OUTB
ENABLE
T
BG +-
4.5k
GND
OC S/D
SC S/D
UV
VREF
70µA
S Q
R Q
SC LATCH
SS LOW
ON
SS
IRTC
RTC
RTD
IRTD
SCSET
SHORT CIRCUIT
DETECTION
CT
SS HI
0.6V
0.4
+
--
+
-
Q
50µS
RETRIGGERABLE
ONE SHOT
OTS
SS LOW
S Q
R Q
PWM LATCH
RESET
DOMINANT
PWM
COMPARATOR
0.27V
R Q
SC S/D
FAULT
VREF
OC S/D
SS
0.5
+
-
4.25V
FAULT LATCH
SET DOMINANT
S Q FL
INHIBIT
OC DETECT
VERROR
0.4
+
-
Q
SS DONE
CS
15µA
R Q
300k
4.5V
SS CLAMP
CLK
OC LATCH
S Q
SS DONE
+
OSCILLATOR
VREF UV 4.65V
VREF/2
+
+
BG +-
ISL6740, 1SL6741
N_SYNC OUT
INTERNAL
OT SHUTDOWN
BI-DIRECTIONAL
+130°C TO +150°C
SYNCHRONIZATION SYNC IN
INHIBIT/VIN UV
1.00V
+
EXT. SYNC
INHIBIT
-
FN9111.4
July 13, 2007
Functional Block Diagram (Continued)
ISL6741
SYNC
VREF
VDD
VREF
5.00 V
1%
+
-
FL
100
3
Q
OUTA
Q
PWM TOGGLE
OUTB
ENABLE
T
BG +-
4.5k
GND
SC S/D
1.00 V
UV
N_SYNC OUT
INTERNAL
OT SHUTDOWN
BI-DIRECTIONAL
+130°C TO +150°C
SYNCHRONIZATION SYNC IN
INHIBIT/VIN UV
+
EXT. SYNC
INHIBIT
-
VREF
70µA
SC LATCH
S Q
ON
R Q
RTC
RTD
IRTC
+
OSCILLATOR
IRTD
4.5V
SS CLAMP
CLK
SCSET
15µA
SS DONE
300k
SHORT CIRCUIT
DETECTION
CT
SS DONE
SS LOW
CS
0.6V
80mV
+-
+
--
+
-
S Q
VERROR
0.2
FAULT
SC S/D
VREF
SS
0.25
OTS
R Q
PWM LATCH
RESET
DOMINANT
PWM
COMPARATOR
0.27V
FAULT LATCH
SET DOMINANT
S Q
FL
R Q
INHIBIT
OC DETECT
+
-
VREF UV 4.65V
VREF/2
+
+
BG +-
ISL6740, 1SL6741
SS
FN9111.4
July 13, 2007
Typical Application (ISL6740) - 48V Input DC Transformer, 12V @ 8A Output (ISL6740EVAL1)
SP1
VIN+
+12V
QR1
L1
C11
QH
C2
QR3
T1
L3
R8
C9
C13
R10
TP1
4
C1
QR2
C14
QR4
R11
C12
CR2
C3
CR1
C7
U1
HIP2101
VDD LO
HB VSS
HO LI
HS HI
C4
R14
R5
TP4
TP2
R6
VREF
C10
RT1
C5
OTS
OUTA
CS
CT
RTC
VREF
RTD
TP6
UV
VDD
R3
SCSET
R17
ISL6740
OUTB
R7
R19
VERROR
GND
VIN-
SYNC
FAULT
U3
SS
C18
TP5
Q5
R13
C15
C17
D1
R18
C6
R12
C16
R15
ISL6740, 1SL6741
R1
R9
QL
CR3
RTN
L2
T2
R2
C8
FN9111.4
July 13, 2007
Typical Application (ISL6740) - 36V to 75V Input, Regulated 12V @ 8A Output (ISL6740EVAL2Z)
SP1
VIN+
CR5
L1
QH
C11
QR1
T1
L3
C2
+12V
R26
QR3
R8
+
C8
RTN
L2
R10
TP1
C21
C9
C13
CR4
5
C1
T2
CR6
R27
QL
R2
C14
CR3
QR2
R11
36V TO 75V
R9
QR4
C12
CR2
C3
CR1
C7
U1
HIP2101
VDD LO
HB VSS
HO LI
HS HI
C4
R14
R5
TP4
TP2
R6
VREF
C10
C5
OTS
R4
R20
R19
CT
SCSET
RTC
UV
RTD
TP6
VREF
VDD
CS
ISL6740
OUTA
R3
R19
VERROR
GND
OUTB
R17
SYNC
VIN-
FAULT
U3
SS
C18
TP5
R7
+ 12V
RT1
Q5
R23
C22
C20
R25
R13
C15
R21
C19
U2
U4
C17
D1
R18
C6
R12
C16
R15
D2
R24
ISL6740, 1SL6741
R1
FN9111.4
July 13, 2007
Typical Application (ISL6741) - 48V to 5V Push-Pull DC/DC Converter
+ 5V
RTN
+48V
QR1
R18
R19
R20
T1
+
C9
CR1
EL7242
+5V
L1
6
C1
CR2
QR2
Q1
U5
RT1
Q2
R12
T3
SYNC
VERROR
OUTA
CS
CT
+ 5V
SCSET
VREF
RTD
R4
OUTA
CR4
RTC
UV
VDD
CR3
U3
SS
GND
OUTB
ISL6741
VIN-
SYNC
R3
OTS
R1
FAULT
R2
R21
R14
R13
R15
C8
R6
R5
C3
Q3
R7
R8
C4
C5
R16
R10
C7
U2
C6
VR1
U4
R17
C2
R9
ISL6740, 1SL6741
OUTB
R11
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUTA, OUTB, Signal Pins . . . . . . . . . . . . . . . . .GND - 0.3V to VREF
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1500V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
Thermal Resistance Junction to Ambient (Typical)
θJA (°C/W)
16 Lead SOIC (Note 1) . . . . . . . . . . . . . . . . . . . . . .
77
16 Lead TSSOP (Note 1) . . . . . . . . . . . . . . . . . . . . .
102
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL6740Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
ISL6741Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . 9VDC - 16VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. 9V < VDD < 20 V, RTD = 51.1kΩ, RTC = 10kΩ, CT = 470pF, TA = -40°C to +105°C (Note 3), Typical
values are at TA = +25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE
Start-Up Current, IDD
VDD < START Threshold
-
95
140
μA
Operating Current, IDD
RLOAD, COUTA,B = 0
-
5.0
8.0
mA
COUTA,B = 1nF
-
7.0
12.0
mA
UVLO START Threshold
6.50
7.25
8.00
V
UVLO STOP Threshold
6.00
6.75
7.50
V
Hysteresis
0.25
0.50
0.75
V
4.900
5.000
5.050
V
-
3
-
mV
Fault Voltage
4.10
4.55
4.75
V
VREF Good Voltage
4.25
4.75
VREF - 0.05
V
Hysteresis
75
165
250
mV
Operational Current (source)
-20
-
-
mA
5
-
-
mA
-25
-
-100
mA
0.55
0.6
0.65
V
CS to OUT Delay
-
35
50
ns
CS Sink Current
-
10
-
mA
-1.00
-
1.00
μA
REFERENCE VOLTAGE
Overall Accuracy
IVREF = 0, -20mA
Long Term Stability
TA = +125°C, 1000 hours (Note 4)
Operational Current (sink)
Current Limit
CURRENT SENSE
Current Limit Threshold
VERROR = VREF
Input Bias Current
CS to PWM Comparator Input Offset (ISL6741)
(Note 4)
-
80
-
mV
Gain (ISL6741)
ACS = ΔVERROR/ΔVCS (Note 4)
-
4
-
V/V
SCSET Input Impedance
1
-
-
MΩ
SC Setpoint Accuracy
-
10
-
%
7
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. 9V < VDD < 20 V, RTD = 51.1kΩ, RTC = 10kΩ, CT = 470pF, TA = -40°C to +105°C (Note 3), Typical
values are at TA = +25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
400
-
-
kΩ
VERROR < CS Offset (ISL6741)
-
-
0
%
VERROR < CT Valley Voltage (ISL6740)
-
-
0
%
Maximum Duty Cycle
VERROR > 4.75V (Note 6)
-
83
-
%
VERROR to PWM Comparator Input Offset
(ISL6741)
(Note 4)
0.4
1.0
1.25
V
VERROR to PWM Comparator Input Gain (ISL6741) (Note 4)
-
0.25
-
VERROR to PWM Comparator Input Gain (ISL6740) (Note 4)
-
0.4
-
V/V
CT to PWM Comparator Input Gain (ISL6740)
(Note 4)
-
0.4
-
V/V
SS to PWM Comparator Input Gain (ISL6740)
(Note 4)
-
0.5
-
V/V
SS to PWM Comparator Input Gain (ISL6741)
(Note 4)
-
0.2
-
V/V
333
351
369
kHz
PULSE WIDTH MODULATOR
VERROR Input Impedance
Minimum Duty Cycle
OSCILLATOR
Frequency Accuracy
TA = +25°C
Frequency Variation with VDD
T = +105°C (f20V- - f9V)/f9V
-
2
3
%
T = -40°C (f20V- - f9V)/f9V
-
2
3
%
(Note 4)
-
8
-
%
1.88
2.0
2.12
μA/μA
45
55
65
μA/μA
CT Valley Voltage
0.75
0.80
0.85
V
CT Peak Voltage
2.70
2.80
2.90
V
-
2.000
-
V
Input High Threshold (VIH), Minimum
4.0
-
-
V
Input Low Threshold (VIL), Maximum
-
-
0.8
V
4.5
-
kΩ
0.6x
Free
Running
-
Free Running
Hz
Temperature Stability
Charge Current Gain
Discharge Current Gain
RTD, RTC Voltage
RLOAD = 0
SYNCHRONIZATION
Input Impedance
Input Frequency Range
(Note 4)
High Level Output Voltage (VOH)
ILOAD = -1mA
-
4.5
-
V
Low Level Output Voltage (VOL)
ILOAD = 10μA
-
-
100
mV
SYNC Output Current
VOH > 2.0V (Note 4)
-10
-
-
mA
SYNC Output Pulse Duration (minimum)
(Notes 4, 5)
250
-
400
ns
SYNC Advance
SYNC rising edge to GATE falling edge,
CGATE = CSYNC = 100pF
(Note 4)
-
5
-
ns
-45
-55
-75
μA
4.35
4.5
4.65
V
0.20
0.25
0.30
V
SOFTSTART
Charging Current
SS = 2V
SS Clamp Voltage
Sustained Over Current Threshold Voltage
(ISL6740)
8
Charged Threshold minus:
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. 9V < VDD < 20 V, RTD = 51.1kΩ, RTC = 10kΩ, CT = 470pF, TA = -40°C to +105°C (Note 3), Typical
values are at TA = +25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Overcurrent/Short Circuit Discharge Current
SS = 2V
13
18
23
μA
Fault SS Discharge Current
SS = 2V
-
10.0
-
mA
0.25
0.27
0.33
V
Reset Threshold Voltage
FAULT
Fault High Level Output Voltage (VOH)
ILOAD = -10mA
2.85
3.5
-
V
Fault Low Level Output Voltage (VOL)
ILOAD = 10mA
-
0.4
0.9
V
Fault Rise Time
CLOAD = 100pF (Note 4)
-
15
-
ns
Fault Fall Time
CLOAD = 100pF (Note 4)
-
15
-
ns
High Level Output Voltage (VOH)
VREF - OUTA or OUTB,
IOUT = -50mA
-
0.5
1.0
V
Low Level Output Voltage (VOL)
OUTA or OUTB - GND, IOUT = 50mA
-
0.5
1.0
V
Rise Time
CGATE = 1nF, VDD = 15V (Note 4)
-
50
100
ns
Fall Time
CGATE = 1nF, VDD = 15V (Note 4)
-
40
80
ns
OUTPUT
THERMAL PROTECTION
Thermal Shutdown
(Note 4)
135
145
155
°C
Thermal Shutdown Clear
(Note 4)
120
130
140
°C
Hysteresis, Internal Protection
(Note 4)
-
15
-
°C
Reference, External Protection
2.375
2.50
2.625
V
Hysteresis, External Protection
18
25
30
μA
0.97
1.00
1.03
V
7
10
15
μA
4.8
-
-
V
1
-
-
MΩ
SUPPLY UVLO/INHIBIT
Input Voltage Low/Inhibit Threshold
Hysteresis, Switched Current Amplitude
Input High Clamp Voltage
Input Impedance
NOTES:
3. Specifications at -40°C and 105°C are guaranteed by 25°C test with margin limits.
4. This parameter, although guaranteed by characterization or correlation testing, is not 100% tested in production.
5. SYNC pulse width is the greater of this value or the CT discharge time.
6. This is the maximum duty cycle achievable using the specified values of RTC, RTD, and CT. Larger or smaller maximum duty cycles may be
obtained using other values for these components. See Equations 2 through 4.
9
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Typical Performance Curves
65
CT DISCHARGE CURRENT GAIN
NORMALIZED VREF
1.001
1.000
0.999
0.998
0.997
-40
-25 -10
5
20
35
50
65
80
95 110
60
55
50
45
40
0
50
100 150 200 250 300 350 400 450 500
TEMPERATURE (°C)
RTD CURRENT (µA)
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. OSCILLATOR CT DISCHARGE CURRENT GAIN
1•106
CT (pF) =
1000
680
470
1•103 330
220
100
FREQUENCY (Hz)
DEADTIME - TD (ns)
1•104
100
10
10
20
30
40
50
60
70
80
90
100
RTD (kΩ)
1•105
RTD = 10k
CT (pF) =
100
220
330
470
1•104
10
20
30
680
1000
40
50
60
70
80
90
100
RTC (kΩ)
FIGURE 3. DEADTIME (TD) vs CAPACITANCE
FIGURE 4. CAPACITANCE vs FREQUENCY
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a ceramic
capacitor as close to the VDD and GND pins as possible.
The total supply current, IDD, will be dependent on the load
applied to outputs OUTA and OUTB. Total IDD current is the
sum of the quiescent current and the average output current.
Knowing the operating frequency, fSW, and the output
loading capacitance charge, Q, per output, the average
output current can be calculated from:
I OUT = 2 • Q • f SW
A
(EQ. 1)
SYNC - A bidirectional synchronization signal used to
coordinate the switching frequency of multiple units.
Synchronization may be achieved by connecting the SYNC
signal of each unit together or by using an external master
clock signal. The oscillator timing capacitor, CT, is always
required regardless of the synchronization method used.
The paralleled unit with the highest oscillator frequency
assumes control.
10
RTC - This is the oscillator timing capacitor charge current
control pin. A resistor is connected between this pin and
GND. The current flowing through the resistor determines
the magnitude of the charge current. The charge current is
nominally twice this current. The PWM maximum ON time is
determined by the timing capacitor charge duration.
RTD - This is the oscillator timing capacitor discharge
current control pin. A resistor is connected between this pin
and GND. The current flowing through the resistor
determines the magnitude of the discharge current. The
discharge current is nominally 50x this current. The PWM
deadtime is determined by the timing capacitor discharge
duration.
CT - The oscillator timing capacitor is connected between
this pin and GND.
VERROR - The inverting input of the PWM comparator. The
error voltage is applied to this pin to control the duty cycle.
Increasing the signal level increases the duty cycle. The
FN9111.4
July 13, 2007
ISL6740, 1SL6741
node may be driven with an external error amplifier or optocoupler.
The ISL6740, ISL6741 features a built-in soft-start. Soft-start
is implemented as a clamp on the error voltage input.
OTS - The non-inverting input to the over-temperature
shutdown comparator. The signal input at this pin is
compared to an internal threshold of VREF/2. If the voltage at
this pin exceeds the threshold, the Fault signal is asserted
and the outputs are disabled until the condition clears. There
is a nominal 25μA switched current source used for
hysteresis. The amount of hysteresis is adjustable by
varying the source impedance of the signal into this pin.
OTS may be used to monitor parameters other than
temperature, such as voltage. Any signal for which a high
out-of-bounds monitor is desired may utilize the OTS
comparator.
FAULT - The Fault signal is asserted high whenever the
outputs, OUTA and OUTB, are disabled. This occurs during
an over-temperature fault, an input UV fault, a VREF UV
fault, or during an overcurrent (ISL6740) or short circuit
shutdown fault. Fault can be used to disable synchronous
rectifiers whenever the outputs are disabled.
Fault is a three-state output and is high impedance during
the soft-start cycle. Adding a pull-up resistor to VREF or a
pull-down resistor to ground determines the state of Fault
during soft-start. This feature allows the designer to use the
Fault signal to enable or disable output synchronous
rectifiers during soft-start.
UV - Undervoltage monitor input pin. A resistor divider
between the input source voltage and GND sets the
undervoltage lock out threshold. The signal is compared to
an internal 1.00V reference to detect an undervoltage or
inhibit condition.
CS - This is the input to the current sense comparator(s).
The IC has the PWM comparator for peak current mode
control (ISL6741) and an overcurrent protection comparator.
The overcurrent comparator threshold is set at 0.600V
nominal.
The CS pin is shorted to GND at the end of each switching
cycle. Depending on the current sensing source impedance,
a series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may allow an overlap such that the CS signal may
be discharged while the current signal is still active. If the
current sense source is low impedance, it will cause
increased power dissipation.
ISL6740 - Exceeding the overcurrent threshold will start a
delayed shutdown sequence. Once an overcurrent condition
is detected, the soft-start charge current source is disabled.
The soft-start capacitor begins discharging through a 25μA
current source, and if it discharges to less than 4.25V
11
(Sustained Overcurrent Threshold), a shutdown condition
occurs and the OUTA and OUTB outputs are forced low.
When the soft-start voltage reaches 0.27V (Reset
Threshold) a soft-start cycle begins.
An overcurrent condition must be absent for 50μs before the
delayed shutdown control resets. If the overcurrent condition
ceases, and an additional 50μs period elapses before the
shutdown threshold is reached, no shutdown occurs. The SS
charging current is re-enabled and the soft-start voltage is
allowed to recover.
ISL6741 - The ISL6741 current mode controller does not
shutdown due to an overcurrent condition. The pulse-bypulse current limit characteristic of peak current mode
control limits the output current to acceptable levels.
GND - Reference and power ground for all functions on this
device. Due to high peak currents and high frequency
operation, a low impedance layout is necessary. Ground
planes and short traces are highly recommended.
OUTA and OUTB - Alternate half cycle output stages. Each
output is capable of 0.5A peak currents for driving logic level
power MOSFETs or MOSFET drivers. Each output provides
very low impedance to overshoot and undershoot.
VREF - The 5.00V reference voltage output. +1%/-2%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.047μF to 2.2μF ceramic capacitor.
Capacitors outside of this range may cause oscillation.
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of
the capacitor determines the rate of increase of the duty
cycle during start up, controls the overcurrent shutdown
delay (ISL6740), and the overcurrent and short circuit hiccup
restart period.
SCSET - Sets the duty cycle threshold that corresponds to a
short circuit condition. A resistive divider between RTC and
GND or RTD and GND, or a voltage between 0V and 2V may
be used to adjust the SCSET threshold. If using a resistor
divider from either RTC or RTD, the impedance to GND
affects the oscillator timing and should be considered when
determining the oscillator timing components. Connecting
SCSET to GND disables short circuit shutdown and hiccup.
Functional Description
Features
The ISL6740, ISL6741 PWMs are an excellent choice for
low cost bridge and push-pull topologies for applications
requiring accurate duty cycle and deadtime control. With its
many protection and control features, a highly flexible design
with minimal external components is possible. Among its
many features are current mode control (ISL6741),
adjustable soft-start, overcurrent protection, thermal
protection, bidirectional synchronization, fault indication, and
adjustable frequency.
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Oscillator
The ISL6740, ISL6741 have an oscillator with a
programmable frequency range to 2MHz, which can be
programmed with two resistors and capacitor. The use of
three timing elements, RTC, RTD, and CT allow great
flexibility and precision when setting the oscillator frequency.
The switching period may be considered the sum of the
timing capacitor charge and discharge durations. The charge
duration is determined by RTC and CT. The discharge
duration is determined by RTD and CT.
T C ≈ 0.5 • R TC • C T
T D ≈ 0.02 • R TD • C T
1
T SW = T C + T D = -----------F SW
(EQ. 2)
S
(EQ. 3)
S
S
(EQ. 4)
where TC and TD are the charge and discharge times,
respectively, TSW is the oscillator free running period, and f
is the oscillator frequency. One output switching cycle
requires two oscillator cycles. The actual times will be
slightly longer than calculated due to internal propagation
delays of approximately 10ns/transition. This delay ads
directly to the switching duration, but also causes overshoot
of the timing capacitor peak and valley voltage thresholds,
effectively increasing the peak-to-peak voltage on the timing
capacitor. Additionally, if very low charge and discharge
currents are used, there will be increased error due to the
input impedance at the CT pin.
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
TC
D = -----------T SW
(EQ. 5)
DT = 1 – D
(EQ. 6)
Implementing Synchronization
The oscillator can be synchronized to an external clock
applied to the SYNC pin or by connecting the SYNC pins of
multiple ICs together. If an external master clock signal is
used, the free running frequency of the oscillator should be
~10% slower than the desired synchronous frequency. The
external master clock signal should have a pulse width
greater than 20ns. The SYNC circuitry will not respond to an
external signal during the first 60% of the oscillator switching
cycle.
The SYNC input is edge triggered and its duration does not
affect oscillator operation. However, the deadtime is affected
by the SYNC frequency. A higher frequency signal applied to
the SYNC input will shorten the deadtime. The shortened
deadtime is the result of the timing capacitor charge cycle
12
being prematurely terminated by the external SYNC pulse.
Consequently, the timing capacitor is not fully charged when
the discharge cycle begins. This effect is only a concern
when an external master clock is used, or if units with
different operating frequencies are paralleled.
Soft-start Operation
The ISL6740, ISL6741 feature a soft-start using an external
capacitor in conjunction with an internal current source. softstart reduces stresses and surge currents during start up.
Upon start up, the soft-start circuitry clamps the error voltage
input (VERROR pin) indirectly to a value equal to the softstart voltage. The soft-start clamp does not actually clamp
the error voltage input as is done in many implementations.
Rather the PWM comparator has two inverting inputs such
that the lower voltage is in control.
The output pulse width increases as the soft-start capacitor
voltage increases. This has the effect of increasing the duty
cycle from zero to the regulation pulse width during the softstart period. When the soft-start voltage exceeds the error
voltage, soft-start is completed. soft-start occurs during
start-up, after recovery from a Fault condition or
overcurrent/short circuit shutdown. The soft-start voltage is
clamped to 4.5V.
The Fault signal output is high impedance during the softstart cycle. A pull-up resistor to VREF or a pull-down resistor
to ground should be added to achieve the desired state of
Fault during soft-start.
Gate Drive
The ISL6740, ISL6741 are capable of sourcing and sinking
0.5A peak current, but are primarily intended to be used in
conjunction with a MOSFET driver due to the 5V drive level.
To limit the peak current through the IC, an external resistor
may be placed between the totem-pole output of the IC
(OUTA or OUTB pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET’s input capacitance.
Undervoltage Monitor and Inhibit
The UV input is used for input source undervoltage lockout
and inhibit functions. If the node voltage falls below 1.00V a
UV shutdown fault occurs. This may be caused by low
source voltage or by intentional grounding of the pin to
disable the outputs. There is a nominal 10μA switched
current source used to create hysteresis. The current source
is active only during an UV/Inhibit fault; otherwise, it is
inactive and does not affect the node voltage. The
magnitude of the hysteresis is a function of the external
resistor divider impedance. If the resistor divider impedance
results in too little hysteresis, a series resistor between the
UV pin and the divider may be used to increase the
hysteresis. A soft-start cycle begins when the UV/Inhibit fault
clears.
FN9111.4
July 13, 2007
ISL6740, 1SL6741
The voltage hysteresis created by the switched current
source and the external impedance is generally small due to
the large resistor divider ratio required to scale the input
voltage down to the UV threshold level. A small capacitor
placed between the UV input and ground may be required to
filter noise out.
VIN
R1
1.00V
+
-
Latching OC shutdown is also possible by using a lower
valued resistor between VREF and SS. If the SS node is not
allowed to discharge below the SS reset threshold, the IC
will not recover from an overcurrent fault. The value of the
resistor must be low enough so that the maximum specified
discharge current is not sufficient to pull SS below 0.33V. A
200kΩ resistor, for example, prevents SS from discharging
below ~0.4V. Again, the external pull-up resistor will
decrease the SS duration, so its effect should be considered
when selecting the value of the SS capacitor.
R3
10μA
R2
ON
FIGURE 5. UV HYSTERESIS
As VIN decreases to a UV condition, the threshold level is:
R1 + R2
V IN ( DOWN ) = ---------------------R2
V
(EQ. 7)
The hysteresis voltage, ΔV, is:
ΔV = 10
–5
R1 + R2
• 〈 R1 + R3 • ⎛ ----------------------⎞ 〉
⎝ R2 ⎠
V
(EQ. 8)
Setting R3 equal to zero results in the minimum hysteresis,
and yields:
ΔV = 10
–5
• R1
V
(EQ. 9)
As VIN increases from a UV condition, the threshold level is:
V IN ( UP ) = V IN ( DOWN ) + ΔV
V
(EQ. 10)
Over Current Operation
ISL6740 - Overcurrent delayed shutdown is enabled once
the soft-start cycle is complete. If an overcurrent condition is
detected, the soft-start charging current source is disabled
and the soft-start capacitor is allowed to discharge through a
15μA source. At the same time a 50μs re-triggerable oneshot timer is activated. It remains active for 50μs after the
overcurrent condition ceases. If the soft-start capacitor
discharges by more then 0.25V to 4.25V, the output is
disabled and the Fault signal asserted. This state continues
until the soft-start voltage reaches 270mV, at which time a
new soft-start cycle is initiated. If the overcurrent condition
stops at least 50μs prior to the soft-start voltage reaching
4.25V, the soft-start charging currents revert to normal
operation and the soft-start voltage is allowed to recover.
13
The duration of the OC shutdown period can be increased
by adding a resistor between VREF and SS. The value of
the resistor must be large enough so that the minimum
specified SS discharge current is not exceeded. Using a
422kΩ resistor, for example, will result in a small current
being injected into SS, effectively reducing the discharge
current. This will increase the OFF time by about 60%,
nominally. The external pull-up resistor will also decrease
the SS duration, so its effect should be considered when
selecting the value of the SS capacitor.
ISL6741 - Overcurrent results in pulse-by-pulse duty cycle
reduction as occurs in any peak current mode controller. This
results in a well controlled decrease in output voltage with
increasing current beyond the overcurrent threshold. An
overcurrent condition in the ISL6741 will not cause a
shutdown.
Short Circuit Operation
A short circuit condition is defined as the simultaneous
occurrence of current limit and a reduced duty cycle. The
degree of reduced duty cycle is user adjustable using the
SCSET input. A resistor divider between either RTD or RTC
and GND to RCSET sets a threshold that is compared to the
voltage on the timing capacitor, CT. The resistor divider
percentage corresponds to the fraction of the maximum duty
cycle below which a short circuit may exist. If the timing
capacitor voltage fails to exceed the threshold before an
overcurrent pulse is detected, a short circuit condition exists.
A shutdown and soft-start cycle will begin if 8 short circuit
events occur within 32 oscillator cycles. Connecting SCSET
to GND disables this feature.
Since the current sourced from both RTC and RTD determine
the charge and discharge currents for the timing capacitor,
the effect of the SCSET divider must be included in the
timing calculations. Typically the resistor between RTC and
GND is formed by two series resistors with the center node
connected to SCSET.
Alternatively, SCSET may be set using a voltage between
0V and 2V. This voltage divided by 2 determines the
percentage of the maximum duty cycle that corresponds to a
short circuit when current limit is active. For example, if the
maximum duty cycle is 95% and 1V is applied to SCSET,
then the short circuit duty cycle is 50% of 95% or 47.5%.
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Fault Conditions
A fault condition occurs if VREF falls below 4.65V, the UV
input falls below 1.00V, the thermal protection is triggered, or
if OTS faults. When a fault is detected, OUTA and OUTB
outputs are disabled, the Fault signal is asserted, and the
soft-start capacitor is quickly discharged. When the fault
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins. The Fault signal is high
impedance during the soft-start cycle.
An overcurrent condition that results in shutdown (ISL6740),
or a short circuit shutdown also cause assertion of the Fault
signal. The difference between a current fault and the faults
described earlier is that the soft-start capacitor is not quickly
discharged. The initiation of a new soft-start cycle is delayed
while the soft-start capacitor is discharged at a 15μA rate.
This keeps the average output current to a minimum.
Thermal Protection
Two methods of over-temperature protection are provided.
The first method is an on board temperature sensor that
protects the device should the junction temperature exceed
145°C. There is approximately 15°C of hysteresis.
The second method uses an internal comparator with a 2.5V
reference (VREF/2). The non-inverting input to the
comparator is accessible through the OTS pin. A thermistor
or thermal sensor located at or near the area of interest may
be connected to this input. There is a nominal 25μA switched
current source used to create hysteresis. The current source
is active only during an OT fault; otherwise, it is inactive and
does not affect the node voltage. The magnitude of the
hysteresis is a function of the external resistor divider
impedance. Either a positive temperature coefficient (PTC)
or a negative temperature coefficient (NTC) thermistor may
be used. If a NTC is desired, position R1 may be substituted.
VREF
ON
R1
25μA
VREF/2
VTH↑ = 2.5V and R1 = R2 (HOT)
To determine the value of the hysteresis resistor, R3, select
the value of thermistor resistance that corresponds to the
desired reset temperature.
5
10 • ( R1 – R2 ) – R1 • R2
R3 = ---------------------------------------------------------------------R1 + R2
Ω
(EQ. 11)
If the hysteresis resistor, R3, is not desired, the value of the
thermistor resistance at the reset temperature can be
determined from:
2.5 • R2
R1 = ---------------------------------------–5
2.5 – 10 • R2
Ω
( NTC )
(EQ. 12)
2.5 • R1
R2 = ----------------------------------------–5
2.5 + 10 • R1
Ω
( PTC )
(EQ. 13)
The OTS comparator may also be used to monitor signals
other than suggested above. It may also be used to monitor
any voltage signal for which an excess requires a response
as described above. Input or output voltage monitoring are
examples of this.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD should
be bypassed directly to GND with good high frequency
capacitance.
Typical Application
The Typical Application Schematic features the ISL6740 in
an unregulated half-bridge DC/DC converter configuration,
often referred to as a DC Transformer or Bus Regulator. The
ISL6740EVAL1 demonstration unit implements this design
and is available for evaluation.
VREF
R3
If a PTC is desired, then position R2 may be substituted. The
threshold with increasing temperature is set by making the
fixed resistance equal in value to the thermistor resistance at
the desired trip temperature.
+
-
R2
The input voltage range is 48 ±10%VDC. The output is a
nominal 12V when the input voltage is at 48V. Since this is
an unregulated topology, the output voltage will vary
proportionately with input voltage. The load regulation is a
function of resistance between the source and the converter
output. The output is rated at 8A.
FIGURE 6. OTS HYSTERESIS
14
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
Input Filtering: L1, C1, R1
Half-Bridge Capacitors: C2, C3
Isolation Transformer: T1
Primary Snubber: C13, R10
Start Bias Regulator: CR3, R2, R7, C6, Q5, D1
Supply Bypass Components: R3, C15, C4, C5
Main MOSFET Power Switch: QH, QL
Current Sense Network: T2, CR1, CR2, R5, R6, R11, C10, C14
Control Circuit: U3, RT1, R14, R19, R13, R15, R17, R18, C16,
C18, C17
energy, the number of turns that have to be wound, and
the wire gauge needed. Often the window area (the space
used for the windings) and power loss determine the final
core size.
• Determine maximum desired flux density. Depending on
the frequency of operation, the core material selected, and
the operating environment, the allowed flux density must
be determined. The decision of what flux density to allow
is often difficult to determine initially. Usually the highest
flux density that produces an acceptable design is used,
but often the winding geometry dictates a larger core than
is indicated based on flux density alone.
• Determine the number of primary turns.
• Select the wire gauge for each winding.
• Determine winding order and insulation requirements.
• Verify the design.
Output Rectification and Filtering: QR1, QR2, QR3, QR4, L2,
C9, C8
Secondary Snubber: R8, R9, C11, C12
nSR
nS
nP
FET Driver: U1
nS
ZVS Resonant Delay (Optional): L3, C7
nSR
Design Criteria
The following design requirements were selected:
Switching Frequency, Fsw: 235kHz
VIN: 48 ±10%V
VOUT: 12V (nominal) @ IOUT = 8A
POUT: 100W
FIGURE 7. TRANSFORMER SCHEMATIC
For this application we have selected a planar structure to
achieve a low profile design. A PQ style core was selected
because of its round center leg cross section, but there are
many suitable core styles available.
Since the converter is operating open loop at nearly 100%
duty cycle, the turns ratio, N, is simply the ratio of the input
voltage to the output voltage divided by 2.
Efficiency: 95%
Ripple: 1%
Transformer Design
The design of a transformer for a half-bridge application is a
straight forward affair, although iterative. It is a process of
many compromises, and even experienced designers will
produce different designs when presented with identical
requirements. The iterative design process is not presented
here for clarity.
V IN
48
N = ------------------------- = --------------- = 2
V OUT • 2
12 • 2
(EQ. 14)
The factor of 2 divisor is due to the half-bridge topology. Only
half of the input voltage is applied to the primary of the
transformer.
The abbreviated design process follows:
A PC44HPQ20/6 “E-Core” plus a PC44PQ20/3 “I-Core” from
TDK were selected for the transformer core. The ferrite
material is PC44.
• Select a core geometry suitable for the application.
Constraints of height, footprint, mounting preference, and
operating environment will affect the choice.
The core parameter of concern for flux density is the
effective core cross sectional area, Ae. For the PQ core
pieces selected:
• Determine the turns ratio.
Ae = 0.62cm2 or 6.2e -5m2
• Select suitable core material(s).
• Select maximum flux density desired for operation.
• Select core size. Core size will be dictated by the
capability of the core structure to store the required
15
Using Faraday’s Law, V = N dΦ/dt, the number of primary
turns can be determined once the maximum flux density is
set. An acceptable Bmax is ultimately determined by the
allowable power dissipation in the ferrite material and is
FN9111.4
July 13, 2007
ISL6740, 1SL6741
influenced by the lossiness of the core, core geometry,
operating ambient temperature, and air flow. The TDK
datasheet for PC44 material indicates a core loss factor of
~400mW/cm3 with a ±2000 gauss 100kHz sinusoidal
excitation. The application uses a 235kHz square wave
excitation, so no direct comparison between the application
and the data can be made. Interpolation of the data is
required. The core volume is approximately 1.6cm3, so the
estimated core loss is
f act
3
mW
200kHz
P loss ≈ ----------- • cm • --------------- = 0.4 • 1.6 • --------------------- = 1.28
3
f meas
100kHz
cm
trace width results in a copper thickness of 4.44 mils
(0.112mm). Using 1.3 mils/oz. of copper requires a copper
weight of 3.4oz. For reasons of cost, 3oz. copper was
selected.
One layer of each secondary winding also contains the
synchronous rectifier winding. For this layer the secondary
trace width is reduced by 0.025 inches to 0.100 inches(0.015
inches for the SR winding trace width and 0.010 inches
spacing between the SR winding and the secondary
winding).
W
(EQ. 15)
1.28W of dissipation is significant for a core of this size.
Reducing the flux density to 1200 gauss will reduce the
dissipation by about the same percentage, or 40%.
Ultimately, evaluation of the transformer’s performance in
the application will determine what is acceptable.
From Faraday’s Law and using 1200 gauss peak flux density
(ΔB = 2400 gauss or 0.24 tesla)
The choice of copper weight may be validated by calculating
the DC copper losses of the secondary winding as follows.
Ignoring the terminal and lead-in resistance, the resistance
of each layer of the secondary may be approximated using
Equation 18.
2πρ
R = -----------------------⎛ r 2⎞
t • ln ⎜ -----⎟
⎝ r 1⎠
Ω
(EQ. 18)
where
V IN • T ON
53 • 2 • 10
N = ------------------------------ = ----------------------------------------------------- = 3.56
–5
2 • A e • ΔB
2 • 6.2 • 10 • 0.24
–6
turns
(EQ. 16)
Rounding up yields 4 turns for the primary winding. The peak
flux density using 4 turns is ~1100 gauss. From Equation 1,
the number of secondary turns is 2.
The volts/turn for this design ranges from 5.4V at VIN = 43V
to 6.6V at VIN = 53V. Therefore, the synchronous rectifier
(SR) windings may be set at 1 turn each with proper FET
selection. Selecting 2 turns for the synchronous rectifier
windings would also be acceptable, but the gate drive losses
would increase.
The next step is to determine the equivalent wire gauge for
the planar structure. Since each secondary winding
conducts for only 50% of the period, the RMS current is
I RMS = I OUT • D = 10 • 0.5 = 7.07
A
(EQ. 17)
where D is the duty cycle. Since an FR-4 PWB planar
winding structure was selected, the width of the copper
traces is limited by the window area width, and the number
of layers is limited by the window area height. The PQ core
selected has a usable window area width of 0.165 inches.
Allowing one turn per layer and 0.020 inches clearance at
the edges allows a maximum trace width of 0.125 inches.
Using 100 circular mils(c.m.)/A as a guideline for current
density, and from Equation 17, 707c.m. are required for each
of the secondary windings (a circular mil is the area of a
circle 0.001 inches in diameter). Converting c.m. to square
mils yields 555mils2 (0.785 sq. mils/c.m.). Dividing by the
16
R = Winding resistance
ρ = Resistivity of copper = 669e-9Ω-inches at 20°C
t = Thickness of the copper (3 oz.) = 3.9e-3 inches
r2 = Outside radius of the copper trace = 0.324 or 0.299
inches
r1 = Inside radius of the copper trace = 0.199 inches
The winding without the SR winding on the same layer has a
DC resistance 2.21mΩ. The winding that shares the layer
with the SR winding has a DC resistance of 2.65mΩ. With
the secondary configured as a 4 turn center tapped winding
(2 turns each side of the tap), the total DC power loss for the
secondary at +20°C is 486mW.
The primary windings have an RMS current of approximately
5A (IOUT x NS/NP at ~ 100% duty cycle). The primary is
configured as 2 layers, 2 turns per layer to minimize the
winding stack height. Allowing 0.020 inches edge clearance
and 0.010 inches between turns yields a trace width of
0.0575 inches. Ignoring the terminal and lead-in resistance,
and using Equation 18, the inner trace has a resistance of
4.25mΩ, and the outer trace has a resistance of 5.52mΩ.
The resistance of the primary then is 19.5mΩ at +20°C. The
total DC power loss for the secondary at +20°C is 489mW.
Improved efficiency and thermal performance could be
achieved by selecting heavier copper weight for the windings.
Evaluation in the application will determine its need.
FN9111.4
July 13, 2007
ISL6740, 1SL6741
The order and geometry of the windings affects the AC
resistance, winding capacitance, and leakage inductance of
the finished transformer. To mitigate these effects,
interleaving the windings is necessary. The primary winding
is sandwiched between the two secondary windings. The
winding layout appears below.
FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING
FIGURE 7A. TOP LAYER: 1 TURN SECONDARY AND SR
WINDINGS
FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING
FIGURE 7B. INT. LAYER 1: 1 TURN SECONDARY WINDING
FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR
WINDINGS
∅0.689
∅0.358
0.807
0.639
FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING
0.403
0.169
0.000
0.000 0.184
0.479
0.774
1.054
FIGURE 7G. PWB DIMENSIONS
17
FN9111.4
July 13, 2007
ISL6740, 1SL6741
MOSFET Selection
The criteria for selection of the primary side half-bridge FETs
and the secondary side synchronous rectifier FETs is largely
based on the current and voltage rating of the device.
However, the FET drain-source capacitance and gate
charge cannot be ignored.
The zero voltage switch (ZVS) transition timing is dependent
on the transformer’s leakage inductance and the
capacitance at the node between the upper FET source and
the lower FET drain. The node capacitance is comprised of
the drain-source capacitance of the FETs and the
transformer parasitic capacitance. The leakage inductance
and capacitance form an LC resonant tank circuit which
determines the duration of the transition. The amount of
energy stored in the LC tank circuit determines the transition
voltage amplitude. If the leakage inductance energy is too
low, ZVS operation is not possible and near or partial ZVS
operation occurs. As the leakage energy increases, the
voltage amplitude increases until it is clamped by the FET
body diode to ground or VIN, depending on which FET
conducts. When the leakage energy exceeds the minimum
required for ZVS operation, the voltage is clamped until the
energy is transferred. This behavior increases the time
window for ZVS operation. This behavior is not without
consequences, however. The transition time and the period
of time during which the voltage is clamped reduces the
effective duty cycle.
The gate charge affects the switching speed of the FETs.
Higher gate charge translates into higher drive requirements
and/or slower switching speeds. The energy required to
drive the gates is dissipated as heat.
The maximum input voltage, VIN, plus transient voltage,
determines the voltage rating required. With a maximum
input voltage of 53V for this application, and if we allow a
10% adder for transients, a voltage rating of 60V or higher
will suffice.
The RMS current through the each primary side FET can be
determined from Equation 17, substituting 5A of primary
current for IOUT. The result is 3.5A RMS. Fairchild FDS3672
FETs, rated at 100V and 7.5A (rDS(ON) = 22mΩ), were
selected for the half-bridge switches.
The synchronous rectifier FETs must withstand
approximately one half of the input voltage assuming no
switching transients are present. This suggests a device
capable of withstanding at least 30V is required. Empirical
testing in the circuit revealed switching transients of 20V
were present across the device indicating a rating of at least
60V is required.
The RMS current rating of 7.07A for each SR FET requires a
low rDS(ON) to minimize conduction losses, which is difficult to
find in a 60V device. It was decided to use two devices in
parallel to simplify the thermal design. Two Fairchild FDS5670
18
devices are used in parallel for a total of four SR FETs. The
FDS5670 is rated at 60V and 10A (rDS(ON) = 14mΩ).
Oscillator Component Selection
The desired operating frequency of 235kHz for the converter
was established in the Design Criteria section. The
oscillator frequency operates at twice the frequency of the
converter because two clock cycles are required for a
complete converter period.
During each oscillator cycle the timing capacitor, CT, must be
charged and discharged. Determining the required
discharge time to achieve zero voltage switching (ZVS) is
the critical design goal in selecting the timing components.
The discharge time sets the deadtime between the two
outputs, and is the same as ZVS transition time. Once the
discharge time is determined, the remainder of the period
becomes the charge time.
The ZVS transition duration is determined by the
transformer’s primary leakage inductance, Llk, by the FET
Coss, by the transformer’s parasitic winding capacitance,
and by any other parasitic elements on the node. The
parameters may be determined by measurement,
calculation, estimate, or by some combination of these
methods.
π L lk • ( 2C oss + C xfrmr )
t zvs ≈ -------------------------------------------------------------------2
S
(EQ. 19)
Device output capacitance, Coss, is non-linear with applied
voltage. To find the equivalent discrete capacitance, Cfet, a
charge model is used. Using a known current source, the
time required to charge the MOSFET drain to the desired
operating voltage is determined and the equivalent
capacitance is calculated.
Ichg • t
Cfet = -------------------V
F
(EQ. 20)
Once the estimated transition time is determined, it must be
verified directly in the application. The transformer leakage
inductance was measured at 125nH and the combined
capacitance was estimated at 2000pF. Calculations indicate
a transition period of ~ 25ns. Verification of the performance
yielded a value of TD closer to 45ns.
The remainder of the switching half-period is the charge
time, TC, and can be found from
–9
1
1
= 2.08
T C = ---------------- – T D = ---------------------------------- – 45 • 10
3
2 • FS
2 • 235 • 10
μs
(EQ. 21)
where FS is the converter switching frequency.
Using Figure 4, the capacitor value appropriate to the
desired oscillator operating frequency of 470kHz can be
selected. A CT value of 100pF, 220pF, or 330pF is
FN9111.4
July 13, 2007
ISL6740, 1SL6741
appropriate for this frequency. A value of 220pF was
selected.
To obtain the proper value for RTD, Equation 3 is used.
Since there is a 10ns propagation delay in the oscillator
circuit, it must be included in the calculation. The value of
RTD selected is 8.06kΩ.
A similar procedure is used to determine the value of RTC using
Equation 2. The value of RTC selected is the series
combination of 17.4kΩ and 1.27kΩ. See section “Overcurrent
Component Selection” on page 19 for further explanation.
of an open loop converter. In particular, the low inductor
ripple current under steady state operation increases
significantly as the duty cycle decreases.
14
V (L1:1)
I (L1)
13
12
11
10
Output Filter Design
The output filter inductor and capacitor selection is simple
and straightforward. Under steady state operating conditions
the voltage across the inductor is very small due to the large
duty cycle. Voltage is applied across the inductor only during
the switch transition time, about 45ns in this application.
Ignoring the voltage drop across the SR FETs, the voltage
across the inductor during the ON time with VIN = 48V is
V IN • N S • ( 1 – D )
V L = V S – V OUT = ------------------------------------------------ ≈ 250
2N P
mV
(EQ. 22)
9
8
0.9950
0.9960
0.9970
0.9980
0.9990
1.000
TIME (ms)
FIGURE 8. STEADY STATE SECONDARY WINDING
VOLTAGE AND INDUCTOR CURRENT
15
V (L1:1)
I (L1)
where
VL is the inductor voltage
VS is the voltage across the secondary winding
10
VOUT is the output voltage
If we allow a current ramp, ΔI, of 5% of the rated output
current, the minimum inductance required is
V L • T ON
0.25 • 2.08
L ≥ ------------------------- = ----------------------------- = 1.04
ΔI
0.5
μH
(EQ. 23)
5
0.986
0.988
0.990
0.992
0.994
0.996
0.998
1.000
TIME (ms)
An inductor value of 1.4μH, rated for 18A was selected.
With a maximum input voltage of 53V, the maximum output
voltage is about 13V. The closest higher voltage rated
capacitor is 16V. Under steady state operating conditions the
ripple current in the capacitor is small, so it would seem
appropriate to have a low ripple current rated capacitor.
However, a high rated ripple current capacitor was selected
based on the nature of the intended load, multiple buck
regulators. To minimize the output impedance of the filter, a
Sanyo OSCON 16SH150M capacitor in parallel with a 22μF
ceramic capacitor were selected.
Overcurrent Component Selection
There are two circuit areas to consider when selecting the
components for overcurrent protection, current limit and
short circuit shutdown. The current limit threshold is fixed at
0.6V while the short circuit threshold is set to a fraction of the
duty cycle the designer wishes to define as a short circuit.
The current level that corresponds to the overcurrent
threshold must be chosen to allow for the dynamic behavior
19
FIGURE 9. SECONDARY WINDING VOLTAGE AND
INDUCTOR CURRENT DURING CURRENT LIMIT
OPERATION
Figures 8 and 9 show the behavior of the inductor ripple
under steady state and overcurrent conditions. In this
example, the peak current limit is set at 11A. The peak
current limit causes the duty cycle to decrease resulting in a
reduction of the average current through the inductor. The
implication is that the converter can not supply the same
output current in current limit that it can supply under steady
state conditions. The peak current limit setpoint must take
this behavior into consideration. A 3.32Ω current sense
resistor was selected for the rectified secondary of current
transformer T2, corresponding to a peak current limit
setpoint of 16.5A.
The short circuit protection involves setting a voltage
between 0 and 2V on the SCSET pin. The applied voltage
divided by 2 is the percent of maximum duty cycle that
corresponds to a short circuit when the peak current limit is
active. A divider from RTC to ground provides an easy
FN9111.4
July 13, 2007
ISL6740, 1SL6741
method to achieve this. The divider between RTC and GND
formed by R13 and R15 determines the percent of maximum
duty cycle that corresponds to a short circuit. The divider
ratio formed by R13 and R15 is
regulation is not required, such as those application that use
downstream DC/DC converters, this design approach is
viable.
Waveforms
R15
1.27k
----------------------------- = ------------------------------------ = 0.068
R13 + R15
1.27k + 17.4k
(EQ. 24)
Typical waveforms can be found in the following Figures.
Figure 13 shows the output voltage during start up.
Therefore, the duty cycle that corresponds to a short circuit
is 6.8% of D max (97.9%), or ~6.6%.
Performance
The major performance criteria for the converter are
efficiency, and to a lesser extent, load regulation. Efficiency,
load regulation and line regulation performance are
demonstrated in the following Figures.
EFFICIENCY (%)
100
95
90
85
80
75
FIGURE 13. OUTPUT SOFT-START
70
0
1
2
3
4
5
6
LOAD CURRENT (A)
7
9
8
Figure 14 shows the output voltage ripple and noise at a 5A
load.
FIGURE 10. EFFICIENCY vs LOAD VIN = 48Vt
OUTPUT VOLTAGE (V)
12.5
12.25
12.00
11.75
11.50
11.25
11
0
1
2
3
4
5
6
LOAD CURRENT (A)
7
9
8
FIGURE 11. LOAD REGULATION AT VIN = 48V
OUPUT VOLTAGE (V)
14.0
13.5
13.0
FIGURE 14. OUTPUT RIPPLE AND NOISE (20MHz BW)
12.5
12.0
11.5
11.0
45
46
47
48 49 50 51 52
INPUT VOLTAGE (V)
53
54
FIGURE 12. LINE REGULATION AT IOUT = 1A
As expected, the output voltage varies considerably with line
and load when compared to an equivalent converter with
closed loop feedback. However, for applications where tight
20
Figures 15 and 16 show the voltage waveforms at the
switching node shared by the upper FET source and the lower
FET drain. In particular, Figure 16 shows near ZVS operation
at 8A of load when the upper FET is turning off and the lower
FET turning on. There is insufficient energy stored in the
leakage inductance to allow complete ZVS operation.
However, since the energy stored in the node capacitance is
proportional to V2, a significant portion of the energy is still
recovered. Figure 17 shows the switching transition between
outputs, OUTA and OUTB during steady state operation. The
deadtime duration of 48.6ns is clearly shown.
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Component List
REFERENCE
DESIGNATOR VALUE
FIGURE 15. FET DRAIN-SOURCE VOLTAGE
DESCRIPTION
C1
1.0μF
Capacitor, 1812, X7R, 100V, 20%
TDK C4532X7R2A105M
C2, C3
3.3μF
Capacitor, 1812, X5R, 50V, 20%
TDK C4532X5R1H335M
C4, C6
1.0μF
Capacitor, 0805, X5R, 16V, 10%
TDK C2012X5R1C105K
C5, C15, C16
0.1μF
Capacitor, 0603, X7R, 50V, 10%
TDK C1608X7R1H104K
C7
Open
Capacitor, 0603, Open
C8
22μF
Capacitor, 1812, X5R, 16V, 20%
TDK C4532X5R1C226M
C9
150μF
Capacitor, Radial, Sanyo 16SH150M
C10, C11, C12, 1000pF Capacitor, 0603, X7R, 50V, 10%
C13, C14
TDK C1608X7R1H102K
C17
220pF
C18
0.047μF Capacitor, 0603, X7R, 16V, 10%
TDK C1608X7R1C473K
CR1, CR2
Diode, Schottky, BAT54S
CR3
Diode, Schottky, BAT54
Zener, 10V, Philips BZX84-C10
D1
FIGURE 16. FET D-S VOLTAGE NEAR-ZVS TRANSITION
FIGURE 17. OUTA TO OUTB TRANSITION
21
Capacitor, 0603, COG, 16V, 5%
TDK C1608COG1C221J
L1
190nH
Pulse, P2004T
L2
1.5μH
Pulse, PG0077.142
L3
Short
Jumper or Optional Discrete Leakage
Inductance
Q5
Transistor, ON MJD31C
QL, QH
FET, Fairchild FDS3672
QR1, QR2,
QR3, QR4
FET, Fairchild FDS5670
R1, R10
3.3
Resistor, 2512, 5%
R2
3.01k
Resistor, 2512, 1%
R3, R6
10.0
Resistor, 0603, 1%
R5
3.32
Resistor, 0603, 1%
R7
75.0k
Resistor, 0805, 1%
R8, R9
20.0
Resistor, 0805, 1%
R11
100
Resistor, 0603, 1%
R12
8.06k
Resistor, 0603, 1%
R13
17.4k
Resistor, 0603, 1%
R14
Open
Resistor, 0603, Open
R15
1.27k
Resistor, 0603, 1%
R17
97.6k
Resistor, 0603, 1%
R18
3.01k
Resistor, 0603, 1%
R19, RT1
10.0k
Resistor, 0603, 1%
T1
Midcom 31718
T2
Pulse P8205T
U1
Intersil HIP2101IB
U3
ISL6740IB
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Adding Line Only Regulation - Feed Forward
Output voltage variation caused by changes in the supply
voltage may be virtually removed through a technique known
as feed forward compensation. Using feed forward, the duty
cycle is directly controlled based on changes in the input
voltage only. No closed loop feedback system is required.
Voltage feed forward may be implemented as shown in
Figure 18..
R110
698
R109
3.48k
R111
806
VREF
1.5V
0.8V
+VIN
R106
100K
R103
49.9k
R100
69.8k
+
-
U100A
U100B
+
-
R105
100k
R102
100k
to VERROR
R104
100k
R101
2k
R107
100k
FIGURE 18. VOLTAGE FEED FORWARD CIRCUIT
The circuit provides feed forward compensation for a 2:1
input voltage range. Resistors R100 and R101 set the input
voltage divider to generate a 1V signal at the input voltage
that corresponds to maximum duty cycle (VIN minimum).
Resistors R109, R110, and R111 form a voltage divider from
VREF to create reference voltages for the amplifiers. The
first stage uses U100A, R102, R103, R104, and C100 to form
a unity gain inverting amplifier. Its output varies inversely
with input voltage and ranges from 1V to 2V. The bandwidth
of the circuit may be controlled by varying the value of C100.
The gain of the first amplifier stage is:
V A = – V D + 3.00
(EQ. 25)
V
It should be noted that the synchronous rectifiers (SRs),
being driven from the transformer secondary, are only gated
on during the ON time of the primary FETs. Conduction
continues through the body diodes during the OFF time
when operating in continuous inductor current mode. This
mode of operation usually results in significant conduction
and switching losses in the SR FETs. These losses may be
reduced considerably by either adding schottky diodes in
parallel to the SR FETs or by driving the SR FETs directly
with a control signal.
Adding Regulation - Closed Loop Feedback
R108
100k
C100
1nF
Other duty ranges are possible, but are still limited to a 2:1
ratio. The voltage applied to VERROR must be scaled to the
peak-to-peak voltage on CT, and offset by the valley voltage.
Since the peak-to-peak CT voltage is 2.00V nominal, the
voltage at the output of U100A must be divided by 2.0V to
obtain the desired duty cycle. For example, if an 80% duty
cycle was required at the minimum operating voltage, the
output of U100A must be 1.60V (80% of 2.00V). From
(Equation 25), the divider voltage must be set to 1.4V for the
input voltage that corresponds to the 80% duty cycle.
where:
VA = Output voltage of U100A
The second Typical Application schematic adds closed loop
feedback with isolation. The ISL6740EVAL2Z demonstration
platform implements this design and is available for
evaluation. The input voltage range was increased to 36V to
75V, which necessitates a few modifications to the open loop
design. The output inductor value was increased to 4.0μH,
schottky rectifier CR4 was added to minimize SR FET body
diode conduction, the turns ratio of the main transformer was
changed to 4:3, and the synchronous rectifier gate drives
were modified. The design process is essentially the same
as it was for the unregulated version, so only the feedback
control loop design will be discussed.
The major components of the feedback control loop are a
programmable shunt regulator and an opto-coupler. The
opto-coupler is used to transfer the error signal across the
isolation barrier. The opto-coupler offers a convenient means
to cross the isolation barrier, but it adds complexity to the
feedback control loop. It adds a pole at about 10kHz and a
significant amount of gain variation due the current transfer
ratio (CTR). The CTR of the opto-coupler varies with initial
tolerance, temperature, forward current, and age.
VD = The input divider voltage
The second stage uses U100B, R105, R106, R107, and R108
to form a summing amplifier which offsets the first stage
output by 0.8V (the value of CT valley voltage). The signal
applied to the VERROR input now matches the offset and
amplitude of the oscillator sawtooth so that the duty cycle
varies linearly from 100% to 50% of maximum with a 2:1
input voltage variation.
22
FN9111.4
July 13, 2007
ISL6740, 1SL6741
A block diagram of the feedback control loop follows in
Figure 19.
40
30
VOUT
ERROR AMPLIFIER
20
GAIN (dB)
POWER
STAGE
PWM
0
Z2
ISOLATION
10
+
-10
Z1
REF
-20
10
+
1•106
0
PHASE (DEGREES)
-
1•105
50
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. A Type 3 error
amplifier configuration was selected.
VERR
1•103
1•104
FREQUENCY (Hz)
FIGURE 21A. CONTROL-TO-OUTPUT GAIN
FIGURE 19. CONTROL LOOP BLOCK DIAGRAM
VOUT
100
-50
-100
-150
REF
-200
10
100
FIGURE 20. TYPE 3 ERROR AMPLIFIER
1•103
1•104
FREQUENCY (Hz)
1•105
1•106
FIGURE 21B. CONTROL-TO-OUTPUT PHASE
The control to output transfer function may be represented
as [1]
s
1 + -----V IN
NS
vo
ωz
------ = ---------------- • -------- • ------------------------------------------------vc
VS • 2 NP
s 2
s
1 + ----------------- + ⎛ -------⎞
⎝ω ⎠
( Q )ω
o
(EQ. 26)
o
where
1
f p2 = ----------------------------------------2π • R21 • C20
Ro
Q = ---------------ωo • L
1
ω o = -----------LC
1
ω z = ----------Rc C
The Type 3 compensation configuration has three poles and
two zeros. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the Typical Application Schematic for
the regulated output, the remaining poles and zeros for the
compensator are located at:
1
f p3 ≈ -------------------------------------2π • R4 • C22
or
1
f o = ------------------2π LC
or
1
f z = ------------------2πR c C
Ro = Output Load Resistance
L = Output Inductance
C = Output Capacitance
Rc = Output Capacitance ESR
VS = Sawtooth Ramp Amplitude
Gain and phase plots of (Equation 26) appear below using
L = 4.0μH, C = 150μF, Rc = 28mΩ, Ro = 1.2Ω, and VIN = 75V.
23
(EQ. 27)
C19 » C20
1
f z1 = ----------------------------------------2π • R21 • C19
1
f z2 ≈ ----------------------------------------2π • R23 • C22
(EQ. 28)
(EQ. 29)
R23 » R4
(EQ. 30)
From (Equation 26), it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitor and
inductor, and the output capacitance ESR. These variations
must be considered when compensating the control loop.
The worst case small signal operating point for a voltage
mode converter tends to be at maximum Vin, maximum load,
maximum COUT, and minimum ESR.
FN9111.4
July 13, 2007
ISL6740, 1SL6741
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the
bandwidth to about fSW/4, where fSW is the switching
frequency of the converter. However, due to the bandwidth
constraints of the opto-coupler and the LM431 shunt
regulator, the bandwidth was reduced to about 25kHz.
The first pole is placed at the origin by default (C20 is an
integrating capacitor). If the two zeroes are placed at the
same frequency, they should be placed at fLC/2, where fLC is
the resonant frequency of the output L-C filter. To reduce the
gain peaking at the L-C resonant frequency, the two zeroes
are often separated. When they are separated, the first zero
may be placed at fLC/5, and the second at just above fLC.
The second pole is placed at the lowest expected zero
cause by the output capacitor ESR. The third, and last pole
is placed at about 1.5 times the cross over frequency.
Some liberties where taken with the generally accepted
compensation procedure described above due to the
transfer characteristics of the opto coupler. The effects of the
opto-coupler tend to dominate over those of the LM431 so
the GBWP effects of the LM431 are not included here.
The following compensation components were selected
R23 = 9.53kΩ
R24 = 2.49kΩ
R4 = 499Ω
R21 = 4.22kΩ
C22 = 1nF
C20 = 82pF
C19 = 0.22μF
From (Equations 27, 28, 29 and 30), the poles and zeroes
are:
fz1 = 171Hz
fz2 = 16.7kHz
fp2 = 460kHz
fp3 = 319kHz
The calculated gain and phase plots of the error amplifier
appear below using an ideal op amp.
The gain and phase characteristics of the opto coupler are
shown in Figure 22A.
20
10
5
GAIN (dB)
10
GAIN (dB)
0
0
-5
-10
-10
10
-15
100
1•103
1•104
1•105
1•106
FREQUENCY (Hz)
-20
10
100
1•103
1•104
1•105
1•106
FIGURE 23A. IDEAL ERROR AMPLIFIER GAIN
FREQUENCY (Hz)
FIGURE 22A. OPTO COUPLER GAIN
90
90
PHASE (°)
PHASE (DEGREES)
45
45
0
0
-45
-45
-90
10
-90
10
100
1•103
1•104
1•105
1•106
FREQUENCY (Hz)
100
1•103
1•104
1•105
1•106
FIGURE 23B. IDEAL ERROR AMPLIFIER PHASE
FREQUENCY (Hz)
FIGURE 22B. OPTO COUPLER
24
FN9111.4
July 13, 2007
ISL6740, 1SL6741
The gain and phase plots combined with the opto coupler’s
transfer characteristics appear in Figures 24A and 24B:
30
Using the control-to-output transfer function combined with
the EA transfer function, the loop gain and phase may be
predicted. The predicted loop gain and phase margin of the
converter appear in Figures 25A and 25B:
50
40
30
20
10
GAIN (dB)
GAIN (dB)
20
0
10
0
-10
-20
-30
-10
10
100
1•103
1•104
1•105
-40
1•106
-50
100
FREQUENCY (Hz)
FIGURE 24A. EA PLUS OPTO COUPLER GAIN
1•103
1•104
FREQUENCY (Hz)
1•105
FIGURE 25A. PREDICTED LOOP GAIN
90
225
180
0
PHASE MARGIN (°)
PHASE (DEGREES)
45
-45
-90
-135
-180
10
100
1•103
1•104
FREQUENCY (Hz)
1•105
FIGURE 24B. EA PLUS OPTO COUPLER GAIN
1•106
135
90
45
0
-45
-90
-135
100
1•103
1•104
1•105
FREQUENCY (Hz)
FIGURE 25B. PREDICTED LOOP PHASE MARGIN
25
FN9111.4
July 13, 2007
ISL6740, 1SL6741
The actual loop gain and phase margin measured on the
ISL6740EVAL2Z demonstration board appear in Figures 26A
and 26B:
Performance
The major performance criteria for the converter are
efficiency and load regulation. These quantities are detailed
in Figures 27 and 28.
50
40
95
30
93
10
EFFICIENCY (%)
GAIN (dB)
20
0
-10
-20
-30
89
87
-40
-50
0.1k
91
1k
10k
100k
85
FREQUENCY (Hz)
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
FIGURE 26A. MEASURED LOOP GAIN
FIGURE 27. EFFICIENCY vs LOAD VIN = 48Vt
225
12.015
135
OUTPUT VOLTAGE (V)
PHASE MARGIN (°)
180
90
45
0
-45
-90
-135
0.1k
1k
10k
100k
FREQUENCY (Hz)
FIGURE 26B. MEASURE LOOP PHASE MARGIN
The only major discrepancies between the predicted
behavior and the measured results are the Q of the L-C filter
and the phase behavior above 60kHz. The actual Q appears
to be significantly less than predicted resulting in less gain
peaking and a less rapid phase shift near the resonant
frequency. This is most likely the result of neglecting other
losses in the converter’s output, such as the FET on
resistance, copper losses, and inductor resistance. The
phase discrepancy above 60kHz is not particularly relevant
to the loop performance since it occurs well above the cross
over frequency. The predicted behavior indicates a much
gentler drop off of phase than was observed in the measured
performance. The discrepancy was not investigated.
26
12.010
12.005
12.000
11.995
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
FIGURE 28. LOAD REGULATION AT VIN = 48V
The efficiency, although very good, could be further
improved using a controlled SR method instead of using a
self-driven method with an auxiliary schottky diode. The
schottky diode conducts when the main switching FETs are
off. Its forward voltage drop is considerably larger than that
of the SR FETs and causes a measurable reduction in
efficiency. The effect becomes more significant as the input
voltage is increased due to the reduction of duty cycle (and
consequent increase in the OFF time).
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Component List
REFERENCE
DESIGNATOR
Component List (Continued)
VALUE
DESCRIPTION
C1
1.0μF
Capacitor, 1812, X7R, 100V, 20%
TDK C4532X7R2A105M
C2, C3
3.3μF
Capacitor, 1812, X5R, 50V, 20%
TDK C4532X5R1H335M
C4, C6
1.0μF
Capacitor, 0805, X5R, 16V, 10%
TDK C2012X5R1C105K
REFERENCE
DESIGNATOR
VALUE
DESCRIPTION
R8, R9, R10
18
Resistor, 2512, 5%
R11
205
Resistor, 0603, 1%
R12
8.06k
Resistor, 0603, 1%
R13
18.2k
Resistor, 0603, 1%
R14
Open
Resistor, 0603, Open
R15
1.27k
Resistor, 0603, 1%
R16, R19
1.00k
Resistor, 0603, 1%
R17
97.6k
Resistor, 0603, 1%
R18
3.01k
Resistor, 0603, 1%
C5, C15, C16
0.1μF
Capacitor, 0603, X7R, 50V, 10%
TDK C1608X7R1H104K
C7
Open
Capacitor, 0603, Open
C8, C21
22μF
Capacitor, 1812, X5R, 16V, 20%
TDK C4532X5R1C226M
C9
150μF
Capacitor, Radial, Sanyo 16SH150M
R20
2.00k
Resistor, 0603, 1%
C10, C14, C22
1000pF
Capacitor, 0603, X7R, 50V, 10%
TDK C1608X7R1H102K
R21
4.22k
Resistor, 0603, 1%
R23
9.53k
Resistor, 0603, 1%
C11, C12
560 pF
Capacitor, 0603, X7R, 100V, 10%
TDK C1608X7R2A561K
R24
2.49k
Resistor, 0603, 1%
C13
220pF
Capacitor, 0603, X7R, 100V, 10%
TDK C1608X7R2A221K
R26, R27
5.11
Resistor, 0805, 1%
RT1
10.0k
Resistor, 0603, 1%
C17
220pF
C18
0.047μF Capacitor, 0603, X7R, 16V, 10%
TDK C1608X7R1C473K
C19
0.22μF
T1
Midcom 31660-LF1
T2
Pulse P8205NL
U1
Intersil HIP2101IBZ
Capacitor, 0603, X7R, 16V, 10%
TDK C1608X7R1C224K
U2
NEC PS2801-1-A
U3
ISL6740IBZ
Capacitor, 0603, X7R, 16V, 10%
TDK C1608X7R1C820K
U4
National LM431BIM3/NOPB
CR1, CR2
Diode, Schottky, BAT54S
References
CR3, CR5, CR6
Diode, Schottky, BAT54
CR4
Diode, Schottky, IR 12CWQ06FNPBF
D1
Zener, 10V, Philips BZX84-C10
D2
Zener, 6.8V, Philips BZX84-C6V8
C20
82pF
Capacitor, 0603, COG, 16V, 5%
TDK C1608COG1C221J
L1
190nH
Pulse, P2004NL
L2
4.0μH
BI Technologies, HM65-H4R0LF
L3
Short
0 Ohm Jumper
Q5
Transistor, ONSemi MJD31CG
QL, QH, QR1,
QR2, QR3, QR4
FET, Fairchild FDS3672
R1
3.3
Resistor, 2512, 5%
R2
3.01k
Resistor, 2512, 2%
R3
10.0
Resistor, 0603, 1%
R4, R25
499
Resistor, 0603, 1%
R5
2.20
Resistor, 0805, 1%
R6
200
Resistor, 0603, 1%
R7
75.0k
Resistor, 0805, 1%
27
[1] Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode
Power Supply Design Seminar, SEM-700, 1990.
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
2
INCHES
E1
GAUGE
PLANE
-B1
B M
L
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
D
0.193
0.201
4.90
5.10
3
E1
0.169
0.177
4.30
4.50
4
A1
3
A
D
-C-
e
α
e
A2
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
c
0.10(0.004)
C A M
B S
0.002
0.246
L
0.020
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
0.026 BSC
E
N
NOTES:
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
6.50
0.70
16
8o
0o
6
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
28
FN9111.4
July 13, 2007
ISL6740, 1SL6741
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
B M
INCHES
E
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
16
0°
16
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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29
FN9111.4
July 13, 2007