EL8176 ® Data Sheet April 3, 2009 Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp The EL8176 is a precision low power, operational amplifier. The device is optimized for single supply operation between 2.4V to 5.5V. The EL8176 draws minimal supply current while meeting excellent DC-accuracy noise and output drive specifications. Competing devices seriously degrade these parameters to achieve micropower supply current. The EL8176 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. The output swings to both rails. Ordering Information PART NUMBER EL8176FWZ-T7* (Note 1) PART MARKING Features • 55µA supply current • 100µV max offset voltage (8 Ld SO) • 2nA input bias current • 400kHz gain-bandwidth product • Single supply operation down to 2.4V • Rail-to-rail input and output • Output sources 31mA and sinks 26mA load current • Pb-free plus (RoHS compliant) Applications • Battery- or solar-powered systems PACKAGE (Pb-Free) BBVA FN7436.8 6 Ld SOT-23 PKG. DWG. # MDP0038 • 4mA to 20mA current loops • Handheld consumer products • Medical devices EL8176FWZ-T7A* BBVA (Note 1) 6 Ld SOT-23 MDP0038 EL8176FSZ (Note 1) 8176FSZ 8 Ld SO MDP0027 EL8176FSZ-T7* (Note 1) 8176FSZ 8 Ld SO MDP0027 EL8176FIZ-T7* (Note 2) 176Z 6 Ld WLCSP (1.5mmx1.0mm) W3x2.6C • Thermocouple amplifiers • Photodiode pre amps • pH probe amplifiers *Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL8176 Pinouts OUT 1 V- 2 IN+ 3 + - EL8176 (6 LD WLCSP) TOP VIEW EL8176 (8 LD SO) TOP VIEW EL8176 (6 LD SOT-23) TOP VIEW 6 V+ NC 1 5 EN IN- 2 4 IN- IN+ 3 V- 4 1 2 A DNC* OUT B V+ V- C IN- IN+ 8 EN + 7 V+ 6 OUT 5 NC *DO NOT CONNECT 2 FN7436.8 April 3, 2009 EL8176 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . 5.75V, 1V/µs Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-, and EN. . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance (Typical, Note 3) θJA (°C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 6 Ld WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . 130 8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Ambient Operating Temperature Range . . . . . . . . -40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. DESCRIPTION CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNIT -100 ±25 100 µV 220 µV 350 µV 350 µV 500 µV DC SPECIFICATIONS VOS Input Offset Voltage 8 Ld SO -220 6 Ld SOT-23 -350 ±80 -350 WLCSP -500 -75 ΔV OS -----------------ΔTime Long Term Input Offset Voltage Stability 2.4 µV/Mo ΔV OS ---------------ΔT Input Offset Drift vs Temperature 0.7 µV/°C IOS Input Offset Current -1 ±0.4 1 nA 4 nA 2 nA -5 5 nA 5 V -4 IB Input Bias Current -2 CMIR Input Voltage Range Guaranteed by CMRR test 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 90 ±0.5 110 90 PSRR Power Supply Rejection Ratio VS = 2.4V to 5.5V 90 dB 110 90 AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ 200 3 dB dB 500 200 VO = 0.5V to 4.5V, RL = 1kΩ dB V/mV V/mV 25 V/mV FN7436.8 April 3, 2009 EL8176 Electrical Specifications PARAMETER VOUT V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) DESCRIPTION Maximum Output Voltage Swing SOT-23/SO-8 CONDITIONS MIN (Note 4) VOL; Output low, RL = 100kΩ VOL; Output low, RL = 1kΩ VOH; Output high, RL = 100kΩ TYP MAX (Note 4) UNIT 3 8 mV 10 mV 200 mV 300 mV 130 4.994 4.997 V 4.992 VOH; Output high, RL = 1kΩ 4.750 V 4.867 V 4.7 Maximum Output Voltage Swing WLCSP VOL; Output low, RL = 100kΩ V 3 VOL; Output low, RL = 1kΩ 130 8 mV 10 mV 200 mV 300 mV VOH; Output high, RL = 100kΩ 4.991 4.997 V VOH; Output high, RL = 1kΩ 4.750 4.867 V 4.7 IS,ON Supply Current, Enabled VEN = 5V, SOT-23/SO-8 35 V 55 30 VEN = 5V, WLCSP 60 85 55 IS,OFF IO+ Supply Current, Disabled Short Circuit Output Sourcing Current VEN = 0V, SOT-23/SO-8 only RL = 10Ω 3 18 75 µA 90 µA 110 µA 120 µA 10 µA 10 µA 31 mA 18 IO- Short Circuit Output Sinking Current RL = 10Ω 17 mA 26 mA 15 VS Supply Voltage Guaranteed by PSRR test 2.4 5.5 V 2.4 5.5 V VINH Enable Pin High Level SOT-23 and SO packages only VINL Enable Pin Low Level SOT-23 and SO packages only IENH Enable Pin Input Current VEN = 5V, SOT-23 and SO packages only 0.25 VEN = 0V, SOT-23 and SO packages only -0.5 IENL Enable Pin Input Current mA 2 V 0.7 0 -1 0.8 V 2.0 µA 2.5 µA +0.5 µA +1 µA AC SPECIFICATIONS GBW Gain Bandwidth Product AV = 100, RF = 100kΩ, RL = 10kΩ, RG = 1kΩ to VCM Unity Gain Bandwidth -3dB Bandwidth AV = 1, RF = 0Ω, RL = 100kΩ to VCM, VOUT = 10mVP-P 4 400 kHz 1 MHz FN7436.8 April 3, 2009 EL8176 Electrical Specifications PARAMETER eN V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) DESCRIPTION MIN (Note 4) CONDITIONS TYP MAX (Note 4) UNIT Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz, RL = 10kΩ to VCM 1.5 µVP-P Input Noise Voltage Density fO = 1kHz 28 nV/√Hz iN Input Noise Current Density fO = 1kHz 0.16 pA/√Hz ISO Off-State Input to Output Isolation VEN = 5V, fO = 1kHz, AV = +1, VIN = 1VP-P SOT-23 and SO packages only -73 dB CMRR Input Common Mode Rejection Ratio fO = 120Hz; VCM = 1VP-P, -70 dB PSRR+ Power Supply Rejection Ratio (V+) fO = 120Hz; V+, V- = ±2.5V, VSOURCE = 1VP-P -90 dB PSRR- Power Supply Rejection Ratio (V-) fO = 120Hz; V+, V- = ±2.5V, VSOURCE = 1VP-P -70 dB TRANSIENT RESPONSE ±0.065 ±0.13 ±0.3 V/µs SR Slew Rate tr, tf, Large Signal Rise Time, 10% to 90%, VOUT AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 10kΩ to VCM 18 µs Fall Time, 90% to 10%, VOUT AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 10kΩ to VCM 19 µs Rise Time, 10% to 90%, VOUT AV = +2, VOUT = 10mVP-P, Rg = Rf = RL = 10kΩ to VCM 2.4 µs Fall Time, 90% to 10%, VOUT AV = +2, VOUT = 10mVP-P, Rg = Rf = RL = 10kΩ to VCM 2.4 µs Enable to Output Turn-on Delay Time, 10% VEN = 5V to 0V, AV = +2, EN to 10% VOUT (SOT-23, SO packages) Rg = Rf = RL = 10kΩ to VCM 4 µs Enable to Output Turn-off Delay Time, 10% VEN = 0V to 5V, AV = +2, EN to 10% VOUT (SOT-23, SO packages) Rg = Rf = RL = 10kΩ to VCM 0.1 µs tr, tf, Small Signal tEN NOTE: 4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Typical Performance Curves 100 200 80 150 PHASE GAIN 80 40 40 0 0 -40 -40 -80 PHASE (°) GAIN (dB) 0 PHASE (°) GAIN (dB) 50 40 -50 0 -20 10 80 100 60 20 120 -100 100 1k 10k 100k -150 1M FREQUENCY (Hz) FIGURE 1. AVOL vs FREQUENCY @ 1kΩ LOAD 5 -80 1 10 100 1k 10k 100k 1M -120 10M FREQUENCY (Hz) FIGURE 2. AVOL vs FREQUENCY @ 100kΩ LOAD FN7436.8 April 3, 2009 EL8176 (Continued) 1 3 0 2 -1 1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) Typical Performance Curves -2 Rf = Rg = 10k -3 -4 V+ = 5V RL = 10k CL = 8.3pF AV = +2 VOUT = 10mVP-P -5 -6 -7 -8 -9 100 1k Rf = Rg = 100k Rf = Rg = 1k 10k FREQUENCY (Hz) 100k 1M VOUT = 10mV -2 VOUT = 50mV -3 -5 V+ = 5V RL = 1k -6 CL = 8.3pF -7 A = +1 V -8 10 100 2 1 1 NORMALIZED GAIN (dB) 3 2 0 -1 VOUT = 10mV -3 VOUT = 50mV -4 -5 -6 -7 V+ = 5V RL = 10k CL = 8.3pF AV = +1 -8 10 100 VOUT = 100mV VOUT = 1V 10k 100k 10k 100k 1M 10M 0 -2 VOUT = 10mV -3 VOUT = 50mV -4 -5 -6 1M V+ = 5V RL = 100k CL = 8.3pF AV = +1 -8 10 10M 100 VOUT = 100mV VOUT = 1V 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 6. GAIN vs FREQUENCY vs VOUT, RL = 100k FIGURE 5. GAIN vs FREQUENCY vs VOUT, RL = 10k 70 3 2 RL = 10k 60 AV = 1001 AV = 1001, Rg = 1k, Rf = 1M 1 0 50 -1 40 RL = 100k -2 -3 -4 -5 -6 -7 -8 10 GAIN (dB) NORMALIZED GAIN (dB) 1k -1 -7 1k VOUT = 1V FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 1k 3 -2 VOUT = 100mV -4 FREQUENCY (Hz) FIGURE 3. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg NORMALIZED GAIN (dB) 0 -1 RL = 1k V+ = 5V CL = 8.3pF AV = +1 VOUT = 10mVP-P 100 20 AV = 10 0 10k 100k 1M FREQUENCY (Hz) FIGURE 7. GAIN vs FREQUENCY vs RL 6 10M V+ = 5V CL = 8.3pF RL = 10k VOUT = 10mVP-P 30 10 1k AV = 101, Rg = 1k, Rf = 100k AV = 101 -10 10 AV = 10, Rg = 1k, Rf = 9.09k AV = 1 AV = 1, Rg = INF, Rf = 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FN7436.8 April 3, 2009 EL8176 Typical Performance Curves (Continued) 2 45 V+ = 2.5V 1 40 0 GAIN (dB) GAIN (dB) 30 -2 V+ = 5V -3 -4 -5 -6 -7 -8 RL = 10k CL = 8.3pF AV = +1 VOUT = 10mVP-P -9 1k 10k 25 V+ = 5V 20 RL = 10k CL = 8.3pF AV = 100 VOUT = 10mVP-P RF = 221kΩ RG = 2.23kΩ 15 V+ = 2V 10 5 100k FREQUENCY (Hz) 1M 0 100 10M FIGURE 9. GAIN vs FREQUENCY vs SUPPLY VOLTAGE V+ = 2V 1k 10k FREQUENCY (Hz) CL = 64.3pF CL = 47.3pF CL = 35.3pF 0 -20 CL = 26.3pF CL = 8.3pF -40 V+ = 5V RL = OPEN CL = 8.3pF AV = +1 VCM = 1VP-P -60 -80 -100 -120 100k 1M 10M 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 12. CMRR vs FREQUENCY; V+, V- = ±2.5V FIGURE 11. GAIN vs FREQUENCY vs CL 0 -10 V+ = 5V RL = OPEN CL = 8.3pF AV = +1 VCM = 1VP-P OFF ISOLATION (dB) PSRR (dB ) 1M 20 6 5 4 3 2 1 0 -1 -2 -3 -4 V = 5V + -5 R = 10k L -6 AV = +1 -7 VOUT = 10mVP-P -8 -9 1k 10k 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 1 100k FIGURE 10. GAIN vs FREQUENCY vs SUPPLY VOLTAGE CMRR (dB) NORMALIZED GAIN (dB) V+ = 2.5V 35 -1 PSRR- PSRR+ -20 -30 -40 V+ = 5V RL = OPEN CL = 8.3pF AV = +1 VIN = 1VP-P -50 -60 -70 -80 -90 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 13. PSRR vs FREQUENCY, V+, V- = ±2.5V 7 1M -100 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 14. OFF ISOLATION vs FREQUENCY; V+, V- = ±2.5V FN7436.8 April 3, 2009 EL8176 Typical Performance Curves (Continued) 10 INPUT CURRENT NOISE (pA√Hz) INPUT VOLTAGE NOISE (nV√Hz) 1000 V+ = 5V RL = OPEN CL = 8.3pF AV = +1 100 10 0.1 1 10 100 1k FREQUENCY (Hz) 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 10k FIGURE 16. INPUT CURRENT NOISE DENSITY vs FREQUENCY 2.5 2.0 V+ = 5V 1.5 RL = OPEN CL = 8.3pF 1.0 Rg = 10, Rf = 10k AV = 1000 0.5 2.0 1.5 LARGE SIGNAL (V) INPUT NOISE (µV) 1 10k FIGURE 15. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY 0 -0.5 -1.0 1.0 0.5 V+, V- = ±2.5V RL = 10k CL = 8.3pF Rg = 10k Rf = 30k AV = 4 VOUT = 4VP-P 0 -0.5 -1.0 -1.5 -1.5 -2.0 0 V+ = 5V RL = OPEN CL = 8.3pF AV = +1 -2.0 1 2 3 4 5 6 TIME (s) 7 8 9 -2.5 10 0 FIGURE 17. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz 50 100 150 200 250 TIME (µs) 300 350 400 FIGURE 18. LARGE SIGNAL STEP RESPONSE 12 3.0 3.0 VENABLE 2.5 2.5 VOUT 2.0 6 V+, V- = ±2.5V RL = 10k CL = 8.3pF Rg = Rf = 10k AV = 2 VOUT = 10mVP-P 4 2 0 2.0 V+, V- = ±2.5V Rg = Rf = RL = 10k CL = 8.3pF AV = +2 VOUT = 2VP-P 1.5 1.0 0.5 1.5 1.0 0.5 0 -2 0 -0.5 0 50 100 150 200 250 TIME (µs) 300 350 FIGURE 19. SMALL SIGNAL STEP RESPONSE 8 400 OUTPUT (V) 8 V-ENABLE (V) SMALL SIGNAL (mV) 10 0 20 40 60 80 100 120 TIME (µs) 140 160 -0.5 200 180 FIGURE 20. ENABLE TO OUTPUT RESPONSE FN7436.8 April 3, 2009 EL8176 Typical Performance Curves (Continued) 100 2.0 80 V+, V- = ±2.5V Rg = 100 Rf = 10k RL = INF CL = 8.3pF AV = +11 VOUT = 2VP-P 1.5 60 1.0 20 IBIAS (µA) VIO (µV) 40 V+, V- = ±2.5V Rg = 100 Rf = 10k RL = INF CL = 8.3pF AV = +11 VOUT = 2VP-P 0 -20 -40 -60 -80 -100 -0.5 0 0 -0.5 -1.0 -1.5 -2.0 -0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCM (V) FIGURE 21. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCM (V) FIGURE 22. INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE 60 200 VCM = VDD/2 AV = -1 150 100 50 VDD = 5V 0 VDD = 2.5V -50 50 SUPPLY CURRENT (µA) INPUT OFFSET VOLTAGE (µV) 0.5 -100 40 30 20 10 -150 0 2.0 -200 0 1 2 3 4 5 2.5 3.0 FIGURE 23. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE 4.5 100 n = 12 5.0 5.5 WLCSP n = 12 SO, SOT-23 PACKAGE 95 70 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 4.0 FIGURE 24. SUPPLY CURRENT vs SUPPLY VOLTAGE 75 65 MAX 60 MIN 55 MEDIAN 50 45 -40 3.5 SUPPLY VOLTAGE (V) OUTPUT VOLTAGE (V) MAX 90 MEDIAN 85 80 75 MIN 70 65 -20 0 20 40 60 80 100 TEMPERATURE (°C) FIGURE 25. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V ENABLED. RL = INF 9 120 60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 26. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V ENABLED. RL = INF FN7436.8 April 3, 2009 EL8176 Typical Performance Curves 2.5 MAX n = 12 6 2.0 n = 12 5 4 CURRENT (nA) DISABLED SUPPLY CURRENT (µA) 7 (Continued) MEDIAN 3 2 1.5 MAX 1.0 0.5 MEDIAN MIN 0 1 MIN 0 -40 -20 0 20 40 60 80 100 -0.5 -40 120 -20 0 3.0 2.0 CURRENT (nA) CURRENT (nA) 100 120 2.0 MAX 1.5 1.0 MEDIAN 0.5 1.5 MAX 1.0 MEDIAN 0.5 0 0 MIN -20 0 20 MIN 40 60 80 100 -0.5 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 29. IBIAS (+) vs TEMPERATURE VS = ±1.2V FIGURE 30. IBIAS (-) vs TEMPERATURE VS = ±2.5V 3.0 2.5 n = 12 n = 12 2.0 2.0 CURRENT (nA) CURRENT (nA) 80 n = 12 2.5 MAX 1.5 1.0 MEDIAN 0.5 0 -0.5 -40 60 2.5 n = 12 2.5 40 FIGURE 28. IBIAS (+) vs TEMPERATURE VS = ±2.5V FIGURE 27. DISABLED SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V RL= INF -0.5 -40 20 TEMPERATURE (°C) TEMPERATURE (°C) 0 20 MAX 1.0 0.5 MEDIAN 0 MIN -20 1.5 MIN 40 60 80 100 120 TEMPERATURE (°C) FIGURE 31. IBIAS (-) vs TEMPERATURE VS = ±1.2V 10 -0.5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 32. INPUT OFFSET CURRENT vs TEMPERATURE VS = ±2.5V FN7436.8 April 3, 2009 EL8176 Typical Performance Curves (Continued) 2.5 200 2.0 150 1.5 MAX 1.0 MAX 100 VOS (µV) CURRENT (nA) SO PACKAGE n = 12 n = 12 MEDIAN 50 0.5 MEDIAN MIN 0 0 MIN -0.5 -40 -20 0 20 40 60 80 100 -50 -40 120 -20 0 TEMPERATURE (°C) FIGURE 33. INPUT OFFSET CURRENT vs TEMPERATURE VS = ±1.2V 200 n = 12 80 100 120 SOT-23 PACKAGE 300 MAX 200 MAX VOS (µV) VOS (µV) 60 400 150 100 40 FIGURE 34. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±2.5V SO PACKAGE n = 12 20 TEMPERATURE (°C) MEDIAN 50 100 MEDIAN 0 0 -100 MIN MIN -50 -40 -20 0 20 40 60 80 100 120 -200 -40 -20 0 TEMPERATURE (°C) FIGURE 35. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±1.2V 200 n = 12 80 100 120 WLCSP n = 12 100 MAX MAX 50 50 0 VOS (µV) VOS (µV) 60 150 150 MEDIAN -50 0 MEDIAN 50 -100 MIN MIN -150 -200 -40 40 FIGURE 36. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±2.5V SOT-23 PACKAGE 100 20 TEMPERATURE (°C) -20 0 20 40 60 100 80 100 120 TEMPERATURE (°C) FIGURE 37. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±1.2V 11 150 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 38. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±2.5V FN7436.8 April 3, 2009 EL8176 Typical Performance Curves (Continued) 150 125 n = 12 WLCSP 100 n = 12 120 MAX CMRR (dB) VOS (µV) 50 MEDIAN 0 -50 MAX 115 110 105 MEDIAN MIN -100 -150 -40 100 -20 0 20 40 60 80 100 95 -40 120 MIN -20 0 20 TEMPERATURE (°C) FIGURE 39. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±1.2V 4.91 n = 12 135 4.90 130 4.89 MAX 125 4.88 120 115 MEDIAN 100 MAX MEDIAN 4.87 4.86 MIN 4.83 MIN -20 0 20 40 60 80 100 4.82 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 41. PSRR vs TEMPERATURE VS = ±1.2V TO ±2.5V FIGURE 42. POSITIVE VOUT vs TEMPERATURE RL = 1k VS = ±2.5V 4.9982 n = 12 n = 12 4.9980 220 MAX 4.9978 200 4.9976 MEDIAN MAX 180 VOUT (V) VOUT (mV) 120 n = 12 TEMPERATURE (°C) 160 140 MIN 4.9974 MEDIAN 4.9972 4.9970 MIN 4.9968 120 4.9966 100 80 -40 100 4.84 105 240 80 4.85 110 95 -40 60 FIGURE 40. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V VOUT (V) PSRR (dB) 140 40 TEMPERATURE (°C) 4.9964 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 43. NEGATIVE VOUT vs TEMPERATURE RL = 1k VS = ±2.5V 12 4.9962 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 44. POSITIVE VOUT vs TEMPERATURE RL = 100k VS = ±2.5V FN7436.8 April 3, 2009 EL8176 Typical Performance Curves (Continued) 0.23 5.5 n = 12 n = 12 0.21 SLEW RATE (V/µs) 5.0 VOUT (mV) 4.5 MAX 4.0 3.5 MEDIAN MIN 0.19 MAX MEDIAN 0.17 0.15 0.13 MIN 3.0 0.11 2.5 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 0.09 -40 120 20 40 60 80 100 120 FIGURE 46. +SLEW RATE vs TEMPERATURE VS = ±2.5V INPUT = ±0.75V, AV = 2 900 0.17 n = 12 n = 12 800 MAX MAX 700 0.15 0.14 AVOL (V/mV) CURRENT (pA) 0 TEMPERATURE (°C) FIGURE 45. NEGATIVE VOUT vs TEMPERATURE RL = 100k VS = ±2.5V 0.16 -20 MEDIAN 0.13 MIN 600 500 MEDIAN 400 MIN 300 0.12 200 0.11 0.10 -40 100 -20 0 20 40 60 80 100 0 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 48. AVOL, RL = 100k, VS ±2.5V, VO = ±2V FIGURE 47. -SLEW RATE vs TEMPERATURE VS = ±2.5V INPUT = ±0.75V, AV = 2 Pin Descriptions SO PIN NUMBER SOT-23 PIN 6 Ld WLCSP NUMBER PIN NUMBER 1, 5 PIN NAME EQUIVALENT CIRCUIT NC DESCRIPTION No internal connection 2 4 C1 IN- Circuit 1 Amplifier’s inverting input 3 3 C2 IN+ Circuit 1 Amplifier’s non-inverting input 4 2 B2 V- Circuit 4 Negative power supply A1 DNC Do not connect. Pin must be left floating. 6 1 A2 OUT Circuit 3 Amplifier’s output 7 6 B1 V+ Circuit 4 Positive power supply 8 5 EN Circuit 2 Amplifier’s enable pin with internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state. V+ V+ V+ CAPACITIVELY COUPLED ESD CLAMP OUT EN IN- V+ IN+ V- V- V- VCIRCUIT 1 CIRCUIT 2 13 CIRCUIT 3 CIRCUIT 4 FN7436.8 April 3, 2009 EL8176 Applications Information Introduction The EL8176 is a rail-to-rail input and output micro-power precision single supply operational amplifier with an enable feature. The device achieves rail-to-rail input and output operation and eliminates the concerns introduced by a conventional rail-to-rail I/O operational amplifier as discussed below. Rail-to-Rail Input The input common-mode voltage range of the EL8176 goes from negative supply to positive supply without introducing offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The EL8176 achieves input rail-to-rail without sacrificing important precision specifications and without degrading distortion performance. The EL8176's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range for the EL8176 gives us an undistorted behavior from typically 10mV above the negative rail all the way up to the positive rail. are tied together in parallel and a channel can be selected by pulling the EN pin to 0.8V or lower.The EN pin has an internal pull-down. If left open or floating, the EN pin will internally be pulled low, enabling the part by default. Proper Layout Maximizes Performance To achieve the maximum performance of the high input impedance and low offset voltage of the EL8176, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 49 shows how the guard ring should be configured and Figure 50 shows the top view of how a surface mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. V+ HIGH IMPEDANCE INPUT IN 3 6 EL8176 1 4 2 5 Input Bias Current Compensation The input bias currents as low as 500pA are achieved while maintaining an excellent bandwidth for a micro-power operational amplifier. Inside the EL8176 is an input bias canceling circuit. The input stage transistors are still biased with an adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current. The input bias current compensation/cancellation is stable from -40°C to +125°C and operates from typically 10mV to the positive supply rail. FIGURE 49. Rail-to-Rail Output A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The EL8176 with a 100kΩ load will swing to within 3mV of the supply rails. FIGURE 50. Enable/Disable Feature The EL8176, in the SOT-23 and SO packages, offers an EN pin. The active low EN pin disables the device when pulled up to at least 2.0V. When disabled, the output is in a high impedance state and the part consumes typically 3µA. When disabled, the high impedance output allows multiple parts to be MUXed together. When configured as a MUX, the outputs 14 FN7436.8 April 3, 2009 EL8176 Typical Applications R4 100kΩ R3 10kΩ R2 K TYPE THERMOCOUPLE 10kΩ V+ + EL8176 V- 410µV/°C + 5V R1 100kΩ FIGURE 51. THERMOCOUPLE AMPLIFIER Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. The EL8176 is used to convert the differential thermocouple voltage into single-ended signal with 10X gain. The EL8176's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5V supply. 15 FN7436.8 April 3, 2009 EL8176 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 16 FN7436.8 April 3, 2009 EL8176 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X TOLERANCE Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 17 0.25 0° +3° -0° FN7436.8 April 3, 2009 EL8176 Wafer Level Chip Scale Package (WLCSP) W3x2.6C 3x2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE E D PIN 1 ID TOP VIEW A2 A A1 SYMBOL MILLIMETERS A 0.51 Min, 0.55 Max A1 0.225 ±0.015 A2 0.305 ±0.013 b Φ0.323 ±0.025 D 0.955 ±0.020 D1 0.50 BASIC E 1.455 ±0.020 E1 1.00 BASIC e 0.50 BASIC SD 0.25 BASIC SE 0.00 BASIC Rev. 3 03/08 b NOTES: SIDE VIEW 1. All dimensions are in millimeters. E1 e SE D1 2 SD 1 b C B A BOTTOM VIEW All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7436.8 April 3, 2009