INTERSIL ISL28136FHZ-T7

ISL28136
Data Sheet
April 5, 2011
5MHz, Single Precision Rail-to-Rail
Input-Output (RRIO) Op Amp
Features
The ISL28136 is a low-power single operational amplifier
optimized for single supply operation from 2.4V to 5.5V,
allowing operation from one lithium cell or two Ni-Cd batteries.
This device features a gain-bandwidth product of 5MHz and is
unity-gain stable with a -3dB bandwidth of 13MHz.
This device features an Input Range Enhancement Circuit
(IREC), which enables it to maintain CMRR performance for
input voltages greater than the positive supply. The input
signal is capable of swinging 0.25V above the positive
supply and to the negative supply with only a slight
degradation of the CMRR performance. The output
operation is rail-to-rail.
• 5MHz Gain bandwidth product @ AV = 100
• 13MHz -3dB unity gain bandwidth
• 900µA typical supply current
• 150µV maximum offset voltage (8 Ld SOIC)
• 5nA typical input bias current
• Down to 2.4V single supply voltage range
• Rail-to-rail input and output
• Enable pin
• -40°C to +125°C operation
• Pb-free (RoHS compliant)
The part typically draws less than 1mA supply current while
meeting excellent DC accuracy, AC performance, noise and
output drive specifications. Operation is guaranteed over
-40°C to +125°C temperature range.
Applications
Ordering Information
• Medical devices
PART
NUMBER
(Notes 2, 3)
FN6153.5
• Low-end audio
• 4mA to 20mA current loops
• Sensor amplifiers
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28136FHZ-T7
(Note 1)
GABP
6 Ld SOT-23
P6.064A
ISL28136FHZ-T7A
(Note 1)
GABP
6 Ld SOT-23
P6.064A
ISL28136FBZ
28136 FBZ
8 Ld SOIC
M8.15E
ISL28136FBZ-T7
(Note 1)
28136 FBZ
8 Ld SOIC
M8.15E
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet
or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
• ADC buffers
• DAC output amplifiers
Pinouts
ISL28136
(8 LD SOIC)
TOP VIEW
ISL28136
(6 LD SOT-23)
TOP VIEW
OUT 1
V- 2
IN+ 3
+ -
6 V+
NC 1
5 EN
IN- 2
4 IN-
IN+ 3
V- 4
8 EN
+
7 V+
6 OUT
5 NC
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL28136. For more information on MSL
please see techbrief TB363.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright © Intersil Americas Inc. 2007-2009, 2011. All Rights Reserved.
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28136
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance
θJA (°C/W)
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
230
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
110
Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
DESCRIPTION
CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNIT
DC SPECIFICATIONS
VOS
Input Offset Voltage
8 Ld SOIC
-150
-270
±10
150
270
µV
6 Ld SOT-23
-400
-450
±10
400
450
µV
ΔV OS
--------------ΔT
Input Offset Voltage vs Temperature
IOS
Input Offset Current
IB
Input Bias Current
VCM
Common-Mode Voltage Range
Guaranteed by CMRR
0
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 5V
90
85
114
dB
PSRR
Power Supply Rejection Ratio
V+ = 2.4V to 5.5V
90
85
99
dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4V, RL = 100kΩ to VCM
600
500
1770
V/mV
140
V/mV
0.4
-10
-15
0
10
15
nA
TA = -40°C to +85°C
-35
-40
5
35
40
nA
TA = -40°C to +85°C
5
V
VO = 0.5V to 4V, RL = 1kΩ to VCM
VOUT
Maximum Output Voltage Swing
IS,ON
Supply Current, Enabled
IS,OFF
Supply Current, Disabled
IO+
Short-Circuit Output Source Current
2
µV/°C
Output low, RL = 100kΩ to VCM
3
6
10
mV
Output low, RL = 1kΩ to VCM
70
90
110
mV
Output high, RL = 100kΩ to VCM
4.99
4.98
4.994
V
Output high, RL = 1kΩ to VCM
4.92
4.89
4.94
V
Per Amp
0.8
0.9
1.1
1.4
mA
10
14
16
µA
RL = 10Ω to VCM
48
45
56
mA
FN6153.5
April 5, 2011
ISL28136
Electrical Specifications
PARAMETER
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
DESCRIPTION
CONDITIONS
MIN
(Note 4)
IO-
Short-Circuit Output Sink Current
RL = 10Ω to VCM
50
45
VSUPPLY
Supply Operating Range
V+ to V-
2.4
VENH
EN Pin High Level
VENL
EN Pin Low Level
IENH
EN Pin Input High Current
VEN = V+
IENL
EN Pin Input Low Current
TYP
MAX
(Note 4)
55
UNIT
mA
5.5
2
V
V
0.8
V
1
1.5
1.6
µA
VEN = V-
16
25
30
nA
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
AV = 100, RF = 100kΩ, RG = 1kΩ to VCM
5
MHz
Unity Gain
Bandwidth
-3dB Bandwidth
AV = 1, RF = 0Ω, RL = 10kΩ to VCM,
VOUT = 10mVP-P
13
MHz
eN
Input Noise Voltage Peak-to-Peak
f = 0.1Hz to 10Hz, RL = 10kΩ to VCM
0.4
µVP-P
Input Noise Voltage Density
fO = 1kHz, RL = 10kΩ to VCM
15
nV/√Hz
iN
Input Noise Current Density
fO = 10kHz, RL = 10kΩ to VCM
0.35
pA/√Hz
CMRR
Input Common Mode Rejection Ratio
fO = to 120Hz; VCM = 1VP-P, RL = 1kΩ to
VCM
-90
dB
PSRR+
to 120Hz
Power Supply Rejection Ratio (V+)
V+, V- = ±1.2V and ±2.5V,
VSOURCE = 1VP-P, RL = 1kΩ to VCM
-88
dB
PSRRto 120Hz
Power Supply Rejection Ratio (V-)
V+, V- = ±1.2V and ±2.5V
VSOURCE = 1VP-P, RL = 1kΩ to VCM
-105
dB
TRANSIENT RESPONSE
SR
Slew Rate
VOUT = ±1.5V; Rf = 50kΩ, RG = 50kΩ to
VCM
±1.9
V/µs
tr, tf, Large
Signal
Rise Time, 10% to 90%, VOUT
AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 1kΩ
to VCM
0.6
µs
Fall Time, 90% to 10%, VOUT
AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 1kΩ
to VCM
0.5
µs
Rise Time, 10% to 90%, VOUT
AV = +2, VOUT = 10mVP-P,
Rg = Rf = RL = 1kΩ to VCM
65
ns
Fall Time, 90% to 10%, VOUT
AV = +2, VOUT = 10mVP-P,
Rg = Rf = RL = 1kΩ to VCM
62
ns
Enable to Output Turn-on Delay Time, 10% VEN = 5V to 0V, AV = +2,
EN to 10% VOUT
Rg = Rf = RL = 1kΩ to VCM
5
µs
Enable to Output Turn-off Delay Time, 10% VEN = 0V to 5V, AV = +2,
Rg = Rf = RL = 1kΩ to VCM
EN to 10% VOUT
0.3
µs
tr, tf, Small
Signal
tEN
NOTE:
4. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
3
FN6153.5
April 5, 2011
ISL28136
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
1
15
Rf = Rg = 100k
5
Rf = Rg = 10k
0
V+ = 5V
RL = 1k
CL = 16.3pF
AV = +2
VOUT = 10mVP-P
-5
-10
-15
100
1k
Rf = Rg = 1k
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
10
10k
100k
1M
FREQUENCY (Hz)
10M
VOUT = 50mV
VOUT = 10mV
-4
-5
-6
-7
V+ = 5V
RL = 1k
CL = 16.3pF
AV = +1
VOUT = 10mVP-P
100k
1M
-2
VOUT = 100mV
-3
VOUT = 50mV
-4
VOUT = 10mV
V+ = 5V
RL = 10k
CL = 16.3pF
AV = +1
VOUT = 10mVP-P
-9
10k
100k
-1
VOUT = 1V
-2
VOUT = 100mV
-3
VOUT = 50mV
-5
-6
-7
-8
1M
10M
VOUT = 10mV
-4
V+ = 5V
RL = 100k
CL = 16.3pF
AV = +1
VOUT = 10mVP-P
-9
10k
100M
100k
1M
FREQUENCY (Hz)
70
0
RL = 100k
60
RL = 10k
50
-1
-2
RL = 1k
-3
GAIN (dB)
NORMALIZED GAIN (dB)
100M
FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 100k
1
-4
-5
-8
10M
FREQUENCY (Hz)
FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k
-7
100M
0
VOUT = 1V
-6
10M
FIGURE 2. GAIN vs FREQUENCY vs VOUT, RL = 1k
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
-3
1
-1
-8
VOUT = 100mV
FREQUENCY (Hz)
0
-7
-2
-9
10k
100M
1
-6
VOUT = 1V
-8
FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR
VALUES Rf/Rg
-5
-1
V+ = 5V
CL = 16.3pF
AV = +1
VOUT = 10mVP-P
-9
10k
100k
40
AV = 1001
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY vs RL
4
100M
V+ = 5V
CL = 16.3pF
RL = 10k
VOUT = 10mVP-P
30
20
0
10M
AV = 101, Rg = 1k, Rf = 100k
AV = 101
AV = 10
AV = 10, Rg = 1k, Rf = 9.09k
10
1M
AV = 1001, Rg = 1k, Rf = 1M
AV = 1
-10
100
AV = 1, Rg = INF, Rf = 0
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FN6153.5
April 5, 2011
ISL28136
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
1
V+ = 5V
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
-2
-3
V+ = 2.4V
-4
-5
RL = 10k
CL = 16.3pF
AV = +1
VOUT = 10mVP-P
-6
-7
-8
-9
10k
100k
1M
10M
100M
8
7
6
5
4
3
2
1
0
-1
-2
-3 V+ = 5V
-4 RL = 1k
-5 A = +1
V
-6
VOUT = 10mVP-P
-7
-8
10k
100k
20
20
0
0
-40
V+ = 2.4V, 5V
RL = 1k
CL = 16.3pF
AV = +1
VCM = 1VP-P
100
1k
10k
100k
-40
100M
PSRR-
PSRR+
-100
-120
10
10M
1M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±1.2V
20
100
V+, V- = ±2.5V
0 RL = 1k
CL = 16.3pF
-20 AV = +1
VSOURCE = 1VP-P
-40
V+ = 5V
RL = 1k
CL = 16.3pF
AV = +1
INPUT VOLTAGE NOISE (nV√Hz)
PSRR (dB)
10M
-80
FIGURE 9. CMRR vs FREQUENCY; V+ = 2.4V AND 5V
PSRR-
-60
PSRR+
-80
-100
10
100
1M
-60
FREQUENCY (Hz)
-120
10
CL = 4.7pF
V+, V- = ±1.2V
RL = 1k
CL = 16.3pF
AV = +1
VSOURCE = 1VP-P
-20
-20
-100
10
CL = 16.7pF
FIGURE 8. GAIN vs FREQUENCY vs CL
PSRR (dB)
CMRR (dB)
FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
-80
CL = 26.7pF
FREQUENCY (Hz)
FREQUENCY (Hz)
-60
CL = 51.7pF
CL = 43.7pF
CL = 37.7pF
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 11. PSRR vs FREQUENCY, V+, V- = ±2.5V
5
1
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
FN6153.5
April 5, 2011
ISL28136
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
10
0.5
0.3
1
0.1
0
-0.1
-0.2
-0.4
1
10
100
1k
FREQUENCY (Hz)
10k
-0.5
100k
2
3
4
5
6
7
8
9
10
0.026
0.024
SMALL SIGNAL (V)
1.0
0.5
0
V+, V- = ±2.5V
RL = 1k
CL = 16.3pF
Rg = Rf = 10k
AV = 2
VOUT = 1.5VP-P
-0.5
-1.0
0
1
2
3
4
0.022
0.020
0.018
0.014
5
6
TIME (µs)
7
8
9
0.012
0
10
V-OUT
5
0.5
1.0
1.5
2.0
2.5
TIME (µs)
3.0
3.5
4.0
FIGURE 16. SMALL SIGNAL STEP RESPONSE
1.3
6
V-ENABLE
V+, V- = ±2.5V
RL = 1k
CL = 16.3pF
Rg= Rf = 10k
AV = 2
VOUT = 10mVP-P
0.016
FIGURE 15. LARGE SIGNAL STEP RESPONSE
100
80
1.1
60
0.9
3
2
1
0.7
0.5
0.3
0.1
0
0
10
20
30
40
50
60
TIME (µs)
70
80
90
FIGURE 17. ENABLE TO OUTPUT RESPONSE
6
-0.1
100
40
VOS (µV)
V+ = 5V
Rg = Rf = RL = 1k
CL = 16.3pF
AV = +2
VOUT = 1VP-P
OUTPUT (V)
4
-1
1
FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz
1.5
-1.5
0
TIME (s)
FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY
LARGE SIGNAL (V)
0.2
-0.3
0.1
V-ENABLE (V)
V+ = 5V
RL = 10k
CL = 16.3pF
Rg = 10, Rf = 100k
AV = 10000
0.4
INPUT NOISE (µV)
INPUT CURRENT NOISE (pA√Hz)
V+ = 5V
RL = 1k
CL = 16.3pF
AV = +1
20
0
-20
V+ = 5V
RL = OPEN
Rf = 100k, Rg = 100
AV = +1000
-40
-60
-80
-100
-1
0
1
2
3
VCM (V)
4
5
6
FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON-MODE
INPUT VOLTAGE
FN6153.5
April 5, 2011
ISL28136
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
1200
100
N = 1150
80
1100
60
CURRENT (µA)
I-BIAS (nA)
40
20
0
-20
V+ = 5V
RL = OPEN
Rf = 100k, Rg = 100
AV = +1000
-40
-60
-80
-100
-1
0
1
2
3
VCM (V)
4
5
0
MAX
60
80
100
120
100
120
MAX
200
MEDIAN
8
7
6
100
MEDIAN
0
-100
-200
MIN
5
MIN
-300
-20
0
20
40
60
80
100
-400
-40
120
-20
0
TEMPERATURE (°C)
300
300
VOS (µV)
100
MEDIAN
0
-100
-200
MIN
0
20
40
MIN
-300
60
80
100
TEMPERATURE (°C)
FIGURE 23. VOS vs TEMPERATURE, V+, V- = ±2.5V,
SOIC PACKAGE
7
MEDIAN
0
-100
-20
MAX
100
-50
-200
80
200
150
-150
60
400
MAX
50
40
FIGURE 22. VOS vs TEMPERATURE, V+, V- = ±2.5V,
SOT PACKAGE
N = 1150
250
200
20
TEMPERATURE (°C)
FIGURE 21. SUPPLY CURRENT DISABLED vs
TEMPERATURE, V+, V- = ±2.5V
VOS (µV)
40
N = 1150
300
9
-250
-40
20
FIGURE 20. SUPPLY CURRENT ENABLED vs
TEMPERATURE, V+, V- = ±2.5V
VOS (µV)
CURRENT (µA)
-20
TEMPERATURE (°C)
400
4
-40
MIN
800
600
-40
6
11
10
MEDIAN
900
700
FIGURE 19. INPUT OFFSET CURRENT vs COMMON-MODE
INPUT VOLTAGE
N = 1150
MAX
1000
120
-400
-40
N = 1150
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 24. VOS vs TEMPERATURE, V+, V- = ±1.2V, SOT
PACKAGE
FN6153.5
April 5, 2011
ISL28136
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
300
30
N = 1150
250
25
MAX
200
100
IBIAS+ (nA)
VOS (µV)
MAX
20
150
MEDIAN
50
0
-50
15
MEDIAN
10
5
-100
0
-150
MIN
-5
-200
-250
-40
-20
0
20
40
60
80
100
-10
-40
120
MIN
-20
0
TEMPERATURE (°C)
FIGURE 25. VOS vs TEMPERATURE, V+, V- = ±1.2VSOIC
PACKAGE
15
25
10
MAX
10
IBIAS+ (nA)
IBIAS- (nA)
15
MEDIAN
5
0
120
MAX
0
MEDIAN
-5
-10
-15
MIN
-20
-5
-10
-40
N = 1150
-20
0
20
40
60
80
100
120
-25
-40
MIN
-20
0
FIGURE 27. IBIAS- vs TEMPERATURE, V+, V- = ±2.5V
N = 1150
40
60
80
100
120
FIGURE 28. IBIAS+ vs TEMPERATURE, V+, V- = ±1.2V
10
N = 1150
8
MAX
10
MAX
6
5
IOS (nA)
4
0
MEDIAN
-5
MEDIAN
2
0
-2
-10
-15
-4
MIN
MIN
-6
-20
-25
-40
20
TEMPERATURE (°C)
TEMPERATURE (°C)
IBIAS- (nA)
100
5
20
15
20
40
60
80
TEMPERATURE (°C)
FIGURE 26. , IBIAS+ vs TEMPERATURE, V+, V- = ±2.5V
30
20
N = 1150
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 29. IBIAS- vs TEMPERATURE, V+, V- = ±1.2V
8
-8
-40
N = 1150
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 30. IOS vs TEMPERATURE, V+, V- = ±2.5V
FN6153.5
April 5, 2011
ISL28136
Typical Performance Curves
10
140
N = 1150
135
8
IOS (nA)
6
125
4
2
MEDIAN
0
-2
MEDIAN
110
-20
0
20
40
60
80
TEMPERATURE (°C)
MIN
95
100
90
-40
120
N = 1150
-20
0
20
40
60
80
4500
4000
115
MAX
3500
MAX
AVOL (V/mV)
110
105
MEDIAN
100
3000
2500
2000
MEDIAN
1500
1000
95
MIN
-20
0
20
40
60
80
TEMPERATURE (°C)
100
MIN
500
N = 1150
0
-40
120
N = 1150
-20
0
20
40
60
80
120
FIGURE 34. AVOL vs TEMPERATURE, V+, V- = ±2.5V, VO = -2V
TO +2V, RL = 100k
200
4.960
180
4.955
N = 1150
MAX
MAX
160
100
TEMPERATURE (°C)
FIGURE 33. PSRR vs TEMPERATURE, V+, V- = ±1.2V TO
±2.75V
4.950
MEDIAN
VOUT (V)
AVOL (V/mV)
120
FIGURE 32. CMRR vs TEMPERATURE, VCM = -2.5V TO +2.5V,
V+, V- = ±2.5V
120
140
120
MEDIAN
4.945
4.940
100
MIN
MIN
4.935
80
60
-40
100
TEMPERATURE (°C)
FIGURE 31. IOS vs TEMPERATURE, V+, V- = ±1.2V
PSRR (dB)
115
100
MIN
-6
90
-40
120
105
-4
-8
-40
MAX
130
MAX
CMRR (dB)
12
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
N = 1150
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 35. AVOL vs TEMPERATURE, V+, V- = ±2.5V, VO = -2V
TO +2V, RL = 1k
9
4.930
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 36. VOUT HIGH vs TEMPERATURE, V+, V- = ±2.5V,
RL = 1k
FN6153.5
April 5, 2011
ISL28136
Typical Performance Curves
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
75
70
VOUT (m V)
MAX
65
60
MEDIAN
55
MIN
50
N = 1150
45
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 37. VOUT LOW vs TEMPERATURE, V+, V- = ±2.5V, RL = 1k
Pin Descriptions
ISL28136
(6 Ld SOT-23)
4
ISL28136
(8 Ld SOIC)
PIN NAME
1, 5
NC
Not connected
2
IN-
inverting input
FUNCTION
EQUIVALENT CIRCUIT
V+
IN-
IN+
VCircuit 1
3
3
IN+
2
4
V-
Non-inverting input
Negative supply
See Circuit 1
V+
CAPACITIVELY
COUPLED
ESD CLAMP
VCircuit 2
1
6
OUT
Output
V+
OUT
VCircuit 3
6
7
V+
Positive supply
5
8
EN
Chip enable
See Circuit 2
V+
LOGIC
PIN
VCircuit 3
10
FN6153.5
April 5, 2011
ISL28136
Applications Information
-
Introduction
The ISL28136 is a single channel Bi-CMOS rail-to-rail input,
output (RRIO) micropower precision operational amplifier.
The part is designed to operate from a single supply 2.4V to
5.5V. The part has an input common mode range that
extends 0.25V above the positive rail and down to the
negative supply rail. The output operation can swing within
about 3mV of the supply rails with a 100kΩ load.
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs; a
long-tail PNP (or PFET) and an NPN (or NFET). Severe
penalties have to be paid for this circuit topology. As the input
signal moves from one supply rail to another, the operational
amplifier switches from one input pair to the other causing
drastic changes in input offset voltage and an undesired
change in magnitude and polarity of input offset current.
The ISL28136 achieves input rail-to-rail operation without
sacrificing important precision specifications and degrading
distortion performance. The device’s input offset voltage
exhibits a smooth behavior throughout the entire commonmode input range. The input bias current versus the
common-mode voltage range gives an undistorted behavior
from typically down to the negative rail to 0.25V higher than
the positive rail.
Rail-to-Rail Output
The output stage uses drain-connected N and P-channel
MOSFETs to achieve rail-to-rail output swing. The P-channel
device sources current to swing the output in the positive
direction and the N-channel sinks current to swing the output
in the negative direction. The ISL28136 with a 100kΩ load will
swing to within 3mV of the positive supply rail and within 3mV
of the negative supply rail.
Results of Over-Driving the Output
Caution should be used when over-driving the output for long
periods of time. Over-driving the output can occur in two ways.
1) The input voltage times the gain of the amplifier exceeds the
supply voltage by a large value or, 2) the output current
required is higher than the output stage can deliver. These
conditions can result in a shift in the Input Offset Voltage (VOS)
as much as 1µV/hr. of exposure under these conditions.
IN+ and IN- Input Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. They also contain
back-to-back diodes across the input terminals (see “Pin
Descriptions” on page 10 - Circuit 1). For applications where
the input differential voltage is expected to exceed 0.5V, an
external series resistor must be used to ensure the input
currents never exceed 5mA (Figure 38).
11
VIN
RIN
+
VOUT
RL
FIGURE 38. INPUT CURRENT LIMITING
Enable/Disable Feature
The ISL28136 offers an EN pin that disables the device
when pulled up to at least 2.0V. In the disabled state (output
in a high impedance state), the part consumes typically 10µA
at room temperature. By disabling the part, multiple
ISL28136 parts can be connected together as a MUX. In this
configuration, the outputs are tied together in parallel and a
channel can be selected by the EN pin. The loading effects
of the feedback resistors of the disabled amplifier must be
considered when multiple amplifier outputs are connected
together. Note that feed through from the IN+ to IN- pins
occurs on any Mux Amp disabled channel where the input
differential voltage exceeds 0.5V (e.g., active channel
VOUT = 1V, while disabled channel VIN = GND), so the mux
implementation is best suited for small signal applications. If
large signals are required, use series IN+ resistors, or a
large value RF, to keep the feed through current low enough
to minimize the impact on the active channel.
See“Limitations of the Differential Input Protection” on
page 11 for more details.
To disable the part, the user needs to supply the 1.5µA
required to pull the EN pin to the V+ rail. If left open, the EN
pin will pull to the negative rail and the device will be enabled
by default. If the EN function is not required (no need to turn
the part off), as a precaution, it is recommended that the
user tie the EN pin to the V- pin.
Limitations of the Differential Input Protection
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the
input current never exceeds 5mA. For non-inverting unity gain
applications, the current limiting can be via a series IN+ resistor,
or via a feedback resistor of appropriate value. For other gain
configurations, the series IN+ resistor is the best choice, unless
the feedback (RF) and gain setting (RG) resistors are both
sufficiently large to limit the input current to 5mA.
Large differential input voltages can arise from several
sources:
1) During open loop (comparator) operation. Used this way,
the IN+ and IN- voltages don’t track, so differentials arise.
2) When the amplifier is disabled but an input signal is still
present. An RL or RG to GND keeps the IN- at GND, while
the varying IN+ signal creates a differential voltage. Mux
Amp applications are similar, except that the active channel
VOUT determines the voltage on the IN- terminal.
FN6153.5
April 5, 2011
ISL28136
3) When the slew rate of the input pulse is considerably
faster than the op amp’s slew rate. If the VOUT can’t keep up
with the IN+ signal, a differential voltage results, and visible
distortion occurs on the input and output signals. To avoid
this issue, keep the input slew rate below 1.9V/µs, or use
appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an
increase in disabled ICC.
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related in Equation 1:
T JMAX = T MAX + ( θ JA xPD MAXTOTAL )
Current Limiting
These devices have no internal current-limiting circuitry. If
the output is shorted, it is possible to exceed the Absolute
Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device.
(EQ. 1)
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using
Equation 2:
V OUTMAX
PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Supply voltage (Magnitude of V+ and V-)
• IMAX = Maximum supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6153.5
April 5, 2011
ISL28136
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
13
FN6153.5
April 5, 2011
ISL28136
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.95
D
0.08-0.20
A
5
6
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
1
(0.60)
3
2
0.20 C
2x
0.40 ±0.05
B
5
SEE DETAIL X
3
0.20 M C A-B
D
TOP VIEW
2.90
5
END VIEW
10° TYP
(2 PLCS)
0.15 C A-B
2x
H
1.14 ±0.15
C
SIDE VIEW
0.10 C
0.05-0.15
1.45 MAX
SEATING PLANE
DETAIL "X"
(0.25) GAUGE
PLANE
0.45±0.1
4
(0.60)
(1.20)
NOTES:
(2.40)
(0.95)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
14
FN6153.5
April 5, 2011