CT T ODU CEMEN 7 R P E A 74 T L 7 E OL REP 00-442OBS ENDED 8 1 m s.co MM ions ECO pplicat p@harri R O N ral A centap Cent : Call or email 220MHz, Video Line Driver, High Speed Operational Amplifier The CA3450 is a large signal video line driver and high speed operational amplifier capable of driving 50Ω transmission lines and flash A/Ds. The uncompensated unity gain crossing occurs at 230MHz without load. It can operate at dual or single supplies of ±7.25V or 14.5V, respectively. The CA3450 can be compensated with a single capacitor network. It has output drive capability of 75mA SINK or SOURCE. The CA3450 is capable of driving Flash A/Ds in video or high speed instrumentation (accurate) applications with bandwidth up to 10MHz. Offset voltage nulling terminals are also available. CA3450 January 1999 File Number 1732.5 Features • High Open Loop Gain at Video Frequencies - AOL . . . . . . . . . . . . . . . . . . . . . . . . . . >40dB at f = 5MHz • Power Bandwidth of 10MHz . . . . . . . ACL = 5; VO = ±3.5V • Slew Rate at Full Load . . . . . . . . . . . . . 330V/µs (AV ≥ 10) • fT = 220MHz; CC = 0pF With a Load of 50Ω ||20pF|| 1MΩ (Scope Input) • VOUT = ±4.1V Into 75Ω • Offset Null Terminals Applications • Video Line Driver Pinout • High Frequency Unity Gain Buffer CA3450 (PDIP) TOP VIEW • Pulse Amplifier • High Speed Comparator OFFSET NULL 1 NC 2 16 OFFSET NULL • High Frequency Oscillator and Video Amplifiers 15 NC • Driver for A/Ds in Video Applications . . . . . . . .10MHz BW 14 + INPUT - INPUT 3 V- 4 13 V- V- 5 12 V- VO 6 11 COMP V+ 7 10 NC Part Number Information PART NUMBER CA3450E TEMP. RANGE (oC) -40 to 85 PACKAGE 16 Ld PDIP PKG. NO. E16.3 9 COMP V+ 8 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CA3450 Block Diagram 7 V+ 8 V+ BIAS CIRCUIT +IN 14 + 3 - X180 X0.50 6 X18 OUTPUT -IN INPUT CURRENT COMPENSATED DIFFERENTIAL AMPLIFIER DC LEVEL SHIFT STAGE 1 16 OUTPUT POWER DRIVER AND OUTPUT POWER STAGE 9 OFFSET NULL 11 4 5 PHASE COMP 12 13 V- Schematic Diagram FREQUENCY COMPENSATION 11 D2 D1 C1 Q8 Q5 Q1 Q4 Q3 Q9 Q6 Q15 C3 Q16 Q12 Q11 Q7 V+ 7 Q14 C2 Q10 Q2 V+ 8 Q17 Q18 D3 V- V- Q19 D4 R5 2K 3 INVERTING INPUT V+ Q26 R1 100K R10 3.2K Q23 Q21 Q22 R2 140 14 NONINVERTING INPUT R7 6 C6 D6 6 R8 30 R6 2K C5 OUTPUT D10 9 FREQUENCY COMPENSATION Q38 Q35 R3 Q27 R11 3k Q24 R9 780 Q20 R4 8.5K D5 C4 Q25 D7 R12 250 D9 Q28 Q29 C7 R13 860 Q30 R14 860 R15 130 1 Q31 Q32 R16 860 R17 500 16 R18 200 4, 5, 12, 13 V- 2 Q33 R19 100 Q34 R20 170 Q36 R21 270 Q37 R22 250 CA3450 Absolute Maximum Ratings Thermal Information Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . 14.5V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. CC = 5pF, VSUPPLY = ±6V, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS DC |VIO| Input Offset Voltage 25 - 8 20 mV Full - 10 35 mV Input Bias current |IIB| 25 - 100 400 nA Input Offset Current |IIO| 25 - 50 200 nA Open Loop DC Gain AOL 25 60 70 - dB VOUT = ±2.5V, RL = 50Ω Full 55 - - dB Power Supply Rejection Ratio PSRR ∆V = ±1V 25 55 65 - dB Common Mode Rejection Ratio CMRR VICR = ±3.5V 25 50 60 - dB 25 ±3.5 ±3.7 - V Full ±3.0 - - V Common Mode Input Range VICR Supply Current I+ 25 - 30 40 mA Full - - 50 mA No Load 25 - 200 - MHz RL = 1MΩ||20pF 25 - 190 - MHz RL = 50Ω||20pF 25 - 185 - MHz No Load 25 210 230 - MHz RL = 20pF||1MΩ 25 180 200 - MHz RL = 50Ω||20pF 25 180 220 - MHz No Load 25 200 210 - MHz 50Ω 25 175 190 - MHz DYNAMIC -3dB Bandwidth AV = 1 (See Figure 2) CC = 5pF Bandwidth (Unity Gain Crossing) AV = Open Loop CC = 0 (See Figure 1) Bandwidth (Unity Gain Crossing) AV = 10, CC = 0pF RFEEDBACK = 450Ω RPIN 3 - G = 50Ω (See Figure 2) Transient Response, Overshoot (See Figure 3) OS tS Settling Time (See Figure 5) (2V Step, RL = 50Ω||20pF) 3 1M||20pF 25 180 195 - MHz 50Ω||1M||20pF 25 170 188 - MHz RL = 50Ω||20pF 25 - 30 - % No Load 25 - 20 - % AV ≥10, CC = 0pF, RL = 50Ω||20pF 25 - 10 - % AV = 1, CC = 5pF AV = -1, CC = 5pF, 0.1%, 10 Bits 25 - 35 - ns AV = 1, CC = 5pF, 0.1%, 10 Bits 25 - 50 - ns AV = 10, CC = 0pF, 0.1%, 10 Bits 25 - 35 - ns AV = 10, CC = 0pF, 1.0%, 7 Bits 25 - 25 - ns CA3450 CC = 5pF, VSUPPLY = ±6V, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEMP. (oC) MIN TYP MAX UNITS No Load 25 - 220 - V/µs RL = 50Ω||20pF 25 - 160 - V/µs No Load 25 370 440 - V/µs RL = 50Ω||20pF 25 300 330 - V/µs AV = 5, CC = 5pF VOUT = ±3.5V No Load 25 - 10 - MHz RL = 50Ω||20pF 25 - 7.2 - MHz AV ≥10, CC = 0pF VOUT = ±2.0V No Load 25 29 35 - MHz RL = 50Ω||20pF 25 24 26 - MHz SYMBOL Slew Rate (See Figures 2, 4) TEST CONDITIONS SR AV = 1, CC = 5pF AV ≥10, CC = 0pF FPBW Full Power Bandwidth (FPBW = SR/π VP-P) Input Noise Voltage eN f = 1kHz 25 - 12 - nV/√Hz Differential Gain DG See Figure 8 25 - 0.2 - % DP Differential Phase See Figure 8 25 - 0.2 - Degrees Output Current IOUT Into +4V or -4V 25 60 75 - mA Output Voltage Swing VOM+ RL = 75Ω 25 3.9 4.1 - V 25 -3.9 -4.1 - V f = 1MHz 25 - 2.2 - pF 25 - 1 - MΩ See Figure 14, AV = 1, 30MHz 25 - 4 - Ω VOM Input Capacitance CI Input Resistance RI Output Resistance ROUT Test Circuits and Waveforms + 0.1µF 10Ω (NOTE 2) +6V 4.7µF (TANT.) - 7 GEN 8 50Ω 14 + 11 CC 0.001µF 9 CC 50Ω SCOPE INPUT 6 CA3450 50Ω - 3 12 4 10Ω MULTILAYER 0.1µF CERAMIC CHIP 1M 16 13 OFFSET NULL 5 0.1µF 20pF 1 + 10Ω (NOTE 2) -6V 4.7µF (TANT.) All 0.1µF and 0.001µF supply decoupling capacitors are multilayer ceramic chip types. 51K 820pF SILVER MICA OR EQUIVALENT NOTE: 2. A 10Ω, 1/4W supply decoupling resistor is shown in all application circuits of this device. The resistor serves two purposes. First it provides a means of decoupling the IC directly at its terminal without introducing additional supply resonance due to parallel connected capacitors. Second, it also provides protection for the device in event of a sustained short circuit applied directly to the output terminals. FIGURE 1. OPEN LOOP GAIN vs FREQUENCY TEST CIRCUIT 4 CA3450 Test Circuits and Waveforms GEN (Continued) 0pF (AV = 10) 5pF (AV = 1) 50Ω 10Ω 9 0.1µF 11 14 + +6V + - 4.7µF (TANT.) 8 7 50Ω 6 CA3450 15 3 12 5 2 CABLE LENGTH 1M 13 10 CABLE LENGTH 1M 4 10Ω 450Ω FOR AV = 10 3 0.1µF 6 + -6V 4.7µF (TANT.) 50Ω TEKTRONIX 2465 OSCILLOSCOPE 50Ω 50Ω FIGURE 2. UNITY GAIN AND X10 NON-INVERTING AMPLIFIER/AND SLEW RATE TEST CIRCUIT Transient Response Waveforms FIGURE 3. TRANSIENT RESPONSE WAVEFORM 5 FIGURE 4. SLEW RATE WAVEFORM CA3450 Test Circuits and Waveforms (Continued) 11 +6V 54Ω 2-10pF 9 10Ω 8 CC 11 0.01 µF 511Ω 7 BITS 8 9 INPUT 7 3 174 Ω - 6 5 CA3450 14 50 Ω 12 4 SIMULATED TWO TRANSMISSION LINE 6 + 4 3 2 11 1 15 5 30 35 40 45 FIGURE 6. ACCURACY IN BITS AS A FUNCTION OF SETTLING TIME 10Ω 82.5Ω 2 10 15 0.5kΩ 2-HP-5082-2835 DIODES 10kΩ 0.5kΩ 1 16 4 V- FIGURE 5. CIRCUIT USED TO MEASURE SETTLING TIME FIGURE 7. NULLING CIRCUIT FOR THE CA3450 5pF 10Ω MODULATED STAIRCASE INPUT SIGNAL +6V 11 + 0.1µF 9 14 + - 4.7µF 8 SHIELDED CABLE 7 75Ω 75Ω 6 CA3450 220Ω 12 - 3 5 2 1VP-P 75Ω 15 TEKTRONIX VM700A NTSC TEST SET 13 10 4 10Ω -6V 0.1µF 220Ω 4.7µF FIGURE 8. CONFIGURATION USED TO MEASURE DIFFERENTIAL GAIN AND PHASE 6 50 SETTLING TIME TO ±1/2LSB (ns) -6V MEASUREMENT POINT 25 20 ALL RESISTORS ARE 1% MULTILAYER CERAMIC CHIP 0.1µF 82.5Ω 2V STEP 10 CA3450 Test Circuits and Waveforms (Continued) +8V 10Ω 0.001µF 7 75Ω, 1VP-P VIDEO INPUT 14 8 + 75Ω 10Ω 11 6 CA3450 5pF 16 9 3 - 390Ω 12 4 21 FLASH A/D INPUT 0.001µF 13 5 10Ω 750Ω -4V 110Ω 0.1µF 0V TO -10V OFFSET SOURCE, RS <10Ω FIGURE 9. TYPICAL HIGH BANDWIDTH X5 AMPLIFIER FOR DRIVING THE CA3318 FLASH A/D 35o MARGIN PHASE SHIFT AOL 1 10 100 1000 FREQUENCY (MHz) FIGURE 10. BODE PLOT FOR THE CA3450 7 -85 -100 -115 -130 -145 -160 -175 -190 -205 -220 -235 -250 -265 10 AV = 1 CC = 5pF 0 CC = 7pF -10 CC = 5pF 0 45 CC = 7pF 90 135 180 1 10 FREQUENCY (MHz) 100 PHASE (DEGREES) RL = 50Ω, || 20pF CC = 0pF, TA = 25oC VS = ±6V CLOSED LOOP GAIN (dB) 60 55 50 45 40 35 30 25 20 15 10 5 0 -5 PHASE ANGLE (DEGREES) OPEN LOOP GAIN (dB) Typical Performance Curves 300 FIGURE 11. CLOSED LOOP GAIN AND PHASE vs FREQUENCY CA3450 (Continued) 30 20 GAIN 10 0 PHASE 45 0 90 135 180 300 -10 1 10 FREQUENCY (MHz) 100 PHASE (DEGREES) CLOSED LOOP GAIN (dB) AV = 10 100 10 1 101 100 10.0 90 9.0 80 70 60 50 40 30 20 102 103 104 FREQUENCY (MHz) 105 106 FIGURE 13. EQUIVALENT INPUT NOISE vs FREQUENCY OUTPUT VOLTAGE SWING (VP-P) OUTPUT RESISTANCE (Ω) FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz) Typical Performance Curves AV = 10, CC = 0pF RL = 660Ω || 20pF RL = 75Ω || 20pF 8.0 7.0 RL = 50Ω || 20pF 6.0 5.0 4.0 3.0 2.0 1.0 10 0.0 0 1 10 FREQUENCY (MHz) 100 200 1 10 100 FREQUENCY (MHz) FIGURE 14. OUTPUT RESISTANCE vs FREQUENCY FIGURE 15. OUTPUT VOLTAGE vs FREQUENCY Metallization Mask Layout 0 66 10 20 30 40 50 60 70 80 90 100 106 Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). 60 50 40 66 (1.676) 30 20 10 0 106 (2.692) 8 The photographs and dimensions of each CMOS chip represent a chip when it is part of the wafer. When the wafer is cut into chips, the angle of cleavage may vary with respect to the chip face for different chips. The actual dimensions of the isolated chip, therefore, may differ slightly from the nominal dimensions shown. The user should consider a tolerance of -3mils to +6mils applicable to the nominal dimensions shown. 300