AD7533 ® Data Sheet June 2004 10-Bit Multiplying D/A Converter Features The AD7533 is a monolithic, low cost, high performance, 10-bit accurate, multiplying digital-to-analog converter (DAC), in a 16 pin DIP. • 8-Bit Linearity Intersil’s thin film resistors on CMOS circuitry provide 10-bit resolution (8-bit accuracy), with TTL/CMOS compatible operation. FN3105.3 • Low Gain and Linearity Temperature Coefficients • Full Temperature Range Operation • Static Discharge Input Protection • TTL/CMOS Compatible The AD7533’s accurate four quadrant multiplication, full input protection from damage due to static discharge by clamps to V+ and GND, and very low power dissipation make them very versatile converters. • Supply Range. . . . . . . . . . . . . . . . . . . . . . . . . +5V to +15V Low noise audio gain controls, motor speed controls, digitally controlled gain and digital attenuators are a few of the wide range of applications of the AD7533. • AD7533 Direct AD7520 Equivalent • Fast Settling Time at 25oC . . . . . . . . . . . . . . 150ns (Max) • Four Quadrant Multiplication Pinout AD7533 (PDIP) TOP VIEW Functional Block Diagram VREF IN 10kΩ 10kΩ 10kΩ 10kΩ (15) IOUT1 1 16 RFEEDBACK IOUT2 2 15 VREF IN 14 V+ GND 3 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ (3) SPDT NMOS SWITCHES 13 BIT 10 BIT 1 (MSB) 4 IOUT2 (2) IOUT1 (1) BIT 2 5 12 BIT 9 BIT 3 6 11 BIT 8 BIT 4 7 10 BIT 7 BIT 5 8 9 BIT 6 10kΩ MSB (4) BIT 2 (5) RFEEDBACK (16) BIT 3 (6) NOTE: Switches shown for digital inputs “High” Ordering Information PART NUMBER NUMBER OF BITS LINEARITY (INL, DNL) TEMP. RANGE (oC) 10 0.2% (8-Bit) 0 to 70 AD7533JN 1 PACKAGE 16 Ld PDIP PKG. NO. E16.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. AD7533 Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . .+17V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . . -100mV to V+ Thermal Resistance (Typical, Note 1) Operating Conditions θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified TA 25oC PARAMETER TEST CONDITIONS TA MIN-MAX MIN MAX MIN MAX UNITS 10 - 10 - Bits - ±0.2 - ±0.2 % of FSR SYSTEM PERFORMANCE Resolution -10V ≤ VREF ≤ +10V, VOUT1 = VOUT2 = 0V (Notes 2, 3, 6) Nonlinearity Monotonicity Guaranteed Gain Error All Digital Inputs High (Note 3) - ±1.4 - ±1.8 % of FSR Nonlinearity Tempco -10V ≤ VREF ≤ + 10V (Notes 3, 4) - ±2 - ±2 ppm of FSR/oC - ±10 - ±10 ppm of FSR/oC VOUT1 = VOUT2 = 0 - ±50 - ±200 nA Power Supply Rejection V+ = 14.0V to 15.0V (Note 3) - ±0.005 - ±0.008 % of FSR/% of ∆V+ Output Current Settling Time To 0.2% of FSR, RL = 100Ω (Note 4) - 600 - 800 ns Feedthrough Error VREF = 20VP-P , 200kHz Sine Wave, All Digital Inputs Low (Note 4) - ±0.05 - ±0.1 LSB All Digital Inputs High IOUT1 at Ground (Note 4) 5 - 5 - kΩ - 20 - 20 kΩ - -300 - -300 ppm/οC Gain Error Tempco Output Leakage Current (Either Output) DYNAMIC CHARACTERISTICS REFERENCE INPUTS Input Resistance (Pin 15) Temperature Coefficient 2 AD7533 Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified (Continued) TA 25oC TA MIN-MAX MIN MAX MIN MAX UNITS COUT1 All Digital Inputs High (Note 4) - 100 - 100 pF COUT2 - 35 - 35 pF COUT1 All Digital Inputs Low (Note 4) - 35 - 35 pF COUT2 - 100 - 100 pF Low State Threshold, VIL - 0.8 - 0.8 V High State Threshold, VIH 2.4 - 2.4 - V - ±1 - ±1 µA 4 pF PARAMETER TEST CONDITIONS ANALOG OUTPUT Output Capacitance DIGITAL INPUTS Input Current (Low or High), IIL, IIH VIN = 0V or + 15V Input Coding See Tables 1 through 3 Input Capacitance (Note 4) Binary/Offset Binary - 4 - POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range (Note 6) +5 to +16 I+ All Digital Inputs High or Low (Excluding Ladder Network) - 2 - V 2.5 mA NOTES: 2. Full Scale Range (FSR) is 10V for unipolar and ±10V for bipolar modes. 3. Using internal feedback resistor, RFEEDBACK . 4. Guaranteed by design or characterization and not production tested. 5. Accuracy not guaranteed unless outputs at ground potential. 6. Accuracy is tested and guaranteed at V+ = +15V, only. Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a “best straight line” through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of n bits can resolve output changes of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g., 1/2 LSB) for a given digital input change, i.e., all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full-scale range, i.e., all digital inputs at HIGH state. It is expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Feedthrough Error: Error caused by capacitive coupling from VREF to IOUT1 with all digital inputs LOW. 3 Output Capacitance: Capacitance from IOUT1 , and IOUT2 terminals to ground. Output Leakage Current: Current which appears on IOUT1 , terminal when all digital inputs are LOW or on IOUT2 terminal when all digital inputs are HIGH. For further information on the use of this device, see the following Application Notes: Application Notes NOTE # DESCRIPTION AN002 “Principles of Data Acquisition and Conversion” AN018 “Do’s and Don’ts of Applying A/D Converters” AN042 “Interpretation of Data Conversion Accuracy Specifications” Detailed Description The AD7533 is a monolithic multiplying D/A converter. A highly stable thin film R-2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power TTL/CMOS AD7533 compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must be held at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure 1. This configuration results in TTL/CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and high accurate leg currents. Typical Applications ±10V +15V VREF R1 4 DATA INPUTS LSB 14 RFEEDBACK 16 OUT1 AD7533 1 R2 15 MSB 11 3 2 OUT2 CR1 - VOUT 6 + GND NOTES: 7. R1 and R2 used only if gain adjustment is required. 8. CR1 protects AD7533 against negative transients. FIGURE 2. UNIPOLAR BINARY OPERATION Unipolar Binary Operation - (10-Bit DAC) The circuit configuration for operating the AD7533 in unipolar mode is shown in Figure 2. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The “Digital Input Code/Analog Output Value” table for unipolar mode is given in Table 1. TABLE 1. UNlPOLAR BINARY CODE - AD7533 DIGITAL INPUT MSB LSB V+ 1 3 4 6 1111111111 1023 – V REF ------------- 1024 1000000001 513 – V REF ------------- 1024 TO LADDER 8 9 1000000000 TTL/ CMOS INPUT 2 5 7 IOUT2 IOUT1 FIGURE 1. CMOS SWITCH (NOTE 9) NOMINAL ANALOG OUTPUT V REF 512 – V REF ------------- = – ------------- 1024 2 0111111111 511 – V REF ------------- 1024 0000000001 1 – V REF ------------- 1024 0000000000 0 – V REF ------------- = 0 1024 NOTES: 9. VOUT as shown in Figure 2. 10. Nominal Full Scale for the circuit of Figure 2 is given by: 1023 FS = – V REF ------------- . 1024 11. Nominal LSB magnitude for the circuit of Figure 2 is given by: 1 LSB = V REF ------------- . 1024 Zero Offset Adjustment 1. Connect all digital inputs to GND. 2. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V ±1mV (Max) at VOUT. Gain Adjustment 1. Connect all digital inputs to V+. 4 AD7533 2. Monitor VOUT for a -VREF (1 - 1/210) reading. 3. To increase VOUT, connect a series resistor, R2, (0Ω to 250Ω) in the IOUT1 amplifier feedback loop. 4. To decrease VOUT, connect a series resistor, R1, (0Ω to 250Ω) between the reference voltage and the VREF terminal. Bipolar (Offset Binary) Operation The circuit configuration for operating the AD7533 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, 4-Quadrant multiplication can be realized. The “Digital Input Code/Analog Output Value” table for bipolar mode is given in Table 2. A “Logic 1” input at any digital input forces the corresponding ladder switch to steer the bit current to IOUT1 bus. A “Logic 0” input forces the bit current to IOUT2 bus. For any code the IOUT1 and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance amplifier at IOUT1 output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is corrected by using an external resistor, (10MΩ), from VREF to IOUT2 . ±10V +15V VREF R1 15 MSB 4 DATA INPUTS AD7533 14 16 1 R2 RFEEDBACK IOUT1 - IOUT2 13 LSB 3 R4 5K 2 R3 5K CR1 R6 10MΩ 6 + VOUT CR2 6 + FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Offset Adjustment TABLE 2. UNlPOLAR BINARY CODE - AD7533 DIGITAL INPUT MSB LSB (NOTE 2) NOMINAL ANALOG OUTPUT 1111111111 511 -V REF ---------- 512 1000000001 1 -V REF ---------- 512 1000000000 0 0111111111 1 +V REF ---------- 512 0000000001 511 +V REF ---------- 512 0000000000 512 +V REF ---------- 512 NOTES: 12. VOUT as shown in Figure 3. 13. Nominal Full Scale for the circuit of Figure 3 is given by: 1023 FSR = V REF ------------- . 512 14. Nominal LSB magnitude for the circuit of Figure 3 is given by: 1 LSB = V REF ---------- . 512 5 5. Adjust VREF to approximately +10V. 6. Connect all digital inputs to “Logic 1”. 7. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at IOUT2 amplifier output. 8. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”. 9. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV at VOUT. Gain Adjustment 1. Connect all digital inputs to V+. 2. Monitor VOUT for a -VREF (1 - 2-9) volts reading. 3. To increase VOUT, connect a series resistor (R2) of up to 250Ω between VOUT and RFEEDBACK . 4. To decrease VOUT, connect a series resistor (R1) of up to 250Ω between the reference voltage and the VREF terminal. AD7533 ±10V BIPOLAR ANALOG INPUT V+ VREF 15 MSB 14 16 4 MAGNITUDE BITS AD7533 1 OUT1 OUT2 DIGITAL INPUT 13 LSB 2 3 10K RFEEDBACK 10K - 5K 6 + VOUT 6 + 1/ IH5140 2 GND SIGN BIT FIGURE 4. 10-BIT AND SIGN MULTIPLYING DAC CALIBRATE 10K 4.7K 6.8V (2) A2 6 + +15V VDD NC MSB DIGITAL FREQUENCY CONTROL WORD 15 4 14 10K 1% 10K 1% 16 1 OUT1 OUT2 LSB SQUARE WAVE C1 AD7533 13 - 1K 3 2 TRIANGULAR WAVE A1 6 + FIGURE 5. PROGRAMMABLE FUNCTION GENERATOR +15V VIN VREF RFB 16 2 OUT2 14 BIT 1 4 MSB AD7533 OUT1 1 3 LSB 13 15 DIGITAL INPUT “D” +15V BIT 1 BIT 10 VREF - MSB DIGITAL INPUT “D” 15 4 BIT 10 13 6 + 14 16 AD7533 LSB R1 3 1 - 2 6 + R2 VOUT 6 + R2 R1 D V OUT = V REF --------------------- – ---------------------- R 1 + R 2 R 1 + R 2 VOUT = -VIN/D Where: Bit 8 Bit 1 Bit 2 D = ------------- + ------------- + … ------------2 1 2 2 2 2 Bit 8 Bit 1 Bit 2 Where D = ------------ + ------------ + … -----------8 1 2 2 2 2 255 0 ≤ D ≤ ---------- 256 0 ≤ D ≤ 255 ---------- 256 FIGURE 6. DIVIDER (DIGITALLY CONTROLLED GAIN) 6 FIGURE 7. MODIFIED SCALE FACTOR AND OFFSET VOUT AD7533 Die Characteristics DIE DIMENSIONS PASSIVATION 101 mils x 103 mils (2565µm x 2616µm) Type: PSG/Nitride PSG: 7 ±1.4kÅ Nitride: 8 ±1.2kÅ METALLIZATION Type: Pure Aluminum Thickness: 10 ±1kÅ PROCESS CMOS Metal Gate Metallization Mask Layout AD7533 PIN 7 BIT 4 PIN 6 BIT 3 PIN 5 BIT 2 PIN 4 BIT 1 (MSB) PIN 3 GND PIN 2 IOUT2 PIN 8 BIT 5 PIN 1 IOUT1 PIN 9 BIT 6 PIN 10 BIT 7 PIN 16 RFEEDBACK PIN 11 BIT 8 (LSB) PIN 15 VREF NC (PIN 12, BIT 9, AD7533) 7 NC NC (PIN 13, BIT 10, AD7533) NC PIN 14 V+ AD7533 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 18.66 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.204 0.355 - 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 N 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 16 10.92 3.81 16 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 6 7 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8