AD7523, AD7533 8-Bit, Multiplying D/A Converters August 1997 Features Description • 8-Bit, 9-Bit and 10-Bit Linearity The AD7523 and AD7533 are monolithic, low cost, high performance, 8-bit and 10-bit accurate, multiplying digital-toanalog converter (DAC), in a 16 pin DIP. • Low Gain and Linearity Temperature Coefficients • Full Temperature Range Operation Intersil’ thin film resistors on CMOS circuitry provide 10-bit resolution (8-bit, 9-bit and 10-bit accuracy), with TTL/CMOS compatible operation. • Static Discharge Input Protection • TTL/CMOS Compatible • Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +5V to +15V • Fast Settling Time at 25oC . . . . . . . . . . . . 150ns (Max) • Four Quadrant Multiplication The AD7523 and AD7533s accurate four quadrant multiplication, full military temperature range operation, full input protection from damage due to static discharge by clamps to V+ and GND, and very low power dissipation make it a very versatile converter. Low noise audio gain controls, motor speed controls, digitally controlled gain and digital attenuators are a few of the wide range of applications of the AD7523 and AD7533. • AD7533 Direct AD7520 Equivalent Ordering Information LINEARITY (INL, DNL) TEMP. RANGE (oC) AD7523JN, AD7533JN 0.2% (8-Bit) 0 to 70 16 Ld PDIP E16.3 AD7523KN, AD7533KN 0.1% (9-Bit) 0 to 70 16 Ld PDIP E16.3 AD7523LN, AD7533LN 0.05% (10-Bit) 0 to 70 16 Ld PDIP E16.3 PART NUMBER Pinout PACKAGE PKG. NO. Functional Block Diagram AD7523, AD7533 (PDIP) TOP VIEW IOUT1 1 16 RFEEDBACK IOUT2 2 15 VREF IN BIT 3 6 14 V+ NC/BIT 10 13 (NOTE 1) 12 NC/BIT 9 (NOTE 1) 11 BIT 8 BIT 4 7 10 BIT 7 GND 3 BIT 1 (MSB) 4 BIT 2 5 BIT 5 8 9 BIT 6 10kΩ VREF IN 10kΩ 10kΩ 10kΩ (15) 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ (3) SPDT NMOS SWITCHES IOUT2 (2) IOUT1 (1) 10kΩ BIT 2 (5) MSB (4) BIT 3 (6) RFEEDBACK (16) NOTE: 1. NC for AD7523 only. NOTE: Switches shown for digital inputs “High” CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 10-8 File Number 3105.1 AD7523, AD7533 Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+ Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature . . . . . . . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified AD7523 TA 25oC PARAMETER TEST CONDITIONS AD7533 TA MIN-MAX TA 25oC TA MIN-MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS 8 - 8 - 10 - 10 - Bits - ±0.2 - ±0.2 - ±0.2 - ±0.2 % of FSR - ±0.1 - ±0.1 - ±0.1 - ±0.1 % of FSR - ±0.05 - ±0.05 - ±0.05 - ±0.05 % of FSR SYSTEM PERFORMANCE Resolution Nonlinearity J K, T -10V ≤ VREF ≤ +10V VOUT1 = VOUT2 = 0V (Notes 2, 3, 6) L Monotonicity Guaranteed Guaranteed Gain Error All Digital Inputs High (Note 3) - ±1.5 - ±1.8 - ±1.4 - ±1.8 % of FSR Nonlinearity Tempco -10V ≤ VREF ≤ + 10V (Notes 3, 4) - ±2 - ±2 - ±2 - ±2 ppm of FSR/oC - ±10 - ±10 - ±10 - ±10 ppm of FSR/oC VOUT1 = VOUT2 = 0 - ±50 - ±200 - ±50 - ±200 nA Power Supply Rejection V+ = 14.0V to 15.0V (Note 3) - ±0.02 - ±0.03 - ±0.005 - ±0.008 % of FSR/% of ∆V+ Output Current Settling Time To 0.2% of FSR, RL = 100Ω (Note 4) - 150 - 200 - 600 - 800 ns Feedthrough Error VREF = 20VP-P , 200kHz Sine Wave, All Digital Inputs Low (Note 4) - ±1/2 - ±1 - ±0.05 - ±0.1 LSB All Digital Inputs High IOUT1 at Ground (Note 4) 5 - 5 - 5 - 5 - kΩ - 20 - 20 - 20 - 20 kΩ - -500 - -500 - -300 - -300 ppm/οC Gain Error Tempco Output Leakage Current (Either Output) DYNAMIC CHARACTERISTICS REFERENCE INPUTS Input Resistance (Pin 15) Temperature Coefficient 10-9 AD7523, AD7533 Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified (Continued) AD7523 TA 25oC AD7533 TA MIN-MAX TA 25oC TA MIN-MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS - 100 - 100 - 100 - 100 pF - 30 - 30 - 35 - 35 pF - 30 - 30 - 35 - 35 pF - 100 - 100 - 100 - 100 pF Low State Threshold, VIL - 0.8 - 0.8 - 0.8 - 0.8 V High State Threshold, VIH 2,4 - 2,4 - 2.4 - 2.4 - V - ±1 - ±1 - ±1 - ±1 µA 4 pF PARAMETER TEST CONDITIONS ANALOG OUTPUT Output Capacitance COUT1 All Digital Inputs High (Note 4) COUT2 COUT1 All Digital Inputs Low (Note 4) COUT2 DIGITAL INPUTS Input Current (Low or High), IIL, IIH VIN = 0V or + 15V Input Coding See Tables 1 and 3 Input Capacitance (Note 4) Binary/Offset Binary - 4 - Binary/Offset Binary 4 - 4 - POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range (Note 6) I+ All Digital Inputs High or Low (Excluding Ladder Network) +5 to +16 - 2 - +5 to +16 2.5 - 2 - V 2.5 mA NOTES: 2. Full Scale Range (FSR) is 10V for unipolar and ±10V for bipolar modes. 3. Using internal feedback resistor, RFEEDBACK . 4. Guaranteed by design or characterization and not production tested. 5. Accuracy not guaranteed unless outputs at ground potential. 6. Accuracy is tested and guaranteed at V+ = +15V, only. Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a “best straight line” through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of n bits can resolve output changes of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g., 1/2 LSB) for a given digital input change, i.e., all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full-scale range, i.e., all digital inputs at HIGH state. It is expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Feedthrough Error: Error caused by capacitive coupling from VREF to IOUT1 with all digital inputs LOW. Output Capacitance: Capacitance from IOUT1 , and IOUT2 terminals to ground. Output Leakage Current: Current which appears on IOUT1 , terminal when all digital inputs are LOW or on IOUT2 terminal when all digital inputs are HIGH. For further information on the use of this device, see the following Application Notes: NOTE # DESCRIPTION AnswerFAX DOC. # AN002 “Principles of Data Acquisition and Conversion” 9002 AN018 “Do’s and Don’ts of Applying A/D Converters” 9018 AN042 “Interpretation of Data Conversion Accuracy Specifications” 9042 10-10 AD7523, AD7533 Detailed Description ±10V +15V VREF The AD7523 and AD7533 are monolithic multiplying D/A converters. A highly stable thin film R-2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power TTL/CMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must be held at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. 14 RFEEDBACK 16 AD7523/ 1 OUT1 AD7533 CR1 OUT2 11 3 2 R2 15 MSB 4 DATA INPUTS LSB - VOUT 6 + GND NOTES: 1. R1 and R2 used only if gain adjustment is required. 2. CF1 protects AD7523 and AD7533 against negative transients. FIGURE 2. UNIPOLAR BINARY OPERATION Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. TABLE 1. UNlPOLAR BINARY CODE - AD7523 DIGITAL INPUT MSB LSB The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure 1. This configuration results in TTL/CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and high accurate leg currents. 11111111 255 – V REF ---------- 256 10000001 129 – V REF ---------- 256 10000000 V+ 6 TO LADDER 8 127 – V REF ---------- 256 00000001 1 – V REF ---------- 256 00000000 2 5 0 – V REF ---------- = 0 256 NOTE: 9 1. 1 LSB = ( 2 TTL/ CMOS INPUT V REF 128 – V REF ---------- = – ---------------- 256 2 01111111 1 3 4 ANALOG OUTPUT –8 1 ) ( V REF ) = ---------- ( V REF ) . 256 7 Zero Offset Adjustment IOUT2 IOUT1 1. Connect all digital inputs to GND. 2. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V ±1mV (Max) at VOUT . FIGURE 1. CMOS SWITCH Gain Adjustment Typical Applications 1. Connect all digital inputs to V+. Unipolar Binary Operation - AD7523 (8-Bit DAC) 2. Monitor VOUT for a -VREF (11/28) reading. The circuit configuration for operating the AD7523 in unipolar mode is shown in Figure 2. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The “Digital Input Code/Analog Output Value” table for unipolar mode is given in Table 1. 3. To increase VOUT , connect a series resistor, R2, (0Ω to 250Ω) in the IOUT1 amplifier feedback loop. 4. To decrease VOUT , connect a series resistor, R1, (0Ω to 250Ω) between the reference voltage and the VREF terminal. 10-11 AD7523, AD7533 Unipolar Binary Operation - AD7533 (10-Bit DAC) The circuit configuration for operating the AD7533 in unipolar mode is shown in Figure 2. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The “Digital Input Code/Analog Output Value” table for unipolar mode is given in Table 2. (NOTE 1) NOMINAL ANALOG OUTPUT 1111111111 1023 – V REF ------------- 1024 1000000001 513 – V REF ------------- 1024 0111111111 511 – V REF ------------- 1024 0000000001 1 – V REF ------------- 1024 0 – V REF ------------- = 0 1024 0000000000 Bipolar (Offset Binary) Operation - AD7523 A “Logic 1” input at any digital input forces the corresponding ladder switch to steer the bit current to IOUT1 bus. A “Logic 0” input forces the bit current to IOUT2 bus. For any code the IOUT1 and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance amplifier at IOUT output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is corrected by suing an external resistor, (10MΩ), from VREF to IOUT2 (Figure 3). V REF 512 – V REF ------------- = – -------------- 1024 2 1000000000 4. To decrease VOUT , connect a series resistor, R1, (0Ω to 250Ω) between the reference voltage and the VREF terminal. The circuit configuration for operating the AD7523 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, Four-Quadrant multiplication can be realized. The “Digital Input Code/Analog Output Value” table for bipolar mode is given in Table 3.) TABLE 2. UNlPOLAR BINARY CODE - AD7533 DIGITAL INPUT MSB LSB 3. To increase VOUT , connect a series resistor, R2, (0Ω to 250Ω) in the IOUT1 amplifier feedback loop. NOTES: TABLE 3. BlPOLAR (OFFSET BINARY) CODE - AD7523 1. VOUT as shown in the Functional Diagram. DIGITAL INPUT MSB LSB 2. Nominal Full Scale for the circuit of Figure 2 is given by: 1023 FS = – V REF ------------- . 1024 ANALOG OUTPUT 11111111 127 – V REF ---------- 128 10000001 1 – V REF ---------- 128 10000000 0 1. Connect all digital inputs to GND. 01111111 1 +V REF ---------- 128 2. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V ±1mV (Max) at VOUT . 00000001 127 +V REF ---------- 128 00000000 128 +V REF ---------- 128 3. Nominal LSB magnitude for the circuit of Figure 2 is given by: 1 LSB = V REF ------------- . 1024 Zero Offset Adjustment Gain Adjustment 1. Connect all digital inputs to V+. NOTE: 2. Monitor VOUT for a -VREF (1 - 1/210) reading. 1. 1 LSB = ( 2 –7 1 ) ( V REF ) = ---------- ( V REF ) . 128 ±10V +15V VREF R1 15 MSB 4 DATA INPUTS AD7523/ AD7533 13 LSB 3 14 16 1 R2 RFEEDBACK IOUT1 IOUT2 R4 5K 2 R3 5K CR1 R6 10MΩ 6 + CR2 6 + FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) 10-12 VOUT AD7523, AD7533 Offset Adjustment 1. Adjust VREF to approximately +10V. 2. Connect all digital inputs to “Logic 1”. 3. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at IOUT2 amplifier output. another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance amplifier at IOUT1 output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is corrected by using an external resistor, (10MΩ), from VREF to IOUT2 . 4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”. TABLE 4. UNlPOLAR BINARY CODE - AD7533 DIGITAL INPUT MSB LSB 5. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV at VOUT . Gain Adjustment 1. Connect all digital inputs to V+. (NOTE 1) NOMINAL ANALOG OUTPUT 1111111111 511 -V REF ---------- 512 1000000001 1 -V REF ---------- 512 1000000000 0 0111111111 1 +V REF ---------- 512 0000000001 511 +V REF ---------- 512 0000000000 512 +V REF ---------- 512 2. Monitor VOUT for a -VREF (11/28) volts reading. 3. To increase VOUT , connect a series resistor, R2, of up to 250Ω between VOUT and RFEEDBACK . 4. To decrease VOUT , connect a series resistor, R1, of up to 250Ω between the reference voltage and the VREF terminal. Bipolar (Offset Binary) Operation - AD7533 The circuit configuration for operating the AD7533 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, 4-Quadrant multiplication can be realized. The “Digital Input Code/Analog Output Value” table for bipolar mode is given in Table 4. A “Logic 1” input at any digital input forces the corresponding ladder switch to steer the bit current to IOUT1 bus. A “Logic 0” input forces the bit current to IOUT2 bus. For any code the IOUT1 and IOUT2 bus currents are complements of one NOTES: 1. VOUT as shown in the Functional Diagram. 2. Nominal Full Scale for the circuit of Figure 6 is given by: 1023 FSR = V REF ------------- . 512 3. Nominal LSB magnitude for the circuit of Figure 3 is given by: 1 LSB = V REF ---------- . 512 ±10V BIPOLAR ANALOG INPUT V+ VREF 15 MSB 4 MAGNITUDE BITS AD7533 14 16 1 RFEEDBACK OUT1 OUT2 DIGITAL INPUT 13 LSB 3 2 10K 10K - 5K 6 + 6 + 1/ IH5140 2 GND SIGN BIT FIGURE 4. 10-BIT AND SIGN MULTIPLYING DAC 10-13 VOUT AD7523, AD7533 Gain Adjustment Offset Adjustment 1. Adjust VREF to approximately +10V. 1. Connect all digital inputs to V+. 2. Connect all digital inputs to “Logic 1”. 2. Monitor VOUT for a -VREF (1 - 2-9) volts reading. 3. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at IOUT2 amplifier output. 3. To increase VOUT , connect a series resistor of up to 250Ω between VOUT and RFEEDBACK . 4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”. 4. To decrease VOUT , connect a series resistor of up to 250Ω between the reference voltage and the VREF terminal. 5. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV at VOUT . CALIBRATE 10K 4.7K 6.8V (2) A2 6 + +15V VDD NC MSB 15 4 14 AD7523/ AD7533 DIGITAL FREQUENCY CONTROL WORD LSB 3 SQUARE WAVE 10K 1% 10K 1% 16 C1 1 OUT1 TRIANGULAR WAVE A1 6 + OUT2 13 - 1K 2 FIGURE 5. PROGRAMMABLE FUNCTION GENERATOR VREF +15V VIN RFB 16 14 2 4 AD7523/ AD7533 1 11 15 3 OUT2 OUT1 +15V BIT 1 MSB LSB DIGITAL INPUT “D” BIT 8 (10) (AD7533) VREF BIT 1 MSB DIGITAL INPUT “D” LSB BIT 8 (10) (AD7533) 15 4 R1 6 + 14 16 AD7523/ AD7533 1 - 13 6 + 3 2 R2 6 + VOUT VOUT = -VIN/D Where: Bit 8 Bit 1 Bit 2 D = ------------- + ------------- + … ------------2 2 1 2 2 2 0 ≤ D ≤ 255 ---------- 256 R2 R1 D VO UT = V REF --------------------- – ---------------------- R1 + R2 R1 + R2 Bit 8 Bit 1 Bit 2 Where D = ------------ + ------------ + … -----------8 1 2 2 2 2 0 ≤ D ≤ 255 ---------- 256 FIGURE 6. DIVIDER (DIGITALLY CONTROLLED GAIN) FIGURE 7. MODIFIED SCALE FACTOR AND OFFSET 10-14 VOUT AD7523, AD7533 Die Characteristics DIE DIMENSIONS: PASSIVATION: 101 mils x 103 mils (2565micrms x 2616micrms) Type: PSG/Nitride PSG: 7 ±1.4kÅ Nitride: 8 ±1.2kÅ METALLIZATION: Type: Pure Aluminum Thickness: 10 ±1kÅ PROCESS: CMOS Metal Gate Metallization Mask Layout AD7523, AD7533 PIN 7 BIT 4 PIN 6 BIT 3 PIN 5 BIT 2 PIN 4 BIT 1 (MSB) PIN 3 GND PIN 2 IOUT2 PIN 8 BIT 5 PIN 1 IOUT1 PIN 9 BIT 6 PIN 10 BIT 7 PIN 16 RFEEDBACK PIN 11 BIT 8 (LSB) PIN 15 VREF NC (PIN 12, BIT 9, AD7533) NC NC (PIN 13, BIT 10, AD7533) 10-15 NC PIN 14 V+ AD7523, AD7533 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 10-16 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029