SiP12109 Datasheet

SiP12109
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Vishay Siliconix
4 A, 4.5 V to 15 V Input
Synchronous Buck Regulator
DESCRIPTION
FEATURES
The SiP12109 is a high frequency current-mode constant
on-time (CM-COT) synchronous buck regulator with
integrated high-side and low-side power MOSFETs. Its
power stage is capable of supplying 4 A continuous current
at 1.5 MHz switching frequency. This regulator produces an
adjustable output voltage down to 0.6 V from 4.5 V to 15 V
input rail to accommodate a variety of applications,
including computing, consumer electronics, telecom, and
industrial.
•
•
•
•
SiP12109’s CM-COT architecture delivers ultra-fast
transient response with minimum output capacitance and
tight ripple regulation at very light load. The part is stable
with any capacitor type and no ESR network is required for
loop stability. The device also incorporates a power saving
scheme that significantly increases light load efficiency.
• Ultrafast transient response
The regulator integrates a full protection feature set,
including output overvoltage protection (OVP), output under
voltage protection (UVP) and thermal shutdown (OTP). It
also has UVLO for input rail and internal soft-start ramp.
• PGOOD Indicator
4.5 V to 15 V input voltage
Adjustable output voltage down to 0.6 V
4 A continuous output current
Selectable switching frequency from 400 kHz to
1.5 MHz with an external resistor
• 95 % peak efficiency
• Stable with any capacitor. No external ESR network
required
•
•
•
•
Power saving scheme for increased light load efficiency
± 1 % accuracy of VOUT setting
Cycle-by-cycle current limit
Fully protected with OTP, SCP, UVP, OVP
• -40 °C to +125 °C operating junction temperature
• Output voltage tracking
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
The SiP12109 is available in lead (Pb)-free power enhanced
3 mm x 3 mm QFN-16 package.
APPLICATIONS
• Point of load regulation for low-power processors,
network processors, DSPs, FPGAs, and ASICs
• Low voltage, distributed power architectures with 5 V
or 12 V rails
• Computing, broadband, networking, LAN/WAN, optical,
test and measurement
• A/V, high density cards, storage, DSL, STB, DVR, DTV,
Industrial PC
TYPICAL APPLICATION CIRCUIT
ENABLE
POWER GOOD
INPUT = 4.5 V to 15 V
PGOOD
EN
BOOT
VOUT
VI N
LX
SS
VFB
VCC
COMP
PG N D
AG N D
RO N
Fig. 1 - Typical Application Circuit for SiP12109
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
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SiP12109
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ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKING
(LINE 2: P/N)
SiP12109DMP-T1-GE4
QFN16 3x3
2109
N/A
-
SiP12109DB
Note
• “DB” means demo board

MARKING
P/N
FYWLL
Format:
Line 1: Dot
Line 2: P/N
Line 3: Siliconix Logo + ESD Symbol
Line 4: Factory Code + Year Code + Work Week Code + LOT Code
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
CONDITIONS
LIMIT
VIN
Reference to PGND
-0.3 to 16
VCC
Reference to AGND
-0.3 to 6
LX
Reference to PGND
-0.3 to 16
LX (AC)
100 ns
Boot
V
-0.3 to VIN + VCC
AGND to PGND
All Logic Inputs
17
UNIT
-0.3 to +0.3
Reference to AGND
-0.3 to VCC + 0.3
TEMPERATURE
Max. Operating Junction Temperature
-40 to 150
Storage Temperature
-65 to 150
°C
POWER DISSIPATION
Junction to Ambient Thermal Impedance
(RthJA)
Maximum Power Dissipation
36.3
Ambient Temperature = 25 °C
3.4
Ambient Temperature = 100 °C
1.3
HBM
2
°C/W
W
ESD PROTECTION
kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
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SiP12109
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RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V)
ELECTRICAL PARAMETER
MINIMUM
TYPICAL
MAXIMUM
VIN
4.5
-
15
VCC
4.5
-
5.5
LX
-1
-
15
VOUT
0.6
-
5.5
UNIT
V
TEMPERATURE
Recommended Ambient Temperature
-40 to 85
Operating Junction Temperature
-40 to 125
°C
ELECTRICAL SPECIFICATIONS (test condition unless otherwise specified)
LIMITS
SYMBOL
TEST CONDITION
VIN = 12 V, TA = -40 °C to 85 °C
MIN.
Power Input Voltage Range
VIN
Note 1
4.5
-
15
VCC Regulator Voltage
VCC
4.5
5
5.5
-
1.2
-
mA
μA
PARAMETER
TYP.
MAX.
UNIT
POWER SUPPLY
Input Current
IVIN_NOLOAD
TA = 25 °C, Ron = 75 k,
Non-switching, IO = 0 A
V
Shutdown Current
IVIN_SHDN
EN = 0 V
-
5
8
VCC UVLO Threshold
VCC_UVLO
VCC rising
2.3
2.55
2.8
V
VCC UVLO Hysteresis
VCC_UVLO_HYS
-
300
-
mV
CONTROLLER AND TIMING
Feedback Reference
VFB
TA = 25 °C
0.596
0.600
0.604
TA = -40 °C to +85 °C
0.594
0.600
0.606
V
VFB Input Bias Current
IFB
-
2
200
nA
Transconductance
gm
-
1
-
mS
ICOMP_SOURCE
-
50
-
ICOMP_SINK
-
50
-
COMP Source Current
COMP Sink Current
On-Time
tON
100
135
170
Minimum Off-Time
tOFF_MIN.
Ron = 75 k
145
200
255
Soft Start Current
ISS
3
5
7
-
45
67
-
27
41
4
5
6
-
21
-
-
-65
-
Rising temperature
-
160
-
Hysteresis
-
35
-
VFB_RISING_VTH_OV
VFB rising above 0.6 V reference
-
21
-
VFB_FALLING_VTH_UV
VFB falling below 0.6 V reference
-
-12.5
-
μA
ns
μA
POWER MOSFETS
High-Side On Resistance
RON_HS
Low-Side On Resistance
RON_LS
VGS = 5 V
m
FAULT PROTECTIONS
Over Current Limit
IOCP
Output OVP Threshold
VFB_OVP
Output UVP Threshold
VFB_UVP
Over Temperature Protection
Inductor valley current
VFB with respect to 0.6 V reference
A
%
°C
POWER GOOD
Power Good Output Threshold
%
Power Good On Resistance
RON_PGOOD
-
30
60

Power Good Delay Time
tDLY_PGOOD
-
5
-
μs
Logic High Level
VEN_H
1.5
-
-
Logic Low Level
VEN_L
-
-
0.4
ENABLE THRESHOLD
V
Note
(1) Tie V
CC to VIN when VIN is < 5.5 V.
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
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SiP12109
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FUNCTIONAL BLOCK DIAGRAM
COMP
VCC
PGOOD
EN
VIN
BOOT
AGND
OTP
VCC
VCC
0.6V
REFERENCE
5V
Regulator
UVLO
5uA
SOFT
START
SS
VFB
+
ON-TIME
GENERATOR
-
Isense
LX
VIN
+
+ OTA
CONTROL
LOGIC
SECTION
ANTIXCOND
CONTROL
LX
VCC
LX
PWM
COMPARATOR
I-V
Converter
ZCD
PGND
RON
+
0.45V
VFB
OCP
PGND
UV Comparator
Current
Mirror
+
-
PAD
OV Comparator
Isense
0.72V
Fig. 2 - SiP12109 Functional Block Diagram
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
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SiP12109
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PGND
PGND
16
15
14
Boot
VIN
PIN CONFIGURATION
13
VIN
1
12
LX
VCC
2
11
LX
AGND
3
10
LX
RON
4
PGND
5
6
7
8
COMP
VFB
SS
EN
9
PGOOD
Fig. 3 - SiP12109 Pin Configuration (Top View)

PIN CONFIGURATION
PIN NUMBER
NAME
1, 16
VIN
Input supply voltage for power MOS. VIN = 4.5 V to 15 V
FUNCTION
2
VCC
Internal regulator output, tie VCC to VIN when VIN is < 5.5 V
3
AGND
Analog ground
4
RON
5
COMP
6
VFB
Feedback voltage. 0.6 V (typ.). Use a resistor divider between VOUT and AGND to set the output voltage.
7
SS
An external capacitor between SS and AGND sets the soft start time.
8
EN
9
PGOOD
10, 11, 12
LX
An external resistor between RON and AGND sets the switching on time.
Connect to an external RC network for loop compensation and droop function.
Enable pin. Pull enable above 1.5 V to enable and below 0.4 V to disable the part. Do not float this pin.
Power good output. Open drain.
Switching node, inductor connection point
13
BOOT
Bootstrap pin - connect a capacitor of at least 100 nF from BOOT to LX to develop the floating supply
for the high-side gate drive.
14, 15, PAD
PGND
Power ground
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
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ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, Fsw = 1 MHz, L0 = 1 μH, C0 = 3 x 22 μF, unless noted otherwise)
100
90
80
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.2 V
70
CH4
60
CH3
50
40
30
20
CH1
10
0
0
0.5
1
1.5
2
IOUT (A)
2.5
3
3.5
4
Fig. 4 - Efficiency vs. IOUT
Fig. 7 - Steady-State, IOUT = 0 A
CH1 (BRN) = LX (5 V/div), CH3 (BLU) = VOUT (20 mV/div),
CH4 (GRN) = ICOIL (1 A/div), Time = 5 μs/div
1
0.8
Load Regulation (%)
0.6
0.4
VOUT = 3.3 V
0.2
CH3
0
- 0.2
VOUT = 1.2 V
CH4
- 0.4
- 0.6
CH1
- 0.8
-1
0
0.5
1
1.5
2
I OUT (A)
2.5
3
3.5
4
Fig. 8 - Steady-State, IOUT = 4 A
CH1 (BRN) = LX (5 V/div), CH3 (BLU) = VOUT (20 mV/div),
CH4 (GRN) = ICOIL (1 A/div), Time = 1 μs/div
Fig. 5 - Load Regulation vs. IOUT
1000
VOUT = 3.3 V
Switching Freqnecy (kHz)
900
800
VOUT =1.2 V
700
CH3
600
500
400
300
200
100
CH4
0
0
0.5
1
1.5
2
I OUT (A)
2.5
3
Fig. 6 - Frequency Variation vs. IOUT
S13-2479-Rev. A, 16-Dec-13
3.5
4
Fig. 9 - Load Step Undershoot Response, IOUT = 0 A to 4 A
CH3 (BLU) = VOUT (100 mV/div),
CH4 (GRN) = LX (5 V/div), Time = 10 μs/div
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CH4
CH3
CH3
CH4
CH1
CH1
Fig. 13 - Start-Up, IOUT = 0 A
CH1 (BRN) = LX (5 V/div), CH3 (BLU) = VOUT (1 V/div),
CH4 (GRN) = EN (5 V/div), Time = 1 ms/div
Fig. 10 - Steady-State, IOUT = 0 A
CH1 (BRN) = LX (5 V/div), CH3 (BLU) = VOUT (20 mV/div),
CH4 (GRN) = ICOIL (1 A/div), Time = 5 ms/div
CH3
CH3
CH4
CH1
CH4
Fig. 14 - Start-Up, IOUT = 4 A
CH1 (BRN) = LX (5 V/div), CH3 (BLU) = VOUT (1 V/div),
CH4 (GRN) = EN (5 V/div), Time = 1 ms/div
Fig. 11 - Load Step Overshoot Response, IOUT = 4 A to 0 A
CH3 (BLU) = VOUT (100 mV/div),
CH4 (GRN) = LX (5 V/div), Time = 10 μs/div
CH3
CH3
CH4
CH4
Fig. 12 - Load Step Undershoot Response, IOUT = 0 A to 2 A
CH3 (BLU) = VOUT (100 mV/div),
CH4 (GRN) = LX (5 V/div), Time = 10 μs/div
S13-2479-Rev. A, 16-Dec-13
Fig. 15 - Load Step Overshoot Response, IOUT = 2 A to 0 A
CH3 (BLU) = VOUT (100 mV/div),
CH4 (GRN) = LX (5 V/div), Time = 10 μs/div
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CH3
CH4
CH4
CH1
CH3
CH1
Fig. 16 - Shut-Down, IOUT = 0 A
CH1 (BRN) = LX (5 V/div), CH3 (BLU) = VOUT (1 V/div),
CH4 (GRN) = EN (5 V/div), Time = 1 ms/div
Fig. 18 - Over Current Protection, IOUT = 5.9 A; IVALLEY = 5.2 A
CH1 (BRN) = ICOIL (1 A/div), CH3 (BLU) = VOUT (200 mV/div),
CH4 (GRN) = LX (5 V/div), Time = 500 μs/div
CH3
CH4
CH4
CH1
CH3
CH1
Fig. 17 - Shut-Down, IOUT = 4 A
CH1 (BRN) = LX (5 V/div), CH3 (BLU) = VOUT (1 V/div),
CH4 (GRN) = EN (5 V/div), Time = 1 ms/div
S13-2479-Rev. A, 16-Dec-13
Fig. 19 - Over Current Protection, IOUT = 5.9 A; IVALLEY = 5.2 A
CH1 (BRN) = ICOIL (1 A/div), CH3 (BLU) = VOUT (200 mV/div),
CH4 (GRN) = LX (5 V/div), Time = 10 μs/div
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OPERATIONAL DESCRIPTION
Device Overview
Power Stage
SiP12109 is a high-efficiency monolithic synchronous buck
regulator capable of delivering up to 4 A continuous current.
The device has programmable switching frequency up to
1.5 MHz. The control scheme is based on current-mode
constant-on-time architecture, which delivers fast transient
response and minimizes external components. Thanks to
the internal current ramp information, no high-ESR output
bulk or virtual ESR network is required for the loop stability.
This device also incorporates a power saving feature by
enabling diode emulation mode and frequency foldback as
load decreases.
SiP12109 integrates a high-performance power stage with
a ~ 45 m high side n-channel MOSFET and a ~ 27 m low
side n-channel MOSFET. The MOSFETs are optimized to
achieve 95 % efficiency at up to 1.5 MHz MHz switching
frequency.
SiP12109 has a full set of protection and monitoring
features:
- Over current protection in pulse-by-pulse mode
- Output over voltage protection
- Output under voltage protection with device latch
- Over temperature protection with hysteresis
- Dedicated enable pin for easy power sequencing
- Power good open drain output
This device is available in QFN16 3x3 package to deliver
high power density and minimize PCB area.
The power input voltage (VIN) can go up to 15 V and down
as low as 4.5 V for the power conversion. The logic bias
voltage (VCC) ranges from 4.5 V to 5.5 V.
PWM Control Mechanism
SiP12109 employs a state-of-the-art current-mode COT
control mechanism. During steady-state operation, output
voltage is compared with internal reference (0.6 V typ.) and
the amplified error signal (VCOMP) is generated on the COMP
pin. In the meantime, inductor valley current is sensed, and
its slope (Isense) is converted into a voltage signal (Vcurrent) to
be compared with VCOMP. Once Vcurrent is lower than VCOMP,
a single shot on-time is generated for a fixed time
programmed by the external RON. Figure 20 illustrates the
basic block diagram for CM-COT architecture and figure 21
demonstrates the basic operational principle:

RON
VOUT
Bandgap
0.8 V
Vref
HG
+
OTA
VIN
-
VIN
Vcomp
HG
ON-TIME
Generator
Control
Logic &
MOSFET
Driver
LG
+
-
+
Current
Mirror
Isense I-AMP
-
Vcurrent
PWM
COMPARATOR
LS FET
LG
Fig. 20 - CM-COT Block Diagram
S13-2479-Rev. A, 16-Dec-13
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Vcurrent
vcomp
Fixed ON-time
PWM
Fig. 21 - CM-COT Operational Principle
The following equation illustrates the relationship between
on-time, VIN, VOUT and RON value:
1
TON = RON x K x
VIN
Once on-time is set, the pseudo constant frequency is then
determined by the following equation:
D
ࢌ sw =
=
TON
-12
, where K = 17.5 x 10 is a
constant set internally


VOUT
VIN
1
x RON x K
VIN
=
VOUT
RON x K
Loop Stability and Compensator Design
Due to the nature of current mode control, a simple RC network (type II compensator) is required between COMP and AGND for
loop stability and transient response purpose. The general concept of this loop design is to introduce a single zero through the
compensator to determine the crossover frequency of overall close loop system.
The overall loop can be broken down into following segments.
Output feedback divider transfer function HfbZ:
R fb2
H fb = -----------------------------R fb1 x R fb2
Voltage compensator transfer function GCOMP (s):
R O x  1 + sC COMP R COMP 
G COMP (s) = ------------------------------------------------------------------------- gm
 1 + sR O C COMP 
Modulator transfer function Hmod (s):
R load x  1 + sC O R ESR 
1
H mod (s) = ----------------------------------- x -------------------------------------------------------------AV 1 x R DS(on)
 1 + sC O R load 
The complete loop transfer function is given by:
R fb2
R O x  1 + sC COMP R COMP 
R load x  1 + sC O R ESR 
1
H mod (s) = ------------------------------ x -------------------------------------------------------------------------gm x ----------------------------------- x -------------------------------------------------------------R fb1 x R fb2
 1 + sR O C COMP 
AV 1 x R DS(on)
 1 + sC O R load 
When:
CCOMP = Compensation capacitor
RDS(on) = LS switch resistance
RCOMP = Compensation resistor
Rfb1
= Feedback resistor connect to LX
gm
= Error amplifier transconductance
Rfb2
= Feedback resistor connect to ground
Rload
= Load resistance
RO
= Output impedance of error amplifier = 20 M
CO
= Output capacitor
AV1
= Voltage to current gain = 3
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
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Light Load Operation
To further improve efficiency at light-load condition,
SiP12109 provides a set of innovative implementations to
eliminate LS recirculating current and switching losses. The
internal Zero Crossing Detector (ZCD) monitors LX node
voltage to determine when inductor current starts to flow
negatively. In light load operation as soon as inductor
valley current crosses zero, the device first deploys diode
emulation mode by turning off LS FET. If load further
decreases, switching frequency is further reduced
proportional to load condition to save switching losses while
keeping output ripple within tolerance. The switching
frequency is set by the controller to maintain regulation. At
zero load this frequency can go as low as hundreds of Hz.
OUTPUT MONITORING AND PROTECTION FEATURES
Output Over-Current Protection (OCP)
SiP12109 has pulse-by-pulse over-current limit control. The
inductor valley current is monitored during LS FET turn-on
period through RDS(on) sensing. After a pre-defined time, the
valley current is compared with internal threshold (5 A typ.)
to determine the threshold for OCP. If monitored current is
higher than threshold, HS turn-on pulse is skipped and LS
FET is kept on until the valley current returns below OCP
limit.
In the severe over-current condition, pulse-by-pulse current
limit eventually triggers output under-voltage protection
(UVP), which latches the device off to prevent catastrophic
thermal-related failure. UVP is described in the next section.
OCP is enabled immediately after VCC passes UVLO level.
OCPthreshold
Iload
Iinductor
GH
Skipped GH Pulse
Fig. 22 - Over-Current Protection Illustration
Output Under-Voltage Protection (UVP)
Over-Temperature Protection (OTP)
UVP is implemented by monitoring output through VFB pin.
Once the voltage level at VFB is below 0.2 V for more than
20 μs, then UVP event is recognized and both HS and LS
MOSFETs are turned off. UVP latches the device off until
either VCC or EN is recycled.
SiP12109 has internal thermal monitor block that turns off
both HS and LS FETs when junction temperature is above
160 °C (typ.). A hysteresis of 30 °C is implemented, so when
junction temperature drops below 130 °C, the device
restarts by initiating the soft-start sequence again.
UVP is only active after the completion of soft-start
sequence.
Soft Start up
For OVP implementation, output is monitored through
VFB pin. After soft-start, if the voltage level at VFB is above
21 % (typ.), OVP is triggered with HS FET turning off and
LS FET turning on immediately to discharge the output.
Normal operation is resumed once VFB drops back to
0.675 V.
SiP12109 soft-start time is adjustable by selecting a
capacitor value from the following equation. Once VCC is
above UVLO level (2.55 V typ.), VOUT will ramp up slowly,
rising monotonically to the programmed output voltage.
There is an internal 5 μA current source tied to the soft start
pin which charges the external soft start cap
Cext x 0.8 V
SS time =
5 μA
OVP is active immediately after VCC passes UVLO level.



During soft-start period, OCP is activated. OVP and
short-circuit protection are not active until soft-start is
complete.

Output Over-Voltage Protection (OVP)
S13-2479-Rev. A, 16-Dec-13
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Power Good (PGOOD)
Pre-bias Startup
In case of pre-bias startup, output is monitored through
VFB pin. If the sensed voltage on VFB is higher than the
internal reference ramp value, control logic prevents HS and
LS FET from switching to avoid negative output voltage
spike and excessive current sinking through LS FET.
VFB_Rising_Vth_OV
(Typ. = 0.725V)
SiP12109’s Power Good is an open-drain output. Pull
PGOOD pin high up to 5 V through a 10K resistor to use this
signal. Power good window is shown in the below diagram.
If voltage level on VFB pin is out of this window, PGOOD
signal is de-asserted by pulling down to GND.
VFB_Falling_Vth_OV
(Typ. = 0.675V)
Vref (0.6V)
VFB
VFB_Falling_Vth_UV
(Typ. = 0.525V)
VFB_Rising_Vth_UV
(Typ. = 0.575V)
Pull-high
PG
Pull-low
Fig. 23 - PGOOD Window and Timing Diagram
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
12
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12109
www.vishay.com
Vishay Siliconix
VIN
VIN_GND
C5
Vcc
C7
2.2u
R1
75k
1
2
3
4
Vin1
Vcc
AGND
Ron
R3
6.04k
C9
0.47nF
GMO
16
Vin2
15
PGND2
SS
IC1
SiP12109
Vfb
C8
10n
7
0.1uF
EN
PGD
6
C4
22uF
1
1
5
1
17
PGND0
R5
100k
14
PGND1
8
PGOOD
13
BOOT
LX3
LX2
LX1
EN
EN
R2 0
12
11
10
9
C6
0.1uF
PGD
L1
1uH
Vcc
R4
100k
C1
22uF
C2
22uF
C3
VOGND
0.1uF
R6
5k11
R7
5k11
1
VOUT
J2
J3
VO_GND
1
J1
J4
EN
PGD
J5
J6
1
Fig. 24 - Reference Board Schematic
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
13
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12109
www.vishay.com
Vishay Siliconix
BILL of MATERIAL
ITEM QTY
REFERENCE
VALUE
VOLTAGE
FOOTPRINT
PART NUMBER
MANUFACTURER
1
3
C1, C5, C6
0.1 μF
35 V
C0402-TDK
GMK105BJ104KV-F
Taiyo Yuden
2
2
C2, C3
22 μF
10 V
C0805-TDK
LMK212BJ226MG-T
Taiyo Yuden
3
1
C4
22 μF
35 V
C0805-TDK
C2012X5R1V226M125AC
TDK
4
1
C7
2.2 μF
16 V
C0603-TDK
C0603C225K4PACTU
Kemet
5
1
C8
10 nF
16 V
C0402-TDK
CC0402KRX7R7BB103
Yageo
6
1
C9
0.47 nF
50 V
C0402-TDK
C1005C0G1H471J050BA
TDK
7
1
IC1
SiP12109
-
QFN16 3 x 3
SiP12109DMP-T1-GE4
Vishay
8
6
J1, J2, J3, J4,
J5, J6
VIN, VOUT, VO_GND,
VIN_GND, EN, PGD
-
TP30
2108-2-00-44-00-00-07
Mill-Max
9
1
L1
1 μH
-
IHLP1616
IHLP1616BZER1R0M11
Vishay
10
1
R1
75k
-
R0402-Vishay
CRCW040275K0FKEDHP
Vishay
11
1
R2
0
-
R0402-Vishay
RCG04020000Z0ED
Vishay
12
1
R3
6.04k
-
R0402-Vishay
CRCW04026K04FKED
Vishay
13
2
R4, R5
100k
-
R0402-Vishay
CRCW0402100KFKED
Vishay
14
2
R6, R7
5k11
-
R0402-Vishay
CRCW04025K11FKED
Vishay
PCB LAYOUT OF REFERENCE BOARD
Fig. 25 - Top Layer
Fig. 27 - Bottom Layer
Fig. 26 - Inner Layer1
Fig. 28 - Inner Layer2
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
14
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12109
www.vishay.com
Vishay Siliconix
CASE OUTLINE
(5)
(4)
MILLIMETERS (1)
INCHES
DIMENSION
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.75
0.85
0.95
0.029
0.033
0.037
A1
0
-
0.05
0
-
0.002
0.30
0.007
1.7
0.059
A3
b
0.20 REF
0.18
D
D2
0.25
0.008 REF
3.00 BSC
1.5
1.6
0.010
0.012
0.118 BSC
0.063
e
0.50 BSC
0.020 BSC
E
3.00 BSC
0.118 BSC
0.067
E2
1.5
1.6
1.7
0.059
0.063
0.067
L
0.3
0.4
0.5
0.012
0.016
0.020
N (3)
16
16
Nd (3)
4
4
Ne (3)
4
4
Notes
(1) Use millimeters as the primary measurement.
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
(3) N is the number of terminals. Nd and Ne is the number of terminals in each D and E site respectively.
(4) Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip.
(5) The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body.
(6) Package warpage max. 0.05 mm.
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
15
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12109
www.vishay.com
Vishay Siliconix
RECOMMENDED LAND PATTERN FOR QFN16 3 mm x 3 mm
DIMENSION ARE IN MILLIMETERS
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Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62694.
S13-2479-Rev. A, 16-Dec-13
Document Number: 62694
16
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 02-Oct-12
1
Document Number: 91000