SiP12110 www.vishay.com Vishay Siliconix 6 A, 4.5 V to 15 V Input Synchronous Buck Regulator DESCRIPTION FEATURES The SiP12110 is a high frequency current-mode constant on-time (CM-COT) synchronous buck regulator with integrated high-side and low-side power MOSFETs. Its power stage is capable of supplying 6 A continuous current at 1.0 MHz switching frequency. This regulator produces an adjustable output voltage down to 0.6 V from 4.5 V to 15 V input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. • • • • SiP12110’s CM-COT architecture delivers ultrafast transient response with minimum output capacitance and tight ripple regulation at very light load. The part is stable with any capacitor type and no ESR network is required for loop stability. The device also incorporates a power saving scheme that significantly increases light load efficiency. • Ultrafast transient response The regulator integrates a full protection feature set, including output overvoltage protection (OVP), output under voltage protection (UVP) and thermal shutdown (OTP). It also has UVLO for input rail and internal soft-start ramp. • PGOOD indicator 4.5 V to 15 V input voltage Adjustable output voltage down to 0.6 V 6 A continuous output current Selectable switching frequency from 400 kHz to 1.0 MHz with an external resistor • 95 % peak efficiency • Stable with any capacitor. No external ESR network required • • • • Power saving scheme for increased light load efficiency ± 1 % accuracy of VOUT setting Cycle-by-cycle current limit Fully protected with OTP, SCP, UVP, OVP • -40 °C to +125 °C operating junction temperature • Output voltage tracking • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 The SiP12110 is available in lead (Pb)-free power enhanced 3 mm x 3 mm QFN-16 package. APPLICATIONS • Point of load regulation for low-power processors, network processors, DSPs, FPGAs, and ASICs • Low voltage, distributed power architectures with 5 V or 12 V rails • Computing, broadband, networking, LAN / WAN, optical, test and measurement • A/V, high density cards, storage, DSL, STB, DVR, DTV, Industrial PC TYPICAL APPLICATION CIRCUIT Enable Power good Input = 4.5 V to 15 V PGOOD EN BOOT VOUT VIN LX SS VFB VCC PGND COMP AGND RON Fig. 1 - Typical Application Circuit for SiP12110 S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix ORDERING INFORMATION PART NUMBER PACKAGE SiP12110DMP-T1-GE4 QFN16 3x3 SiP12110DB MARKING (LINE 2: P/N) 2110 Reference board MARKING P/N FYWLL Format: Line 1: Dot Line 2: P/N Line 3: Siliconix logo + ESD symbol Line 4: Factory code + year code + work week code + LOT code ABSOLUTE MAXIMUM RATINGS ELECTRICAL PARAMETER CONDITIONS LIMIT VIN Reference to PGND -0.3 to +16 VCC Reference to AGND -0.3 to +6 LX Reference to PGND -1 to +16 100 ns; reference to PGND -2 to +17 LX (AC voltage) 10 ns; reference to PGND BOOT V -0.3 to VIN + VCC AGND to PGND All Logic Inputs and Outputs (RON, COMP, VFB, SS, EN, PGOOD) -6 to +17 UNIT -0.3 to +0.3 Reference to AGND -0.3 to VCC +0.3 TEMPERATURE Max. Operating Junction Temperature -40 to +150 Storage Temperature -65 to +150 °C POWER DISSIPATION Junction to Ambient Thermal Impedance (RthJA) Maximum Power Dissipation 36.3 Ambient temperature = 25 °C 3.4 Ambient temperature = 100 °C 1.3 Human body model, JESD22-A114 2 °C/W W ESD PROTECTION Electrostatic Discharge Protection kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V) ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM VIN 4.5 - 15 VCC 4.5 - 5.5 VOUT 0.6 - 5.5 UNIT V TEMPERATURE Recommended Ambient Temperature -40 to 85 Operating Junction Temperature -40 to 125 °C ELECTRICAL SPECIFICATIONS (test condition unless otherwise specified) LIMITS SYMBOL TEST CONDITION VIN = 12 V, TA = -40 °C to 85 °C MIN. Power Input Voltage Range VIN Note 1 4.5 - 15 VCC Regulator Voltage VCC 4.5 5 5.5 - 1.2 - mA μA PARAMETER TYP. MAX. UNIT POWER SUPPLY Input Current IVIN_NOLOAD TA = 25 °C, Ron = 75 kΩ, Non-switching, IO = 0 A V Shutdown Current IVIN_SHDN EN = 0 V - 5 8 VCC UVLO Threshold VCC_UVLO VCC rising 2.3 2.55 2.8 V VCC UVLO Hysteresis VCC_UVLO_HYS - 300 - mV TA = 25 °C 0.596 0.600 0.604 TA = -40 °C to +85 °C 0.594 0.600 0.606 CONTROLLER AND TIMING Feedback Reference VFB V VFB Input Bias Current IFB - 2 200 nA Transconductance gm - 1 - mS ICOMP_SOURCE - 50 - ICOMP_SINK - 50 - COMP Source Current COMP Sink Current On-Time tON 100 135 170 Minimum Off-Time tOFF_MIN. Ron = 75 kΩ 145 200 255 Soft Start Current ISS 3 5 7 - 45 67 - 27 41 μA ns μA POWER MOSFETS High-Side On Resistance RON_HS Low-Side On Resistance RON_LS VGS = 5 V mΩ FAULT PROTECTIONS Over Current Limit IOCP Output OVP Threshold VFB_OVP Output UVP Threshold VFB_UVP Over Temperature Protection Inductor valley current - 7.5 - - 21 - - -65 - Rising temperature - 160 - Hysteresis - 35 - VFB with respect to 0.6 V reference A % °C POWER GOOD Power Good Output Threshold VFB_RISING_VTH_OV VFB rising above 0.6 V reference - 21 - VFB_FALLING_VTH_UV VFB falling below 0.6 V reference - -12.5 - % Power Good On Resistance RON_PGOOD - 30 60 Ω Power Good Delay Time tDLY_PGOOD - 5 - μs Logic High Level VEN_H 1.5 - - Logic Low Level VEN_L - - 0.4 ENABLE THRESHOLD V Note (1) Tie V CC to VIN when VIN < 5.5 V. S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VCC COMP PGOOD EN VIN BOOT AGND OTP VCC VCC 0.6 V reference 5V regulator UVLO 5 μA Soft start SS VFB LX VIN + + OTA Control logic sectionl + On-time generator - AntiXCOND control LX PWM comparator I-V converter Isense LX VCC - ZCD PGND RON - OCP PGND + UV comparator 0.45 V VFB Current mirror + - PAD Isense OV comparator 0.72 V Fig. 2 - SiP12110 Functional Block Diagram VIN 1 VCC 2 PGND 14 BOOT VIN 15 13 PGND 3 12 LX 11 LX 10 LX 9 5 6 7 8 SS EN 4 VFB RON 16 COMP AGND PGND PIN CONFIGURATION PGOOD Fig. 3 - SiP12110 Pin Configuration (Top View) PIN CONFIGURATION PIN NUMBER NAME 1, 16 VIN Input supply voltage for power MOS. VIN = 4.5 V to 15 V FUNCTION 2 VCC Internal regulator output, tie VCC to VIN when VIN < 5.5 V 3 AGND Analog ground 4 RON An external resistor between RON and AGND sets the switching on time. 5 COMP 6 VFB Connect to an external RC network for loop compensation and droop function. Feedback voltage. 0.6 V (typ.). Use a resistor divider between VOUT and AGND to set the output voltage. 7 SS An external capacitor between SS and AGND sets the soft start time. 8 EN Enable pin. Pull enable above 1.5 V to enable and below 0.4 V to disable the part. Do not float this pin. 9 PGOOD 10, 11, 12 LX 13 BOOT Bootstrap pin - connect a capacitor of at least 100 nF from BOOT to LX to develop the floating supply for the high-side gate drive. 14, 15, PAD PGND Power ground S14-1891-Rev. A, 15-Sep-14 Power good output. Open drain. Switching node, inductor connection point Document Number: 64299 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 12 V, VOUT = 1.2 V, L = 1.5 μH, C = 3 x 22 μF, unless otherwise noted) 100 1.6 90 1.2 VOUT = 5 V 80 0.8 Load Regulation (%) VOUT = 1.2 V Efficiency (%) 70 60 50 0.4 -0.4 40 -0.8 30 -1.2 20 VOUT = 5 V 0 VOUT = 1.2 V -1.6 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 0.0 0.6 1.2 1.8 IOUT (A) 3.0 3.6 IOUT (A) 4.2 4.8 5.4 6.0 Fig. 7 - Load Regulation vs. IOUT Fig. 4 - Efficiency vs. IOUT 1600 1.6 1400 1.4 VOUT = 1.2 V 1200 VOUT = 5 V 1000 VEN_H EN Threshold Voltage, VEN (V) Switching Frequency, FSW (kHz) 2.4 800 600 400 1.2 1.0 VEN_L 0.8 0.6 0.4 200 0.2 0 0.0 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 -60 -40 -20 IOUT (A) Fig. 5 - Frequency Variation vs. IOUT 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 8 - EN Threshold vs. Temperature CH2 CH2 CH3 CH3 CH1 CH1 Fig. 6 - Steady-State, IOUT = 0 A CH1 (BRN) = LX (10 V/div), CH3 (BLU) = VOUT (20 mV/div), CH2 (RED) = ICOIL (1 A/div), Time = 10 μs/div S14-1891-Rev. A, 15-Sep-14 Fig. 9 - Steady-State, IOUT = 6 A CH1 (BRN) = LX (10 V/div), CH3 (BLU) = VOUT (20 mV/div), CH2 (RED) = ICOIL (1 A/div), Time = 1 μs/div Document Number: 64299 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix CH3 CH3 CH1 CH1 Fig. 10 - Load Step Undershoot Response, IOUT = 0 A to 6 A CH3 (BLU) = VOUT (500 mV/div), CH1 (BRN) = LX (10 V/div), Time = 20 μs/div Fig. 13 - Load Step Overshoot Response, IOUT = 6 A to 0 A CH3 (BLU) = VOUT (500 mV/div), CH1 (BRN) = LX (10 V/div), Time = 20 μs/div CH2 CH2 CH3 CH3 CH1 CH1 Fig. 11 - Load Step Undershoot Response, IOUT = 0 A to 3 A CH2 (RED) = ICOIL (5 A/div), CH3 (BLU) = VOUT (200 mV/div), CH1 (BRN) = LX (10 V/div), Time = 10 μs/div Fig. 14 - Load Step Overshoot Response, IOUT = 3 A to 0 A CH2 (RED) = ICOIL (5 A/div), CH3 (BLU) = VOUT (200 mV/div), CH1 (BRN) = LX (10 V/div), Time = 10 μs/div CH2 CH3 CH3 CH2 CH1 CH1 Fig. 12 - Start-Up, IOUT = 0 A CH1 (BRN) = LX (10 V/div), CH3 (BLU) = VOUT (0.5 V/div), CH2 (RED) = ICOIL (2 A/div), Time = 200 μs/div S14-1891-Rev. A, 15-Sep-14 Fig. 15 - Start-Up, IOUT = 6 A CH1 (BRN) = LX (10 V/div), CH3 (BLU) = VOUT (0.5 V/div), CH2 (RED) = ICOIL (5 A/div), Time = 500 μs/div Document Number: 64299 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com CH3 Vishay Siliconix CH3 CH2 CH2 CH1 CH1 Fig. 16 - Shut-Down, IOUT = 0 A CH1 (BRN) = LX (10 V/div), CH3 (BLU) = VOUT (0.5 V/div), CH2 (RED) = ICOIL (2 V/div), Time = 5 ms/div CH3 Fig. 18 - Shut-Down, IOUT = 6 A CH1 (BRN) = LX (10 V/div), CH3 (BLU) = VOUT (0.5 V/div), CH2 (RED) = ICOIL (5 A/div), Time = 200 μs/div CH2 CH3 CH1 CH2 CH1 Fig. 17 - Over Current Protection, IVALLEY = 6 A CH2 (RED) = ICOIL (1 A/div), CH3 (BLU) = VOUT (200 mV/div), CH1 (BRN) = LX (10 V/div), Time = 100 μs/div S14-1891-Rev. A, 15-Sep-14 Fig. 19 - Over Current Protection, IVALLEY = 6 A CH2 (RED) = ICOIL (1 A/div), CH3 (BLU) = VOUT (200 mV/div), CH1 (BRN) = LX (10 V/div), Time = 10 μs/div Document Number: 64299 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix OPERATIONAL DESCRIPTION Device Overview Power Stage SiP12110 is a high-efficiency monolithic synchronous buck regulator capable of delivering up to 6 A continuous current. The device has programmable switching frequency up to 1 MHz. The control scheme is based on current-mode constant-on-time architecture, which delivers fast transient response and minimizes external components. Thanks to the internal current ramp information, no high-ESR output bulk or virtual ESR network is required for the loop stability. This device also incorporates a power saving feature by enabling diode emulation mode and frequency foldback as load decreases. SiP12110 integrates a high-performance power stage with a ~ 45 mΩ high side n-channel MOSFET and a ~ 27 mΩ low side n-channel MOSFET. The MOSFETs are optimized to achieve 95 % efficiency at up to 1 MHz switching frequency. SiP12110 has a full set of protection and monitoring features: - Over current protection in pulse-by-pulse mode - Output over voltage protection - Output under voltage protection with device latch - Over temperature protection with hysteresis - Dedicated enable pin for easy power sequencing The power input voltage (VIN) can go up to 15 V and down as low as 4.5 V for the power conversion. The logic bias voltage (VCC) ranges from 4.5 V to 5.5 V. PWM Control Mechanism SiP12110 employs a state-of-the-art current-mode COT control mechanism. During steady-state operation, output voltage is compared with internal reference (0.6 V typ.) and the amplified error signal (VCOMP) is generated on the COMP pin. In the meantime, inductor valley current is sensed, and its slope (Isense) is converted into a voltage signal (Vcurrent) to be compared with VCOMP. Once Vcurrent is lower than VCOMP, a single shot on-time is generated for a fixed time programmed by the external RON. Figure 20 illustrates the basic block diagram for CM-COT architecture and figure 21 demonstrates the basic operational principle: - Power good open drain output This device is available in QFN16 3 x 3 package to deliver high power density and minimize PCB area. VOUT RON Bandgap Vref 0.8 V + OTA - VIN VIN Vcomp HG Current mirror + Isense I-AMP - HG On-time generator + Control logic & MOSFET driver LG Vcurrent PWM comparator LS FET LG Fig. 20 - CM-COT Block Diagram Vcurrent Vcomp Fixed on-time PWM Fig. 21 - CM-COT Operational Principle S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix The following equation illustrates the relationship between on-time, VIN, VOUT and RON value: TON = RON x K x 1 VIN , where K = 17.5 x 10-12 is a constant set internally Once on-time is set, the pseudo constant frequency is then determined by the following equation: V OUT -------------V IN V OUT D ----------------------------------------- = --------------------= f sw = 1 R ON × K t on -------- × R ON × K V IN Loop Stability and Compensator Design Due to the nature of current mode control, a simple RC network (type II compensator) is required between COMP and AGND for loop stability and transient response purpose. The general concept of this loop design is to introduce a single zero through the compensator to determine the crossover frequency of overall close loop system. The overall loop can be broken down into following segments. Output feedback divider transfer function HfbZ: R fb2 H fb = -----------------------------R fb1 x R fb2 Voltage compensator transfer function GCOMP (s): R O x ( 1 + sC COMP R COMP ) G COMP (s) = ------------------------------------------------------------------------- gm ( 1 + sR O C COMP ) Modulator transfer function Hmod (s): R load x ( 1 + sC O R ESR ) 1 H mod (s) = ----------------------------------- x -------------------------------------------------------------( 1 + sC O R load ) AV 1 x R DS(on) The complete loop transfer function is given by: R fb2 R O x ( 1 + sC COMP R COMP ) R load x ( 1 + sC O R ESR ) 1 H mod (s) = ------------------------------ x -------------------------------------------------------------------------gm x ----------------------------------- x -------------------------------------------------------------R fb1 x R fb2 ( 1 + sR O C COMP ) AV 1 x R DS(on) ( 1 + sC O R load ) When: CCOMP = compensation capacitor RDS(on) = LS switch resistance RCOMP = compensation resistor Rfb1 = feedback resistor connect to LX gm = error amplifier transconductance Rfb2 = feedback resistor connect to ground Rload = load resistance RO = output impedance of error amplifier = 20 MΩ CO = output capacitor AV1 = voltage to current gain = 3 Light Load Operation To further improve efficiency at light-load condition, SiP12110 provides a set of innovative implementations to eliminate LS recirculating current and switching losses. The internal zero crossing detector (ZCD) monitors LX node voltage to determine when inductor current starts to flow negatively. In light load operation as soon as inductor valley current crosses zero, the device first deploys diode emulation mode by turning off LS FET. If load further decreases, switching frequency is further reduced proportional to load condition to save switching losses while keeping output ripple within tolerance. The switching frequency is set by the controller to maintain regulation. At zero load this frequency can go as low as hundreds of Hz. OUTPUT MONITORING AND PROTECTION FEATURES Output Over-Current Protection (OCP) SiP12110 has pulse-by-pulse over-current limit control. The inductor valley current is monitored during LS FET turn-on period through RDS(on) sensing. After a pre-defined time, the valley current is compared with internal threshold (7.5 A typ.) to determine the threshold for OCP. If monitored current is higher than threshold, HS turn-on pulse is skipped and LS FET is kept on until the valley current returns below OCP limit. S14-1891-Rev. A, 15-Sep-14 In the severe over-current condition, pulse-by-pulse current limit eventually triggers output under-voltage protection (UVP), which latches the device off to prevent catastrophic thermal-related failure. UVP is described in the next section. OCP is enabled immediately after VCC passes UVLO level. Document Number: 64299 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix OCPthreshold Iload Iinductor GH Skipped GH pulse Fig. 22 - Over-Current Protection Illustration Output Under-Voltage Protection (UVP) Soft Start up UVP is implemented by monitoring output through VFB pin. Once the voltage level at VFB is below 0.2 V for more than 20 μs, then UVP event is recognized and both HS and LS MOSFETs are turned off. UVP latches the device off until either VCC or EN is recycled. SiP12110 soft-start time is adjustable by selecting a capacitor value from the following equation. Once VCC is above UVLO level (2.55 V typ.), VOUT will ramp up slowly, rising monotonically to the programmed output voltage. There is an internal 5 μA current source tied to the soft start pin which charges the external soft start cap UVP is only active after the completion of soft-start sequence. Cext × 0.8 V SS time = --------------------------------5 μA Output Over-Voltage Protection (OVP) For OVP implementation, output is monitored through VFB pin. After soft-start, if the voltage level at VFB is above 21 % (typ.), OVP is triggered with HS FET turning off and LS FET turning on immediately to discharge the output. Normal operation is resumed once VFB drops back to 0.675 V. OVP is active immediately after VCC passes UVLO level. Over-Temperature Protection (OTP) SiP12110 has internal thermal monitor block that turns off both HS and LS FETs when junction temperature is above 160 °C (typ.). A hysteresis of 30 °C is implemented, so when junction temperature drops below 130 °C, the device restarts by initiating the soft-start sequence again. VFB_Rising_Vth_OV (typ. = 0.725 V) During soft-start period, OCP is activated. OVP and short-circuit protection are not active until soft-start is complete. Pre-bias Startup In case of pre-bias startup, output is monitored through VFB pin. If the sensed voltage on VFB is higher than the internal reference ramp value, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. Power Good (PGOOD) SiP12110’s power good is an open-drain output. Pull PGOOD pin high up to 5 V through a 10K resistor to use this signal. power good window is shown in the below diagram. If voltage level on VFB pin is out of this window, PGOOD signal is de-asserted by pulling down to GND. VFB_Falling_Vth_OV (typ. = 0.675 V) Vref (0.6 V) VFB_Falling_Vth_UV (typ. = 0.525 V) VFB VFB_Rising_Vth_UV (typ. = 0.575 V) Pull-high PG Pull-low Fig. 23 - PGOOD Window and Timing Diagram S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix VIN VIN_GND C5 Vcc C7 2.2u R1 75k 1 2 3 4 Vin1 Vcc AGND Ron R3 6.04k C9 0.47nF GMO 16 Vin2 15 PGND2 SS IC1 SiP12110 Vfb C8 10n 7 0.1uF EN PGD 6 C4 22uF 1 1 5 1 17 PGND0 R5 100k 14 PGND1 8 PGOOD 13 BOOT LX3 LX2 LX1 EN EN R2 0 12 11 10 9 C6 0.1uF PGD L1 1uH Vcc R4 100k C1 22uF C2 22uF C3 VOGND 0.1uF R6 5k11 R7 5k11 1 VOUT J2 J3 VO_GND 1 J1 J4 EN PGD J5 J6 1 Fig. 24 - Reference Board Schematic S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix BILL OF MATERIAL ITEM QTY REFERENCE VALUE VOLTAGE FOOTPRINT PART NUMBER MANUFACTURER 1 3 C1, C5, C6 0.1 μF 35 V C0402-TDK GMK105BJ104KV-F Taiyo Yuden 2 2 C2, C3 22 μF 10 V C0805-TDK LMK212BJ226MG-T Taiyo Yuden 3 1 C4 22 μF 35 V C0805-TDK C2012X5R1V226M125AC TDK 4 1 C7 2.2 μF 16 V C0603-TDK C0603C225K4PACTU Kemet 5 1 C8 10 nF 16 V C0402-TDK CC0402KRX7R7BB103 Yageo 6 1 C9 0.47 nF 50 V C0402-TDK C1005C0G1H471J050BA TDK 7 1 IC1 SiP12110 - QFN16 3 x 3 SiP12110DMP-T1-GE4 Vishay 8 6 J1, J2, J3, J4, J5, J6 VIN, VOUT, VO_GND, VIN_GND, EN, PGD - TP30 2108-2-00-44-00-00-07 Mill-Max 9 1 L1 1 μH - IHLP1616 IHLP1616BZER1R0M11 Vishay 10 1 R1 75 kΩ - R0402-Vishay CRCW040275K0FKEDHP Vishay 11 1 R2 0 - R0402-Vishay RCG04020000Z0ED Vishay 12 1 R3 6.04 kΩ - R0402-Vishay CRCW04026K04FKED Vishay 13 2 R4, R5 100 kΩ - R0402-Vishay CRCW0402100KFKED Vishay 14 2 R6, R7 5.11kΩ - R0402-Vishay CRCW04025K11FKED Vishay PCB LAYOUT OF REFERENCE BOARD Fig. 25 - Top Layer Fig. 27 - Bottom Layer Fig. 26 - Inner Layer1 Fig. 28 - Inner Layer2 S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 12 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix CASE OUTLINE D2 D D/2 (5) Pin 1 dot by marking 16 15 Pin 1 location indentifier 14 13 L 1 12 2 11 1 E/2 2 E 3 10 3 4 9 4 5 6 7 8 E2 b (4) Terminal tip e 3xe Top view Bottom view A1 C A A3 Seating plane Side view DIMENSION MILLIMETERS (1) INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.75 0.85 0.95 0.029 0.033 0.037 A1 0 - 0.05 0 - 0.002 A3 b 0.20 ref. 0.18 D D2 0.25 0.001 ref. 0.30 0.007 3.00 BSC 1.5 e 1.6 1.7 0.059 0.50 BSC E 0.010 0.012 0.118 BSC 0.063 0.067 0.020 BSC 3.00 BSC 0.118 BSC E2 1.5 1.6 1.7 0.059 0.063 0.067 L 0.3 0.4 0.5 0.012 0.016 0.020 N (3) 16 16 Nd (3) 4 4 Ne (3) 4 4 Notes (1) Use millimeters as the primary measurement. (2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994. (3) N is the number of terminals. Nd and Ne is the number of terminals in each D and E site respectively. (4) Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. (5) The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. (6) Package warpage max. 0.05 mm. S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 13 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12110 www.vishay.com Vishay Siliconix RECOMMENDED LAND PATTERN FOR QFN16 3 mm x 3 mm 16 x 0.300 4 x 0.200 16 x 0.580 2 x 3.300 2 x 1.740 0.500 pitch Dimensions are in millimeters Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64299. S14-1891-Rev. A, 15-Sep-14 Document Number: 64299 14 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PAD Pattern www.vishay.com Vishay Siliconix Recommended Land Pattern QFN16 3x3 All dimensions are in millimeters Revision: 10-Jul-14 Document Number: 65752 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000