SiP12117 Datasheet

SiP12117
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3 A Current Mode Constant On-Time
Synchronous Buck Regulator
DESCRIPTION
FEATURES
The SiP12117 is a high frequency current-mode constant
on-time (CM-COT) synchronous buck regulator with
integrated high-side and low-side power MOSFETs. Its
power stage is capable of supplying up to 3 A continuous
current at 600 kHz switching frequency. This regulator
produces an adjustable output voltage down to 0.6 V from
4.5 V to 15 V input rail to accommodate a variety of
applications, including consumer electronics, computing,
telecom, and industrial.
• 4.5 V to 15 V input voltage
SiP12117’s CM-COT architecture delivers ultrafast transient
response and low ripple over the full load range with
minimum output capacitance and no ESR requirements.
The device features a built in soft start of 2.9 ms and
integrated compensation.
• Cycle by cycle current limit
• Adjustable output voltage down to 0.6 V
• 3 A continuous output current
• Integrated compensation
• 600 kHz switching frequency
• Ultrafast transient response
• < 5 μA typical shutdown current
• Power good function
• Fixed soft start: 2.9 ms, typ.
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
The device also includes cycle-by-cycle current limit, over
temperature protection (OTP) and input under-voltage
lockout (UVLO).
APPLICATIONS
The SiP12117 is available in lead (Pb)-free 3 mm x 3 mm
DFN 10 lead package with thermal pad.
• Set-top-box
• Graphics cards
• LCD TV
• Notebook computers
• HDD / SSD
TYPICAL APPLICATION CIRCIUT AND PACKAGE OPTIONS
Enable
Power good
Input
PGOOD
4.5 V to 15 V
EN
VOUT
VIN
VCC
BOOT
LX
SiP12117
FB
PGND
Fig. 1 - Typical Application Circuit for SiP12117
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
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PIN CONFIGURATION
EN 10
PGOOD 9
BOOT 8
1 FB
AGND
pad
2 VCC
3 VIN
LX 7
4 PGND
LX 6
5 PGND
Fig. 2 - SiP12117 Pin Configuration (Bottom View)
PIN CONFIGURATION
PIN NUMBER
NAME
FUNCTION
1
FB
Feedback voltage 0.6 V (typ.) input. Use a resistor divider between VOUT and thermal pad to set the output
voltage
2
VCC
Internal regulator output
3
VIN
Input supply voltage for power MOS and regulator. VIN = 4.5 V to 15 V
4, 5
PGND
6, 7
LX
Power ground
Switching node, inductor connection point
8
BOOT
Bootstrap pin - connect a capacitor of at least 100 nF from BOOT to LX to develop the floating supply
for the high-side gate driver
9
PGOOD
Power good output. Open drain
10
EN
Pad
AGND
Enable input. Pull enable above 1.5 V to enable and below 0.4 V to disable the part. Do not float this pin
Analog ground. The pad also improves thermal performance
ORDERING INFORMATION
PART NUMBER
SiP12117DMP-T1-GE4
PACKAGE
MARKING (LINE 1: P/N)
DFN10 3 x 3
2117
SiP12117DB
Reference board
MARKING
P/N
FYWLL
Format:
Line 1: Dot
Line 2: P/N
Line 3: Siliconix logo + ESD dymbol
Line 4: Factory code + year code + work week code + LOT code
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
CONDITIONS
LIMIT
VIN
Reference to PGND
-0.3 to +16
VCC
Reference to AGND
-0.3 to +6
LX
Reference to PGND
-1 to +16
LX (AC)
100 ns
-2 to +17
10 ns
-6 to +17
BOOT
Reference to PGND
-0.3 to VIN + VCC
All Logic Input and Output (EN, FB, PGOOD)
Reference to AGND
-0.3 to VCC + 0.3
UNIT
V
TEMPERATURE
Junction Temperature
-40 to +150
Storage Temperature
-65 to +150
°C
POWER DISSIPATION
Junction to Ambient Thermal Impedance
(RthJA)
36.3
°C/W
2
kV
ESD PROTECTION
Electronic Discharge Protection
HBM
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V)
ELECTRICAL PARAMETER
MINIMUM
TYPICAL
MAXIMUM
VIN
4.5
-
15
VOUT
0.6
-
5.5
UNIT
V
TEMPERATURE
Recommended Ambient Temperature
-40 to +85
Operating Junction Temperature
-40 to +125
S14-1936-Rev. A, 29-Sep-14
°C
Document Number: 62973
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ELECTRICAL SPECIFICATIONS (test condition unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITION
VIN = 12 V, TA = -40 °C to +85 °C
LIMITS
MIN.
TYP.
MAX.
UNIT
POWER SUPPLY
Input Voltage
VIN
4.5
-
15
VCC Voltage
VCC
-
5
-
Input Current
V
IVIN_NOLOAD
TA = 25 °C, non-switching, no load
-
1.5
-
mA
Shutdown Current
IVIN_SHDN
EN = 0 V
-
5
10
μA
VIN UVLO Threshold
VIN_UVLO
Rising edge
-
2.8
-
V
VIN UVLO Hysteresis
VIN_UVLO_HYS
-
550
-
mV
CONTROLLER AND TIMING
Feedback Voltage
VFB
VFB Input Bias Current
IFB
On-Time (600 kHz)
tON
TA = 25 °C
588
600
612
TA = -40 °C to +85 °C
585
600
615
-
-
100
-
138
-
ns
-
2.9
5
ms
-
85
140
-
55
105
3.6
4.25
5.1
Rising temperature
-
145
-
Hysteresis
-
35
-
VIN = 12 V, (VOUT = 1 V)
Soft Start Timing (1)
mV
nA
POWER MOSFETs
High-Side On Resistance
RON_HS
Low-Side On Resistance
RON_LS
VGS = 5 V
mΩ
FAULT PROTECTIONS
Over Current Limit
IOCP
Over Temperature Protection (1)
Inductor valley current, TA = 25 °C
A
°C
POWER GOOD
Power Good Output Threshold
VFB_RISING_VTH_OV
Rising (% VOUT)
-
95
-
VFB_FALLING_VTH_UV
Falling (% VOUT)
-
-10
-
%
Power Good Pull Low Resistance
RON_PGOOD
-
28
50
Ω
Power Good Delay Time
tDLY_PGOOD
-
8
-
μs
Logic High Level
VEN_H
1.5
-
-
Logic Low Level
VEN_L
-
-
0.4
ENABLE THRESHOLD
V
Note
(1) Not tested, guaranteed by design.
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
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FUNCTIONAL BLOCK DIAGRAM
VCC
2
PGOOD
9
EN
3
10
Regulator
VIN
BOOT
8
OTP
0.6 V
reference
BOOT
UVLO
Soft
start
+
+ OTA
-
1
VFB
+
-
Control
logic
section
ON-time
generator
LX
Anti-xcond
control
6, 7
VCC
PWM comparator
Isense
I-V
converter
ZCD
PGND
4, 5
OCP
PAD
Isense
Current
mirror
Fig. 3 - SiP12117 Functional Block Diagram
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
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ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1 V, L = 1.5 μH, C = 3 x 22 μF (ceramic), unless noted otherwise)
100
90
5 VOUT
VOUT
50 mV/div
80
1 VOUT
Efficiency (%)
70
60
50
ICOIL
1 A/div
40
30
20
LX
10 V/div
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
IOUT (A)
Fig. 4 - Efficiency vs. IOUT
Fig. 7 - Steady-State, IOUT = 3 A
Time = 2 μs/div
1000
900
Switching Frequency (kHz)
800
VOUT
50 mV/div
1 VOUT
700
600
500
5 VOUT
400
ICOIL
1 A/div
300
200
100
LX
10 V/div
0
0
0.5
1.0
1.5
IOUT (A)
2.0
2.5
3.0
Fig. 5 - Frequency Variation vs. IOUT
Fig. 8 - Steady-State, IOUT = 0 A
Time = 2 μs/div
1.0
0.8
Load Regulation (%)
0.6
0.4
5 VOUT
0.2
0
1 VOUT
-0.2
-0.4
-0.6
-0.8
-1.0
0
0.5
1.0
1.5
IOUT (A)
2.0
2.5
3.0
Fig. 6 - Load Regulation vs. IOUT
S14-1936-Rev. A, 29-Sep-14
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VOUT
50 mV/div
Vishay Siliconix
VOUT
50 mV/div
ICOIL
2 A/div
ICOIL
2 A/div
LX
10 V/dIv
LX
10 V/div
Fig. 9 - Load Step Undershoot Response,IOUT = 0 A to 1.5 A
Time = 10 μs/div
Fig. 12 - Load Step Overshoot Response, IOUT = 1.5 A to 0 A
Time = 10 μs/div
VOUT
100 mV/div
VOUT
100 mV/div
ICOIL
2 A/div
ICOIL
2 A/div
LX
10 V/div
LX
10 V/div
Fig. 10 - Load Step Undershoot Response, IOUT = 0 A to 3 A
Time = 10 μs/div
Fig. 13 - Load Step Overshoot Response, IOUT = 3 A to 0 A
Time = 10 μs/div
EN
5 V/div
EN
5 V/div
VOUT
500 mV/div
VOUT
500 mV/div
ICOIL
1 A/div
ICOIL
1 A/div
LX
10 V/div
LX
10 V/div
Fig. 11 - Start-Up, IOUT = 0 A
Time = 1 μs/div
S14-1936-Rev. A, 29-Sep-14
Fig. 14 - Shut-Down, IOUT = 0 A
Time = 200 ms/div
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EN
5 V/div
EN
5 V/div
VOUT
500 mV/div
VOUT
500 mV/div
ICOIL
2 A/div
ICOIL
2 A/div
LX
10 V/div
LX
10 V/div
Fig. 17 - Shut-Down, IOUT = 3 A
Time = 50 μs/div
Fig. 15 - Load Step Undershoot Response IOUT = 0 A to 3 A
Time = 1 ms/div
VOUT
500 mV/div
ICOIL
2 A/div
LX
10 V/div
Fig. 16 - Over Current Protection, IVALLEY = 4 A
Time = 100 μs/div
S14-1936-Rev. A, 29-Sep-14
VOUT
500 mV/div
ICOIL
2 A/div
LX
10 V/div
Fig. 18 - Over Current Protection, IVALLEY = 4 A
Time = 20 μs/div
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OPERATIONAL DESCRIPTION
Device Overview
PWM Control Mechanism
SiP12117 is a high-efficiency monolithic synchronous
buck regulator capable of delivering up to 3 A continuous
current. The device has fixed switching frequency of
600 kHz. The control scheme is based on current - mode
constant-on-time architecture, which delivers fast transient
response and minimizes external components. Thanks to
the internal current ramp information, no high-ESR output
bulk or virtual ESR network is required for the loop stability.
SiP12117 has a full set of protection features:
SiP12117 employs a state-of-the-art current - mode COT
(CM-COT) control mechanism. During steady-state
operation, output voltage is compared with internal
reference (0.6 V typ.) and the amplified error signal (Vcomp) is
generated. In the meantime, inductor valley current is
sensed, and its slope (Isense) is converted into a voltage
signal (Vcurrent) to be compared with Vcomp. Once Vcurrent is
lower than Vcomp, a single shot on-time is generated for a
fixed time set by an internal RON.
• Cycle by cycle over current protection
Light Load Operation
• Over temperature protection with hysteresis
To further improve efficiency at light-load condition,
SiP12117 provides a set of innovative implementations to
eliminate LS recirculating current and switching losses. The
internal Zero Crossing Detector (ZCD) monitors LX node
voltage to determine when inductor current starts to flow
negatively. In light load operation as soon as inductor valley
current crosses zero, the device first deploys diode
emulation mode by turning off LS FET. If load further
decreases, switching frequency is further reduced
proportional to load condition to save switching losses while
keeping output ripple within tolerance. The switching
frequency is set by the control loop to maintain regulation.
At zero load this frequency can go as low as hundreds of Hz.
The device also features a dedicated enable pin for easy
power sequencing and an open drain power good output.
The device is available in 3 x 3 DFN10 package with an
exposed power pad to deliver high power density with ease
of use.
Power Stage
SiP12117 integrates a high-performance power stage with
an 85 mΩ n-channel high side MOSFET and a 55 mΩ
n-channel low side MOSFET. The MOSFETs are optimized
to achieve up to 95 % efficiency at 600 kHz switching
frequency.
Fig. 19 illustrates the basic block diagram for CM-COT
architecture and fig. 20 demonstrates the basic operational
principle:
The power input voltage (VIN) can go up to 15 V and down
as low as 4.5 V for power conversion.
VOUT
RON
Bandgap
Vref
HG
+
OTA
VIN
VIN
Vcomp
HG
Current
mirror
+
Isense I-AMP
-
On-time
generator
+
Control
logic &
MOSFET
driver
LG
Vcurrent
PWM
comperator
LS FET
LG
Fig. 19 - CM-COT Block Diagram
Vcurrent
Vcomp
Fixed on-time
PWM
Fig. 20 - CM-COT Operational Principle
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
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OUTPUT MONITORING AND PROTECTION FEATURES
Output Over-Current Protection (OCP)
SiP12117 has cycle by cycle over-current limit control. The
inductor valley current is monitored during LS FET
turn-on period through RDS(on) sensing. After a pre-defined
blanking time, the valley current is compared with internal
threshold (4.25 A typ.) to determine the threshold for OCP.
If the monitored current is higher than the internal threshold,
HS turn-on pulse is skipped and LS FET is kept on until the
valley current returns below OCP limit.
OCP is enabled immediately after VIN passes UVLO level
and enable is high.
In the figure below we see the ripple current riding on the DC
load current. The valley current is calculated by taking one
half the ripple current minus the DC load current.
For example if IOUT = 3 A and ripple current = 1.2 A,
IVALLEY = 3 A - 0.6 A = 2.4 A. The typical DC full load
current would be 4.85 A which is calculated by 4.25 A
(OCP typ.) + 0.6 A. Here we see changing the ripple current
(inductor value) can change the maximum DC load current
value.
OCPthreshold
Iload
Iinductor
GH
Skipped GH pulse
Fig. 21 - Over-Current Protection Illustration
Negative Current Protection
Design Procedure
Similar to the output over-current protection, the negative
current protection is realized by monitoring the current
across the LS FET.
When the valley point of the inductor current reaches -2.5 A
for first cycles, both HS and LS FETs are off.
The design process of the SiP12117 is quite straight
forward. Only few passive components such as output
capacitors and Inductor need to be selected.
Over-Temperature Protection (OTP)
The following paragraph describes the selection procedure
for these peripheral components for a given operating
conditions.
SiP12117 has internal thermal monitor block that turns
off both HS and LS FETs when junction temperature is
above 145 °C (typ.). A hysteresis of 35 °C is implemented,
so when junction temperature drops below 110 °C, the
device restarts by initiating soft-start sequence again.
In the next example the following definitions apply:
Soft Start
There are two values of load current to evaluate - continuous
load current and peak load current.
SiP12117 has a built in soft-start function of ~2.9 ms. Once
VIN is above UVLO level (2.8 V typ.), VOUT will ramp up
slowly, rising monotonically to the programmed output
voltage.
Pre-bias Startup
In case of pre-bias startup, the output is monitored through
the FB pin. If the sensed voltage on FB is higher than the
internal reference ramp value, control logic prevents HS and
LS FET from switching to avoid a negative output voltage
spike due to LS FET turn on.
VIN max.: the highest specified input voltage
VIN min.: The minimum effective input voltage subject to
voltage drops due to connectors, fuses, switches, and PCB
traces.
Continuous load current relates to thermal stress
considerations which drive the selection of the inductor and
input capacitors.
Peak load current determines instantaneous component
stresses and filtering requirements such as inductor
saturation, output capacitors, and design of the current limit
circuit.
The following specifications are used in this design:
• VIN = 12 V ± 10 %
• VOUT = 1.2 V ± 1 %
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
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Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Cost, PCB size, output ripple, and efficiency
are all used in the selection process. Low inductor values
result in smaller size and allow faster transient performance
but create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current, and
transient response. Efficiency especially at higher load
currents will also be compromised due to the higher DCR
(within a given case size).
The ripple current also sets the boundary for power-save
operation. The switching regulator will typically enter
power-save mode when the load current decreases to 1/2 of
the ripple current. For example, if ripple current is 1 A then
power-save operation will typically start at loads
approaching 0.5 A. Alternatively, if ripple current is set at
40 % of maximum load current, then power-save will start
for loads less than ~20 % of maximum current.
A smaller value of 1.5 μH is selected which is a standard
value. This will increase the maximum ripple current by
25 %.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current. The actual ripple
current using the chosen 1 μH inductor comes out to be.
Δi = (13.2 V - 1.2 V) x
151 ns
1.5 μH
= 1.2 A
Output Capacitance Calculation
This table provides a simple easy guide for setting up the
board. If excessive jitter is noticed then reducing the
inductor to the next standard value may be needed.
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current
is at the peak, determines the required capacitance. If the
load release is instantaneous (load changes from maximum
to zero in < 1/fsw μs), the output capacitor must absorb all
the inductor's stored energy. This will approximately cause
a peak voltage on the capacitor according to the following
equation.
L x (IOUT + 1 x IRIPPLE max.)2
2
COUT min. =
(VPEAK)2 - (VOUT)2
SiP12117 CONFIGURATION LOOK UP TABLE
Assuming a peak voltage VPEAK of 1.3 V (100 mV rise upon
load release), and a 3 A load release, the required
capacitance is shown by the next equation.
Setting the ripple current 20 % to 50 % of the maximum load
current provides an optimal trade-off of the areas mentioned
above.
VIN
(V)
VOUT
(V)
INDUCTOR
(μH)
RFB_TOP
(Ω)
RFB_BOTTOM
(Ω)
12
1
1.5
4.53k
6.81k
12
3.3
3.3
4.53k
1k
12
5
3.3
4.53k
619R
5
1
1.5
4.53k
6.81k
5
3.3
1.5
4.53k
1k
The equation for determining inductance is shown next.
Example
In this example, the inductor ripple current is set equal to
30 % of the maximum load current. Thus ripple current will
be 30 % x 3 A or 0.9 A. To find the minimum inductance
needed, use the VIN and tON values that correspond to
VIN max..
L = (VIN - VOUT) x
tON
Δi
1.5 μH x (3 A + 0.5 x (1.2 A)2
COUT min. =
(1.3 V)2 - (1.2 V)2
= 77.8 μF
If the load release is relatively slow, the output capacitance
can be reduced.
Using MLCC ceramic capacitors we will use 3 x 22 μF or
66 μF as the total output capacitance.
Switching Frequency Variations
The switching frequency variation in COT can be mainly
attributed to the increase in conduction losses as the load
increases. Since the on time is constant the controller must
account for losses and maintain output regulation by
reducing the off time. Hence the fsw tends to increase with
load.
Plugging numbers into the above equation we get
L = (13.2 V - 1.2 V) x
S14-1936-Rev. A, 29-Sep-14
151 x 10-9 s
0.9 A
= 2 μH
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LAYOUT CONSIDERATIONS
The SiP12117 offers the designer a small part count,
3 A buck regulator solution. If the below layout
recommendations are followed, the same layout can be
used to cover a wide range of output currents and voltages
without any changes to the board design and only minor
changes to the component values in the schematic.
The reference design has a majority of the components
placed on the top layer. This allows for easy assembly and
straightforward layout.
Fig. 22 outlines the pointers for the layout considerations
and the explanations follow.
9
7
2
VIN
8
0V
10
LX
1
6
5
3
4
11
VOUT
5
Fig. 22 - Reference Design Pointers
1. Place input ceramic capacitors close to the voltage input
pins with a small 10 nF / 100 nF placed as close as the
design rules will allow. This will help reduce the size of
the input high frequency current loop and consequently
reduce the high frequency ripple noise seen at the input
and the LX node.
S14-1936-Rev. A, 29-Sep-14
2. Place the setup and control passive devices logically
around the IC with the intention of placing a quiet ground
plane beneath them on a secondary layer.
3. It is advisable to use ceramic capacitors at the output to
reduce impedance. Place these as close to the IC PGND
and output voltage node as design will allow. Place a
small 10 nF / 100 nF ceramic capacitor closest to the IC
and inductor loop.
4. The loop between LX, VOUT and the IC PGND should be
as compact as possible. This will lower series resistance
and also make the current loop smaller enabling the high
frequency response of the output capacitors to take
effect.
5. The output impedance should be small when high
current is required; use high current traces, multiple
layers can be used with many vias if the design allows.
6. Use many vias when multiple layers are involved. This
will have the effect of lowering the resistance between
layers and reducing the via inductance of the PCB nets.
7. The quiet AGND should be connected to the PGND plane
near to the input GND at one connection only of at least
1 mm width.
8. PGND can be used on internal layers if the resistance of
the PCB is to be small; this will also help remove heat.
Use extra vias if needed but be mindful to allow a path
between the vias.
9. A quiet plane should be employed for the AGND, this is
placed under the small signal passives. This can be
placed on multiple layers if needed for heat removal.
10. The LX copper can also be used on a single or multiple
layers, use a number of vias to stitch the layers.
11. The copper area beneath the inductor has been removed
(on all layers) in this design to reduce the inductive
coupling that occurs between the inductor and the GND
trace. No other voltage planes should be placed under
this area.
Document Number: 62973
12
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12117
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Vishay Siliconix
PCB LAYOUT
Fig. 23 - Top Layer
Fig. 25 - Inner Layer 1
Fig. 24 - Inner Layer 2
Fig. 26 - Bottom Layer
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
13
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12117
www.vishay.com
Vishay Siliconix
SCHEMATIC
U1 SiP12117
P1
VIN
1
2
R1
4.53 kΩ
3
VIN
BOOT
Terminal
EN 10
0V
1
2
P4
Header 2
PGD9
1
2
R6
0V
Header 2
10 kΩ
0V
C1 C2 C3
10 10 10
μH μH nH
R5
1 kΩ
LX
EN
LX
5V2 V
CC
C4
7
LX 100 nH
L1
VOUT
3.3 μH
C9
6
R3
4.53
kΩ C6 C7 C8
PGD
4 GND
5 GND
GND
P1
P3
8 BS R2 BS 1
20 Ω
C5
VFB
1 VFB
Omit
R4
1 kΩ
10 22 22
nH μH μH
P2
P5
1
2
1
2
Terminal Header 2
1 μH
P6
1
2
0V
Header 2
BILL OF MATERIAL (VIN = 12 V, VOUT = 3.3 V, FSW = 600 kHz)
ITEM
QTY
REFERENCE
PCB
FOOTPRINT
VALUE
VOLTAGE
PART NUMBER
MANUFACTURER
1
2
C1, C2
1210
10 μF
35 V
C1210C106M6PACTU
Kemet
2
2
C3, C6
0402
10 nF
50 V
GRM155R71H103KA88D
Murata
3
1
C4
0603
1 μF
10 V
C0402C105M8PACTU
Kemet
4
1
C5
0402
100 nF
35 V
CGA2B3X7R1V104K050BB
Vishay
5
2
C7, C8
0805
22 μF
10 V
CL21A226MPQNNNE
Samsung
6
1
R2
0402
20R
-
CRCW040220R0FKED
Vishay
7
1
R3
0402
4K53
-
CRCW04024K53FKED
Vishay
8
1
R4
0402
1K
-
CRCW0402249KFKED
Vishay
9
1
L1
IHLP2525
3μ3
-
IHLP2020BZER3R3M01
Vishay
10
1
U1
DFN10-3x3
-
-
SiP12117
Vishay
11
1
R1
0402
4K53
-
CRCW04024K53FKED
Vishay
12
1
R5
0402
1K
-
CRCW0402249KFKED
Vishay
13
1
R6
0402
10K
-
CRCW040210K0FKED
Vishay
14
4
P3, P4, P5, P6
HDR1x2
-
-
90120-0126
Vishay
15
2
P1, P2
TERM2
-
-
282834-2
TE Connectivity
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
14
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12117
www.vishay.com
Vishay Siliconix
CASE OUTLINE
D
e
Terminal tip (3)
NXb
D/2
(3)
0.10 M C A B
Index area
D/2 x E/2
(5)
2x
E/2
E2
0.15
C
E
NXL
Exposed pad
Index area
D/2 x E/2
D2
0.15
(5)
// 0.10
C
2x
Top view
Bottom view
C
A
0.08
(4) NX
Seating
plane
C
A1
A3
Side view
DIMENSION
MILLIMETERS (1)
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.80
0.90
1.00
0.031
0.035
0.039
A1
0
0.02
0.05
0
0.001
0.002
A3
b
0.20 BSC
0.18
D
D2
0.23
0.008 BSC
0.30
0.007
3.00 BSC
2.20
e
2.38
2.48
0.087
0.50 BSC
E
0.009
0.012
0.118 BSC
0.094
0.098
0.020 BSC
3.00 BSC
0.118 BSC
E2
1.49
1.64
1.74
0.059
0.065
0.069
L
0.30
0.40
0.50
0.012
0.016
0.020
Notes
(2) Use millimeters as the primary measurement.
(3) N is the number of terminals.
(4) Dimensions b applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip.
(5) Coplanarity applies to the exposed heat sink slug as well as the terminal.
(6) The pin #1 identifier may be either a mold or marked feature, it must be located within the zone indicated.
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
15
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12117
www.vishay.com
Vishay Siliconix
RECOMMENDED LAND PATTERN
Recommended Land Pattern
Recommended Land Pattern vs. Case Outline
0.500
3.300
1.700
2.100
0.600
0.300
2.400
Dimensions are in millimeters
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?69273.
S14-1936-Rev. A, 29-Sep-14
Document Number: 62973
16
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
DFN-10 LEAD (3 X 3)
D
e
Terminal Tip
3
D/2
3
NXb
0.10
M
C
A
B
5
0.15
C
E2
NXL
Exposed Pad
Index Area
D/2 E/2
D2
0.15
5
BOTTOM VIEW
// 0.10
E/2
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
2x
Index Area
D/2 E/2
C
E
2x
TOP VIEW
C
A
4
NX
0.08
SEATING
PLANE
C
A1
A3
SIDE VIEW
MILLIMETERS
NOTES:
1.
All dimensions are in millimeters and inches.
2.
N is the total number of terminals.
3.
4.
5.
Dimension b applies to metallized terminal and is measured
between 0.15 and 0.30 mm from terminal tip.
Coplanarity applies to the exposed heat sink slug as well as the
terminal.
The pin #1 identifier may be either a mold or marked feature, it
must be located within the zone iindicated.
INCHES
Dim
Min
Nom
Max
Min
Nom
Max
A
0.80
0.90
1.00
0.031
0.035
0.039
A1
0.00
0.02
0.05
0.000
0.001
0.002
A3
b
D
D2
E
E2
e
L
0.20 BSC
0.18
0.23
0.008 BSC
0.30
0.007
2.48
0.087
3.00 BSC
2.20
2.38
1.64
0.40
0.094
0.098
0.118 BSC
1.74
0.059
0.50 BSC
0.30
0.012
0.118 BSC
3.00 BSC
1.49
0.009
0.065
0.069
0.020 BSC
0.50
0.012
0.016
0.020
*Use millimeters as the primary measurement.
ECN: S-42134—Rev. A, 29-Nov-04
DWG: 5943
Document Number: 73181
29-Nov-04
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Revision: 02-Oct-12
1
Document Number: 91000