SiP12108, SiP12108A Datasheet

SiP12108, SiP12108A
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2.8 V to 5.5 V Input
5 A Synchronous Buck Regulator
DESCRIPTION
FEATURES
The SiP12108 is a high frequency current-mode constant
on-time (CM-COT) synchronous buck regulator with
integrated high-side and low-side power MOSFETs. Its
power stage is capable of supplying 5 A continuous current
at 4 MHz switching frequency. This regulator produces an
adjustable output voltage down to 0.6 V from 2.8 V to 5.5 V
input rail to accommodate a variety of applications,
including computing, consumer electronics, telecom, and
industrial.
•
•
•
•
•
•
•
•
SiP12108’s CM-COT architecture delivers ultra-fast
transient response with minimum output capacitance and
tight ripple regulation at very light load. The part is stable
with any capacitor type and no ESR network is required for
loop stability. The device also incorporates a power saving
scheme that significantly increases light load efficiency.
•
•
•
•
•
The SiP12108 integrates a full protection feature set,
including output overvoltage protection (OVP), output under
voltage protection (UVP) and thermal shutdown (OTP). The
“A” version of the device, SiP12108A, does not have the
UVP feature. They also incorporate UVLO for the input rail
and an internal soft-start ramp.
2.8 V to 5.5 V input voltage
Adjustable output voltage down to 0.6 V
5 A continuous output current
Programmable switching frequency up to 4 MHz
95 % peak efficiency
Stable with any capacitor. No external ESR
network required.
Ultrafast transient response
Selectable power saving (PSM) mode or forced
continuous mode
± 1 % accuracy of VOUT setting
Pulse-by-pulse current limit
Scalable with SiP12107 - 3 A
SiP12108 is fully protected with OTP, SCP, UVP, OVP
SiP12108A is fully protected with OTP, SCP, OVP
• PGOOD Indicator
• PowerCAD Simulation software available at
vishay.transim.com/login.aspx
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
The SiP12108 is available in lead (Pb)-free power enhanced
3 mm x 3 mm QFN-16 package.
APPLICATIONS
• Point of load regulation for low-power processors,
network processors, DSPs, FPGAs, and ASICs
• Low voltage, distributed power architectures with
3.3 V or 5 V rails
• Computing, broadband, networking, LAN/WAN, optical,
test and measurement
• A/V, high density cards, storage, DSL, STB, DVR, DTV,
Industrial PC
TYPICAL APPLICATION CIRCUIT
POWER SAVE MODE
ENABLE
POWER GOOD
INPUT = 2.8 V to 5.5 V
PGOOD
EN AUTO
VIN
VOUT
LX
VOUT
VFB
AVIN
PGND
GMO
AGND
RON
Fig. 1 - Typical Application Circuit for SiP12108
S13-2257-Rev. B, 11-Nov-13
Document Number: 62699
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
CONDITIONS
LIMIT
VIN
Reference to PGND
-0.3 to 6
AVIN
Reference to AGND
-0.3 to 6
LX
Reference to PGND
UNIT
V
-0.3 to 6
AGND to PGND
-0.3 to +0.3
All Logic Inputs
Reference to AGND
-0.3 to AVIN + 0.3
TEMPERATURE
Max. Operating Junction Temperature
150
Storage Temperature
°C
-65 to 150
POWER DISSIPATION
Junction to Ambient Thermal Impedance
(RthJA)
Maximum Power Dissipation
36.3
Ambient temperature = 25 °C
3.4
Ambient temperature = 100 °C
1.3
HBM
4
°C/W
W
ESD PROTECTION
kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
MINIMUM
TYPICAL
MAXIMUM
VIN
2.8
-
5.5
AVIN
2.8
-
5.5
LX
-1
-
5.5
VOUT
0.6
-
0.85 x VIN
Ambient Temperature
S13-2257-Rev. B, 11-Nov-13
-40 to 85
UNIT
V
°C
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ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITION
UNLESS OTHERWISE SPECIFIED
VIN = AVIN = 3.3 V, TA = -40 °C to 85 °C
LIMITS
MIN.
TYP.
MAX.
VIN
2.8
-
5.5
AVIN
2.8
-
5.5
UNIT
POWER SUPPLY
Power Input Voltage Range
Bias Input Voltage Range
V
IIN_NOLOAD
Non- switching, IO = 0 A,
Ron = 100 k, AUTO = Low
-
1200
-
IIN_SHDN
EN = 0 V
-
6
9.5
AVIN UVLO Threshold
AVIN_UVLO
AVIN rising
2.3
2.55
2.8
V
AVIN UVLO Hysteresis
AVIN_UVLO_HYS
-
300
-
mV
TA = 0 °C to +70 °C
0.594
0.600
0.606
TA = -40 °C to +85 °C
0.591
0.600
0.609
2
200
nA
mS
Input Current
Shutdown Current
μA
PWM CONTROLLER
Feedback Reference
VFB
VFB Input Bias Current
IFB
-
Transconductance
GMO Source Current
GMO Sink Current
Switching Frequency Range
gm
-
1
-
IGMO_SOURCE
-
50
-
IGMO_SINK
-
50
-
fSW
Guaranted by design
0.2
-
4
Minimum On-Time
tON_MIN
Guaranted by design
-
50
-
Minimum Off-Time
tOFF_MIN
VOUT = 1.2 V, RON = 100 k
-
125
-
-
1.5
-
-
35
51
-
23
35
Soft Start Time
tSS
V
μA
MHz
ns
ms
INTEGRATED MOSFETS
High-Side On Resistance
RON_HS
Low-Side On Resistance
RON_LS
VIN = AVIN = 5 V
m
FAULT PROTECTIONS
Over Current Limit
IOCP
-
7.5
-
-
21
-
-
-25
-
Rising temperature
-
160
-
Hysteresis
-
30
-
VFB_RISING_VTH_OV
VFB rising above 0.6 V reference
-
21
-
VFB_FALLING_VTH_UV
VFB falling below 0.6 V reference
-
-12.5
-
Output OVP Threshold
VFB_OVP
Output UVP Threshold
VFB_UVP
Over Temperature Protection
Inductor valley current
VFB with respect to 0.6 V reference
A
%
°C
POWER GOOD
Power Good Output Threshold
%
Power Good On Resistance
RON_PGOOD
-
30
60

Power Good Delay Time
tDLY_PGOOD
-
4
-
μs
Logic High Level
VEN_H
1.5
-
-
Logic Low Level
VEN_L
-
-
0.4
ENABLE THRESHOLD
S13-2257-Rev. B, 11-Nov-13
V
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FUNCTIONAL BLOCK DIAGRAM
2
7
6
AVIN
GMO
AGND
PGOOD
5
3
1,16
EN
AUTO
VIN
8
OTP
VIN
0.6 V
REFERENCE
UVLO
SOFT
START
VIN
+
+ OTA
9
+
ON-TIME
GENERATOR
VFB
CONTROL
LOGIC
SECTION
LX
ANTI-XCOND
CONTROL
11,12,13
VIN
PWM COMPARATOR
I-V
Converter
Isense
ZCD
PGND
RON
4
14,15
-
OCP
+
VOUT
UV Comparator
(SiP12108 only)
0.45 V
10
Current
Mirror
+
VFB
0.72 V
PAD
-
OV Comparator
Isense
Fig. 2 - SiP12108 Functional Block Diagram
ORDERING INFORMATION
PART NUMBER
MARKING
(LINE 2: P/N)
PACKAGE
SiP12108DMP-T1GE4
QFN16 3x3
2108
SiP12108ADMP-T1GE4(1)
QFN16 3x3
108A
SiP12108DB
N/A
SiP12108ADB(1)
Note
Output undervoltage protection (UVP) disabled
(1)
P/N
FYWLL
Format:
Line 1: Dot
Line 2: P/N
Line 3: Siliconix Logo + ESD Symbol
Line 4: Factory Code + Year Code + Work Week Code + LOT Code
S13-2257-Rev. B, 11-Nov-13
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PGND
LX
16
PGND
VIN
PIN CONFIGURATION
15
14
13
1
12 LX
AVIN 2
11 LX
VIN
4
9 VFB
5
6
7
8
AGND
RON
GMO
10 VOUT
PGOOD
3
AUTO
EN
QFN16 3x3
Fig. 3 - SiP12108 Pin Configuration (Top View)


PIN CONFIGURATION
PIN NUMBER
NAME
FUNCTION
1, 16
VIN
2
AVIN
3
EN
Enable pin. Pull enable above 1.5 V to enable the part and below 0.4 V to disable. Do not float this pin.
4
RON
An external resistor between RON and GND sets the switching on time.
5
AUTO
6
PGOOD
Input supply voltage for power MOS. VIN = 2.8 V to 5.5 V
Input supply voltage for internal circuitry. AVIN = 2.8 V to 5.5 V
Sets switching mode. Connect AUTO to AVIN for forced continuous mode and AUTO to GND for power
save mode. Do not float.
Power good output. Open drain.
7
GMO
Connect to an external RC network for loop compensation and droop function
8
AGND
Analog ground
9
VFB
10
VOUT
11, 12, 13
LX
14, 15
PGND
EP
S13-2257-Rev. B, 11-Nov-13
Feedback voltage. 0.6 V (typ.). Use a resistor divider between VOUT and AGND to set the output voltage.
VOUT, output voltage sense connection
Switching output, inductor connection point
Power ground
Exposed paddle (bottom). Connect to a good PCB thermal ground plane.
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ELECTRICAL CHARACTERISTICS (VIN = 3.3 V, L = 1 μH, C = 3 x 22 μF, fSW = 1.2 MHz unless noted otherwise)
100
100
90
80
Vo -1.2V
70
Efficiency (%)
Efficiency (%)
80
60
50
60
50
40
30
30
20
0.01
0.1
1
IOUT (A)
Vo - 1.2V
70
40
20
Vo - 1.8V
90
Vo- 1.8V
10
0.01
0.12
0.1
0.1
0.08
0.08
Load Regulation (%)
Load Regulation (%)
0.12
Vo - 1.8V
0.04
Vo - 1.2V
0.02
0
-0.02
-0.04
Vo - 1.8V
0.04
0.02
0
-0.02
0.01
0.1
IOUT (A)
1
10
-0.04
0.01
0.1
IOUT (A)
1
10
Fig. 8 - Load Regulation - PSM Mode
1.2
1.2
1
1
Vo - 1.2V
0.8
Vo - 1.2V
0.8
Fsw (MHz)
Fsw (MHz)
10
Vo - 1.2V
0.06
Fig. 5 - Load Regulation - PWM Mode
Vo - 1.8V
0.6
0.6
0.4
0.4
0.2
0.2
0
1
IOUT (A)
Fig. 7 - Efficiency - PSM Mode
Fig. 4 - Efficiency - PWM Mode
0.06
0.1
0.01
0.1
IOUT (A)
1
Fig. 6 - FSW Variation - PWM Mode
S13-2257-Rev. B, 11-Nov-13
10
0
Vo - 1.8V
0.01
0.1
IOUT (A)
1
10
Fig. 9 - FSW Variation - PSM Mode
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ELECTRICAL CHARACTERISTICS (VIN = 3.3 V, L = 1 μH, C = 3 x 22 μF, fSW = 1.2 MHz unless noted otherwise)
CH1
CH1
CH2
CH2
Fig. 10 - PWM Mode- Steady - State Ripple and LX, 5 A Load
CH1 = VOUT , 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div
Fig. 13 - PWM Mode- Steady - State Ripple and LX, 0 A Load
CH1 = VOUT , 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div
CH1
CH1
CH2
CH2
Fig. 11 - PSM Mode- Steady - State Ripple and LX, 0 A Load
CH1 = VOUT , 20 mV/div, CH2 = LX, 2 V/div, Time = 10 ms/div
Fig. 14 - PSM Mode- Steady - State Ripple and LX, 0 A Load
CH1 = VOUT , 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div
CH1
CH1
CH2
CH2
CH4
CH4
Fig. 12 - Load Step 0 A to 5 A to 0 A
CH1 = Iload, CH2 = VOUT, 500 mV/div,
CH4 = Icoil, 5 A/div, Time = 100 μs/div
S13-2257-Rev. B, 11-Nov-13
Fig. 15 - Load Step 0 A to 5 A, Rising Edge
CH1 = Iload, CH2 = VOUT, 200 mV/div,
CH4 = Icoil, 5 A/div, Time = 20 μs/div
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ELECTRICAL CHARACTERISTICS (VIN = 3.3 V, L = 1 μH, C = 3 x 22 μF, fSW = 1.2 MHz unless noted otherwise)
CH1
CH2
CH3
CH2
CH1
CH4
CH4
Fig. 16 - Load Step 0 A to 5 A, Falling Edge
CH1 = Iload, CH2 = VOUT, 200 mV/div,
CH4 = Icoil, 5 A/div, Time = 20 μs/div
Fig. 19 - Turn-On Time PSM Mode, 0 A Load
CH1 = VOUT , 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD,
5 V/div, CH4 = Icoil, 2 A/div, Time = 500 μs/div
CH2
CH2
CH3
CH3
CH1
CH1
CH4
CH4
Fig. 17 - Turn-Off Time PSM Mode, 0 A Load
CH1 = VOUT , 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD,
5 V/div, CH4 = Icoil, 2 A/div, Time = 500 μs/div
Fig. 20 - Turn-On Time PWM Mode, 5 A Load
CH1 = VOUT , 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD,
5 V/div, CH4 = Icoil, 2 A/div, Time = 500 μs/div
CH2
CH3
CH1
CH4
Fig. 18 - Turn-Off Time PWM Mode, 5 A Load
CH1 = VOUT , 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD,
5 V/div, CH4 = Icoil, 2 A/div, Time = 500 μs/div
S13-2257-Rev. B, 11-Nov-13
Document Number: 62699
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OPERATIONAL DESCRIPTION
Device Overview
Power Stage
SiP12108 is a high-efficiency monolithic synchronous buck
regulator capable of delivering up to 5 A continuous current.
The device has programmable switching frequency up to
4 MHz. The control scheme is based on current-mode
constant-on-time architecture, which delivers fast transient
response and minimizes external components. Thanks to
the internal current ramp information, no high-ESR output
bulk or virtual ESR network is required for the loop stability.
This device also incorporates a power saving feature by
enabling diode emulation mode and frequency foldback as
load decreases.
SiP12108 integrated synchronous MOSFETs . The MOSFETs
are optimized to achieve 95 % efficiency at 2 MHz switching
frequency.
The power input voltage (VIN) can go up to 5.5 V and as low
as 2.8 V for power conversion. The logic bias voltage (AVIN)
ranges from 2.8 V to 5.5 V.
PWM Control Mechanism
SiP12108 employs a state-of-the-art current-mode COT
control mechanism. During steady-state operation, output
voltage is compared with internal reference (0.6 V typ.) and
the amplified error signal (VCOMP) is generated on the COMP
pin. In the meantime, inductor valley current is sensed, and
its slope (Isense) is converted into a voltage signal (Vcurrent) to
be compared with VCOMP. Once Vcurrent is lower than VCOMP,
a single shot on-time is generated for a fixed time
programmed by the external RON. Figure 4 illustrates the
basic block diagram for CM-COT architecture and figure 5
demonstrates the basic operational principle:


SiP12108 has a full set of protection and monitoring
features:
- Over current protection in pulse-by-pulse mode
- Output over voltage protection
- Output under voltage protection with device latch
- Over temperature protection with hysteresis
- Dedicated enable pin for easy power sequencing
- Power Good open drain output
This device is available in QFN16 3x3 package to deliver
high power density and minimize PCB area.
RON
Bandgap
VOUT
VOUT
Vref
HG
+
R1
OTA
VIN
-
VIN
R2
V comp
HG
ON-TIME
Generator
Control
Logic &
MOSFET
Driver
LG
+
-
+
Current
Mirror
Isense I-AMP
-
V current
PWM
COMPARATOR
LS FET
LG
Fig. 21 - CM-COT Block Diagram
S13-2257-Rev. B, 11-Nov-13
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Vcurrent
vcomp
Fixed ON-time
PWM
Fig. 22 - CM-COT Operational Principle
The following equation illustrates the relationship between
on-time, VIN, VOUT and RON value:
TON = RON x K x
Once on-time is set, the pseudo constant frequency is then
determined by the following equation:
VOUT
D
VIN
1
ࢌ sw =
=
=
RON x K
VOUT
TON
x RON x K
VIN
VOUT
, where K = 10.45 x 10-12 a constant set internally
VIN


Loop Stability and Compensator Design
Due to the nature of current mode control, a simple RC network (type II compensator) is required between COMP and AGND for
loop stability and transient response purposes. The general concept of this loop design is to introduce a single zero through the
compensator to determine the crossover frequency of overall close loop system.
The overall loop can be broken down into following segments.
Output feedback divider transfer function Hfb:
R fb2
H fb = -----------------------------R fb1 x R fb2
Voltage compensator transfer function GCOMP (s):
R O x  1 + sC COMP R COMP 
G COMP (s) = ------------------------------------------------------------------------- gm
 1 + sR O C COMP 
Modulator transfer function Hmod (s):
R load x  1 + sC O R ESR 
1
H mod (s) = ----------------------------------- x -------------------------------------------------------------AV 1 x R DS(on)
 1 + sC O R load 
The complete loop transfer function is given by:
R fb2
R O x  1 + sC COMP R COMP 
R load x  1 + sC O R ESR 
1
H mod (s) = ------------------------------ x -------------------------------------------------------------------------gm x ----------------------------------- x -------------------------------------------------------------R fb1 x R fb2
 1 + sR O C COMP 
AV 1 x R DS(on)
 1 + sC O R load 
When:
CCOMP = Compensation capacitor
RDS(on) = LS switch resistance
RCOMP = Compensation resistor
Rfb1
= Feedback resistor connect to LX
gm
= Error amplifier transconductance
Rfb2
= Feedback resistor connect to ground
Rload
= Load resistance
RO
= Output impedance of error amplifier = 20 M
CO
= Output capacitor
AV1
= Voltage to current gain = 3
S13-2257-Rev. B, 11-Nov-13
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Power Save Mode using AUTO Pin
To further improve efficiency at light loads, SiP12108
provides a set of innovative implementations to eliminate LS
recirculating current and switching losses. The internal Zero
Crossing Detector (ZCD) monitors LX node voltage to
determine when inductor current starts to flow negatively. In
power saving mode (PSM), as soon as inductor valley
current crosses zero, the device first deploys diode
emulation mode by turning off LS FET. If load further
decreases, switching frequency is further reduced
proportional to load condition to save switching losses. The
switching frequency is set by the controller to maintain
regulation. At zero load this frequency can go as low as
hundreds of Hz.
Whenever fixed frequency PWM operation is required over
the entire load span, the power saving mode feature can be
disabled by connecting AUTO pin to VIN or AVIN.
OUTPUT MONITORING AND PROTECTION FEATURES
Output Over-Current Protection (OCP)
SiP12108 has pulse-by-pulse over-current limit control. The
inductor valley current is monitored during LS FET turn-on
period through RDS(on) sensing. After a pre-defined time, the
valley current is compared with internal threshold (7.5 A typ.)
to determine the threshold for OCP. If monitored current is
higher than threshold, HS turn-on pulse is skipped and LS
FET is kept on until the valley current returns below OCP
limit.
In the severe over-current condition, pulse-by-pulse current
limit eventually triggers output under-voltage protection
(UVP), which latches the device off to prevent catastrophic
thermal-related failure. UVP is described in the next section.
OCP is enabled immediately after AVIN passes UVLO level.
Figure 6 illustrates the OCP operation.
OCPthreshold
Iload
Iinductor
GH
Skipped GH Pulse
Fig. 23 - Over-Current Protection Illustration
Output Under-Voltage Protection (UVP)
UVP is implemented by monitoring output through VFB pin.
Once the voltage level at VFB is below 0.45 V for more than
20 μs, then UVP event is recognized and both HS and LS
MOSFETs are turned off. UVP latches the device off until
either AVIN or EN is recycled.
UVP is only active after the completion of soft-start
sequence. This function only exists on SiP12108. On the “A”
version of the device, SiP12108A, this feature is disabled.
Over-Temperature Protection (OTP)
SiP12108 has internal thermal monitor block that turns off
both HS and LS FETs when junction temperature is above
160 °C (typ.). A hysteresis of 30 °C is implemented, so when
junction temperature drops below 130 °C, the device
restarts by initiating the soft-start sequence again.
Soft Startup
For OVP implementation, output is monitored through VFB
pin. After soft-start, if the voltage level at VFB is above 21 %
(typ.), OVP is triggered with HS FET turning off and LS FET
turning on immediately to discharge the output. Normal
operation is resumed once VFB drops back to 0.6 V.
SiP12108 deploys an internally regulated soft-start
sequence to realize a monotonic startup ramp without any
output overshoot. Once AVIN is above UVLO level (2.55 V
typ.). Both the reference and VOUT will ramp up slowly to
regulation in 1 ms (typ.) with the reference going from 0 V to
0.6 V and VOUT rising monotonically to the programmed
output voltage.
OVP is active immediately after AVIN passes UVLO level.


During soft-start period, OCP is activated. OVP and
short-circuit protection are not active until soft-start is
complete.
Output Over-Voltage Protection (OVP)
S13-2257-Rev. B, 11-Nov-13
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Pre-bias Startup
Power Good (PGOOD)
In case of pre-bias startup, output is monitored through VFB
pin. If the sensed voltage on VFB is higher than the internal
reference ramp value, control logic prevents HS and LS FET
from switching to avoid negative output voltage spike and
excessive current sinking through LS FET.
SiP12108’s Power Good is an open-drain output. Pull
PGOOD pin high up to 5 V through a 10K resistor to use this
signal. Power Good window is shown in the below diagram.
If voltage level on VFB pin is out of this window, PGOOD
signal is de-asserted by pulling down to GND.
VFB_Rising_Vth_OV
(Typ. = 0.725 V)
VFB_Falling_Vth_OV
(Typ. = 0.675 V)
Vref (0.6 V)
VFB
VFB_Falling_Vth_UV
(Typ. = 0.525 V)
VFB_Rising_Vth_UV
(Typ. = 0.575 V)
Pull-high
PGOOD
Pull-low
Fig. 24 - PGOOD Window and Timing Diagram
DESIGN PROCEDURE
The design process of the SiP12108 is quite straight
forward. Only few passive components such as output
capacitors, inductor and Ron resistor need to be selected.
The following paragraph describes the selection procedure
for these peripheral components for a given operating
conditions.
Setting the Output Voltage
The output voltage is set by using a resistor divider on the
feedback (VFB) pin. The VFB pin is the negative input of the
internal error amplifier.
When in regulation the VFB voltage is 0.6 V. The output
voltage VO is set based on the following formula.
In the next example the following definitions apply:
VO = VFB (1 + R1/R2)
VINmax.: the highest specified input voltage
where R1 and R2 are shown in figure 21.
VINmin.: the minimum effective input voltage subject to
voltage drops due to connectors, fuses, switches,
and PCB traces
Setting Switching Frequency
Continuous load current relates to thermal stress
considerations which drive the selection of the inductor and
input capacitors.
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency. The desired switching frequency,
1 MHz was chosen based on optimizing efficiency while
maintaining a small footprint and minimizing component
cost.
Peak load current determines instantaneous component
stresses and filtering requirements such as inductor
saturation, output capacitors, and design of the current limit
circuit.
In order to set the design for 1 MHz switching frequency,
(RON) resistor which determines the on-time (indirectly
setting the frequency) needs to be calculated using the
following equation.
There are two values of load current to evaluate - continuous
load current and peak load current.
The following specifications are used in this design:
• VIN = 3.3 V ± 10 %
1
1
-  105 k
R ON = ---------------------- = -------------------------------------------------------------6
-12
F SW x K
1 x 10 x 10.45 x 10
• VOUT = 1.2 V ± 1 %
• FSW = 1 MHz
• Load = 5 A maximum
S13-2257-Rev. B, 11-Nov-13
Document Number: 62699
12
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INDUCTOR SELECTION
STABILITY CONSIDERATIONS
In order to determine the inductance, the ripple current must
first be defined. Cost, PCB size, output ripple, and efficiency
are all used in the selection process. Low inductor values
result in smaller size and allow faster transient performance
but create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current while
compromising the efficiency (higher DCR) and transient
response.
Using the output capacitance as a starting point for
compensation values. Then, taking Bode plots and transient
response measurements we can fine tune the compensation
values.
The ripple current will also set the boundary for power-save
operation. The switcher will typically enter power-save
mode when the load current decreases to 1/2 of the ripple
current. For example, if ripple current is 1 A then power-save
operation will typically start at loads approaching 0.5 A.
Alternatively, if ripple current is set at 40 % of maximum load
current, then power-save will start for loads less than
~ 20 % of maximum current.
Inductor selection for the SiP12108 should be designed
where the ripple current is ~ 50 % in all situations with VIN
3.6 V and less.
For example 3.3 VIN to 1.2 VOUT at 1 MHz.
dI = V/L x dt = ((3.3 - 1.2)/0.33) x 0.36 = 2.3 A, %dI = 2.3/5
= 46 %.
For higher VIN > 3.6 V ripple current should be set to less
then 40 %.
For 5 VIN to 1.2 VOUT at 1 MHz dI = ((5 - 1.2)/0.68) x 0.36)
= 2 A, %dI = 2/5 = 40 %.
Output Capacitance Calculation
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current
is at the peak, determines the required capacitance. If the
load release is instantaneous (load changes from maximum
to zero in < 1/FSW μs), the output capacitor must absorb all
the inductor’s stored energy. This will approximately cause
a peak voltage on the capacitor according to the following
equation.
2
1
L x  I OUT + --- x I RIPPLEmax.


2
C OUTmin. = -----------------------------------------------------------------------2
2
 V peak  -  V OUT 
Assuming a peak voltage VPEAK of 1.3 V (100 mV rise upon
load release), and a 5 A load release, the required
capacitance is shown by the next equation.
COUTmin. =
1 μH x (5 A + 0.5 x (0.81 A))2
= 116.8 μF
(1.3 V)2 - (1.2 V)2
Setting the crossover frequency to 1/5 of the switching
frequency: 
F0 = Fsw/5 = 1 MHz/5 = 200 kHz
Setting the compensation zero at 1/5 to 1/10 the crossover
frequency for the phase boost:
FZ =
F
1
= 0
2π x RC x CC
5
Setting CC = 0.47 nF and solve for RC
RC =
5
2π x CC x F0
=
5
= 8.469K
2π x 0.47 nF x 200K
SWITCHING FREQUENCY VARIATIONS
The switching frequency variation in COT can be mainly
attributed to the increase in conduction losses as the load
increases. The on time is “ideally constant” so the controller
must account for losses by reducing the off time which
increases the overall duty cycle. Hence the FSW will tend to
increase with load.
In power save mode (PSM) the IC will run in pulse skip mode
at light loads. As the load increases the FSW will increase
until it reaches the nominal set FSW. This transition occurs
approximately when the load reaches to 20 % of the full load
current.
DESIGN CONSIDERATION
For VOUT higher then UVLO (2.55 V typ) and/or very slow VIN
slew rates. The IC may have difficulty in starting-up because
VIN level is limiting how fast VOUT can rise. In these situations
a divider for EN pin threshold (~1.15 V) derived from VIN
can be used. Allowing a higher VIN level before switching
begins and a smooth start-up. For example Rtop = 60K and
Rbot = 25K when VIN=4 V, EN level will be 1.18 V.
THERMAL DESIGN
The 16 pin package includes a thermal pad for much
better thermal performance when incorporated in the PCB
footprint. As shown in the PCB layout at the end of this
document. There are four vias evenly placed on the pad that
help transfer the heat to other layers. Tying the paddle to the
bottom layer through vias will provide the best thermal
performance.
If the load release is relatively slow, the output capacitance
can be reduced. Using MLCC ceramic capacitors we will
use 5 x 22 μF or 110 μF as the total output capacitance.


S13-2257-Rev. B, 11-Nov-13
Document Number: 62699
13
For technical questions, contact: [email protected]
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SiP12108, SiP12108A
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Vishay Siliconix
J1
VIN
J4
1
1
VIN_GND
VIN
C4
22uF
C5
0.1uF
R8
1
J7
EN
1
C6
0.1uF
R2 100K
R3 100K
R4 100K
R1
100K
J5
MODE
1
1
VIN1
17
AVIN
R5
6K04
C7
470pF
8
AUTO
VIN2
PGOOD
U1
SiP12107/8
COMP 7
EN
6
RON
MODE 5
PGOOD
3
4
J6
PGOOD
1
AVIN 2
RON
COMP
AGND
PGND2
PGND1
LX1
16
15
14
13
AGND-PAD
LX2
LX3
FB
VO
12
11
10
9FB
LX
VO
C8*
0.1uF
C1
0.1uF
C2
22uF
VOGND
C3
22uF
1
1
.lanoitpo si roticapac sihT *
L1
0.47uH
R6
5K11
R7
2K55
J2
VO
J3
VO_GND
Fig. 25 - Reference Board Schematic
S13-2257-Rev. B, 11-Nov-13
Document Number: 62699
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BILL OF MATERIALS
ITEM
QTY.
REFERENCE
VALUE
VOLTAGE
PCB FOOTPRINT
PART NUMBER
MANUFACTURER
1
2
C1, C5
0.1 μF
50 V
C0402-TDK
VJ0402Y104MXQCW1BC
Vishay
2
2
C2, C3, C4
22 μF
10 V
C0805-TDK
LMK212BJ226MG-T
Murata
4
1
C6
0.1 μF
10 V
C0603-TDK
GRM188R71C104KA01D
Murata
5
1
C7
470 pF
50 V
C0402-TDK
VJ0402A471JXACW1BC
TDK
6
1
C8 (1)
DNP
-
C0603-TDK
-
-
7
1
J1
VIN
-
TP30
5002K-ND
Keystone
8
1
J2
VO
-
TP30
5002K-ND
Keystone
9
1
J3
VO_GND
-
TP30
5002K-ND
Keystone
10
1
J4
VIN_GND
-
TP30
5002K-ND
Keystone
11
1
J5
MODE
-
TP30
5002K-ND
Keystone
12
1
J6
PGOOD
-
TP30
5002K-ND
Keystone
13
1
J7
EN
-
TP30
5002K-ND
Keystone
14
1
L1
0.47 μH
-
IHLP1616
IHLP1616BZERR47M11
Vishay
15
4
R1, R2, R3, R4
100K
50 V
R0402-Vishay
CRCW0402100KFKED
Vishay
16
1
R5
6K04
50 V
R0402-Vishay
TNPW04026K04BETD Vishay
17
1
R6
5K11
50 V
R0402-Vishay
CRCW04025K11FKED
Vishay
18
1
R7
2K55
50 V
R0402-Vishay
TNPW04022K55BETD Vishay
19
1
R8
1
50 V
R0402-Vishay
RC0402FR-071RL
Yageo
20
1
U1
SiP12107,
SiP12108
-
MLP33-16
SiP1210x
Vishay
S13-2257-Rev. B, 11-Nov-13
Document Number: 62699
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PCB LAYOUT OF REFERENCE BOARD
Fig. 26 - Top Layer
S13-2257-Rev. B, 11-Nov-13
Fig. 27 - Bottom Layer
Document Number: 62699
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MLP33-16L CASE OUTLINE
(5)
(4)
MILLIMETERS (1)
INCHES
DIMENSION
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.75
0.85
0.95
0.029
0.033
0.037
A1
0
-
0.05
0
-
0.002
0.30
0.007
1.7
0.059
A3
b
0.20 REF
0.18
D
D2
0.25
0.001 REF
3.00 BSC
1.5
1.6
0.010
0.012
0.118 BSC
0.063
e
0.50 BSC
0.020 BSC
E
3.00 BSC
0.118 BSC
0.067
E2
1.5
1.6
1.7
0.059
0.063
0.067
L
0.3
0.4
0.5
0.012
0.016
0.020
N (3)
16
16
Nd (3)
4
4
Ne (3)
4
4
Notes
(1) Use millimeters as the primary measurement.
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
(3) N is the number of terminals. Nd and Ne is the number of terminals in each D and E site respectively.
(4) Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip.
(5) The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body.
(6) Package warpage max. 0.05 mm.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62699.
S13-2257-Rev. B, 11-Nov-13
Document Number: 62699
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Revision: 02-Oct-12
1
Document Number: 91000