TI SN74LVT8986PM

SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
D
D
D
D
D
D
D
D
Members of the Texas Instruments (TI)
Family of JTAG Scan-Support Products
Extend Scan Access From Board Level to
Higher Level of System Integration
Three IEEE Std 1149.1-Compatible
Configurable Secondary Scan Paths to One
Primary Scan Path
Multiple Devices Can Be Cascaded to Link
24 Secondary Scan Paths to One Primary
Scan Path
Simple (Linking Shadow) Protocol Is Used
to Connect the Primary Test Access Port
(TAP) to Secondary TAPs. This Single
Protocol Is Used to Address and Configure
the Secondary Scan Path.
The LASP(8986) and ASP(8996) Can Be
Configured on the Same Backplane Using
Similar Shadow Protocols
Linking Shadow Protocols Can Occur in
Any of Test-Logic-Reset, Run-Test/Idle,
Pause-DR, Pause-IR TAP States to Provide
Board-to-Board and Built-In Self-Test
D
D
D
D
D
Bypass (BYP5–BYP0) Forces Primary to
Configured Secondary Paths Without Use
of Linking Shadow Protocols
Connect (CON2–CON0) Provides Indication
of Primary-to-Secondary Paths
Connections
Secondary TAPs Can Be Configured at
High Impedance Via the OE Input to Allow
an Alternate Test Master to Take Control of
the Secondary TAPs
High-Drive Outputs (–32 mA IOH, 64 mA IOL)
Support Backplane Interface at Primary
Outputs and High Fanout at Secondary
Outputs
While Powered at 3.3 V, Both the Primary
and Secondary TAPs Are Fully 5-V Tolerant
for Interfacing 5-V and/or 3.3-V Masters and
Targets
Package Options Include Plastic BGA
(GGV) and LQFP (PM) Packages and
Ceramic Quad Flat (HV) Packages Using
25-mil Center-to-Center Spacing
description/ordering information
The ’LVT8986 Linking Addressable Scan Ports (LASPs) are members of the Texas Instruments family of IEEE
Std 1149.1 (JTAG) scan-support products. The scan-support product family facilitates testing of fully
boundary-scannable devices. The LASP applies linking shadow protocols through the test access port (TAP)
to extend scan access to the system level and divide scan chains at the board level.
The LASP consists of a primary TAP for interfacing to the backplane IEEE Std 1149.1 serial-bus signals (PTDI,
PTMS, PTCK, PTDO, PRTST) and three secondary TAPs for interfacing to the board-level IEEE Std 1149.1
serial-bus signals. Each secondary TAP consists of signals STDIx, STMSx, STCKx, STDOx, and STRSTx.
Conceptually, the LASP is a simple switch that can be used to connect directly a set of primary TAP signals to
a set of secondary TAP signals—for example, to interface backplane TAP signals to a board-level TAP. The
LASP provides all signal buffering that might be required at these two interfaces. Primary-to-secondary TAP
connections can be configured with the help of linking shadow protocol or protocol bypass (BYP5–BYP0) inputs.
All possible configurations are tabulated in Function Tables 1, 2, and 3.
ORDERING INFORMATION
TA
–40°C to 85°C
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PBGA (GGV)
SN74LVT8986GGV
LVT8986
LQFP – PM
SN74LVT8986PM
LVT8986
–55°C to 125°C
CFP – HV
SNJ54LVT8986HV
SNJ54LVT8986HV
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
GGV package pinout (top view)
2
1
2
3
4
5
6
7
8
A
A0
STRST0
GND
STDO0
SXO
GND
STMS1
STDI1
B
A1
OE
STMS0
SY0
VCC
STCK1
VCC
STDO1
C
GND
A2
STCK0
STDI0
CON0
SY1
GND
SX1
D
A5
A6
A4
A3
STRST1
CON1
VCC
STRST2
E
A8
A7
A9
BYP5
GND
STDI2
STCK2
STMS2
F
P0
P1
P2
PTRST
PTDO
PY
SY2
STDO2
G
VCC
BYP0
BYP3
PTMS
PTDI
GND
PX
SX2
H
BYP1
BYP2
BYP4
PTCK
CTDI
CTDO
VCC
CON2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
STMS2
STDI 2
GND
STDO2
SY2
SX2
CON 2
39
37
35
33
34
STCK 2
40
36
STRST2
VCC
42
38
CON 1
43
41
SX1
GND
45
44
STDO1
SY1
47
46
VCC
48
SN74LVT8986 . . . PM PACKAGE
(TOP VIEW)
STDI1
49
32
PX
STMS1
50
31
VCC
STCK1
51
30
PY
GND
52
29
GND
STRST1
53
28
CTDO
CON0
54
27
PTDO
SX0
55
26
CTDI
VCC
56
25
PTDI
SY0
57
24
PTMS
STDO0
58
23
PTCK
STDI0
59
22
PTRST
10
11
12
13
14
15
16
P0
P1
P2
V CC
BYP0
8
A9
A1
A2
A0
9
BYP1
A8
17
7
64
A6
A7
BYP2
OE
6
18
A5
63
A4
BYP3
STRST0
5
STCK0
19
4
BYP4
62
GND
A3
BYP5
20
3
21
61
2
60
1
GND
STMS0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
STDO1
SY1
SX1
GND
CON 1
STRST2
VCC
NC
STCK 2
STMS 2
STDI 2
GND
STDO 2
SY2
SX2
CON 2
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCC
59
60
SN54LVT8986 . . . HV PACKAGE
(TOP VIEW)
SY0
PTMS
STDO0
3
33
PTCK
STDI0
4
32
PTRST
GND
5
31
BYP5
STMS0
6
30
BYP4
STCK0
7
29
BYP3
STRST0
8
28
BYP2
OE
9
27
BYP1
BYP0
26
NC
34
25
35
2
24
1
P2
VCC
NC
23
PTDI
22
36
P1
68
21
VCC
P0
CTDI
A9
PTDO
37
20
38
67
19
66
SX0
A8
CON0
18
CTDO
NC
A7
39
17
65
16
STRST1
A6
GND
A5
40
15
PY
A4
41
64
14
63
GND
13
STCK1
A3
VCC
GND
42
12
62
11
STMS1
A2
PX
10
43
A1
61
A0
STDI1
NC – No internal connection
description/ordering information (continued)
Most operations of the LASP are synchronous to the primary test clock (PTCK) input. PTCK always is buffered
directly onto the secondary test clock (STCK2–STCK0) outputs. Upon power up of the device, the LASP
assumes a condition in which the primary TAP is disconnected from the secondary TAPs (unless the bypass
signals are used, as shown in Function Tables 1 and 2). This reset condition also can be entered by asserting
the primary test reset (PTRST) input or by using the linking shadow protocol. PTRST always is buffered directly
onto the secondary test reset (STRST2–STRST0) outputs, ensuring that the LASP and its associated secondary
TAPs can be reset simultaneously. The primary test data output (PTDO) can be configured to receive secondary
test data inputs (STDI2–STDI0). Secondary test data outputs (STDO2–STDO0) can be configured to receive
either the primary test data input (PTDI), STDI2–STDI0, or the cascade test data input (CTDI). Cascade test data
output (CTDO) can be configured to receive either of STDI2–STDI0, or CTDI. CTDI and CTDO facilitate
cascading multiple LASPs, which is explained in the latter part of this section. Similarly, secondary test-mode
select (STMS2–STMS0) outputs can be configured to receive the primary test-mode select (PTMS) input. When
any secondary TAP is disconnected, its respective STDO is at high impedance. Upon disconnecting the
secondary TAP, the corresponding STMS holds its last low or high level, allowing the secondary TAP to be held
in its last stable state.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
description/ordering information (continued)
The address (A9–A0) inputs to the LASP are used to identify the LASP. The position (P2–P0) inputs to the LASP
are used to identify the position of the LASP within a cascade chain when multiple LASPs are cascaded. Up
to 8 LASPs can be cascaded to link a maximum of 24 secondary scan paths to 1 primary scan path.
In a system, primary-to-secondary connection is based on linking shadow protocols that are received and
acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states,
other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential
nature of the protocols is to receive/transmit an address, position the LASP in the cascade chain that is being
configured, and configuration of secondary TAPs via a serial bit-pair signaling scheme. When address and
position bits received serially at PTDI match those at the parallel address (A9–A0) inputs and position (P2–P0)
inputs respectively, the secondary TAPs are configured per the configuration bits received during the linking
shadow protocol, then LASP serially retransmits the entire linking shadow protocol as an acknowledgment and
assumes the connected (ON) status. If the received address or position does not match that at the address
(A9–A0) inputs or position (P2–P0) inputs, the LASP immediately assumes the disconnected (OFF) status,
without acknowledgment.
The LASP also supports three dedicated addresses that can be received globally (that is, to which all LASPs
respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the LASP to
disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures
that at least one address is available to disconnect all receiving LASPs. The DSA is especially useful when the
secondary TAPs of multiple LASPs are to be left in different stable states. Receipt of the reset address (RSA)
causes the LASP to assume the reset condition. Receipt of the test-synchronization address (TSA) causes the
LASP to assume a connect status (MULTICAST) in which PTDO is at high impedance, but the configuration
of the secondary TAPs are maintained to allow simultaneous operation of the secondary TAPs of multiple
LASPs. This is useful for multicast TAP-state movement, simultaneous test operation, such as in Run-Test/Idle
state, and scanning of common test data into multiple like scan chains. The MULTICAST status may also be
useful for concurrent in-system programming (ISP) of common modules. The TSA is valid only when received
in the Pause-DR or Pause-IR TAP states. Refer to Table 9 for different address mapping.
Alternatively, primary-to-secondary connection can be selected by asserting a low level at the bypass (BYP5)
input. The remaining bypass (BYP4–BYP0) inputs are used for configuring the secondary TAPs as shown in
Table 1 and Table 2. This operation is asynchronous to PTCK and is independent of PTRST and/or power-up
reset. This bypassing feature is especially useful in the board-test environment because it allows board-level
automated test equipment (ATE) to treat the LASP as a simple transceiver. When BYP5 is high, the LASP is
free to respond to linking shadow protocols. Otherwise, when BYP5 is low, linking shadow protocols are ignored.
Whether the connected status is achieved by use of linking shadow protocol or by use of bypass inputs, this
status is indicated by a low level at the connect (CON2–CON0) outputs. Likewise, when the secondary TAP is
disconnected from the primary TAP, the corresponding CON output is high. Each secondary TAP has a
pass-through input and output consisting of SX2–SX0 and SY2–SY0, respectively. Similarly, the primary TAP
also has a pass-through input and output consisting of PX and PY, respectively. Pass-through input PX drives
the SY outputs of the secondary TAPs that are connected to the primary TAP. Disconnected secondary TAPs
have their SY outputs at high impedance. Pass-through inputs SY2–SY0 of the connected secondary TAPs are
logically ANDed and drive the PY output. Refer to Table 4–7 for pass-through input/output operation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
functional block diagram
VCC
VCC
CTDI
STDI2
STCK2
CTDO
STRST2
PTCK
STMS2
VCC
STDO2
CON2
PTRST
VCC
PTMS
SY2
VCC
VCC
SX2
PTDI
VCC
STDI1
PTDO
STCK1
STRST1
Secondary
TAP Network
STMS1
STDO1
CON1
SY1
VCC
Linking Shadow
Protocol
Transmit
VCC
SX1
A0-A9
VCC
VCC
P0-P2
STDI0
VCC
STCK0
Connect
Control
BYP0-BYP5
STRST0
STMS0
STDO0
VCC
CON0
SY0
PX
PY
VCC
Linking Shadow
Protocol
Receive
SX0
OE
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
FUNCTION TABLE 1
(primary to secondary connect status)
INPUTS
LINKING SHADOW
PROTOCOL RESULT
PRIMARY-TOSECONDARY
CONNECT
STATUS
CON2
CON1
CON0
H
OUTPUTS
BYP5
BYP4
BYP3
BYP2
BYP1
BYP0
PTRST
L
X
X
H
H
H
L
–
BYP/TRST
H
H
L
X
X
H
H
L
L
–
BYP/TRST
H
H
L
L
X
X
H
L
H
L
–
BYP/TRST
H
L
H
L
X
X
H
L
L
L
–
BYP/TRST
H
L
L
L
X
X
L
H
H
L
–
BYP/TRST
L
H
H
L
X
X
L
H
L
L
–
BYP/TRST
L
H
L
L
X
X
L
L
H
L
–
BYP/TRST
L
L
H
L
X
X
L
L
L
L
–
BYP/TRST
L
L
L
L
X
X
H
H
H
H
–
BYP
H
H
H
L
X
X
H
H
L
H
–
BYP
H
H
L
L
X
X
H
L
H
H
–
BYP
H
L
H
L
X
X
H
L
L
H
–
BYP
H
L
L
L
X
X
L
H
H
H
–
BYP
L
H
H
L
X
X
L
H
L
H
–
BYP
L
H
L
L
X
X
L
L
H
H
–
BYP
L
L
H
L
X
X
L
L
L
H
–
BYP
L
L
L
H
X
X
X
X
X
L
–
TRST
H
H
H
H
X
X
X
X
X
H
RESET
RESET
H
H
H
H
X
X
X
X
X
H
MATCH
ON
See Function Table 3
H
X
X
X
X
X
H
NO MATCH
OFF
H
H
H
H
X
X
X
X
X
H
HARD ERROR
OFF
H
H
H
H
X
X
X
X
X
H
DISCONNECT
OFF
H
H
H
H
TEST
SYNCHRONIZATION
MULTICAST
H
X
X
X
X
X
See Note 1
NOTE 1: The result of receipt of the test synchronization address (TSA) on a secondary TAP, whose TAP state is Pause-DR or Pause-IR, is ON
and the corresponding CON output is set low. The result of receipt of the TSA on a secondary TAP whose TAP state is Test-Logic-Reset
or Run-Test-Idle is disconnect, and the corresponding CON output is set high.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
FUNCTION TABLE 2
(secondary TAP configuration using bypass inputs)
INPUTS
BYP5–0
PTRST
LINKING SHADOW
PROTOCOL
RESULT
LLLHHH
L
–
OUTPUTS
STRST
2–0
STCK
2–0
STMS2
STMS1
STMS0
STDO2
STDO1
L
PTCK
H†
H†
H†
Z
Z
Z
Z
CTDI
H†
H†
Z
Z
PTDI
STDI0
STDI0
PTDO
CTDO
LLLHHL
L
–
L
PTCK
H†
LLLHLH
L
–
L
PTCK
H†
H†
H†
Z
PTDI
Z
STDI1
STDI1
LLLHLL
L
–
L
PTCK
H†
H†
H†
Z
STDI0
PTDI
STDI1
STDI1
LLLLHH
L
–
L
PTCK
H†
H†
H†
PTDI
Z
Z
STDI2
STDI2
H†
H†
LLLLHL
L
–
L
PTCK
H†
STDI0
Z
PTDI
STDI2
STDI2
LLLLLH
L
–
L
PTCK
H†
H†
H†
STDI1
PTDI
Z
STDI2
STDI2
LLLLLL
L
–
L
PTCK
H†
H†
H†
STDI1
STDI0
PTDI
STDI2
STDI2
LLHHHH
L
–
L
PTCK
H†
H†
H†
Z
Z
Z
Z
CTDI
LLHHHL
L
–
L
PTCK
H†
H†
H†
Z
Z
PTDI
Z
STDI0
LLHHLH
L
–
L
PTCK
H†
H†
H†
Z
PTDI
Z
Z
STDI1
H†
H†
LLHHLL
L
–
L
PTCK
H†
Z
STDI0
PTDI
Z
STDI1
LLHLHH
L
–
L
PTCK
H†
H†
H†
PTDI
Z
Z
Z
STDI2
LLHLHL
L
–
L
PTCK
H†
H†
H†
STDI0
Z
PTDI
Z
STDI2
LLHLLH
L
–
L
PTCK
H†
H†
H†
STDI1
PTDI
Z
Z
STDI2
LLHLLL
L
–
L
PTCK
H†
H†
H†
STDI1
STDI0
PTDI
Z
STDI2
LHLHHH
L
–
L
PTCK
H†
H†
H†
Z
Z
Z
Z
CTDI
H†
H†
LHLHHL
L
–
L
PTCK
H†
Z
Z
CTDI
STDI0
STDI0
LHLHLH
L
–
L
PTCK
H†
H†
H†
Z
CTDI
Z
STDI1
STDI1
LHLHLL
L
–
L
PTCK
H†
H†
H†
Z
STDI0
CTDI
STDI1
STDI1
LHLLHH
L
–
L
PTCK
H†
H†
H†
CTDI
Z
Z
STDI2
STDI2
LHLLHL
L
–
L
PTCK
H†
H†
H†
STDI0
Z
CTDI
STDI2
STDI2
LHLLLH
L
–
L
PTCK
H†
H†
H†
STDI1
CTDI
Z
STDI2
STDI2
LHLLLL
L
–
L
PTCK
H†
H†
H†
STDI1
STDI0
CTDI
STDI2
STDI2
LHHHHH
L
–
L
PTCK
H†
H†
H†
Z
Z
Z
Z
CTDI
H†
H†
Z
Z
CTDI
Z
STDI0
LHHHHL
L
–
L
PTCK
H†
LHHHLH
L
–
L
PTCK
H†
H†
H†
Z
CTDI
Z
Z
STDI1
LHHHLL
L
–
L
PTCK
H†
H†
H†
Z
STDI0
CTDI
Z
STDI1
LHHLHH
L
–
L
PTCK
H†
H†
H†
CTDI
Z
Z
Z
STDI2
H†
H†
LHHLHL
L
–
L
PTCK
H†
STDI0
Z
CTDI
Z
STDI2
LHHLLH
L
–
L
PTCK
H†
H†
H†
STDI1
CTDI
Z
Z
STDI2
LHHLLL
L
–
L
PTCK
H†
H†
H†
STDI1
STDI0
CTDI
Z
STDI2
LLLHHH
H
–
H
PTCK
Z
Z
Z
Z
CTDI
H
–
H
PTCK
STMS1‡
STMS1‡
STMS0‡
LLLHHL
PTMS
Z
Z
PTDI
STDI0
STDI0
LLLHLH
H
–
H
PTCK
PTMS
STMS0‡
Z
PTDI
Z
STDI1
STDI1
PTMS
PTMS
Z
STDI0
PTDI
STDI1
STDI1
STMS0‡
PTDI
Z
Z
STDI2
STDI2
PTMS
STDI0
Z
PTDI
STDI2
STDI2
LLLHLL
H
–
H
PTCK
STMS2‡
STMS2‡
STMS2‡
STMS2‡
LLLLHH
H
–
H
PTCK
PTMS
LLLLHL
H
–
H
PTCK
PTMS
STMS1‡
STMS1‡
LLLLLH
H
–
H
PTCK
PTMS
PTMS
STMS0‡
STDI1
PTDI
Z
STDI2
STDI2
LLLLLL
H
–
H
PTCK
PTMS
PTMS
PTMS
STDI1
STDI0
PTDI
STDI2
STDI2
NOTE: Footnotes are on the next page.
8
STDO0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
FUNCTION TABLE 2
(secondary TAP configuration using bypass inputs) (continued)
INPUTS
OUTPUTS
BYP5–0
PTRST
LINKING SHADOW
PROTOCOL
RESULT
LLHHHH
H
–
H
PTCK
LLHHHL
H
–
H
PTCK
LLHHLH
H
–
H
PTCK
LLHHLL
H
–
H
LLHLHH
H
–
LLHLHL
H
LLHLLH
H
LLHLLL
STRST
2–0
STCK
2–0
STMS2
STMS1
STMS0
STDO2
STDO1
STDO0
PTDO
STMS1‡
STMS1‡
STMS0‡
Z
PTMS
Z
PTMS
STMS0‡
Z
PTCK
STMS2‡
STMS2‡
STMS2‡
STMS2‡
PTMS
PTMS
Z
H
PTCK
PTMS
STMS0‡
PTDI
–
H
PTCK
PTMS
STMS1‡
STMS1‡
PTMS
–
H
PTCK
PTMS
PTMS
STMS0‡
H
–
H
PTCK
PTMS
PTMS
LHLHHH
H
–
H
PTCK
LHLHHL
H
–
H
PTCK
LHLHLH
H
–
H
PTCK
PTMS
CTDO
Z
Z
Z
CTDI
Z
PTDI
Z
STDI0
PTDI
Z
Z
STDI1
STDI0
PTDI
Z
STDI1
Z
Z
Z
STDI2
STDI0
Z
PTDI
Z
STDI2
STDI1
PTDI
Z
Z
STDI2
PTMS
STDI1
STDI0
PTDI
Z
STDI2
STMS1‡
STMS1‡
STMS0‡
Z
Z
Z
Z
CTDI
PTMS
Z
Z
CTDI
STDI0
STDI0
PTMS
STMS0‡
Z
CTDI
Z
STDI1
STDI1
PTMS
Z
STDI0
CTDI
STDI1
STDI1
STMS0‡
CTDI
Z
Z
STDI2
STDI2
PTMS
STDI0
Z
CTDI
STDI2
STDI2
LHLHLL
H
–
H
PTCK
STMS2‡
STMS2‡
STMS2‡
STMS2‡
LHLLHH
H
–
H
PTCK
PTMS
LHLLHL
H
–
H
PTCK
PTMS
STMS1‡
STMS1‡
LHLLLH
H
–
H
PTCK
PTMS
PTMS
STMS0‡
STDI1
CTDI
Z
STDI2
STDI2
LHLLLL
H
–
H
PTCK
PTMS
PTMS
PTMS
STDI1
STDI0
CTDI
STDI2
STDI2
LHHHHH
H
–
H
PTCK
Z
Z
Z
Z
CTDI
H
–
H
PTCK
STMS1‡
STMS1‡
STMS0‡
LHHHHL
PTMS
Z
Z
CTDI
Z
STDI0
LHHHLH
H
–
H
PTCK
PTMS
STMS0‡
Z
CTDI
Z
Z
STDI1
LHHHLL
H
–
H
PTCK
STMS2‡
STMS2‡
STMS2‡
STMS2‡
PTMS
PTMS
Z
STDI0
CTDI
Z
STDI1
LHHLHH
H
–
H
PTCK
PTMS
STMS0‡
CTDI
Z
Z
Z
STDI2
LHHLHL
H
–
H
PTCK
PTMS
STMS1‡
STMS1‡
PTMS
STDI0
Z
CTDI
Z
STDI2
LHHLLH
H
–
H
PTCK
PTMS
PTMS
STMS0‡
STDI1
CTDI
Z
Z
STDI2
LHHLLL
H
–
H
PTCK
PTMS
PTMS
PTMS
STDI1
STDI0
CTDI
Z
STDI2
HXXXXX
L
–
L
PTCK
H
H
H
Z
Z
Z
Z
H
HXXXXX
H
RESET
H
PTCK
H
H
H
Z
Z
Z
Z
CTDI
HXXXXX
H
MATCH
H
PTCK
HXXXXX
H
NO MATCH
H
PTCK
Z
Z
CTDI
HARD ERROR§
H
PTCK
Z
Z
Z
Z
CTDI
HXXXXX
H
DISCONNECT
H
PTCK
STMS0‡
STMS0‡
STMS0‡
Z
H
STMS1‡
STMS1‡
STMS1‡
Z
HXXXXX
STMS2‡
STMS2‡
STMS2‡
Z
Z
Z
Z
CTDI
H
TEST
SYNCHRONIZATION
PTCK
PTMS¶
PTMS¶
PTMS¶
PTDI¶
PTDI¶
PTDI¶
Z
CTDI
HXXXXX
H
See Function Table 3
† In normal operation of IEEE Std 1149.1-compliant architectures, it is recommended that TMS be high prior to release of TRST. The BYP/TRST
connect status ensures that this condition is met at STMS, regardless of the applied PTMS. Also, it is recommended that STMS be kept high
for a minimum duration of five PTCK cycles following assertion of PTRST, either by maintaining PTRST low or by setting PTMS high. This ensures
that devices with and without TRST inputs are moved to their Test-Logic-Reset TAP states. It is expected that, in normal application, this condition
occurs only when BYP5 is fixed at the low state. In such a case, upon release of PTRST, the LASP immediately resumes the BYP connect status.
‡ STMS level before steady-state conditions were established
§ The linking shadow protocol is well defined. Some variations in the protocol are tolerated (see protocol errors). Those that are not tolerated
produce the result HARD ERROR and cause disconnect, as indicated.
¶ PTDI and PTMS are connected to STDO and STMS, respectively, only on those secondary TAPs whose TAP state is Pause-DR or Pause-IR
while PTDO is high impedance. The result of linking shadow protocol on a secondary TAP whose state is Test-Logic-Reset or Run-Test-Idle is
DISCONNECT.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
FUNCTION TABLE 3
(secondary TAP configuration using linking shadow protocol)
POSITION
Single device
First device in
cascade chain
Not first
and not last
device in
d chain
h i
cascade
Last device in
cascade chain
CONFIG
BITS
2–0
STRST
2–0
STCK
2–0
HHH
H
PTCK
HHL
H
PTCK
HLH
H
PTCK
STMS2
STMS1
STMS0
STDO2
STDO1
STMS1†
STMS1†
STMS0†
Z
Z
Z
PTMS
Z
Z
PTDI
PTMS
STMS0†
Z
PTDI
Z
PTMS
PTMS
Z
STDI0
STMS1†
STMS1†
STMS0†
PTDI
Z
PTMS
STDI0
Z
HLL
H
PTCK
STMS2†
STMS2†
STMS2†
STMS2†
LHH
H
PTCK
PTMS
LHL
H
PTCK
PTMS
PTDO
CTDO
CON2
CON1
CON0
Z
CTDI
H
H
H
STDI0
STDI0
H
H
L
STDI1
STDI1
H
L
H
PTDI
STDI1
STDI1
H
L
L
Z
STDI2
STDI2
L
H
H
PTDI
STDI2
STDI2
L
H
L
H
LLH
H
PTCK
PTMS
PTMS
STMS0†
STDI1
PTDI
Z
STDI2
STDI2
L
L
LLL
H
PTCK
PTMS
PTMS
PTMS
STDI1
STDI0
PTDI
STDI2
STDI2
L
L
L
HHH
H
PTCK
STMS0†
Z
Z
Z
Z
CTDI
H
H
H
HHL
H
PTCK
STMS1†
STMS1†
PTMS
Z
Z
PTDI
Z
STDI0
H
H
L
HLH
H
PTCK
PTMS
STMS0†
Z
PTDI
Z
Z
STDI1
H
L
H
PTMS
PTMS
Z
STDI0
PTDI
Z
STDI1
H
L
L
STMS1†
STMS1†
STMS0†
PTDI
Z
Z
Z
STDI2
L
H
H
PTMS
STDI0
Z
PTDI
Z
STDI2
L
H
L
H
HLL
H
PTCK
STMS2†
STMS2†
STMS2†
STMS2†
LHH
H
PTCK
PTMS
LHL
H
PTCK
PTMS
LLH
H
PTCK
PTMS
PTMS
STMS0†
STDI1
PTDI
Z
Z
STDI2
L
L
LLL
H
PTCK
PTMS
PTMS
PTMS
STDI1
STDI0
PTDI
Z
STDI2
L
L
L
HHH
H
PTCK
STMS0†
Z
Z
Z
Z
CTDI
H
H
H
HHL
H
PTCK
STMS1†
STMS1†
PTMS
Z
Z
CTDI
Z
STDI0
H
H
L
HLH
H
PTCK
PTMS
STMS0†
Z
CTDI
Z
Z
STDI1
H
L
H
PTMS
PTMS
Z
STDI0
CTDI
Z
STDI1
H
L
L
STMS0†
CTDI
Z
Z
Z
STDI2
L
H
H
PTMS
STDI0
Z
CTDI
Z
STDI2
L
H
L
STMS0†
STDI1
CTDI
Z
Z
STDI2
L
L
H
HLL
H
PTCK
STMS2†
STMS2†
STMS2†
STMS2†
LHH
H
PTCK
PTMS
LHL
H
PTCK
PTMS
STMS1†
STMS1†
LLH
H
PTCK
PTMS
PTMS
LLL
H
PTCK
PTMS
PTMS
PTMS
STDI1
STDI0
CTDI
Z
STDI2
L
L
L
HHH
H
PTCK
STMS0†
Z
Z
Z
Z
CTDI
H
H
H
HHL
H
PTCK
STMS1†
STMS1†
PTMS
Z
Z
CTDI
STDI0
STDI0
H
H
L
HLH
H
PTCK
PTMS
STMS0†
Z
CTDI
Z
STDI1
STDI1
H
L
H
PTMS
PTMS
Z
STDI0
CTDI
STDI1
STDI1
H
L
L
STMS0†
CTDI
Z
Z
STDI2
STDI2
L
H
H
PTMS
STDI0
Z
CTDI
STDI2
STDI2
L
H
L
STMS0†
PTMS
STDI1
STDI1
CTDI
Z
L
H
CTDI
STDI2
STDI2
L
STDI0
STDI2
STDI2
L
L
L
HLL
H
PTCK
STMS2†
STMS2†
STMS2†
STMS2†
LHH
H
PTCK
PTMS
LHL
H
PTCK
PTMS
STMS1†
STMS1†
LLH
H
PTCK
PTMS
PTMS
LLL
H
PTCK
PTMS
PTMS
† STMS level before steady-state conditions were established
10
STDO0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
FUNCTION TABLE 4
(SYX output configuration using bypass inputs)
BYP5–BYP0
SY2
SY2
SY2
LXXHHH
Z
Z
Z
LXXHHL
Z
Z
PX
LXXHLH
Z
PX
Z
LXXHLL
Z
PX
PX
LXXLHH
PX
Z
Z
LXXLHL
PX
Z
PX
LXXLLH
PX
PX
Z
LXXLLL
PX
PX
PX
As requested by linking shadow protocol
(see Function Table 5)
HXXXXX
FUNCTION TABLE 5
(SYX output configuration using linking shadow protocol)
CON2–CON0
SY2
SY2
SY2
HHH
Z
Z
Z
HHL
Z
Z
PX
HLH
Z
PX
Z
PX
HLL
Z
PX
LHH
PX
Z
Z
LHL
PX
Z
PX
LLH
PX
PX
Z
LLL
PX
PX
PX
FUNCTION TABLE 6
(PY output configuration using bypass inputs)
BYP5–BYP0
LXXHHH
PY
LXXHHL
SX1
SX2
Z
LXXHLH
LXXHLL
SX2 AND SX1
SX3
LXXLHH
LXXLHL
SX3 AND SX1
SX3 AND SX2
LXXLLH
LXXLLL
HXXXXX
SX3 AND SX2 AND SX1
As requested by linking shadow protocol
(see Function Table 5)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
FUNCTION TABLE 7
(PY output configuration using linking shadow protocol)
CON2–CON0
PY
HHH
Z
HHL
SX1
SX2
HLH
HLL
SX2 AND SX1
SX3
LHH
LHL
LLH
SX3 AND SX1
SX3 AND SX2
LLL
SX3 AND SX2 AND SX1
Terminal Functions
TERMINAL
NAME
A9–A0
P2–P0
DESCRIPTION
Address inputs. The LASP compares addresses received via linking shadow protocol against the value at A9–A0
to determine address match. The bit order is from most significant to least significant. An internal pullup at each
A9–A0 terminal forces the terminal to a high level if it has no external connection.
Position inputs. The LASP compares position received via linking shadow protocol against the value at P2–P0 to
determine position match. The bit order is from most significant to least significant. An internal pullup at each P2–P0
terminal forces the terminal to a high level if it has no external connection.
BYP5–BYP0
Bypass inputs. A low input at BYP5 forces the LASP into BYP or BYP/TRST status, depending on PTRST being
high or low, respectively. While BYP5 is low, linking shadow protocols are ignored and the remaining bypass
BYP4–BYP0 inputs are used for configuring the secondary scan ports as shown in Tables 1 and 2. Otherwise, while
BYP5 is high, the LASP is free to respond to linking shadow protocols. An internal pullup forces BYP5–BYP0 to a
high level if it has no external connection.
CON2–CON0
Connect indicators (outputs). The LASP indicates secondary-scan-port activity (resulting from BYP, BYP/TRST,
MULTICAST, or ON status) by forcing the corresponding CON bit to be low. Inactivity (resulting from OFF, RESET,
or TRST status) is indicated when the corresponding CON bit is high. This output is synchronous to the falling edge
of PTCK.
PTCK
Primary test clock. PTCK receives the TCK signal required by IEEE Std 1149.1. The LASP always buffers PTCK
to STCK2–STCK0. Linking shadow protocols are received/acknowledged synchronously to PTCK and
connect-status changes invoked by the linking shadow protocol are made synchronously to PTCK.
PTDI
Primary test data input. PTDI receives the TDI signal required by IEEE Std 1149.1. During appropriate TAP states,
the LASP monitors PTDI for linking shadow protocols. During linking shadow protocols, data at PTDI is captured
on the rising edge of PTCK. When a valid linking shadow protocol is received in this fashion, the LASP compares
the received address and position against the A9–A0 and P2–P0 inputs, respectively. If the LASP detects a match,
it outputs an acknowledgment, then connects its primary TAP terminals to its secondary TAP terminals. Under BYP,
BYP/TRST, MULTICAST, or ON status, the LASP buffers the PTDI signal to STDO2–STDO0, depending on the
state of BYP4–BYP0 pins or the configuration requested during linking shadow protocol. An internal pullup forces
PTDI to a high level if it has no external connection.
PTDO
Primary test data output. PTDO transmits the TDO signal required by IEEE Std 1149.1. During linking shadow
protocols, the LASP transmits any required acknowledgment via the PTDO. Under BYP, BYP/TRST, or ON status,
the LASP buffers the PTDO signal from PTDI or STDI2–STDI0, depending on the state of BYP4–BYP0 pins or the
configuration requested during linking shadow protocol. Under OFF, MULTICAST, RESET, or TRST status, PTDO
is at high impedance. This output is synchronous to the falling edge of PTCK.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
PTMS
Primary test mode select. PTMS receives the TMS signal required by IEEE Std 1149.1. The LASP monitors PTMS
to determine the TAP-controller state. During stable TAP states, other than Shift-DR or Shift-IR (i.e.,
Test-Logic-Reset, Run-Test-Idle, Pause-DR, Pause-IR), the LASP can respond to linking shadow protocols. Under
BYP, MULTICAST, or ON status, the LASP buffers the PTMS signal to STMS2–STMS0, depending on the state of
BYP4–BYP0 pins or the configuration requested during linking shadow protocol. An internal pullup forces PTMS
to a high level if it has no external connection.
PTRST
Primary test reset. PTRST receives the TRST signal allowed by IEEE Std 1149.1. The LASP always buffers PTRST
to STRST2–STRST0. A low input at PTRST forces the LASP to assume TRST or BYP/TRST status, depending
on BYP5 being high or low, respectively. Such operation also asynchronously resets the internal LASP state to its
power-up condition. Otherwise, while PTRST is high, the LASP is free to respond to linking shadow protocols. An
internal pullup forces PTRST to a high level if it has no external connection.
STCK2–STCK0
Secondary test clocks. STCK2–STCK0 retransmit the TCK signal required by IEEE Std 1149.1. The LASP always
buffers STCK2–STCK0 from PTCK.
STDI2–STDI0
STDO2–STDO0
Secondary test data inputs. STDI2–STDI0 receive the TDI signal required by IEEE Std 1149.1. Under BYP,
BYP/TRST, or ON status, the LASP buffers STDI2–STDI0 to STDO2–STDO0 or PTDO, depending on the state of
BYP4–BYP0 pins or the configuration requested during linking shadow protocol. An internal pullup forces
STDI2–STDI0 to a high level if it has no external connection.
Secondary test data outputs. STDO2–STDO0 transmit the TDO signal required by IEEE Std 1149.1. Under BYP,
BYP/TRST, MULTICAST, or ON status, the LASP buffers STDO2–STDO0 from STDI2–STDI0, PTDI, or CTDI,
depending on the state of BYP4–BYP0 pins or the configuration requested during linking shadow protocol. Under
OFF, RESET, or TRST status, STDO2–STDO0 is at high impedance. These outputs are synchronous to the falling
edge of PTCK.
STMS2–STMS0
Secondary test mode selects. STMS2–STMS0 retransmit the TMS signal required by IEEE Std 1149.1. Under BYP,
MULTICAST, or ON status, the LASP buffers STMS2–STMS0 from PTMS, depending on the state of BYP4–BYP0
pins or the configuration requested during linking shadow protocol. When disconnected (as a result of OFF status),
STMS2–STMS0 maintain their last valid state until the LASP assumes BYP/TRST, RESET, or TRST status (upon
which it is forced high) or the LASP again assumes BYP, MULTICAST, or ON status.
STRST2–STRST0
Secondary test resets. STRST2–STRST0 retransmit the TRST signal allowed by IEEE Std 1149.1. The LASP
always buffers STRST2–STRST0 from PTRST.
CTDI
Cascade test data input. CTDI facilitates cascading multiple LASPs. CTDI is connected to CTDO of the preceding
LASP in the cascade chain. When the LASP is the first device in the cascade chain or is not cascaded to any other
LASPs, CTDI has no external connection and an internal pullup forces CTDI to a high level.
CTDO
Cascade test data output. CTDO facilitates cascading multiple LASPs. CTDO is connected to CTDI of the
succeeding LASP in the cascade chain. The LASP buffers CTDO from STDI2–STDI0 or CTDI, depending on the
state of BYP4–BYP0 pins or the configuration requested during linking shadow protocol. This output is synchronous
to the falling edge of PTCK.
SX2–SX0
Secondary pass-through inputs. General-purpose inputs that can be driven to the PY output of the primary TAP.
An internal pullup forces SX2–SX0 to a high level if it has no external connection.
SY2–SY0
Secondary pass-through outputs. Primary pass-through input PX drives the general-purpose SY outputs of the
secondary TAPs that are connected to the primary TAP. Disconnected secondary TAPs have their SY outputs at
high impedance.
PX
Primary pass-through input. A general-purpose input driven to SY outputs of the secondary TAPs that are
connected to the primary TAP. An internal pullup forces PX to a high level if it has no external connection.
PY
Primary pass-through output. A general-purpose output that can be driven from SX2–SX0.
OE
Output-enable input. When high, this active-low control signal puts the secondary TAPs of the LASP at high
impedance to enable an alternative resource to access one or more of the three scan chains.
GND
Ground
VCC
Supply voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
application information
In application, the LASP is used at each of several serially-chained groups of IEEE Std 1149.1-compliant
devices. The LASP for each such group is assigned an address (via inputs A9–A0) that is unique from that
assigned to LASPs for the remaining groups. Additionally, within each group, each LASP is assigned a position
(via inputs P2–P0) that is unique from that assigned to LASPs in the same groups. This allows individually
configuring the secondary scan ports of each LASP within a group with a single linking shadow protocol when
cascaded. Each LASP is wired at its primary TAP to common (multidrop) TAP signals (sourced from a central
IEEE Std 1149.1 bus master) and fans out its secondary TAP signals to a specific linked group of
IEEE Std 1149.1-compliant devices with which it is associated. Additionally, LASPs can be cascaded together
to link additional secondary scan ports to one primary scan port. LASPs also can coexist with existing boards
implementing the TI ASP (8996). The ASP has one primary to one secondary port, but a LASP has three
secondary ports per device; Figure 1 shows an example.
1149.1-Compliant
Device Chain
1149.1
ASP
(8996)
1149.1
1149.1
LASP
(8986)
1149.1
1149.1
1149.1
1149.1
1149.1
1149.1
LASP
(8986)
LASP
(8986)
Cascading
Capability
1149.1
Bus
Master
To
Other
Modules
NOTE A: 1149.1 means IEEE Std 1149.1.
Figure 1. LASP/ASP Application
This application allows the LASP to be wired to a four- or five-wire multidrop test access bus, such as might be
found on a backplane. Each LASP would then be on a module, for example, a printed circuit board (PCB) that
contains a serial chain of IEEE Std 1149.1-compliant devices and that would plug into the module-to-module
bus (e.g., backplane). In the complete system, the LASP linking shadow protocols would allow the selection of
the scan chain on a single module. Then, the selected scan chain could be controlled, via the multidrop TAP,
as if it were the only scan chain in the system. Normal IR and DR scans could then be performed to accomplish
the module test objectives. If ASPs are to be addressed, they would be selected by the standard shadow
protocol.
Once scan operations to a given module are complete, another module can be selected in the same fashion,
at which time the LASP-based connection to the first module is dissolved. This procedure can be continued
progressively for each module to be tested. Finally, one of two global addresses can be issued to either leave
all modules unselected [disconnect address (DSA)] or to deselect and reset scan chains for all modules [reset
address (RSA)].
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
application information (continued)
Additionally, in Pause-DR and Pause-IR TAP states, a third global address [test-synchronization address (TSA)]
can be invoked to allow simultaneous TAP-state changes and multicast scan-in operations to selected modules.
In this case, PTDO is at high impedance. This is especially useful in the former case, for allowing selected
modules to be moved simultaneously to the Run-Test-Idle TAP state for module-level or module-to-module
built-in self-test (BIST) functions, which operate synchronously to TCK in that TAP state and, in the latter case,
for scanning common test setup/data into multiple like modules. In conjunction with the use of the pass-through
input/output pairs (PX to SX2–SX0 and PY to SY2–SY0), the multicast mode can be effective for ISP of like
modules.
addressing the LASP
Addressing of an LASP in a system is accomplished by linking shadow protocols, which are received at PTDI
synchronously to PTCK. These protocols can occur only in the following stable TAP states: Test-Logic-Reset,
Run-Test/Idle, Pause-DR, and Pause-IR. Linking shadow protocols never occur in Shift-DR or Shift-IR states
to prevent contention on the signal bus to which PTDO is wired. Additionally, the LASP PTMS must be held at
a constant low or high level throughout a linking shadow protocol. If TAP-state changes occur in the midst of
a protocol, the protocol is aborted and the select-protocol state machine returns to its initial state.
These protocols are based on a serial bit-pair signaling scheme used by the ASP (8996), in which two bit-pair
combinations (data one, data zero) are used to represent data and the other two bit-pair combinations (select,
idle) are used for framing—that is, to indicate where data begins and ends. This allows the LASP to coexist and
be fully compatible with the ASP.
These bit pairs are received serially at PTDI (or transmitted serially at PTDO) synchronously to PTCK as follows
and as illustrated in Figure 2:
1. The idle bit pair (I) is represented as two consecutive high signals.
2. The select bit pair (S) is represented as two consecutive low signals.
3. The data-one bit pair (D) is represented as a low signal, followed by a high signal.
4. The data-zero bit pair (D) is represented as a high signal, followed by a low signal.
PTDI
or
PTDO
PTCK
First Bit of Pair Is Transmitted
First Bit of Pair Is Received
Second Bit of Pair Is Transmitted
Second Bit of Pair Is Received
Figure 2. Bit-Pair Timing (Data Zero Shown)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
linking shadow protocol
A complete linking shadow protocol is composed of the receipt of a select protocol, followed, if applicable, by
the transmission of an acknowledge protocol. Both select and acknowledge protocols are composed of two
fields (address and command) comprising a message. Select bit pairs frame each field at the beginning and
end, and idle bit pairs frame the message at the beginning and end. The address is composed of 10 data bit
pairs and selects the LASP by matching it against address inputs A9–A0. The command consists of two
subfields, position and configuration. Position identifies the physical position of the LASP in the cascaded chain
and selects the LASP within the cascaded group by matching it against position inputs P2–P0. When the LASP
is stand alone, its inputs P2–P0 are tied low. The configuration portion of the protocol is used for configuring the
primary-to-secondary TAPs connections of the LASP whose address and position matches. Figure 3 shows a
complete linking shadow protocol. (The symbol T is used to represent a high-impedance condition on the
associated signal line. Because the high-impedance state at PTDI is logically high due to pullup, it maps onto
the idle bit pair).
Select Protocol
Message
LSB
T
I
S
D
LSB
MSB
D
D
D
D
D
D
D
D
D
S
D
MSB LSB
D
D
Position
Received at
PTDI
Address
D
MSB
D
D
S
I
T
S
I
T
Configuration
Command
Acknowledge Protocol
Message
LSB
T
I
S
D
LSB
MSB
D
Transmitted at
PTDO
D
D
D
D
D
D
D
D
S
D
MSB LSB
D
D
Position
Address
D
MSB
D
D
Configuration
Command
Figure 3. Complete Linking Shadow Protocol
select protocol
The select protocol is the LASP’s means of receiving (at PTDI) address, position, and secondary TAP
configuration information from an IEEE Std 1149.1 bus master. A 10-bit address value, 3-bit position value, and
3-bit configuration are decoded from the received data-one and/or data-zero bit pairs. These bit pairs are
interpreted in least-significant-bit-first order.
acknowledge protocol
Following the receipt of a complete select-protocol sequence, the protocol result provisionally is set to
NO MATCH and the connect status set to OFF. The received address and position then are compared to that
at the LASP address (A9–A0) inputs and position (P2–P0) inputs, respectively. If these values match, the LASP
immediately (with no delay) responds with an acknowledge protocol transmitted from PTDO. A 10-bit address
value, 3-bit position value, and 3-bit configuration are encoded into data-one and/or data-zero bit pairs and
transmitted. These are, by definition, the same as received in the select protocol. The bit pairs are to be
interpreted in least-significant-bit-first order. If either received address or position do not match that at the A9–A0
or P2–P0 inputs, respectively, no acknowledge protocol is transmitted and the linking shadow protocol is
considered complete.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
protocol errors
Protocol errors occur when bit pairs are received out of sequence. Some of these sequencing errors can be
tolerated and produce protocol result SOFT ERROR, and no specific action occurs as a result. Other errors
represent cases where the message information could be incorrectly received and produce protocol result
HARD ERROR, and these are characterized by sequences in which at least one bit of message data has been
properly transmitted, followed by a sequencing error; when protocol result HARD ERROR occurs, any
connection to an LASP is dissolved. Table 1 lists the bit-pair sequences that produce protocol results
SOFT ERROR and HARD ERROR. A HARD ERROR also results when the primary TAP state changes during
select protocol, following the proper transmission of at least one bit of address data. Figures 5, 6, and 7 show
shadow-protocol timing in case of protocol result HARD ERROR, while Figure 8 shows shadow-protocol timing
in the case of protocol result SOFT ERROR.
Table 1. Linking Shadow Protocol Errors†
SOFT ERROR
HARD ERROR
I(D)I
I(D)(S)I
I(D)(S)(D)I
IS(D)I
I(S)I
IS(D)S(D)I
IS(S)(D)I
IS(D)S(S)I
IS(S)(D)(S)I
† A bit-pair token in parentheses represents
one or more instances.
long address
Receipt of an address longer than 10 bits produces protocol result HARD ERROR, and the LASP assumes
OFF status. The sole exceptions are when all data 1s are received or all data 0s are received. In these special
cases, the global addresses represented by these bit sequences are observed and appropriate action taken.
That is, in the case that only data 1s (ten or more) are received, the shadow-protocol result is TEST
SYNCHRONIZATION (if the primary TAP state is Pause-DR or Pause-IR) and, in the case that only data 0s (ten
or more) are received, the linking shadow-protocol result is RESET (see test-synchronization address and reset
address).
short address
In all cases, receipt of an address of less than ten bits produces protocol result HARD ERROR, and the LASP
assumes OFF status.
long/short command
In all cases, receipt of a command that is not a multiple of six bits produces protocol result HARD ERROR, and
the LASP assumes OFF status.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
architecture
Blocks for linking shadow protocol receive and linking shadow protocol transmit are responsible for receipt of
select protocol and transmission of acknowledge protocol, respectively. Connect control block monitors the
primary TAP state to enable receipt/acknowledge of shadow protocols in appropriate states (namely, the stable,
non-shift TAP states: Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR). Upon receipt of a valid
shadow protocol, this block performs the address and position matching required to compute the
shadow-protocol result.
Based on the linking shadow protocol result or protocol bypass (BYP4–BYP0) inputs, the connect control block
configures the secondary TAP network. In conjunction, it also sets the states of and CON2–CON0 outputs.
TAP-state monitor
The TAP-state monitor is a synchronous finite-state machine that monitors the primary TAP state. The state
diagram is shown in Figure 4 and mirrors that specified by IEEE Std 1149.1. The TAP-state monitor proceeds
through its states based on the level of PTMS at the rising edge of PTCK. Each state is described both in terms
of its significance for LASP devices and for connected IEEE Std 1149.1-compliant devices (called targets).
However, the monitor state (primary TAP) can be different from that of disconnected scan chains (secondary
TAP).
Test-Logic-Reset
The LASP TAP-state monitor powers up in the Test-Logic-Reset state. Alternatively, the LASP can be forced
asynchronously to this state by assertion of its PTRST input. In the stable Test-Logic-Reset state, the LASP is
enabled to receive and respond to linking shadow protocols. The LASP does not recognize the TSA in this state.
For a target device in the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal
logic function of the device is performed. The instruction register is reset to an opcode that selects the optional
IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their
power-up values.
Run-Test/Idle
In the stable Run-Test/Idle state, the LASP is enabled to receive and respond to linking shadow protocols. The
LASP does not recognize the TSA in this state. For a target device, Run-Test/Idle is a stable state in which the
test logic actively can be running a test or can be idle.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
Test-Logic-Reset
PTMS = H
PTMS = L
PTMS = H
PTMS = H
PTMS = H
Run-Test /Idle
Select-DR-Scan
Select-IR-Scan
PTMS = L
PTMS = L
PTMS = L
PTMS = H
PTMS = H
Capture-DR
Capture-IR
PTMS = L
PTMS = L
Shift-DR
Shift-IR
PTMS = L
PTMS = L
PTMS = H
PTMS = H
PTMS = H
PTMS = H
Exit1-DR
Exit1-IR
PTMS = L
PTMS = L
Pause-DR
Pause-IR
PTMS = L
PTMS = L
PTMS = H
PTMS = L
PTMS = H
PTMS = L
Exit2-DR
Exit2-IR
PTMS = H
Update-DR
PTMS = H
PTMS = L
PTMS = H
Update-IR
PTMS = H
PTMS = L
Figure 4. TAP Monitor State Diagram
Select-DR-Scan, Select-lR-Scan
The LASP is not enabled to receive and respond to linking shadow protocols in the Select-DR-Scan and
Select-lR-Scan states. For a target device, no specific function is performed in the Select-DR-Scan and
Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states
allow the selection of either data-register scan or instruction-register scan.
Capture-DR
The LASP is not enabled to receive and respond to linking shadow protocols in the Capture-DR state. For a
target device in the Capture-DR state, the selected data register can capture a data value as specified by the
current instruction. Such capture operations occur on the rising edge of TCK, upon which the Capture-DR state
is exited.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
Shift-DR
The LASP is not enabled to receive and respond to linking shadow protocols in the Shift-DR state. For a target
device, upon entry to the Shift-DR state, the selected data register is placed in the scan path between TDI and
TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO
outputs the logic level present in the least-significant bit of the selected data register. While in the stable Shift-DR
state, data is serially shifted through the selected data register on each TCK cycle.
Exit1-DR, Exit2-DR
The LASP is not enabled to receive and respond to linking shadow protocols in the Exit1-DR and Exit2-DR
states. For a target device, the Exit1-DR and Exit2-DR states are temporary states that end a data-register scan.
It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data
register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the
high-impedance state.
Pause-DR
In the stable Pause-DR state, the LASP is enabled to receive and respond to linking shadow protocols.
Additionally, the TSA can be recognized in this state. For target devices, no specific function is performed in the
stable Pause-DR state. The Pause-DR state suspends and resumes data-register scan operations without loss
of data.
Update-DR
The LASP is not enabled to receive and respond to linking shadow protocols in the Update-DR state. For a target
device, if the current instruction calls for the selected data register to be updated with current data, such update
occurs on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
The LASP is not enabled to receive and respond to linking shadow protocols in the Capture-IR state. For a target
device in the Capture-IR state, the instruction register captures its current status value. This capture operation
occurs on the rising edge of TCK, upon which the Capture-IR state is exited.
Shift-IR
The LASP is not enabled to receive and respond to linking shadow protocols in the Shift-IR state. For a target
device, upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO,
and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO outputs
the logic level present in the least-significant bit of the instruction register. While in the stable Shift-IR state,
instruction data is serially shifted through the instruction register on each TCK cycle.
Exit1-IR, Exit2-IR
The LASP is not enabled to receive and respond to linking shadow protocols in the Exit1-IR and Exit2-IR states.
For target devices, the Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan.
It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction
register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the
high-impedance state.
Pause-IR
In the stable Pause-IR state, the LASP is enabled to receive and respond to linking shadow protocols.
Additionally, the TSA can be recognized in this state. For target devices, no specific function is performed in the
stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and
resumes instruction-register scan operations without loss of data.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
Update-IR
The LASP is not enabled to receive and respond to linking shadow protocols in the Update-IR state. For target
devices, the current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
address matching
Connect status of the LASP is computed by a match of the address received in the last valid linking-shadow
protocol against that at the address (A9–A0) inputs as well as against the three dedicated addresses that are
internal to the LASP (DSA, RSA, and TSA). Table 2 shows the address map.
Table 2. Address Map
ADDRESS
NAME
BINARY
CODE
Reset address (RSA)
0000000000
Matching address
Disconnect address (DSA)
A9–A0
1111111110
Test Synchronization address (TSA)
1111111111
All other addresses
All others
LINK SHADOW
PROTOCOL RESULT
RESULTANT
PRIMARY-TO-SECONDARY
CONNECT STATUS
000
RESET
RESET
A9–A0
3FE
MATCH
ON
DISCONNECT
OFF
3FF
TEST SYNCHRONIZATION
MULTICAST
All others
NO MATCH
OFF
HEX CODE
Upon receipt of a valid linking shadow protocol, if the linking shadow protocol address and position match the
address inputs A9–A0 and position inputs P2–P0 respectively, the LASP responds by transmitting an
acknowledge protocol. Following the complete transmission of the acknowledge protocol, the LASP assumes
ON status, in which the secondary TAPs are configured as requested by the linking shadow protocol. The ON
status allows the scan chains associated with the LASP secondary TAPs to be controlled from the multidrop
primary TAP as if it were directly wired as such. Figures 9 and 10 show the linking shadow protocol timing for
MATCH result when the prior LASP connect status is ON and OFF, respectively. If the linking-shadow protocol
address or position does not match the address inputs A9–A0 or position inputs P2–P0 (unless the address is
one of the three dedicated global addresses described below), the LASP responds immediately by assuming
the OFF status, in which PTDO and STDO2–STDO0 are high impedance and STMS2–STMS0 are held at their
last levels. This has the effect of deselecting the scan chains associated with the LASP secondary TAPs, but
leaves the TAP state of the scan chains unchanged. No acknowledge protocol is sent. Figures 11 and 12 show
the linking shadow protocol timing for a NO MATCH result when the prior LASP connect status is ON and OFF,
respectively.
disconnect address
The disconnect address (DSA) is one of the three internally dedicated addresses that are recognized globally.
When an LASP receives the DSA, it immediately responds by assuming the OFF status, in which PTDO and
STDO2–STDO0 are high impedance and STMS2–STMS0 are held at their last levels. This has the effect of
deselecting the scan chain associated with the LASP secondary TAP, but leaves the TAP state of the scan chain
unchanged. No acknowledge protocol is sent. Figures 13 and 14 show the linking shadow protocol timing for
DISCONNECT result when the prior LASP connect status is ON and OFF, respectively. The same result occurs
when a nonmatching address is received. No specific action to disconnect an LASP is required, as a given LASP
is disconnected by the address that connects another. The dedicated DSA ensures that at least one address
is available for the purpose of disconnecting all receiving LASPs. It is especially useful when the currently
selected scan chain is in a different TAP state than that to be selected. In such a case, the DSA is used to leave
the former scan chain in the proper state, after which the primary TAP state is moved to that needed to select
the latter scan chain.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
reset address
The reset address (RSA) is one of the three internally dedicated addresses that are recognized globally. When
an LASP receives the RSA, it immediately responds by assuming the RESET status in which PTDO and
STDO2–STDO0 are at high impedance and STMS2–STMS0 are forced to the high level. This has the effect of
deselecting and resetting to Test-Logic-Reset state the scan chain associated with the LASP secondary TAP.
No acknowledge protocol is sent. Figures 15 and 16 show the linking shadow protocol timing for RESET result
when the prior LASP connect status is ON and OFF, respectively.
test synchronization address
The test synchronization address (TSA) is one of the three internally dedicated addresses that are recognized
globally. When an LASP receives the TSA, it immediately responds by assuming the MULTICAST status, in
which PTDI and PTMS are connected to STDO and STMS, respectively, of only those secondary TAPs whose
TAP state is Pause-DR or Pause-IR while PTDO is high impedance. No acknowledge protocol is sent. The result
of receipt of TSA on a secondary TAP whose TAP state is Test-Logic-Reset or Run-Test-Idle is disconnect.
Figures 17 and 18 show the linking shadow protocol timing for TEST SYNCHRONIZATION result when the prior
LASP connect status is ON and OFF, respectively. The TSA allows simultaneous operation of the scan chains
of all selected LASPs, either for global TAP-state movement or for scan input of common serial test data via
PTDI. This is especially useful in the former case, to simultaneously move such scan chains into the
Run-Test/Idle state in which module-level or module-to-module BIST operations can operate synchronous to
TCK in that TAP state and, in the later case, to scan common test setup/data into multiple like modules. In
conjunction with the use of the pass-through input/output pairs (PX to SX2–SX0 and PY to SY2–SY0), the
multicast mode can be effective for ISP of like modules.
protocol bypass
Protocol bypass is selected by a low BYP5 input. This protocol-bypass mode forces the LASP into BYP status.
The remaining bypass BYP4–BYP0 inputs are used for configuring the primary-to-secondary TAP connections,
regardless of previous linking shadow protocol results, and the corresponding CON2–CON0 outputs are made
active (low). Receipt of the linking shadow protocols is disabled. When BYP5 is taken low, the
primary-to-secondary TAP connections are configured immediately (asynchronously to PTCK). The PTMS
signal also is connected to its respective secondary TAP signal STMS2–STMS0 unless PTRST is low, in which
case STMS2–STMS0 remain high until PTRST is released. Also, the linking-shadow protocol receive block is
reset to its power-up state and is held in this state, such that select protocols appearing at the primary TAP are
ignored. When the BYP5 input is released (taken high), the LASP immediately (asynchronously to PTCK)
resumes the connect status selected by the last valid linking shadow protocol. The linking shadow protocol
receive block again is enabled to respond to select protocols. Figures 19 and 20 show protocol-bypass timing
when the LASP connect status before BYP5 active is ON and OFF, respectively.
asynchronous reset
While the PTRST input always is buffered directly to the STRST2–STRST0 outputs, it also serves as an
asynchronous reset for the LASP. Given that BYP5 is high, when PTRST goes low, the LASP immediately
assumes TRST status, in which CON2–CON0 are high and PTDO and STDO2–STDO0 are at high impedance.
Otherwise, if BYP5 is low, the LASP assumes BYP/TRST status. In either case, STMS2–STMS0 are set high
so that connected IEEE Std 1149.1-compliant devices can be driven synchronously to their Test-Logic-Reset
states. While PTRST is low, receipt of linking shadow protocols is disabled. Figures 21 and 22 show
asynchronous reset timing when the LASPs connect status before PTRST active is ON and OFF, respectively.
Figure 23 shows asynchronous reset timing when BYP5 is low.
connect indicators
The CON2–CON0 outputs indicate secondary-scan-port activity (STDO2–STDO0, STMS2 – STMS0 active),
regardless of whether such activity is achieved via protocol bypass or linking shadow protocol. When
acknowledge protocol is in progress, the CON2–CON0 outputs are high.
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
Don’t Care
P2–P0
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
A0P
A9P
SEL
P0P
C2P
SEL
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
UNDETERMINED
STDO1
STDO0
STMS2
A0P
A9P
P0P
PTMS
STMS20
STMS1
STMS0
PY
SY2
C2P
STMS10
PTMS
STMS00
SX2 * SX0
PX
SY1
SY0
PX
SELECT PROTOCOL
OFF
Figure 5. Linking Shadow Protocol Timing
Protocol Result = HARD ERROR (PTMS Change During Select Protocol);
Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
Don’t Care
Don’t Care
P2–P0
Don’t Care
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
A0P
A9P
SEL
P0P
C2P
SEL
CTDI
Don’t Care
Idle
Don’t Care
Don’t Care
PTMS
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
Idle
SEL
UNDETERMINED
STDO1
STDO0
STMS2
A0P
A9P
P0P
PTMS
STMS20
STMS1
STMS0
PY
SY2
C2P
STMS10
PTMS
STMS00
SX2 * SX0
PX
SY1
SY0
PX
SELECT PROTOCOL
ACKNOWLEDGE PROTOCOL (aborted)
OFF
Figure 6. Linking Shadow Protocol Timing
Protocol Result = HARD ERROR (PTMS Change During Acknowledge Protocol);
Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
Don’t Care
P2–P0
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
A0P
A9P
SEL
Idle
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
UNDETERMINED
STDO1
STDO0
A0P
STMS2
PTMS
A9P
STMS20
STMS10
STMS1
STMS0
PY
SY2
STMS00
PTMS
SX2 * SX0
PX
SY1
SY0
PX
SELECT PROTOCOL
OFF
Figure 7. Linking Shadow Protocol Timing
Protocol Result = HARD ERROR (No Command); Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
Don’t Care
A9–A0
P2–P0
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
Idle
PTDI
SEL
SEL
Idle
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
STDO1
STDO0
PTDI
STMS2
PTMS
STMS1
STMS10
STMS0
PTMS
PY
SY2
SX2 * SX0
PX
SY1
SY0
PX
SELECT PROTOCOL (ABORTED)
TAP2–ON, TAP1–OFF, TAP0–ON
Figure 8. Linking Shadow Protocol Timing
Protocol Result = SOFT ERROR; Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
P2–P0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
A0P
A9P
SEL
P0P
C2P
SEL
Don’t Care
Idle
Don’t Care
CTDI
Don’t Care
PTMS
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
Idle
SEL
A0P
A9P
SEL
P0P
C2P
SEL
Idle
UNDETERMINED
STMS2
STDI0
A0P
A9P
P0P
PY
SY2
C2P
PTDI
PTMS
STMS20
STMS1
STMS0
PTMS
PTMS
PTMS
STMS10
STMS00
PTMS
SX2 * SX0
SX2 * SX1 * SX0
PX
PX
PX
SY1
SY0
STDI2
STDI1
STDO1
STDO0
STDI2
PX
PX
SELECT PROTOCOL
ACKNOWLEDGE PROTOCOL
ON
Figure 9. Linking Shadow Protocol Timing
Protocol Result = MATCH; Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
P2–P0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
A0P
A9P
SEL
P0P
C2P
SEL
Don’t Care
Idle
Don’t Care
CTDI
Don’t Care
PTMS
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
CTDO
Idle
STDI2
CTDI
SEL
A0P
A9P
SEL
P0P
C2P
SEL
UNDETERMINED
STDI2
STDI2
STDO2
STDI1
STDO1
STDI0
STDO0
PTDI
STMS2
STMS20
PTMS
STMS1
STMS10
PTMS
STMS0
STMS00
PTMS
PY
SX2 * SX1 * SX0
SY2
PX
SY1
PX
SY0
PX
SELECT PROTOCOL
ACKNOWLEDGE PROTOCOL
Figure 10. Linking Shadow Protocol Timing
Protocol Result = MATCH; Prior Connect Status = OFF
28
Idle
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ON
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
P2–P0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
A0P
A9P
SEL
P0P
C2P
SEL
CTDI
Don’t Care
Idle
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
UNDETERMINED
STDO1
STDO0
STMS2
A0P
A9P
P0P
PTMS
STMS20
STMS1
STMS0
PY
SY2
C2P
STMS10
PTMS
STMS00
SX2 * SX0
PX
SY1
SY0
PX
SELECT PROTOCOL
OFF
Figure 11. Linking Shadow Protocol Timing
Protocol Result = NO MATCH; Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
P2–P0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
A0P
A9P
SEL
P0P
C2P
SEL
Idle
Don’t Care
Don’t Care
CTDI
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
CTDI
CTDO
STDO2
STDO1
STDO0
STMS2
STMS20
STMS1
STMS10
STMS0
STMS00
PY
SY2
SY1
SY0
SELECT PROTOCOL
OFF
Figure 12. Linking Shadow Protocol Timing
Protocol Result = NO MATCH; Prior Connect Status = OFF
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
Don’t Care
A9–A0
P2–P0
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
DSAP
SEL
Idle
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
UNDETERMINED
STDO1
STDO0
STMS2
DSAP
PTMS
STMS20
STMS10
STMS1
STMS0
PY
SY2
STMS00
PTMS
SX2 * SX0
PX
SY1
SY0
PX
SELECT PROTOCOL
OFF
Figure 13. Linking Shadow Protocol Timing
Protocol Result = DISCONNECT; Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
Don’t Care
A9–A0
P2–P0
Don’t Care
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
DSAP
SEL
Idle
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
UNDETERMINED
CTDO
STDO2
STDO1
STDO0
STMS2
STMS20
STMS1
STMS10
STMS0
STMS00
PY
SY2
SY1
SY0
SELECT PROTOCOL
OFF
Figure 14. Linking Shadow Protocol Timing
Protocol Result = DISCONNECT; Prior Connect Status = OFF
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
Don’t Care
A9–A0
Don’t Care
P2–P0
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
RSAP
SEL
Idle
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
UNDETERMINED
STDO1
STDO0
RSAP
STMS2
PTMS
STMS1
STMS10
STMS0
PTMS
PY
SY2
SX2 * SX0
PX
SY1
SY0
PX
SELECT PROTOCOL
OFF
Figure 15. Linking Shadow Protocol Timing
Protocol Result = RESET; Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
Don’t Care
Don’t Care
P2–P0
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
RSAP
SEL
Idle
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
UNDETERMINED
CTDO
STDO2
STDO1
STDO0
STMS2
STMS20
STMS1
STMS10
STMS0
STMS00
PY
SY2
SY1
SY0
SELECT PROTOCOL
OFF
Figure 16. Linking Shadow Protocol Timing
Protocol Result = RESET; Prior Connect Status = OFF
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
Don’t Care
A9–A0
Don’t Care
P2–P0
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
TSAP
SEL
Idle
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
UNDETERMINED
STDO2
STDI0
PTDI
STDO1
STDO0
PTDI
TSAP
PTDI
STMS2
STMS1
PTMS
STMS10
PTMS
PTMS
STMS0
PY
SX2 * SX0
SX2 * SX1 * SX0
SY2
PX
SY1
PX
SY0
PX
SELECT PROTOCOL
MULTICAST
Figure 17. Linking Shadow Protocol Timing
Protocol Result = TEST SYNCHRONIZATION (all on);
Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
Don’t Care
A9–A0
Don’t Care
P2–P0
BYP5
Don’t Care
BYP4–BYP0
PTDI
Idle
SEL
TSAP
SEL
Idle
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
CON2
CON1
CON0
PTDO
CTDO
UNDERTERMINED
STDO2
PTDI
STDO1
PTDI
STDO0
PTDI
STMS2
STMS20
PTMS
STMS1
STMS10
PTMS
STMS0
STMS00
PTMS
PY
SX2 * SX1 * SX0
SY2
PX
SY1
PX
SY0
PX
SELECT PROTOCOL
MULTICAST
Figure 18. Linking Shadow Protocol Timing
Protocol Result = TEST SYNCHRONIZATION (all on); Prior Connect Status = OFF
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
Don’t Care
Don’t Care
P2–P0
BYP5
BYP4–BYP0
Don’t Care
”00000”
PTDI
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
Don’t Care
CON2
CON1
CON0
PTDO
STDI2
CTDO
STDI2
STDO2
STDI0
STDI1
STDO1
STDI0
STDO0
PTDI
STMS2
PTMS
STMS1
STMS10
STMS10
PTMS
STMS0
PY
PTMS
STDI0
SX2 * SX0
SX2 * SX1* SX0
SY2
PX
SY1
PX
SY0
PX
TAP2–ON, TAP1–OFF, TAP0–ON
TAP2–ON, TAP1–ON, TAP0–ON
SX2 * SX0
TAP2–ON, TAP1–OFF, TAP0–ON
Figure 19. Protocol Bypass Timing, All TAPs ON,
Stand-Alone Device, Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
A9–A0
Don’t Care
Don’t Care
P2–P0
BYP5
BYP4–BYP0
Don’t Care
”00000”
PTDI
Don’t Care
CTDI
Don’t Care
PTMS
Don’t Care
PX
Don’t Care
SX2–SX0
Don’t Care
STDI2
Don’t Care
STDI1
Don’t Care
STDI0
Don’t Care
Don’t Care
CON2
CON1
CON0
STDI2
PTDO
CTDO
UNDETERMINED
STDI2
STDO2
STDI1
STDO1
STDI0
STDO0
PTDI
STMS2
STMS20
PTMS
STMS20
STMS1
STMS10
PTMS
STMS10
STMS0
STMS00
PTMS
STMS10
PY
SX2 * SX1* SX0
SY2
PX
SY1
PX
SY0
PX
TAP2–ON, TAP1–ON, TAP0–ON
Figure 20. Protocol Bypass Timing, All TAPs ON,
Stand-Alone Device, Prior Connect Status = OFF
38
UNDETERMINED
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
OE
PTCK
STCK2
STCK1
STCK0
PTRST
STRST2
STRST1
STRST0
BYP5
BYP4–BYP0
Don’t Care
CON2
CON1
CON0
STDI2
PTDO
STDI2
CTDO
UNDETERMINED
STDI0
STDI0
STDO0
PTDI
PTDI
STMS2
PTMS
PTMS
STMS1
STMS10
STMS10
STMS0
PTMS
PTMS
STDO2
STDO1
SX2 * SX0
PY
SY2
PX
PX
PX
PX
SY1
SY0
ON
Secondary TAPs Hi-Z
ON
RESET
OFF
Figure 21. Asynchronous Reset and Output-Enable Timing,
Prior Connect Status = TAP2–ON, TAP1–OFF, TAP0–ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
STCK2
STCK1
STCK0
PTRST
STRST2
STRST1
STRST0
BYP5
BYP4–BYP0
Don’t Care
CON2
CON1
CON0
PTDO
CTDO
UNDETERMINED
STDO2
STDO1
STDO0
STMS2
STMS20
STMS1
STMS10
STMS0
STMS00
PY
SY2
SY1
SY0
OFF
RESET
Figure 22. Asynchronous Reset Timing,
Prior Connect Status = OFF
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
OFF
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PTCK
STCK2
STCK1
STCK0
PTRST
STRST2
STRST1
STRST0
BYP5
BYP4–BYP0
‘‘00000”
CON2
CON1
CON0
PTDO
STDI2
STDI2
CTDO
STDI2
STDI2
STDO2
STDI1
STDI1
STDO1
STDI0
STDI0
STDO0
PTDI
PTDI
STMS2
PTMS
PTMS
STMS1
PTMS
PTMS
STMS0
PTMS
PTMS
PY
SX0 * SX1 * SX2
SY2
PX
SY1
PX
SY0
PX
ON
RESET
ON
Figure 23. Asynchronous Reset Timing,
Bypass Mode, Prior Connect Status = All ON
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to 7 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Current into any output in the low state, IOL: SN54LVT8986 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVT8986 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVT8986 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVT8986 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
recommended operating conditions
SN54LVT8986
SN74LVT8986
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
–24
–32
mA
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
High-level input voltage
2
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
V
–40
V
µs/V
200
125
V
85
°C
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
MIN
VCC = 2.7 V, II = –18 mA
VCC = 2.7 V to 3.6 V, IOH = –100 µA
VCC = 2.7 V,
VOH
VCC = 3 V
–1.2
VCC–0.3
2.4
IOH = –32 mA
IOL = 100 µA
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
0.55
IOL = 64 mA
VCC = 0 or 3.6 V, VI = 5.5 V
10
10
VCC = 3.6 V,
±1
±1
1
1
1
1
A9–0, P2–0, BYP5–0,
STDI2–0, SX2–1, CTDI,
OE
Ioff
PTDO, STDO2–0,
IOZH STMS2–0, STCK2–0,
STRST2–0, PY, SY2–0
PTDO, STDO2–0,
IOZL STMS2–0, STCK2–0,
STRST2–0, PY, SY2–0
IOZPU
IOZPD
VCC = 3.6 V,
VI = VCC or GND
–8
–30
–8
–30
–25
–100
–25
–100
µA
VI = GND
VI or VO = 0 to 4.5 V
VCC = 3.6 V,
VO = 3 V
VCC = 3.6 V,
VO = 0.5 V
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
VCC = 1.5 V to 0, VO = 0.5 V to 3 V
OFF, STCK2–0 = H,
STMS2–0 = H
ICC
µA
µA
VI = VCC
VCC = 0,
VCC = 3.6 V,
VI = VCC or
GND,
IO = 0
V
0.55
PTDI, PTMS, PTRST,
PX
IIL
V
2
0.2
VCC = 3.6 V,
UNIT
V
2
PTDI, PTMS, PTRST,
PX
A9–0, P2–0, BYP5–0,
STDI2–0, SX2–1, CTDI,
OE
VCC–0.3
2.4
0.5
VCC = 3 V
IIH
–1.2
IOL = 24 mA
IOL = 16 mA
VOL
PTCK
IOH = – 8 mA
IOH = –24 mA
SN74LVT8986
TYP†
MAX
MIN
0.2
7V
VCC = 2
2.7
II
SN54LVT8986
TYP†
MAX
TEST CONDITIONS
ON, PTDO = L,
STCK2–0= L,
STDO2–0 = L,
STMS2–0 = L
ON, PTDO = H,
STCK2–0 = H,
STDO2–0 = H,
STMS2–0 = H
TRST2–0,
STCK2–0 = L
±100
µA
5
5
µA
–5
–5
µA
±100*
±100
µA
±100*
±100
µA
2
2
25
25
mA
7
7
10
10
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
SN54LVT8986
TYP†
MAX
TEST CONDITIONS
VCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC‡
Ci
MIN
0.2
VI = 3 V or 0
VO = 3 V or 0
Co
SN74LVT8986
TYP†
MAX
MIN
0.2
UNIT
mA
7.5
7.5
pF
8.5
8.5
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 24)
SN54LVT8986
MIN
fclock1
fclock2
Clock frequency, LASP not cascaded
tw1
1
Pulse duration,
duration LASP not cascaded
Clock frequency, LASP cascaded
tw2
2
Pulse duration
duration, LASP cascaded
tw3
Pulse duration
PTCK
Setup time
Hold time
MIN
40
33
33
15
PTCK low
10
10
PTCK high
15
15
PTCK low
15
15
PTRST low
MAX
40
15
9
9
10.2
8
10.1
10
CTDI before PTCK↑
2
2
PTMS before PTCK↑
10
10
BYP5 before PTCK↑
BYP4, BYP2–BYP0 before PTCK↓
A9–A0 and P2–P0 after PTCK↓§
th
SN74LVT8986
PTCK high
A9–A0 and P2–P0 before PTCK↓§
STDI0–STDI2, PTDI before PTCK↑
tsu
MAX
UNIT
MHz
ns
ns
8
8
4
4
CTDI, STDI0–STDI2, PTDI after
PTCK↑
4
4
PTMS after PTCK↑
4
4
BYP5 after PTCK↑
BYP4, BYP2–BYP0 after PTCK↓
4
4
4
§ These requirements apply only in the case in which the address inputs are changed during a linking shadow protocol. For normal application
of the LASP, it is recommended that the address and position inputs remain static throughout any shadow protocols. In such cases, the timing
of address and position inputs relative to PTCK need not be considered.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4
ns
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 24)
SN54LVT8986
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
MAX
VCC = 2.7 V
MIN
UNIT
MAX
tpd
BYP5–BYP0
CON2–CON0
13.5
14.5
ns
tpd
BYP5–BYP0↓
STMS2–STMS0
16.5
18
ns
tpd
PTCK
STCK2–STCK0
9.5
10.5
ns
tpd
PTCK↓
CON2–CON0
15
17.5
ns
tpd
PTCK↓
(linking shadow protocol
acknowledge)
PTDO
12
14.5
ns
tpd†
PTCK↓
(connect)
STMS2–STMS0
17
21
ns
tpd
PTCK↓
STDO2–STDO0
13.5
16
ns
tpd
PTMS
STMS2–STMS0
13
14
ns
tpd
PTRST
STRST2–STRST0
CON2–CON0
11
12
ns
19.5
21.5
STMS2–STMS0
17.5
18.5
tPLH
PTRST↓
ns
tpd
PTCK↓
PTDO, CTDO
12
14.5
ns
tpd
PX
SY2–SY0
8
9
ns
tpd
ten‡
SX2–SX0
PY
9
10
ns
BYP5–BYP0↓
PTDO, STDO2–STDO0
13
15
ns
tdis
ten‡
BYP5–BYP0↓
16
18
ns
OE↓
PY, SY2–SY0
STDO2–STDO0
14
15
ns
ten
OE↓
SY2–SY0
14
15
ns
tPZH‡
PTCK↓
PTDO, STDO2–STDO0
17
18
ns
tdis‡
BYP5–BYP0↑
PTDO, STDO2–STDO0
11
12
ns
tdis
BYP5–BYP0↑
PY, SY2–SY0
11
12
ns
tdis‡
OE↑
STDO2–STDO0
10
11
ns
tdis
OE↑
SY2–SY0
10
11
ns
tdis‡
PTCK↓
PTDO, STDO2–STDO0
15
17
ns
tdis
PTCK↓
PY, SY2–SY0
17
19
ns
tdis‡
PTRST↓
PTDO, STDO2–STDO0
18
20
ns
tdis
PY, SY2–SY0
21.5
23.5
ns
PTRST↓
† The transitions at STMSx are possible only when a linking shadow protocol select is issued while STMSx is held (in the OFF status) at a level
that differs from that at PTMS. Such operation is not recommended because state synchronization of the primary TAP to secondary TAP cannot
be ensured.
‡ In most applications, the node to which PTDO and STDO2-STDO0 are connected has a pullup resistor. In such cases, this parameter is not
significant.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 24) (continued)
SN74LVT8986
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
MAX
VCC = 2.7 V
MIN
UNIT
MAX
tpd
BYP5–BYP0
CON2–CON0
13.5
14.5
ns
tpd
BYP5–BYP0↓
STMS2–STMS0
16.5
18
ns
tpd
PTCK
STCK2–STCK0
9.5
10.5
ns
tpd
PTCK↓
CON2–CON0
15
17.5
ns
tpd
PTCK↓
(linking shadow protocol
acknowledge)
PTDO
12
14.5
ns
tpd†
PTCK↓
(connect)
STMS2–STMS0
17
21
ns
tpd
PTCK↓
STDO2–STDO0
13.5
16
ns
tpd
PTMS
STMS2–STMS0
13
14
ns
tpd
PTRST
STRST2–STRST0
CON2–CON0
11
12
ns
19.5
21.5
STMS2–STMS0
17.5
18.5
tPLH
PTRST↓
ns
tpd
PTCK↓
PTDO, CTDO
12
14.5
ns
tpd
PX
SY2–SY0
8
9
ns
tpd
ten‡
SX2–SX0
PY
9
10
ns
BYP5–BYP0↓
PTDO, STDO2–STDO0
13
15
ns
tdis
ten‡
BYP5–BYP0↓
16
18
ns
OE↓
PY, SY2–SY0
STDO2–STDO0
14
15
ns
ten
OE↓
SY2–SY0
14
15
ns
tPZH‡
PTCK↓
PTDO, STDO2–STDO0
17
18
ns
tdis‡
BYP5–BYP0↑
PTDO, STDO2–STDO0
11
12
ns
tdis
BYP5–BYP0↑
PY, SY2–SY0
11
12
ns
tdis‡
OE↑
STDO2–STDO0
10
11
ns
tdis
OE↑
SY2–SY0
10
11
ns
tdis‡
PTCK↓
PTDO, STDO2–STDO0
15
17
ns
tdis
PTCK↓
PY, SY2–SY0
17
19
ns
tdis‡
PTRST↓
PTDO, STDO2–STDO0
18
20
ns
tdis
PY, SY2–SY0
21.5
23.5
ns
PTRST↓
† The transitions at STMSx are possible only when a linking shadow protocol select is issued while STMSx is held (in the OFF status) at a level
that differs from that at PTMS. Such operation is not recommended because state synchronization of the primary TAP to secondary TAP cannot
be ensured.
‡ In most applications, the node to which PTDO and STDO2-STDO0 are connected has a pullup resistor. In such cases, this parameter is not
significant.
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B – OCTOBER 2002 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
2.7 V
1.5 V
Input
th
2.7 V
1.5 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
0V
1.5 V
1.5 V
VOL
VOH
Output
1.5 V
tPLZ
3V
1.5 V
tPZH
tPLH
tPHL
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
2.7 V
Output
Control
1.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 24. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
SN74LVT8986GGV
SN74LVT8986PM
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
Package
Type
Package
Drawing
ACTIVE
BGA
GGV
64
225
TBD
Call TI
Level-3-220C-168 HR
ACTIVE
LQFP
PM
64
160
TBD
CU NIPDAU
Level-3-220C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPBG089A – DECEMBER 1998 – REVISED JUNE 2002
GGV (S–PBGA–N64)
PLASTIC BALL GRID ARRAY
8,10
SQ
7,90
5,60 TYP
0,80
0,40
0,80
H
G
F
E
D
0,40
C
B
A1 Corner
A
1
2
3
4
5
6
7
8
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08
0,45
0,35
0,10
4073224-3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration
MicroStar BGA is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2005, Texas Instruments Incorporated