HI1172 TM Data Sheet 6-Bit, 20MSPS, Video A/D Converter (CMOS) HI1172 is a 6-bit, CMOS A/D converter for video use. The adoption of a 2-step parallel conversion achieves speeds of 20MSPS minimum, 35MSPS typical. Ordering Information PART NUMBER -20 to 75 File Number 4102.2 Features • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-Bit • Maximum Sampling Frequency . . . . . . . . . . . . . .20MSPS • Low Power Consumption at 20MSPS (Typ) (Reference Current Excluded) . . . . . . . . . . . . . . . . .40mW • Built-In Sample and Hold Circuit TEMP. RANGE (oC) HI1172JCB September 2000 PACKAGE 16 Ld SOIC PKG. NO. M16.2-S • Three-State TTL Compatible Output • Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Single • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . .4pF Pinout • Reference Impedance . . . . . . . . . . . . . . . . . . . 250Ω (Typ) HI1172 (SOIC) TOP VIEW Applications D0 1 16 AVSS • Video Digitizing D1 2 15 DVDD • Wireless Communications D2 3 14 AVDD D3 4 13 VRB D4 5 12 VIN D5 6 11 VRT CLK 7 10 AVDD DVSS 8 9 DVDD Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” Functional Block Diagram REFERENCE VOLTAGE D0 1 D1 2 D2 3 D3 4 D4 5 D5 6 CLK 7 DVSS 8 16 AVSS LOWER DATA LATCHES LOWER ENCODER (3-BIT) LOWER COMPARATORS WITH S/H (3-BIT) 15 DVDD 14 AVDD 13 VRB UPPER DATA LATCHES LOWER ENCODER (3-BIT) LOWER COMPARATORS WITH S/H (3-BIT) UPPER ENCODER (3-BIT) UPPER COMPARATORS WITH S/H (3-BIT) 12 VIN 11 VRT 10 AVDD 9 DVDD CLOCK GENERATOR 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HI1172 Typical Application Circuit (LSB) D0 D1 +5V D2 D3 VRB D4 VIN (MSB) D5 VRT + C4 C3 +5V CLK +5V + C1 + - 0.1 C2 VRT + + VRB - - 0.1 Pin Descriptions PIN NUMBER SYMBOL 1 to 6 D0 to D5 EQUIVALENT CIRCUIT DESCRIPTION D0 (LSB) to D5 (MSB) Output. D1 7 CLK Clock Input. DVDD 7 DVSS 8 DVSS Digital GND. 9, 15 DVDD Digital +5V. 10, 14 AVDD Analog +5V. 11 VRT 13 VRB Reference Voltage (Top). AVDD Reference Voltage (Bottom). 11 13 AVSS 12 VIN AVDD Analog Input. 12 AVSS 16 AVSS Analog GND. 2 VIN HI1172 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Supply Voltage (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Reference Voltage (VRT, VRB). . . . . . . . . . . . . . . . . . . . VDD to VSS Analog Input Voltage (VIN). . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage (CLK). . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Output Voltage (VOH , VOL). . . . . . . . . . . . . . . . . VDD to VSS Operating Conditions Supply Voltage Range, AVDD, AVSS . . . . . . . . . . . . 4.75V to 5.25V Reference Voltage, DVDD, DVSS VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 5V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 4.1V VRT - VRB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to AVDD Analog Input Voltage (VIN). . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. VDD = +5V, VRB = 1V, VRT = 2V, TA = 25oC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 0.5 - 20 MSPS Conversion Speed, fC fC VIN = 1V to 2V fIN = 1kHz Ramp Integral Non-Linearity EL fC = 20MSPS VIN = 1V to 2V - ±0.3 ±0.5 LSB Differential Non-Linearity ED fC = 20MSPS VIN = 1V to 2V - ±0.3 ±0.5 LSB Supply Current IDD fC = 20MSPS NTSC Ramp Wave Input - 7 12 mA Reference Pin Current IREF 3 4 5.7 mA Analog Input (-1dB) BW - 18 - MHz Analog Input Capacitance CIN - 4 - pF RREF 175 250 325 Ω EOT 0 -20 -40 mV EOB 15 35 55 mV VIH 4.0 - - V VIL - - 1.0 V VIH = VDD - - 5 µA VIL = 0V - - 5 µA VOH = VDD = 0.5V -1.1 - - mA VOL = 0.4V 3.7 - - mA Reference Resistance (VRT to VRB) Offset Voltage Digital Input Voltage Digital Input Current IIH VIN = 1.5V + 0.07VRMS VDD = Max IIL Digital Output Current IOH IOL VDD = Min Output Data Delay TDL With TTL 1 Gate and 10pF Load - 18 30 ns Differential Gain Error DG NTSC 40 IRE Mod - 1.0 - % Differential Phase Error DP Ramp, fC = 14.3MSPS - 1.0 - deg Aperture Jitter tAJ - 40 - ps Sampling Delay tSD - 4 - ns 3 HI1172 Test Circuits +V S2 - S1 : ON IF A < B S2 : ON IF B > A S1 + -V A<B A>B COMPARATOR VIN DUT HI1172 6 “0” A6 B6 A1 A0 B1 B0 6 BUFFER “1” DVM 000 • • • 00 TO 111 • • • 10 6 CLK (20MHz) CONTROLLER FIGURE 1. INTEGRAL NON-LINEARITY ERROR, DIFFERENTIAL NON-LINEARITY, OFFSET VOLTAGE 2V ERROR RATE fC -1kHz SG HPF 1V 1 100 IAE 0 -40 SG (CW) VIN AMP 2 NTSC SIGNAL SOURCE 6 TTL HI1172 1 6 10-BIT D/A ECL 40 IRE MODULATION COUNTER HI20201 620 2 CLK VECTOR SCOPE 2V BURST DG DP -5.2V 620 1V SYNC -5.2V TTL fC ECL FIGURE 2. MAXIMUM OPERATIONAL SPEED, DIFFERENTIAL GAIN ERROR, DIFFERENTIAL PHASE ERROR I 2.0V VDD VRT 2.0V IOL VIN 1.0V 1.0V CLK VRB CLK VOL VOH + - GND FIGURE 3. DIGITAL OUTPUT CURRENT TEST CIRCUIT 4 IOH VIN VRB GND VDD VRT + - HI1172 Timing Diagrams tPW1 tPW0 CLOCK ANALOG INPUT DATA OUTPUT N N+1 N-3 N+3 N-2 N-1 N-2 N+4 N N+1 tD = 18ns FIGURE 4. TIMING CHART 1 VI (1) VI (2) VI (3) VI (4) ANALOG INPUT EXTERNAL CLOCK UPPER COMPARATOR BLOCK S (1) S (1) DIGITAL OUTPUT S (3) C (1) C (0) RV (3) H (3) C (3) LD (1) S (2) LD (-2) OUT (-2) C (4) MD (3) S (3) LD (-1) H (0) S (4) RV (2) H (2) C (2) LD (0) OUT (-1) FIGURE 5. TIMING CHART 2 5 C (3) MD (2) RV (1) H (1) LOWER DATA A LOWER DATA B C (2) MD (1) RV (0) LOWER REFERENCE VOLTAGE LOWER COMPARATOR BLOCK B S (2) MD (0) UPPER DATA LOWER COMPARATOR BLOCK A C (1) S (4) H (4) LD (2) OUT (0) OUT (1) HI1172 Digital Output Compatibility between analog input voltage and the digital output code is indicated in the chart below. DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP MSB VRT 0 1 • • • • • • • • • • 31 1 0 0 0 0 1 • 32 0 1 1 1 1 1 • • • • • • • • • VRB 63 Operation 0 LSB 1 0 1 0 1 1 1 Notes On Operation 0 0 0 (See Block Diagram and Waveform) The HI1172 is a 2-step parallel system A/D converter featuring a 3-bit upper comparators group and 2 lower comparators groups of 3-bit each. The reference voltage that is equal to the voltage between VRT-VRB/8 is constantly applied to the upper 3-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart with S, H, C symbols, i.e., input sampling (auto zero) mode, input hold mode and comparison mode. The operation of respective parts is as indicated in the chart. Input voltage Vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. 6 The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock. simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock. Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. • VDD, VSS - To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the respective GNDs. • Analog Input - Compared with a flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to drive with an amplifier featuring sufficient bandwidth and drive capability. When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be prevented by inserting a resistance of about 100Ω in series between the amplifier output and A/D input. • Clock Input - The clock line wiring should be as short as possible. Also, to avoid any interference with other signals, separate it from the other circuits. • Reference Input - Voltage between VRT to VRB is compatible with the dynamic range of the analog input. By bypassing VRT and VRB pins to GND with a capacitor of about 0.1µF, stable characteristics are obtained. • Timing - Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 18ns. • About Latch Up - It is necessary that AVDD and DVDD pins to be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON. HI1172 Small Outline Plastic Packages (SOIC) M16.2-S N INDEX AREA 1 2 16 LEAD SMALL OUTLINE PLASTIC PACKAGE (200 MIL) H INCHES E 3 L SEATING PLANE D A e A1 B SYMBOL MIN MAX MIN MAX NOTES A 0.067 0.078 1.70 2.00 - A1 0.002 0.011 0.05 0.30 - B 0.014 0.021 0.35 0.55 - C 0.006 0.011 0.15 0.30 - D 0.386 0.405 9.80 10.30 1 E 0.205 0.220 5.20 5.60 2 e α C 0.15(0.006) 0.24 M MILLIMETERS 0.050 BSC 1.27 BSC - H 0.296 0.326 7.50 8.3 - L 0.012 0.027 0.30 0.70 3 10o 0o N α 16 0o 16 4 10o Rev. 0 2/96 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. 2. Dimension “E” does not include interlead flash or protrusions. 3. “L” is the length of terminal for soldering to a substrate. 4. “N” is the number of terminal positions. 5. Terminal numbers are shown for reference only. 6. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 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