ISL9014 ® Data Sheet April 26, 2006 Dual LDO with Low Noise, Low IQ, and High PSRR ISL9014 is a high performance dual LDO capable of sourcing 300mA current from both outputs. The device has a low standby current and high-PSRR and is stable with output capacitance of 1μF to 10μF with ESR of up to 200mΩ. A reference bypass pin allows an external capacitor for adjusting a noise filter for low noise and high PSRR applications. The quiescent current is typically only 45μA with both LDOs enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1μA. Several combinations of voltage outputs are standard. Others are available on request. Output voltage options for each LDO range from 1.2V to 3.6V. FN9245.2 Features • Integrates two high performance LDOs - VO1 - 300mA output - VO2 - 300mA output • Excellent transient response to large current steps • Excellent load regulation: <1% voltage change across full range of load current • High PSRR: 70dB @ 1kHz • Wide input voltage capability: 2.3V - 6.5V • Extremely low quiescent current: 45μA (both LDOs active) • Low dropout voltage: typically 200mV @ 300mA • Low output noise: typically 30μVrms @ 100μA (1.5V) • Stable with 1-10μF ceramic capacitors • Separate enable pins for each LDO • Soft-start to limit input current surge during enable Pinout • Current limit and overheat protection ISL9014 10 LD 3X3 DFN TOP VIEW • ±1.8% accuracy over all operating conditions • Tiny 10 Ld 3x3mm DFN package VIN 1 10 VO1 • -40°C to +85°C operating temperature range EN1 2 9 VO2 • Pin compatible with Micrel MIC2211 EN2 3 8 NC CBYP 4 7 NC NC 5 6 GND • Pb-free plus anneal available (RoHS compliant) Applications • PDAs, Cell Phones and Smart Phones • Portable Instruments, MP3 Players • Handheld Devices including Medical Handhelds 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL9014 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING VO1 VOLTAGE VO2 VOLTAGE TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL9014IRNNZ DCBS 3.3V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRNJZ DBBK 3.3V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRNFZ DBBL 3.3V 2.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRNCZ DCBT 3.3V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRMNZ DCBV 3.0V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRMMZ DBBV 3.0V 3.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRMGZ DCCC 3.0V 2.7V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRLLZ DCEA 2.9V 2.9V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRKNZ DCCG 2.85V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRKKZ DBBW 2.85V 2.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRKJZ DCFA 2.85V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRKFZ DBBM 2.85V 2.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRKPZ DDJA 2.85V 1.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRKCZ DCBA 2.85V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRJNZ DCCH 2.8V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRJMZ DBBT 2.8V 3.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRJRZ DCDA 2.8V 2.6V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRJCZ DBBP 2.8V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRJBZ DCCA 2.8V 1.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRGPZ DDBA 2.7V 1.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRGCZ DBBR 2.7V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRFJZ DBBN 2.5V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRFDZ DCCV 2.5V 2.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRFCZ DCDB 2.5V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRPLZ DBBY 1.85V 2.9V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRPPZ DDCA 1.85V 1.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRCJZ DCDH 1.8V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRCCZ DCDL 1.8V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRBLZ DCDS 1.5V 2.9V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRBJZ DBBS 1.5V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRBCZ DCDV 1.5V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014IRBBZ DDFA 1.5V 1.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C NOTES: 1. Add “-T” to part number for tape and reel. 2. For availability and lead time of devices with voltage combinations not listed in the table, contact Intersil Marketing. 3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN9245.2 April 26, 2006 ISL9014 Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V Thermal Resistance (Notes 4, 5) Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . . .-40°C to 85°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V θJA (°C/W) θJC (°C/W) 3x3 DFN Package . . . . . . . . . . . . . . . . 50 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO+1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1μF; CO = 1μF; CBYP = 0.01μF PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 6.5 V DC CHARACTERISTICS Supply Voltage VIN Ground Current 2.3 Quiescent condition: IO1 = 0μA; IO2 = 0μA IDD1 One LDO active 25 40 μA IDD2 Both LDO active 45 60 μA Shutdown Current IDDS @25°C 0.1 1.0 μA UVLO Threshold VUV+ 1.9 2.1 2.3 V 1.6 1.8 VUVRegulation Voltage Accuracy Variation from nominal voltage output, VIN = VO +0.5 to 5.5V, TJ = -40°C to 125°C -1.8 Line Regulation VIN = (VOUT+1.0V relative to highest output voltage) to 5.5V -0.2 Load Regulation IOUT = 100μA to 150mA 2.0 V +1.8 % 0 0.2 %/V 0.1 0.7 % IOUT = 100μA to 300mA Maximum Output Current IMAX Internal Current Limit Thermal Shutdown Temperature % 300 mA VO2: Continuous 300 mA ILIM Dropout Voltage (Note 6) 1.0 VO1: Continuous 350 475 600 mA VDO1 IO = 150mA; VO > 2.1V 125 200 mV VDO2 IO = 300mA; VO < 2.5V 300 500 mV VDO3 IO = 300mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV VDO4 IO = 300mA; VO > 2.8V 200 325 mV TSD+ 145 °C TSD- 110 °C @ 1kHz 70 dB @ 10kHz 55 dB @ 100kHz 40 dB IO = 100μA, VO = 1.5V, TA = 25°C, CBYP = 0.1μF BW = 10Hz to 100kHz 30 μVrms AC CHARACTERISTICS Ripple Rejection IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1μF Output Noise Voltage 3 FN9245.2 April 26, 2006 ISL9014 Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO+1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1μF; CO = 1μF; CBYP = 0.01μF (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO(nom) 250 500 μs Slope of linear portion of LDO output voltage ramp during start-up 30 60 μs/V DEVICE START-UP CHARACTERISTICS Device Enable TIme TEN LDO Soft-Start Ramp Rate TSSR EN1, EN2 PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.5 V Input High Voltage VIH 1.4 VIN+0.3 V 0.1 μA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF NOTES: 6. VOx = 0.98 * VOx(NOM); Valid for VOx greater than 1.85V. 4 FN9245.2 April 26, 2006 ISL9014 Typical Performance Curves 0.10 0.8 VO = 3.3V ILOAD = 0mA 0.4 0.2 -40°C 0.0 25°C -0.2 85°C -0.4 VIN = 3.8V VO = 3.3V 0.08 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE, VO (%) 0.6 -0.6 0.06 0.04 -40°C 0.02 25°C 0.00 -0.02 85°C -0.04 -0.06 -0.08 -0.8 3.4 3.8 4.6 4.2 5.0 5.4 5.8 6.2 -0.10 6.6 0 50 200 250 300 350 400 LOAD CURRENT - IO (mA) FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT 0.10 3.4 VIN = 3.8V VO = 3.3V ILOAD = 0mA 0.08 0.06 VO = 3.3V IO = 0mA 3.3 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE CHANGE (%) 150 100 INPUT VOLTAGE (V) 0.04 0.02 0.00 -0.02 -0.04 -0.06 3.2 IO = 150mA 3.1 IO = 300mA 3.0 2.9 -0.08 -0.10 -40 -25 -10 5 20 35 50 65 TEMPERATURE (°C) 80 95 2.8 110 125 3.1 DROPOUT VOLTAGE, VDO (mV) OUTPUT VOLTAGE, VO (V) 2.7 IO = 150mA 2.6 IO = 300mA 2.5 2.4 3.1 3.6 4.1 4.6 5.1 5.6 INPUT VOLTAGE (V) FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (VO2 = 2.8V) 5 5.1 5.6 6.1 6.5 350 VO2 = 2.8V 2.8 2.6 4.6 FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 2.9 2.3 4.1 INPUT VOLTAGE (V) FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE IO = 0mA 3.6 6.1 6.5 300 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400 FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT FN9245.2 April 26, 2006 ISL9014 Typical Performance Curves (Continued) 55 175 VO1 = 3.3V 50 GROUND CURRENT (µA) DROPOUT VOLTAGE, VDO (mV) 150 125 85°C 25°C 100 -40°C 75 50 125°C 25°C 45 -40°C 40 35 VO1 = 3.3V VO2 = 2.8V 30 25 IO(BOTH CHANNELS) = 0µA 0 25 0 25 50 75 100 125 OUTPUT LOAD (mA) 150 175 200 3.0 4.0 3.5 4.58 5.0 5.5 6.5 6.0 INPUT VOLTAGE (V) FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE 55 200 180 50 GROUND CURRENT (µA) GROUND CURRENT (µA) 160 140 25°C 85°C 120 -40°C 100 80 60 40 45 40 35 VIN = 3.8V VO1 = 3.3V VO2 = 2.8V 20 BOTH OUTPUTS ON 0 0 50 100 150 200 250 300 350 VIN = 3.8V VO = 3.3V ILOAD = 0µA 30 25 -40 400 -25 -10 5 LOAD CURRENT (mA) VIN VO1 VO1 (V) 3 VO2 2 1 1 0 0 5 0 1 2 3 4 5 TIME (s) 6 7 8 FIGURE 11. POWER-UP/POWER-DOWN 6 110 125 VIN = 5.0V VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA CL-1, CL-2 = 1µF CBYP = 0.01µF 3 VEN (V) VOLTAGE (V) IL2 = 300mA 2 95 VO2 (10mV/DIV) VO1 = 3.3V VO2 = 2.8V IL1 = 300mA 4 80 FIGURE 10. GROUND CURRENT vs TEMPERATURE FIGURE 9. GROUND CURRENT vs LOAD 5 20 35 50 65 TEMPERATURE (°C) 9 10 0 0 100 200 300 400 500 600 700 800 900 1000 TIME (µs) FIGURE 12. TURN-ON/TURN-OFF RESPONSE FN9245.2 April 26, 2006 ISL9014 Typical Performance Curves (Continued) VO = 3.3V ILOAD = 300mA VO2 = 2.8V ILOAD = 300mA CLOAD = 1µF CBYP = 0.01µF CLOAD = 1µF CBYP = 0.01µF 4.3V 4.2V 3.6V 3.5V 10mV/DIV 10mV/DIV 400µs/DIV 400µs/DIV FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT 100 VIN = 3.6V VO = 1.8V IO = 10mA 90 80 VO (25mV/DIV) CBYP = 0.1μF VO = 1.8V VIN = 2.8V 300mA PSRR (dB) 70 CLOAD = 1μF 60 50 40 30 ILOAD 20 100μA 10 0 0.1 100μs/DIV 1 10 100 FREQUENCY (kHz) 1000 FIGURE 16. PSRR vs FREQUENCY FIGURE 15. LOAD TRANSIENT RESPONSE SPECTRAL NOISE DENSITY (nV/√Hz) 1000 100 10 VIN = 3.6V VO = 1.8V ILOAD = 10mA 1 CBYP = 0.1μF CIN = 1μF CLOAD = 1μF 0.1 10 100 1K 10K FREQUENCY (Hz) 100K 1M FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY 7 FN9245.2 April 26, 2006 ISL9014 Pin Description PIN # PIN NAME 1 VIN Analog I/O Supply Voltage/LDO Input: Connect a 1μF capacitor to GND. 2 EN1 Low Voltage Compatible CMOS Input LDO-1 Enable. 3 EN2 Low Voltage Compatible CMOS Input LDO-2 Enable. 4 CBYP Analog I/O Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01μF to 1μF between this pin and GND to tune in the desired noise and PSRR performance. 5, 7, 8 NC NC No Connection 6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane. 9 VO2 Analog I/O LDO-2 Output: Connect capacitor of value 1μF to 10μF to GND (1µF recommended). 10 VO1 Analog I/O LDO-1 Output: Connect capacitor of value 1μF to 10μF to GND (1µF recommended). TYPE DESCRIPTION Typical Application ISL9014 1 VIN (2.3-6.5V) ON 2 Enable 1 OFF ON Enable 2 OFF 3 10 VIN 9 EN1 VO2 C1 Vout 2 8 EN2 NC CBYP NC 7 4 5 Vout 1 VO1 6 NC GND C2 C3 C4 C1, C3, C4: 1μF X5R ceramic capacitor C2: 0.1μF X5R ceramic capacitor 8 FN9245.2 April 26, 2006 ISL9014 Block Diagram VIN IS1 LDO VREF 1V VO1 ERROR TRIM VO1 AMPLIFIER QEN1 ~1.0V VO2 LDO-1 EN1 QEN2 QEN1 IS2 IS1 LDO-2 CONTROL LOGIC EN2 UVLO GND BANDGAP AND TEMPERATURE SENSOR 1.00V CBYP Functional Description The ISL9014 contains all circuitry required to implement two high performance LDO’s. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9014 adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, staged turn-on and soft-start. Smart Thermal shutdown protects the device against overheating. Staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time. Power Control The ISL9014 has two separate enable pins, EN1 and EN2, to individually control power to each of the LDO outputs. When both EN1 and EN2 are low, the device is in shutdown 9 VOLTAGE REFERENCE GENERATOR mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1μA. When one or both of the enable pins are asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. After the bypass capacitor has been charged, the LDO’s power up. If EN1 is brought high, and EN2 goes high before the VO1 output stabilizes, the ISL9014 delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high before VO2 starts its output ramp, then VO1 turns on first and the ISL9014 FN9245.2 April 26, 2006 ISL9014 delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high after VO2 starts its output ramp, then the ISL9014 immediately starts to ramp up the VO1 output. If both EN1 and EN2 are brought high at the same time, the VO1 output has priority, and is always powered up first. During operation, whenever the VIN voltage drops below about 1.8V, the ISL9014 immediately disables both LDO outputs. When VIN rises back above 2.1V, the device reinitiates its start-up sequence and LDO operation will resume automatically. Reference Generation The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01μF capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1μF or greater CBYP capacitor should be used. This filters the reference noise to below the 10Hz – 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference and other voltage references required for current generation and overtemperature detection. The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. 10 LDO Regulation and Programmable Output Divider The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9014 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1μF to 10μF output capacitor that has a tolerance better than 20% and ESR less than 200mΩ. The design is performance-optimized for a 1μF capacitor. Unless limited by the application, use of an output capacitor value above 4.7μF is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30μs/V to minimize current surge. The ISL9014 provides short-circuit protection by limiting the output current to about 475mA. Each LDO uses an independently trimmed 1V reference. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory. Overheat Detection The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about 145°C, one or both of the LDO’s momentarily shut down until the die cools sufficiently. In the overheat condition, only the LDO sourcing more than 50mA will be shut off. This does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs are disabled. Once the die temperature falls back below about 110°C, the disabled LDO(s) are re-enabled and soft-start automatically takes place. FN9245.2 April 26, 2006 ISL9014 Dual Flat No-Lead Plastic Package (DFN) L10.3x3C 2X 0.10 C A A 10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE D MILLIMETERS 2X 0.10 C B E SYMBOL MIN NOMINAL MAX NOTES A 0.85 0.90 0.95 - A1 - - 0.05 - A3 6 INDEX AREA b 0.20 REF 0.20 D TOP VIEW B D2 // A C SEATING PLANE D2 6 INDEX AREA 0.08 C 7 8 D2/2 1 2.33 2.38 2.43 7, 8 1.69 7, 8 3.00 BSC 1.59 e 1.64 - 0.50 BSC - k 0.20 - - - L 0.35 0.40 0.45 8 N 10 2 Nd 5 3 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. NX k 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. E2 E2/2 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. NX L N N-1 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 0.10 M C A B (A1) 9 L 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. CL NX (b) 5, 8 Rev. 1 4/06 2 (DATUM A) 8 0.30 3.00 BSC E E2 A3 SIDE VIEW (DATUM B) 0.10 C 0.25 - 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN9245.2 April 26, 2006