ISL97653A ® Data Sheet December 6, 2007 5-Channel Integrated LCD Supply Features The ISL97653A represents a fully integrated supply IC for LCD-TV applications. With an input operating range of 4V to 14V, both commonly used LCD-TV input supplies, 5V and 12V, are supported. An AVDD supply up to 20V is generated by a high-performance PWM BOOST converter with an integrated 4.4A FET. VON is generated using an integrated charge pump with on-chip diodes and can be modulated using an on-chip VON slice control circuit. VOFF is generated using an integrated charge pump controller. Additionally, the chip allows for two logic supplies. A buck regulator with an included 2.5A high side switch is used for the main logic output and an internal LDO controller can be used to generate a second logic LDO output. • 5V to 14V Input Supply FN6367.0 • Integrated 4.4A Boost Converter • Integrated VON Charge Pump and VON Slice Circuit • Integrated VOFF Charge Pump Output • Integrated 2.5A Buck Converter • LDO Controller for an Additional Logic Supply • High Voltage Stress (HVS) Test Mode • Thermal Shutdown • 40 Ld QFN (6mmx6mm) Package • Pb-Free (RoHS Compliant) To facilitate production test, an integrated HVS circuit is included which can provide high voltage stress of the LCD panel. Applications An on-board temperature sensor is also provided for system thermal management control. • Industrial/Medical LCD Displays Pinout NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 TEMP 36 35 34 33 32 31 PVIN2 1 30 COMP CB 2 29 FBB LXL1 3 28 RSET LXL2 4 27 HVS PGND3 5 26 EN PGND4 6 25 CDEL CM2 7 24 CTL FBL 8 23 DRN VL 9 22 COM VREF 10 21 POUT 11 12 13 14 15 16 17 18 19 20 FBP *Please refer to TB347 for details on reel specifications. PGND1 L40.6X6 37 SUPP 40 Ld 6X6 QFN Tape and Reel PGND2 ISL97653AIRZ-TK* ISL97653A 38 C2N L40.6X6 LX1 40 Ld 6X6 QFN Tape and Reel 39 C2P ISL97653A LX2 ISL97653AIRZ-T* 40 C1N L40.6X6 PROT 40 Ld 6X6 QFN C1P ISL97653A AGND ISL97653AIRZ PGND5 PKG. DWG. # PVIN1 PACKAGE (Pb-Free) NOUT PART MARKING SUPN PART NUMBER (Note) LDO-FB Ordering Information LDO-CTL ISL97653A 40 LD 6X6 QFN TOP VIEW FBN The ISL97653A is packaged in a 40 Ld 6mmx6mm QFN package and is specified for operation over the -40°C to +105°C temperature range. • LCD-TVs CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97653A Absolute Maximum Ratings (TA = +25°C) Thermal Information Maximum Pin Voltages, all pins except below . . . . . . . . . . . . . . 6.5V LX1, LX2, SUPP, SUPN, NOUT, PROT, C1N, C2N . . . . . . . . .24V PVIN1, PVIN2, LXL1, LXL2 . . . . . . . . . . . . . . . . . . . . . . . . . 16.8V EN, CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V DRN, POUT, COM, C1P, C2P. . . . . . . . . . . . . . . . . . . . . . . . . .33V CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21V Operating Ambient Temperature Range . . . . . . . . -40°C to +105°C Operating Junction Temperature . . . . . . . . . . . . . . -40°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4V to 14V Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10µF Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . . . . +20V Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . . . 3x22µF Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH-10µH VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . +15V to +30V VOFF Output Range, VOFF . . . . . . . . . . . . . . . . . . . . . . . -15V to -5V Logic Output Voltage Range, VLOGIC . . . . . . . . . . . . +1.5V to +3.3V Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications VIN = 12V, VBOOST = VSUPN = VSUPP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +105°C, unless otherwise stated. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT 14 V 4 5 mA 2.7 3.5 mA 580 680 780 kHz 1.190 1.215 1.240 V 1.187 1.215 1.243 V SUPPLY PINS VIN Supply Voltage IS Quiescent Current 4 Enabled, no switching Disabled FSW Switching Frequency VREF Reference Voltage TA = +25°C VLOR Undervoltage Lockout Threshold VL rising 3.4 3.55 3.7 V VLOF Undervoltage Lockout Threshold VL falling 2.9 3.0 3.2 V Thermal Shutdown Temperature rising Thermal Shutdown Hysteresis 150 °C 20 °C LOGIC SIGNALS HVS, EN, CTL Logic Input High 2.0 V Logic Input Low Pull-down Resistance 130 174 0.4 V 215 kΩ HVS, RSET RSET RSET Pull-down Resistance HVS = HIGH IRSET RSET Leakage Current HVS = LOW, VRSET = 1.2V Ω 200 0.4 µA 12 % AVDD BOOST DLIM Min Duty Cycle 8.5 Max Duty Cycle 90 % VBOOST Boost Output Range 20 V EFFBOOST Boost Efficiency VIN = 12V, VBOOST = 15V 90+ % VFB Boost Feedback Voltage TA = +25°C 2 1.203 1.215 1.227 V 1.198 1.215 1.232 V FN6367.0 December 6, 2007 ISL97653A Electrical Specifications VIN = 12V, VBOOST = VSUPN = VSUPP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +105°C, unless otherwise stated. (Continued) PARAMETER DESCRIPTION CONDITIONS IBOOST Boost FET Current Limit RDSON-BOOST Switch On Resistance ΔVBOOST/ΔVIN Line Regulation - Boost ΔVBOOST/ΔIOUT Load Regulation - Boost Load 100mA to 200mA EFFBUCK Buck Efficiency VIN = 5V, VLOGIC = 3.3V IBUCK Buck FET Current Limit RDSON-BUCK Switch On Resistance ΔVLDO/ΔIOUT Load Regulation - Buck Load 100mA to 500mA VFL Feedback Voltage TA = +25°C MIN TYP MAX UNIT 3.7 4.4 4.95 A 93 200 mΩ 0.08 0.15 % 0.004 1 % LOGIC BUCK 90+ 1.9 % 4.0 A 150 210 mΩ 0.5 1 % 1.195 1.215 1.235 V 1.189 1.215 1.241 V VON CHARGE PUMP ILoad_PCP_min VFBP External Load Driving Capability Feedback Voltage, ION = 1mA VON = 24V (2X Charge Pump) 40 mA VON = 28V (3X Charge Pump) 40 mA TA = +25°C RON (VSUP_SW) ON Resistance of VSUP Input Switch I(switch) = +40mA RON (C1/2-)H High-Side Driver ON Resistance at C1- and C2- I(C1/2-) = +40mA RON (C1/2-)L Low-Side Driver ON Resistance at C1- and C2- I(C1/2-) = -40mA VON Load Reg VON Output Load Regulation ION = 10mA to 40mA V(diode) Internal Schottky Diode Forward Voltage I(diode) = +40mA Drop 1.195 1.215 1.235 V 1.189 1.215 1.241 V 10 17 Ω 30 Ω 10 Ω +1 % 800 mV 4 700 VOFF CHARGE PUMP ILoad_NCP_min External Load Driving Capability SUPN>13.5V VOFF=-8V VFBN Feedback Voltage, IOFF = 10mA TA = +25°C 100 120 mA 0.173 0.203 0.233 V 0.171 0.203 0.235 V RON (NOUT)H High-Side Driver ON Resistance at NOUT I(NOUT) = +60mA 10 Ω RON (NOUT)L Low-Side Driver ON Resistance at NOUT I(NOUT) = -60mA 5 Ω VOFF Load Reg VOFF Output Load Reg IOFF = 10mA to 100mA, TA = +25°C 2.4 % IDRVP Sink Current VFBP = 1.1V, VLDO_CTL = 10V LDO-FB Feedback Voltage w/transistor load 1mA TA = +25°C LDO Controller 12 15 mA 1.191 1.215 1.239 V 1.189 1.215 1.241 V FAULT DETECTION THRESHOLDS T_off Thermal Shut-Down (latched and reset Temperature rising by power cycle or EN cycle) 150 °C Vth_AVDD(FBB) AVDD Boost Short Detection 0.9 V 3 V(FBB) falling less than FN6367.0 December 6, 2007 ISL97653A Electrical Specifications VIN = 12V, VBOOST = VSUPN = VSUPP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +105°C, unless otherwise stated. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT Vth_POUT (FBP) POUT Charge Pump Short Detection V(FBP) falling less than 0.9 V Vth_NOUT (FBN) NOUT Charge Pump Short Detection V(FBN) rising more than 0.4 V CTL = VDD, sequence complete 400 500 µA CTL = AGND, sequence complete 150 200 µA VON Slice POSITIVE SUPPLY = V(POUT) I(POUT)_slice VON Slice Current from POUT Supply RON (POUT-COM) ON Resistance between POUT-COM CTL = VDD, sequence complete 5 10 Ω RON (DRN-COM) ON Resistance between DRN-COM CTL = AGND, sequence complete 30 60 Ω RON_COM ON Resistance between DRN-COM and PGND 200 260 400 Ω PROT Pull-Down Current or Resistance VPROT > 0.9V when Enabled by the Start-U VPROT < 0.9V 38 50 60 µA 500 760 1000 Ω 2 3 4 mA PROT IPROT_ON IPROT_OFF PROT Pull-Up Current when Disabled 4 VPROT < 20V FN6367.0 December 6, 2007 ISL97653A Typical Application Diagrams D1 L L1 VIN M0 6.8µH R22 75k R21 75k C3 22µF x3 C1 2.2µF 34 C30 Optional C2 R2 4.7nF 0 C4 220nF C5 220nF C6 0.22µF COMP 30 PGND1 32 PGND2 33 HVS 27 EN 26 PROT 36 C1P 15 C1N 16 C2P 17 C2N 18 CTL 24 CDEL 25 PGND5 VL C8 4.7nF BOOST HVS R3 55k LX1 35 LX2 29 FBB 28 RSET R4 5k R5 20k SEQUENCING/FAULT CONTROL VON CP 19 SUPP 21 POUT R6 983k 20 VON C9 470nF FBP R8 1k R7, 50k 23 R10 DRN VON SLICE 15 22 COM 12 SUPN R9 C22 0.1µF 1k 14 9 C7 4.7µF C0 10µF AVDD PVIN1 38 PVIN2 1 CM2 7 R20 10k INTERNAL REGULATOR VOFF CP 5 PGND4 6 VREF 11 FBN 13 NOUT 2 BUCK PGND3 10 CB R11 40k R12 328k VOFF C11 220nF 3 LXL1 C13 1µF 4 LXL2 D4 8 R17 100k C19 220nF D2 C12 470nF D3 L L2 VLOGIC 6.8µH C14 20µF R13 2k FBL VLOGIC R14 1.2k VLOGIC2 R17 LDO CONTROLLER AGND 5 37 TEMP SENSOR 40 LDO-CTL 39 LDO-FB 31 TEMP Q1 R15 5.4k C15 4.7µF R16 5k C16 10nF FN6367.0 December 6, 2007 ISL97653A Typical Application Diagrams (Continued) VREF PROT RSET HVS HVS LOGIC CM1 GM AMPLIFIER SAWTOOTH GENERATOR SLOPE COMPENSATION + FBB VREF CONTROL LOGIC Ε UVLO COMPARATOR LX1 LX2 BUFFER + RSENSE PGND1 PGND2 CURRENT AMPLIFIER 0.75 VREF 680kHz OSCILLATOR FREQ VL PVIN1,2 CURRENT LIMIT COMPARATOR REGULATOR REFERENCE BIAS AND CDEL CURRENT LIMIT THRESHOLD SEQUENCE CONTROLLER EN VL PVIN1,2 CB SUPN LXL1 LXL2 NOUT CONTROL LOGIC CURRENT LIMIT COMPARATOR + FBN BUFFER CURRENT AMPLIFIER GM AMPLIFIER SLOPE COMPENSATION CURRENT LIMIT THRESHOLD UVLO COMPARATOR + Ε + 0.2V CM2 FBL VREF SAWTOOTH GENERATOR + 0.4V 0.75 VREF LDO CONTROL LOGIC2 + FBP SUPP + TEMP SENSOR LDO-CTL LDO-FB TEMP VREF POUT SUPP C1- 6 C1+ POUT C2+ C2- DRN CTL COM FN6367.0 December 6, 2007 ISL97653A Typical Performance Curves 0.5 90 LOAD REGULATION (%) EFFICIENCY (%) 100 VIN = 12V VIN = 8V VIN = 5V 80 70 0.3 VIN = 5V 0.2 500 1000 VIN = 12V 0.1 0.0 0 VIN = 8V 0.4 1500 0 500 IO (mA) 0.08 100 0.06 90 VIN = 5V 0.04 IO = 100mA 0.02 0.00 80 VIN = 8V VIN = 12V 70 60 -0.02 -0.04 5 IO = 400mA 6 7 8 9 10 11 12 13 50 14 0 500 1000 1500 2000 IO (mA) VIN (V) FIGURE 3. BOOST LINE REGULATION FIGURE 4. BUCK EFFICIENCY 0.10 0.3 0.2 0.1 LINE REGULATION (%) LOAD REGULATION (%) 1500 FIGURE 2. BOOST LOAD REGULATION EFFICIENCY (%) LINE REGULATION (%) FIGURE 1. BOOST EFFICIENCY VIN = 5V 0.0 VIN = 12V -0.1 -0.2 -0.3 1000 IO (mA) VIN = 8V 0 500 1000 1500 IO (mA) FIGURE 5. BUCK LOAD REGULATION 7 2000 0.08 IO = 400mA 0.06 0.04 IO = 100mA 0.02 0.00 5 6 7 8 9 10 11 12 13 14 VIN (V) FIGURE 6. BUCK LINE REGULATION FN6367.0 December 6, 2007 ISL97653A Typical Performance Curves (Continued) 1.2 LOAD REGULATION (%) LOAD REGULATION (%) 0 VON = 25V -1 -2 -3 -4 -5 0 10 20 30 40 50 60 ION (mA) FIGURE 7. VON LOAD REGULATION 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 VON = 25V 0 10 20 30 ION (mA) 40 50 60 FIGURE 8. VOFF LOAD REGULATION CH1 = AVDD (VBOOST)(500mV/DIV) CH2 = IO (BOOST)(200mA/DIV) LOAD REGULATION (%) 0.0 -0.2 -0.4 -0.6 -0.8 VLOGIC = 2.3V -1.0 -1.2 -1.4 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 ILDO (mA) 1ms/DIV FIGURE 9. LOGIC LDO LOAD REGULATION FIGURE 10. BOOST TRANSIENT RESPONSE CH1 = AVDD (VBOOST) (100mV/DIV) CH2 = IO (BOOST) (100mA/DIV) CH1 = VCTL (5V/DIV) CH2 = COM (10V/DIV) 1ms/DIV FIGURE 11. BUCK TRANSIENT RESPONSE 8 40µs/DIV FIGURE 12. VON SLICE OPERATION FN6367.0 December 6, 2007 ISL97653A Typical Performance Curves (Continued) Ch1 = LXL (400ns/DIV) Ch2 = ILXL (400ns/DIV) Ch1 = LXL (400ns/DIV) Ch2 = ILXL (400ns/DIV) FIGURE 13. BOOST CURRENT LIMIT FIGURE 14. BUCK CURRENT LIMIT Pin Descriptions PIN NUMBER PIN NAME 1 PVIN2 2 CB Logic buck boot strap pin. Generate the gate drive voltage for the N-Channel MOSFET by connecting a 1µF cap to the switching node LXL1,2. 3, 4 LXL1, 2 Logic buck switching node. Source of the high side internal power N-Channel MOSFET for the Buck. 5, 6 PGND3,4 7 CM2 Buck compensation pin. An RC network is recommended. Increase R for better transient response at the expense of stability. 8 FBL Logic buck feedback pin. High impedance input to regulate at 1.215V. 9 VL 10 VREF 11 FBN Negative charge pump feedback pin. High impedance input to regulate to 0.203V. 12 SUPN Negative charge pump supply voltage. Can be the same as or different from AVDD. 13 NOUT Negative charge pump driver output. 14 PGND5 15 C1P Charge pump capacitor 1, positive connection. 16 C1N Charge pump capacitor 1, negative connection. 17 C2P Charge pump capacitor 2, positive connection. 18 C2N Charge pump capacitor 2, negative connection. 19 SUPP 20 FBP 21 POUT VON charge pump output. 22 COM High voltage switch control output. VON slice output. 23 DRN Lower reference voltage for VON slice output. Usually connected to AVDD. 24 CTL Input control pin for VON slice output. 9 DESCRIPTION Logic buck supply voltage. This is also the analog supply from which the VL is generated. Needs at least 1µF bypassing. Logic buck ground pin. 5.25V internal regulator output. Bypass with a 4.7µF cap. Ref voltage is generated from VL. Reference voltage output. Bypass with a low valued cap for transients - recommend 220nF. Should not be greater than 5 times CDEL cap to ensure correct start-up sequence. Charge pump ground pin. Positive charge pump supply. Can be the same as or different from AVDD. Positive charge pump feedback pin. High impedance input to regulate at 1.215V FN6367.0 December 6, 2007 ISL97653A Pin Descriptions (Continued) PIN NUMBER PIN NAME DESCRIPTION 25 CDEL VON slice control delay input. Minimum 47nF. Recommend 220nF but is only limited by leakage in the cap reaching µA levels. 26 EN 27 HVS 28 RSET 29 FBB 30 COMP Boost compensation network pin. An RC network is recommended. Increase R for better transient response at the expense of stability. An R = 0Ω is recommended for 4.4A Boost requirements. 31 TEMP Temperature sensor output voltage. An analog voltage from 0V to 3V for temperatures of -40°C to +150°C. 32, 33 PGND1, 2 34, 35 LX1, 2 Boost switch output. Drain of the internal power NMOS for the Boost. 36 PROT Gate driver of the Input protection switch. Goes low when EN is high. Can be used to modulate the passive input inrush current as shown by R21,R22, and C30 in the typical application diagram. 37 AGND Analog ground. Separate from PGND’s and star under the chip. 38 PVIN1 Logic buck supply voltage.This is also the analog supply from which the VL is generated. Needs at least 1µF bypassing. 39 LDO-FB 40 LDO-CTL 10 Chip enable (active high). Can be driven to VIN levels. High-voltage stress input select pin. High selects high voltage mode. Voltage set pin for HVS test. RSET connects to ground in the high voltage mode - RSET high. AVDD boost feedback pin. High impedance input to regulate at 1.215V. Boost ground pins. LDO controller feedback. High impedance input to regulate at 1.215V. LDO control pin. Gate drive for the external PNP BJT. FN6367.0 December 6, 2007 ISL97653A Application Information Table 1 gives typical values (worst case margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, FSWand IOMAX): AVDD Boost Converter The AVDD boost converter features a fully integrated 4.4A boost FET. The regulator uses a current mode PI control scheme which provides good line regulation and good transient response. It can operate in both discontinuous conduction mode (DCM) at light loads and continuous mode (CCM). In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by Equation 1: V boost 1 ------------------ = ------------1–D V IN TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION VIN (V) VO (V) L (µH) IOMAX (mA) 5 9 6.8 2215 5 12 6.8 1673 5 15 6.8 1344 12 15 6.8 3254 12 18 6.8 2670 (EQ. 1) Boost Converter Input Capacitor where D is the duty cycle of the switching MOSFET. The boost soft-start function is digitally controlled within a fixed 10ms time frame during which the current limit is increased in eight linear steps. The boost converter uses a summing amplifier architecture for voltage feedback, current feedback, and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is triggered. Since this comparison is cycle based, the PWM output will be released after the peak current goes below the current limit threshold. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60kΩ is recommended. The boost converter output voltage is determined by Equation 2: R3 + R4 A VDD = --------------------- × V FBB R4 An input capacitor is used to suppress the voltage ripple injected into the boost converter. A ceramic capacitor with capacitance larger than 10µF is recommended. The voltage rating of input capacitor should be larger than the maximum input voltage. Some capacitors are recommended in Table 2 for input capacitor. TABLE 2. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/25V 1210 TDK C3225X7R1E106M 10µF/25V 1210 Murata GRM32DR61E106K Boost Inductor The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Values of 3.3µH to 10µH are recommended to match the internal slope compensation as well as to maintain a good transient response performance. The inductor must be able to handle the average and peak currents expressed in Equations 5 and 6: IO I LAVG = ------------1–D (EQ. 5) where R3 and R4 are in the “” on page 5. Unless otherwise stated, component variables referred to in equations refer to the Typical Application Diagram. ΔI L I LPK = I LAVG + -------2 (EQ. 6) The current through the MOSFET is limited to 4.4A peak. This restricts the maximum output current (average) based on Equation 3: Some inductors are recommended in Table 3. (EQ. 2) ΔI L V IN I OMAX = ⎛ I LMT – --------⎞ × --------⎝ ⎠ 2 VO TABLE 3. BOOST INDUCTOR RECOMMENDATION INDUCTOR (EQ. 3) Where ΔIL is peak to peak inductor ripple current, and is set by Equation 4. fs is the switching frequency (680kHz). V IN D ΔI L = --------- × ----L fS 10µH/ 5.1APEAK 5.9µH/ 6APEAK DIMENSIONS (mm) VENDOR 13x13x4.5 TDK 12.9X12.9X4 Sumida PART NUMBER RLF12545T-100M5R1 CDEP12D38NP-5R9MB-120 (EQ. 4) 11 FN6367.0 December 6, 2007 ISL97653A Rectifier Diode (Boost Converter) A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output voltage. The rectifier diode must meet the output current and peak inductor current requirements. The following table lists two recommendations for boost converter diode. TABLE 4. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION DIODE VR/IAVG RATING PACKAGE FYD0504SA 50V/2A DPAK 30WQ04FN 40V/3.5A VENDOR Fairchild Semiconductor DPAK Stability can be examined by repeatedly changing the load between 100mA and a max level that is likely to be used in the system being used. The AVDD voltage should be examined with an oscilloscope set to AC 100mV/DIV and the amount of ringing observed when the load current changes. Reduce excessive ringing by reducing the value of the resistor in series with the CM1 pin capacitor. Cascaded MOSFET Application A 20V N-Channel MOSFET is integrated in the boost regulator. For applications requiring output voltages greater than 20V, an external cascaded MOSFET is needed as shown in Figure 15. The voltage rating of the external MOSFET should be greater than AVDD. VIN AVDD International Rectifier LX1, LX2 Output Capacitor Integrating output capacitors supply the load directly and reduce the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor. V O – V IN IO 1 V RIPPLE = I LPK × ESR + ------------------------ × ---------------- × ---V C f O OUT s (EQ. 7) For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in Equation 7 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts. Table 5 shows some selections of output capacitors. TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/25V 1210 TDK C3225X7R1E106M 10µF/25V 1210 Murata GRM32DR61E106K PI Loop Compensation (Boost Converter) The boost converter of ISL97653A can be compensated by a RC network connected from COMP pin to ground. C2 = 4.7nF and R2 = 0Ω to 10Ω. A RC network is used in the demo board. A higher capacitor value can be used to increase system stability. 12 FBB INTERSIL ISL97653A FIGURE 15. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS VIN Protection A series external P-FET can be used to prevent passive power-up inrush current from the Boost output caps charging to VIN - VSCHOTTKY via the boost inductor and Schottky diode. This FET also adds protection in the event of a short circuit on AVDD. The gate of the PFET (shown as M0 in the “” on page 5) is controlled by PROT. When EN is low, PROT is pulled internally to PVIN1, thus M0 is switched off. When EN goes high, PROT is pulled down slowly via a 50µA current source, switching M0 on. If the device is powered up with EN tied to high, M0 will remain switched off until the voltage on VL exceeds the VLOR threshold. Once the voltage on PROT falls below 0.6V and the step-up regulator is within 90% of its target voltage, PROT is pulled down to ground via a 1.3kΩ impedance. If AVDD falls 10% below regulation, the drive to PROT reverts to a 50µA current source. If a timed fault is detected, M0 is actively switched off. Several additional external components can optionally be used to fine-tune the function of pin PROT (shown in the dashed box near M0 in application diagram). PROT ramp rate can be controlled by adding a capacitor C30 between gate and source of M0. M0 gate voltage can be limited during soft-start by adding a resistor (~75kΩ) between gate FN6367.0 December 6, 2007 ISL97653A and source of M0. In addition, a resistor can be connected between PROT and the gate of M0, in order to limit the maximum VGS of M0 at all times. Buck Converter The buck converter is a step down converter supplying power to the logic circuit of the LCD system. The ISL97653A integrates a high voltage N-channel MOSFET to save cost and reduce external component count. In the continuous current mode, the relationship between input voltage and output voltage as expressed in Equation 8: V LOGIC ---------------------- = D V IN (EQ. 8) Where D is the duty cycle of the switching MOSFET. Because D is always less than 1, the output voltage of a buck converter is lower than input voltage. The peak current limit of buck converter is set to 2.5A, which restricts the maximum output current (average) based on Equation 9: I OMAX = 2.5A – ΔI P-P (EQ. 9) Where ΔIP-P is the ripple current in the buck inductor as shown in Equation 10: V LOGIC ΔI pp = ---------------------- ⋅ ( 1 – D ) L ⋅ fs Where Io is the output current of the buck converter. Table 6 shows some recommendations for input capacitor. TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/16V 1206 TDK C3216X7R1C106M 10µF/10V 0805 Murata GRM21BR61A106K 22µF/16V 1210 Murata C3225X7R1C226M Buck Inductor A 3.3µH to 10µH inductor range is recommended for the buck converter. Besides the inductance, the DC resistance and the saturation current are also factors that need to be considered when choosing a buck inductor. Low DC resistance can help maintain high efficiency. Saturation current rating should be higher than 2A. Here are some recommendations for buck inductor. TABLE 7. BUCK INDUCTOR RECOMMENDATION INDUCTOR DIMENSIONS (mm) VENDOR PART NUMBER 4.7µH/ 2.7APEAK 5.7x5.0x4.7 Murata LQH55DN4R7M01K 6.8µH/ 3APEAK 7.3x6.8x3.2 TDK RLF7030T-6R8M2R8 (EQ. 10) Rectifier Diode (Buck Converter) Where L is the buck inductor, fs is the switching frequency (680kHz). Feedback Resistors The buck converter output voltage is determined by Equation 11: R 14 + R 13 V LOGIC = --------------------------- × V FBL R 14 A Schottky diode is recommended for fast recovery and low forward voltage. The reverse voltage rating should be higher than the maximum input voltage. The peak current rating is 2.5A, and the average current is given by Equation 13: I avg = ( 1 – D )*I o (EQ. 11) Where R13 and R14 are the feedback resistors in the buck converter loop to set the output voltage Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 1kΩ is recommended. (EQ. 13) Where Io is the output current of buck converter. The following table shows some diode recommended. TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION DIODE VR/IAVG RATING PACKAGE PMEG2020EJ 20V/2A SOD323F Philips Semiconductors SS22 20V/2A SMB Fairchild Semiconductor VENDOR Buck Converter Input Capacitor Input capacitance should support the maximum AC RMS current which occurs at D = 0.5 and maximum output current. I acrms ( C IN ) = D ⋅ ( 1 – D ) ⋅ IO (EQ. 12) 13 FN6367.0 December 6, 2007 ISL97653A Output Capacitor (Buck Converter) Positive Charge Pump Design Consideration Four 10µF or two 22µF ceramic capacitors are recommended for this part. The overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer. All positive charge pump diodes (D1, D2 and D3 shown in the “NEGATIVE CHARGE PUMP BLOCK DIAGRAM” on page 16) for x2 (doubler) and x3 (Tripler) modes of operation are included in the ISL97653A. During the chip start-up sequence the mode of operation is automatically detected when the charge pump is enabled. With both C7 and C8 present, the x3 mode of operation is detected. With C7 present, C8 open and with C1+ shorted to C2+, the x2 mode of operation will be detected. TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE VENDOR PART NUMBER 10µF/6.3V 0805 TDK C2012X5R0J106M 10µF/6.3V 0805 Murata GRM21BR60J106K 22µF/6.3V 1210 TDK C3216X5R0J226M 100µF/6.3V 1206 Murata GRM31CR60J107M PI Loop Compensation (Buck Converter) The buck converter of ISL97653A can be compensated by a RC network connected from CM2 pin to ground. C8 = 4.7nF and R20 = 10k RC network is used in the demo board. A larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. The stability can be optimized in a similar manner to that described in “PI Loop Compensation (Boost Converter)” on page 12. Internal switches M1, M2 and M3 isolate POUT from SUPP until the charge pump is enabled. This is important for TFT applications that require the negative charge pump output (VOFF) and AVDD supplies to be established prior to POUT. The maximum POUT charge pump current can be estimated from the following equations assuming a 50% switching duty: I MAX ( 2x ) ∼ min of 40mA or 2 • V SUPP – 2 • V DIODE ( 2 • I MAX ) – V ( V ON ) -------------------------------------------------------------------------------------------------------------------------- • 0.95A ( 2 • ( 2 • R ONH + R ONL ) ) Bootstrap Capacitor (C13) I MAX ( 3x ) ∼ min of 40mA or This capacitor provides the supply to the high driver circuitry for the buck MOSFET. The bootstrap supply is formed by an internal diode and capacitor combination. A 1µF is recommended for ISL97653A. A low value capacitor can lead to overcharging and in turn damage the part. 3•V · – 3 • V DIODE ( 2 • I MAX ) – V ( V ON ) SUP P ------------------------------------------------------------------------------------------------------------------------- • 0.95V ( 2 • ( 3 • R ONH + 2 • R ONL ) ) (EQ. 14) Note: VDIODE (2 • IMAX) is the on-chip diode voltage as a function of IMAX and VDIODE (40mA) < 0.7V. During very light loads, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. Additionally, if VIN - VBUCK < 1.5V, the internal MOSFET pull-up device may be unable to turn-on until VLOGIC falls. Hence, there is a minimum load requirement in this case. The minimum load can be adjusted by the feedback resistors to FBL. Charge Pump Controllers (VON and VOFF) The ISL97653A includes 2 independent charge pumps (see charge pump block and connection diagram). The negative charge pump inverts the SUPN voltage and provides a regulated negative output voltage. The positive charge pump doubles or triples the SUPP voltage and provides a regulated positive output voltage. The regulation of both the negative and positive charge pumps is controlled by internal comparators that sense the output voltage. These sensed voltages are then compared to scaled internal reference voltages. Charge pumps use pulse width modulation to adjust the pump period, depending on the load present. The pumps can provide 100mA for VOFF and 40mA for VON. 14 FN6367.0 December 6, 2007 ISL97653A External Connections and Components SUPP x2 Mode x3 Mode Both M2 C1C7 M4 C1+ SUPP M1 Control D3 D2 D1 680KHz POUT C14 0.9V SUPP C2+ Error M3 C8 VREF C2FB C21 R8 M5 FBP C22 R9 FIGURE 16. VON FUNCTION DIAGRAM The maximum VOFF output voltage of a single stage charge pump is: In voltage doubler configuration, the maximum VON is as given by the following equation: V ON_MAX(2x) = 2 • ( V SUPP – V DIODE ) – 2 • I OUT • ( 2 • R ONH + R ONL ) (EQ. 15) V OFF_MAX ( 2x ) = – V SUPP + V DIODE + 2 • I OUT • ( R ON ( NOUT )H + R ON ( NOUT )L ) (EQ. 18) For Voltage Tripler: VON_MAX(3x) = 3 • ( V SUPP – V DIODE ) – 2 • I OUT • ( 3 • R ONH + 2 • RONL (EQ. 16) VON output voltage is determined by the following equation: R 8⎞ ⎛ V ON = V FBP • ⎜ 1 + -------⎟ R 9⎠ ⎝ (EQ. 17) R6 and R7 in the Typical Application Diagram determine VOFF output voltage. R7 R7 V OFF = V FBN • ⎛ 1 + --------⎞ – V REF • ⎛ --------⎞ ⎝ R6⎠ ⎝ R6⎠ (EQ. 19) *Although in the given typical application diagram, SUPP and SUPN are connected to AVDD, depending on a specific application, SUPN and/or SUPP could be connected to either AVDD or VIN. Negative Charge Pump Design Consideration The negative charge pump consists of an internal switcher M1, M2 which drives external steering diodes D2 and D3 via a pump capacitor (C12) to generate the negative VOFF supply. An internal comparator (A1) senses the feedback voltage on FBN and turns on M1 for a period up to half a CLK period to maintain V(FBN) in regulated operation at 0.2V. External feedback resistor R6 is referenced to VREF. Faults on VOFF which cause VFBN to rise to more than 0.4V, are detected by comparator (A2) and cause the fault detection system to start the internal fault timer which will cause the chip to power down if the fault persists. 15 FN6367.0 December 6, 2007 ISL97653A VREF A2 C19 100pF SUPN VDD FAULT 0.4V FBN C20 820pF R6 40k A1 R7 328k 0.2V 1.2MHz STOP M2 CLK NOUT C12 220nF D2 VOFF (-8V) D3 PWM CONTROL EN C13 470nF M1 PGND FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM VON Slice Circuit VLOGIC2 LDO The VON slice circuit functions as a three way multiplexer, switching the voltage on COM between ground, DRN and POUT, under control of the start-up sequence and the CTL pin. An LDO controller is also integrated to provide a second logic supply. The LDO-CTL pin drives the base of an external transistor which should be sized for the current required. A resistor divider is used to set the output voltage by feeding back a reference voltage to LDO-FB. The internal feedback reference is 1.215V. During the start-up sequence, COM is pulled to ground via an NDMOS FET with RDS(on) of 260 ohms. After the start-up sequence has completed, CTL is enabled and acts as a multiplexer control such that if CTL is low, COM connects to DRN through a 30Ω internal MOSFET, and if CTL is high, COM connects to POUT internally via a 5Ω MOSFET. The slew rate of the switch control circuit is mainly restricted by the load capacitance at COM pin and is given by Equation 20: Vg ΔV -------- = -----------------------------------|| Δt ( Ri RL ) × CL (EQ. 20) Where Vg is the supply voltage applied to DRN or voltage at POUT, which range is from 0V to 30V. Ri is the resistance between COM and DRN or POUT including the internal MOSFET rDS(on), the trace resistance and the resistor inserted, RL is the load resistance of VON slice circuit, and CL is the load capacitance of switch control circuit. In the Typical Application Circuit, R8, R9 and C22 give the bias to DRN based on Equation 21: V ON ⋅ R 9 +AVDD ⋅ R 8 V DRN = --------------------------------------------------------R9 + R (EQ. 21) 8 And R10 can be adjusted to adjust the slew rate. 16 HVS Operation When the HVS input is taken high, the ISL97653A enters HVS test mode. In this mode, the output of AVDD is increased by switching RSET to ground, and the AVDD is set to: R3 + Rx A VDD = --------------------- × V FBB Rx (EQ. 22) Where Rx is the value of R4 in parallel with R5. AVDD voltage higher than the maximum rating of the boost MOSFET may damage the part. Fault Protection The ISL97653A incorporates a number of fault protection schemes. AVDD, VON, and VOFF are constantly monitored. If fault conditions are detected for longer than 1ms on these FB inputs, the device stops switching and the outputs are disconnected. The ISL97653A also integrates over temp and over current protection. Supply Sequencing When the input voltage VIN is higher than 4V(UVLO), VREF, VLOGIC, and VLOGIC2 are turned on. VLOGIC has a 9ms fixed soft-start at start-up. AVDD, VON, and VOFF are dependant on the EN pin. FN6367.0 December 6, 2007 ISL97653A When EN is taken high, voltage of pin PROT and VOFF start ramping down. Once the PROT voltage falls below 0.9V, AVDD starts up with a 9ms fixed soft-start time. Please note if VOFF is to start earlier than AVDD, then the SUPN needs to connect to Vin, and Vin voltage should be larger than VOFF absolute value. The delay between VOFF and AVDD can be controlled by C30 in the typical application diagram and is given by Equation 23: T DELAY = ( V IN – 0.9V ) × C 30 ⁄ ( 50μA ) (EQ. 23) The successful completion of the AVDD soft-start cycle triggers two simultaneous events. VON begins to ramp up and the voltage on CDEL starts ramping up. When the voltage reaches 1.215V, VON slice starts. Fault Sequencing The ISL97653A has advanced overall fault detection systems including Over Current Protection (OCP) for both boost and buck converters, Under Voltage Lockout Protection (UVLP) and Over-Temperature Protection. Once the peak current flowing through the switching MOSFET of the boost and buck converters triggers the current limit threshold, the PWM comparator will disable the output, cycle by cycle, until the current is back to normal. Layout Recommendation The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: VIN VREF VLOGIC EN 0.9V PROT AVDD VON VOFF 2.8V CDEL 1.215V VON Slice * For demonstration only, not to scale FIGURE 18. Temperature Sensor The ISL97653A also includes a temperature output for use in system thermal management control. The integrated sensor measures the die temperature over the -40°C to +150°C range. Output is in the form of an analog voltage on the TEMP pin in the range of 0V to 3V, which is proportional to the sensed die temperature. Temperature accuracy is ±8.5°C over the -40°C to +150°C temperature range. The device should be disabled by the user when the TEMP pin output reaches 3V ( = +150°C die junction). Operation of the device between +125°C and +150°C can be tolerated for short periods, however in order to maximize the life of the IC, it is recommended that the effective continuous operating junction temperature of the die should not exceed +125°C. 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VL bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. Minimize feedback input track lengths to avoid switching noise pick-up. A demo board is available to illustrate the proper layout implementation. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN6367.0 December 6, 2007 ISL97653A Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 4X 4.5 6.00 36X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 40 31 30 1 6.00 4 . 10 ± 0 . 15 21 10 0.15 (4X) 11 20 0.10 M C A B TOP VIEW 40X 0 . 4 ± 0 . 1 4 0 . 23 +0 . 07 / -0 . 05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0 . 1 ( C BASE PLANE ( 5 . 8 TYP ) SEATING PLANE 0.08 C SIDE VIEW 4 . 10 ) ( 36X 0 . 5 ) C 0 . 2 REF 5 ( 40X 0 . 23 ) 0 . 00 MIN. 0 . 05 MAX. ( 40X 0 . 6 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 18 FN6367.0 December 6, 2007