ISL28276, ISL28476 ® Data Sheet April 20, 2007 Dual and Quad Precision Micropower Single Supply Rail-to-Rail Input and Output Precision Op Amps FN6301.1 Features • 60µA supply current per channel The ISL28276 and ISL28476 are Dual and Quad channel micropower precision operational amplifier optimized for single supply operation at 5V and can operate down to 2.4V. For equivalent performance in a single channel op-amp reference EL8176. The ISL28276 and ISL28476 feature an Input Range Enhancement Circuit (IREC) which enables both parts to maintain CMRR performance for input voltages equal to the positive and negative supply rails. The input signal is capable of swinging 0.5V above a 5.0V supply (0.25V for a 2.4V supply) and to within 10mV from ground. The output operation is rail to rail. • 100µV max offset voltage • 500pA input bias current • 400kHz gain-bandwidth product • 115dB PSRR and CMRR • Single supply operation down to 2.4V • Input is capable of swinging above V+ and within 10mV of Ground • Rail-to-rail output • Output sources 31mA load current • Pb-free plus anneal available (RoHS compliant) The both parts draw minimal supply current while meeting excellent DC-accuracy, AC-performance, noise and output drive specifications. Offset current, voltage and current noise, slew rate, and gain-bandwidth product are all two to ten times better than other micropower op-amps with equivalent supply current ratings. Applications The ISL28276 and ISL28476 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. • Medical devices • Battery- or solar-powered systems • 4mA to 25mA current loops • Handheld consumer products • Thermocouple amplifiers • Photodiode pre-amps • pH probe amplifiers Ordering Information PART NUMBER (Note) PART TAPE & MARKING REEL PACKAGE (Pb-Free) PKG. DWG. # ISL28276IAZ 28276 IAZ 97/Tube 16 Ld QSOP MDP0040 ISL28276IAZ-T7 28276 IAZ 7” 16 Ld QSOP MDP0040 (1k pcs) Coming Soon ISL28476FAZ 28476 FAZ 97/Tube 16 Ld QSOP MDP0040 Coming Soon 28476 FAZ 7” 16 Ld QSOP MDP0040 ISL28476FAZ-T7 (1k pcs) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL28276, ISL28476 Pinouts ISL28476 (16 LD QSOP) TOP VIEW ISL28276 (16 LD QSOP) TOP VIEW OUT_A 1 NC 2 15 V+ IN-_A 2 14 OUT_B IN+_A 3 16 OUT_D 15 IN-_D + 16 NC 14 IN+_D + 13 IN-_B V+ 4 IN+_A 5 12 IN+_B IN+_B 5 EN_A 6 11 EN_B IN-_B 6 V- 7 10 NC OUT_B 7 NC 8 9 NC NC 8 2 13 V12 IN+_C + - IN-_A 4 + - + OUT_A 3 + NC 1 11 IN-_C 10 OUT_C 9 NC FN6301.1 April 20, 2007 ISL28276, ISL28476 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V, 1V/μs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . . . .3kV ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . . .300V Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Operating Junction Electrical Specifications PARAMETER V+ = 5V, 0V, VCM = 0.1V, VO = 1.4V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C DESCRIPTION CONDITIONS MIN TYP MAX UNIT -100 -150 20 100 150 µV VOS Input Offset Voltage ΔV OS -----------------ΔTime Long Term Input Offset Voltage Stability 1.2 µV/Mo ΔV OS ---------------ΔT Input Offset Drift vs Temperature 0.3 µV/°C IOS Input Offset Current 0.25 1.3 2.0 nA IB Input Bias Current 0.5 2 2.5 nA eN Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 1 µVP-P Input Noise Voltage Density fO = 1kHz 25 nV/√Hz iN Input Noise Current Density fO = 1kHz 0.1 pA/√Hz CMIR Input Voltage Range Guaranteed by CMRR test 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 90 80 115 dB PSRR Power Supply Rejection Ratio V+ = 2.4V to 5V 90 80 115 dB AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ 350 350 550 V/mV VO = 0.5V to 4.5V, RL = 1kΩ 25 V/mV Output low, RL = 100kΩ 3 6 30 mV 130 175 225 mV VOUT Maximum Output Voltage Swing -2 -2.5 Output low, RL = 1kΩ 5 V Output high, RL = 100kΩ 4.990 4.97 4.996 V Output high, RL = 1kΩ 4.800 4.750 4.880 V SR+ Positive Slew Rate 0.13 0.10 0.17 0.20 0.25 V/µs SR- Negative Slew Rate 0.10 0.09 0.13 0.17 0.19 V/µs GBW Gain Bandwidth Product 3 400 kHz FN6301.1 April 20, 2007 ISL28276, ISL28476 Electrical Specifications PARAMETER V+ = 5V, 0V, VCM = 0.1V, VO = 1.4V, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C (Continued) DESCRIPTION CONDITIONS MIN ISL28276 all channels enabled. TYP MAX UNIT 120 156 175 µA 4 7 9 µA 240 312 350 µA 8 14 18 µA IS,ON Supply Current, Enabled IS,OFF Supply Current, Disabled IS,ON Supply Current, Enabled IS,OFF Supply Current, Disabled ISC+ Short Circuit Sourcing Capability RL = 10Ω 29 23 31 mA ISC- Short Circuit Sinking Capability RL = 10Ω 24 19 26 mA VS Minimum Supply Voltage VINH Enable Pin High Level VINL Enable Pin Low Level IENH Enable Pin Input Current VEN = 5V IENL Enable Pin Input Current VEN = 0V ISL28476 all channels enabled. 2.4 V 2 V 0.8 V -0.1 0.7 1.3 1.5 µA 0 +0.1 µA Typical Performance Curves 8 45 40 GAIN (dB) VS = ±1.25V 35 VS = ±1.0V 30 GAIN (dB) 4 0 AV = 1 -4 RL = 10kΩ CL = 2.7pF RF = 100Ω RG = OPEN -8 100 1k VS = ±2.5V 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE 4 25 VS = ±2.5V 20 AV = 100 15 RL = 10kΩ CL = 2.7pF 10 R /R = 99.02 F G RF = 221kΩ 5 RG = 2.23kΩ 0 100 1k VS = ±1.25V VS = ±1.0V 10k 100k 1M FREQUENCY (Hz) FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE FN6301.1 April 20, 2007 ISL28276, ISL28476 Typical Performance Curves (Continued) 0 VCM = VDD/2 150 AV = -1 INPUT OFFSET VOLTAGE (µV) 100 50 VDD = 5V 0 VDD = 2.5V -50 -100 -150 -200 -20 -40 -60 -80 -100 0 1 2 3 4 0 5 80 80 40 0 40 -40 0 -80 100 10k 1k 100k 3 4 5 1M 200 100 150 80 PHASE -80 -40 10 2 FIGURE 4. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE GAIN (dB) 120 PHASE (°) GAIN (dB) FIGURE 3. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE 1 1 COMMON-MODE INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 100 60 50 40 0 20 GAIN -50 0 -20 10 -120 10M -100 100 1k 10k 100k -150 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. AVOL vs FREQUENCY @ 100kΩ LOAD FIGURE 6. AVOL vs FREQUENCY @ 1kΩ LOAD 90 120 110 100 90 80 70 60 50 40 30 20 10 0 10 PSRR VS = 5VDC VSOURCE = 1VP-P RL = 100kΩ AV = +1 100 VS = 5VDC VSOURCE = 1VP-P RL = 100kΩ AV = +1 80 PSRR + CMRR (dB) PSRR (dB) VOS, µV PHASE (°) INPUT OFFSET VOLTAGE (µV) 200 70 60 50 40 1k 10k 100k FREQUENCY (Hz) FIGURE 7. PSRR vs FREQUENCY 5 1M 30 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 8. CMRR vs FREQUENCY FN6301.1 April 20, 2007 ISL28276, ISL28476 Typical Performance Curves (Continued) 2.56 VIN 2.54 VIN VS = 5VDC VOUT = 0.1VP-P RL = 500Ω AV = -2 2.52 VOUT 2.50 2.48 VS = 5VDC VOUT = 0.1VP-P RL = 500Ω AV = +1 2.46 2.44 VOUT 2.42 0 2 4 6 8 10 12 14 16 18 0 20 200 300 500 1k VOLTAGE NOISE (nV/√Hz) 10.00 1.00 0.10 100 10 1 10 0.01 1 10 100 1k 10k 100k 100 FREQUENCY (Hz) 1k 10k 100k FREQUENCY (Hz) FIGURE 12. VOLTAGE NOISE vs FREQUENCY FIGURE 11. CURRENT NOISE vs FREQUENCY 6 V+ = 5V VIN 5 VOLTS (V) VOLTAGE NOISE (200nV/DIV) 400 FIGURE 10. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 9. SMALL SIGNAL TRANSIENT RESPONSE CURRENT NOISE (pA/√Hz) 100 4 100K VS + 100K 3 DUT + 1K VS - VOUT Function Generator 33140A 2 1 1µVP-P 0 TIME (1s/DIV) FIGURE 13. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE 6 0 50 100 150 200 TIME (ms) FIGURE 14. INPUT VOLTAGE SWING ABOVE THE V+ SUPPLY FN6301.1 April 20, 2007 ISL28276, ISL28476 Typical Performance Curves (Continued) 155 1k IB+ 100 IOS 135 SUPPLY CURRENT (µA) INPUT BIAS, OFFSET CURRENTS (pA) 10k IB- 10 115 95 75 55 1 0 1 2 3 4 35 2.0 5 2.5 COMMON-MODE INPUT VOLTAGE (V) 5.0 5.5 n=6 140 CURRENT (µA) 110 CURRENT (µA) 4.5 150 n=7 100 90 80 130 120 110 100 -20 0 20 40 60 80 100 90 -40 120 -20 0 TEMPERATURE (°C) FIGURE 17. SUPPLY CURRENT vs TEMPERATURE VS = ±1.2V ENABLED. RL = INF 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 18. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V ENABLED. RL = INF 1400 1200 n=7 n=7 1200 CURRENT (pA) 1000 CURRENT (pA) 4.0 FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE 120 800 600 400 200 0 -40 3.5 SUPPLY VOLTAGE (V) FIGURE 15. INPUT BIAS + OFFSET CURRENTS vs COMMON-MODE INPUT VOLTAGE 70 -40 3.0 1000 800 600 400 200 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 19. IBIAS+ vs TEMPERATURE VS = ±2.5V 7 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 20. IBIAS+ vs TEMPERATURE VS = ±1.2V FN6301.1 April 20, 2007 ISL28276, ISL28476 Typical Performance Curves 1700 n=7 1200 1500 1000 1300 CURRENT (pA) CURRENT (pA) 1400 (Continued) 800 600 400 1100 900 700 200 0 -40 n=7 500 -20 0 20 40 60 80 100 300 -40 120 -20 0 TEMPERATURE (°C) FIGURE 21. IBIAS- vs TEMPERATURE VS = ±2.5V 1300 n=7 CURRENT (pA) CURRENT (pA) 800 600 400 200 n=7 900 700 500 300 100 -20 0 20 40 60 80 100 -100 -40 120 -20 0 TEMPERATURE (°C) FIGURE 23. INPUT OFFSET CURRENT vs TEMPERATURE VS = ±2.5V 200 n=5 100 120 n=6 150 100 VOS (µV) 100 VOS (µV) 20 40 60 80 TEMPERATURE (°C) FIGURE 24. INPUT OFFSET CURRENT vs TEMPERATURE VS = ±1.2V 150 50 0 -50 50 0 -50 -100 -100 -150 -40 120 1100 1000 200 100 FIGURE 22. IBIAS- vs TEMPERATURE VS = ±1.2V 1200 0 -40 20 40 60 80 TEMPERATURE (°C) -150 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 25. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±2.5V 8 -200 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = ±1.2V FN6301.1 April 20, 2007 ISL28276, ISL28476 Typical Performance Curves 130 (Continued) 114 n=7 n=6 112 PSRR (dB) CMRR (dB) 120 110 110 108 106 100 104 90 -40 -20 0 20 40 60 80 100 102 -40 120 -20 0 TEMPERATURE (°C) FIGURE 27. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V n=5 -2.32 2.39 -2.33 2.38 -2.34 VOUT (V) VOUT (V) 40 60 80 100 120 FIGURE 28. PSRR vs TEMPERATURE VS = ±1.2V TO ±2.5V 2.37 2.36 n=5 -2.35 -2.36 -2.37 -2.38 2.35 -2.39 2.34 -40 -20 0 20 40 60 80 100 120 -2.4 -40 TEMPERATURE (°C) 2.4992 0 20 40 60 80 100 120 FIGURE 30. NEGATIVE VOUT vs TEMPERATURE RL = 1k VS = ±2.5V -2.4956 n=7 2.499 -2.4958 2.4988 -2.496 2.4986 n=7 VOUT (V) -2.4962 2.4984 2.4982 2.498 -2.4964 -2.4966 2.4978 -2.4968 2.4976 -2.497 2.4974 -40 -20 TEMPERATURE (°C) FIGURE 29. POSITIVE VOUT vs TEMPERATURE RL = 1k VS = ±2.5V VOUT (V) OU 2.40 20 TEMPERATURE (°C) -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 31. POSITIVE VOUT vs TEMPERATURE RL = 100k VS = ±2.5V 9 -2.4972 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 32. NEGATIVE VOUT vs TEMPERATURE RL = 100k VS = ±2.5V FN6301.1 April 20, 2007 ISL28276, ISL28476 Typical Performance Curves 14 (Continued) 0.9 n=7 n=5 12 10 0.8 IIH (µA) IIL (nA) 8 6 4 0.7 2 0.6 0 -2 -4 -40 -20 0 20 40 60 80 100 0.5 -40 120 -20 0 TEMPERATURE (°C) FIGURE 33. IIL (EN) vs TEMPERATURE VS = ±2.5V 0.16 80 100 120 0.15 SLEW RATE (V/µs) 0.16 SLEW RATE (V/µs) 60 n=7 n=5 0.14 0.12 0.1 0.14 0.13 0.12 0.11 0.08 -40 -20 0 20 40 60 80 100 0.1 -40 120 -20 0 FIGURE 35. + SLEW RATE vs TEMPERATURE VS = ±2.5V INPUT = ±0.75V AV = 2 60 80 100 120 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1.2 1 POWER DISSIPATION (W) 1.4 893mW QS θ OP JA 16 =1 12 °C /W 0.6 40 FIGURE 36. - SLEW RATE vs TEMPERATURE VS = ±2.5V INPUT = ±0.75V AV = 2 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.8 20 TEMPERATURE (°C) TEMPERATURE (°C) POWER DISSIPATION (W) 40 FIGURE 34. IIH (EN) vs TEMPERATURE VS = ±2.5V 0.18 1 20 TEMPERATURE (°C) 0.4 0.2 0.8 633mW 0.6 θJ 0.4 QS O A =1 58 P1 °C 6 /W 0.2 0 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 10 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6301.1 April 20, 2007 ISL28276, ISL28476 Pin Descriptions ISL28276 (16 LD QSOP) ISL28476 (16 LD QSOP) PIN NAME EQUIVALENT CIRCUIT 3 1 OUT_A Circuit 3 Amplifier A output 4 2 IN-_A Circuit 1 Amplifier A inverting input 5 3 IN+_A Circuit 1 Amplifier A non-inverting input 15 4 V+ Circuit 4 Positive power supply 12 5 IN+_B Circuit 1 Amplifier B non-inverting input 13 6 IN-_B Circuit 1 Amplifier B inverting input 14 7 OUT_B Circuit 3 Amplifier B output 1, 2, 8, 9, 10, 16 8, 9 NC 10 OUT_C Circuit 3 Amplifier C output 11 IN-_C Circuit 1 Amplifier C inverting input 12 IN+_C Circuit 1 Amplifier B non-inverting input 7 DESCRIPTION No internal connection 13 V- Circuit 4 Negative power supply 14 IN+_D Circuit 1 Amplifier D non-inverting input 15 IN-_D Circuit 1 Amplifier D inverting input 16 OUT_D Circuit 3 Amplifier D output 6 EN_A Circuit 2 Amplifier A enable pin internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state. 11 EN_B Circuit 2 Amplifier B enable pin with internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state. V+ V+ IN- IN+ V+ LOGIC PIN V- VCIRCUIT 2 Applications Information Introduction The ISL28276 and ISL28476 are Dual and Quad channel CMOS rail-to-rail input, output (RRIO) micropower precision operational amplifier with an enable feature. The parts are designed to operate from single supply (2.4V to 5.0V) or dual supply (±1.2V to ±2.5V) while drawing only 120μA of supply current. The device has an input common mode range that extends 10% above the positive rail and up to 100mV below the negative supply rail. The output operation can swing within about 4mV of the supply rails with a 100kΩ load (reference Figures 29 through 32). This combination of low power and precision performance makes them suitable for solar and battery power applications. Rail-to-Rail Input The input common-mode voltage range of the ISL28276 and ISL28476 is from the negative supply to 10% greater than 11 CAPACITIVELY COUPLED ESD CLAMP OUT V- CIRCUIT 1 V+ VCIRCUIT 3 CIRCUIT 4 the positive supply without introducing additional offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. Many rail-to-rail input stages use two differential input pairs, a longtail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL28276 and ISL28476 achieve input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range gives us an undistorted behavior from typically 100mV below the FN6301.1 April 20, 2007 ISL28276, ISL28476 negative rail and 10% higher than the V+ rail (0.5V higher than V+ when V+ equals 5V). components can be mounted to the PC board using Teflon standoff insulators. Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They have additional back-to-back diodes across the input terminals. For applications where the input differential voltage is expected to exceed 0.5V, external series resistors must be used to ensure the input currents never exceed 5mA. Input Bias Current Compensation The input bias currents are decimated down to a typical of 500pA while maintaining an excellent bandwidth for a micropower operational amplifier. Inside the ISL28276 and ISL28476 is an input bias canceling circuit. The input stage transistors are still biased with an adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current. Rail-to-Rail Output A pair of complementary MOSFET devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The output with a 100kΩ load will swing to within 3mV of the supply rails. Enable/Disable Feature The ISL28276 offers an EN pin that disables the device when pulled up to at least 2.2V. In the disabled state (output in a high impedance state), the part consumes typically 4µA. By disabling the part, multiple ISL28276 parts can be connected together as a MUX. The outputs are tied together in parallel and a channel can be selected by the EN pin. The EN pin also has an internal pull down. If left open, the EN pin will pull to the negative rail and the device will be enabled by default. V+ HIGH IMPEDANCE INPUT IN FIGURE 39. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER Example Application Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. The ISL28276 (Figure 40) is used to convert the differential thermocouple voltage into single-ended signal with 10X gain. The ISL28276's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5V supply. R4 100kΩ R3 10kΩ R2 10kΩ K TYPE THERMOCOUPLE V+ + ISL28276 V- 410µV/°C + 5V R1 100kΩ FIGURE 40. THERMOCOUPLE AMPLIFIER Proper Layout Maximizes Performance To achieve the maximum performance of the high input impedance and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 39 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, 12 FN6301.1 April 20, 2007 ISL28276, ISL28476 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN6301.1 April 20, 2007