The following document contains information on Cypress products. FUJITSU MICROELECTRONICS DATA SHEET DS07-12526-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89920 Series MB89923/925/P928/PV920 ■ DESCRIPTION The MB89920 series is a line of single-chip microcontrollers using the F2MC*-8L CPU core which can operate at low voltage but at high speed. The microcontrollers in this series contain peripheral functions such as a PWM timer, an input capture/output compare control counter, an LCD controller/driver, an A/D converter, and a UART. The MB89920 series can suit a wide range of applications such as analog input conversion, pulse input measurement/pulse output control, serial communications control, and display control. *: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • High speed processing at low voltage Minimum execution time: 0.5 µs/8.0 MHz • F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • 8-bit PWM timer: 2 channels (also usable as a reload timer) • 16-bit input capture: 2 channels / 16-bit output compare: 2 channels (Continued) For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ Copyright©1999-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2008.10 MB89920 Series (Continued) • 20-bit time-base counter • UART: 1 channel (with asynchronous transfer mode and 8-bit synchronous serial mode) • 8-bit serial interface: 1 channel (LSB first/MSB first selectability) • 10-bit A/D converter: 8 channels • LCD controller/driver: 28 segments × 4 commons (max. 112 pixels) • Low-voltage detection reset • Watchdog timer reset • External interrupt: 4 channels Four channels are independent and capable of wake-up from the low-power consumption mode (with edge detection function) • Buzzer output/clock output • Low-power consumption modes: Stop mode (The software stops oscillation to minimize the current consumption.) Sleep mode (The CPU stops to reduce current consumption to approx. 1/3 of normal.) Hardware standby mode (The pin input stops oscillation.) 2 DS07-12526-2E MB89920 Series ■ PRODUCT LINEUP Part number Parameter Classification ROM size RAM size CPU functions Ports Options 20-bit time-base timer Real-time I/O LCD controller/ driver 8-bit PWM timer UART 8-bit serial I/O 10-bit A/D converter Watchdog timer Low-voltage detection reset Hardware standby Buzzer/clock output External interrupt Package Operating voltage EPROM for use MB89923 MB89925 MB89P928 MB89PV920 Mass production products Piggyback/evaluation One-time PROM product (for development) product (for development) (mask ROM products) 8 K × 8 bits 16 K × 8 bits 48 K × 8 bits 48 K × 8 bits (internal mask ROM) (internal mask ROM) (internal PROM) (external ROM) 256 × 8 bits 512 × 8 bits 1024 × 8 bits Number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum execution time: 0.5 µs/8 MHz Interrupt processing time: 4.5 µs/8 MHz I/O ports (CMOS): 35 (25 ports also serve as peripherals.) I/O ports (N-ch open-drain): 34 (All also serve as peripherals.) Total: 69 Set with EPROM programmer Specify with mask options None 20 bits (interval time selection: 4.10 ms, 16.38 ms, 65.54 ms, 262 ms/8 MHz) 16-bit timer: operating clock cycle (0.5 µs, 1.0 µs, 2.0 µs, 4.0 µs), overflow interrupt Input capture: 16 bits × 2 channels, external trigger edge selectability Output compare: 16 bits × 2 channels Common output: 4 (selectable from 2 to 4 by software) Segment output: 28 (can be switched to ports in 4-pin unit by software) Bias power supply pins: 3 LCD display RAM size: 14 × 8 bits Dividing resistor for LCD driving: bult-in (external resistor selectability) 8 bits × 2-channel reload timer operation 8 bits × 2-channel PWM operation (4 cycles selectable) 8 bits × 1-channel PPG operation (4 oscillation clocks selectable) Variable data length (7 or 8 bits), internal baud rate generator, error detection function, full-duplex with internal double buffer, NRZ transmission formation, Clock synchronous/asynchronous transfer capable 8 bits, LSB first/MSB first selectability, One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 1.0 µs, 4.0 µs, 16.0 µs) 10-bit resolution × 8 channels A/D conversion mode (conversion time: 16.5 µs (33 instruction cycles)) Sense mode (conversion time: 9.0 µs (18 instruction cycles)) Continuous activation by an internal clock capable Interval time: approx. 130 to 260 ms Reset activation voltage: 3.0 to 4.3 V Reset release voltage: 3.1 to 4.5 V Stop the clock oscillation by pin input 1 channel (output a frequency from 1 KHz, 2 KHz, 4 KHz, and divided clock frequency) 4 channels (rising edge/falling edge selectability) QFP-80 MQFP-80 2.2 to 6.0 V* 2.7 to 6.0 V* 2.7 to 6.0 V* MBM27C512-20TV ⎯ (LCC package) * : The minimum operating voltage varies with conditions such as the operating frequencies, functions, and development tool. DS07-12526-2E 3 MB89920 Series ■ PACKAGE AND CORRESPONDING PRODUCTS MB89923 MB89925 MB89P928 Package × FPT-80P-M06 MQP-80C-P01 : Available MB89PV920 × × : Not available Note: For more information about each package, see section “■ Package Dimensions”. ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • The stack area, etc., is set at the upper limit of the RAM. • The external area is used. 2. Current Consumption • In the case of the MB89PV920, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section “■ Electrical Characteristics”.) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options”. 4 DS07-12526-2E MB89920 Series ■ PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P71/SEG17 P70/SEG16 P67/SEG15 P66/SEG14 P65/SEG13 P64/SEG12 P63/SEG11 P62/SEG10 P61/SEG9 P60/SEG8 P57/SEG7 P56/SEG6 P55/SEG5 P54/SEG4 P53/SEG3 P52/SEG2 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Lead pitch: 0.80 mm) (Body size: 20 mm × 14 mm) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P51/SEG1 P50/SEG0 P40/COM0 P41/COM1 P42/COM2 P43/COM3 P44/V1 P45/V2 V3 VCC AVCC AVR AVSS P10/AN0 P11/AN1 P12/AN2 P13/AN3 P14/AN4 P15/AN5 P16/AN6 P17/AN7 P00/INT0 P01/INT1 P02/INT2 P32/UCK P31/UO P30/UI P27 P26 P25 P24 P23/RTI1 P22 P21 P20/RTI0 P07 P06 P05 P04 P03/INT3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P72/SEG18 P73/SEG19 P74/SEG20 P75/SEG21 P76/SEG22 P77/SEG23 P80/SEG24 P81/SEG25 P82/SEG26 P83/SEG27 P90/RTO0 P91/RTO1 P92/BUZ/CLK P93/PWM0 VSS MODA X1 X0 P94/PWM1 HST RST P95/SCK P96/SO P97/SI (FPT-80P-M06) (Only for mass production or one-time PROM products) DS07-12526-2E 5 MB89920 Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P71/SEG17 P70/SEG16 P67/SEG15 P66/SEG14 P65/SEG13 P64/SEG12 P63/SEG11 P62/SEG10 P61/SEG9 P60/SEG8 P57/SEG7 P56/SEG6 P55/SEG5 P54/SEG4 P53/SEG3 P52/SEG2 (Top view) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 100 99 98 97 96 95 94 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 93 92 91 90 89 88 87 86 85 110 111 112 81 82 83 84 101 102 103 104 105 106 107 108 109 P51/SEG1 P50/SEG0 P40/COM0 P41/COM1 P42/COM2 P43/COM3 P44/V1 P45/V2 V3 V CC AV CC AVR AVSS P10/AN0 P11/AN1 P12/AN2 P13/AN3 P14/AN4 P15/AN5 P16/AN6 P17/AN7 P00/INT0 P01/INT1 P02/INT2 P32/UCK P31/UO P30/UI P27 P26 P25 P24 P23/RTI1 P22 P21 P20/RTI0 P07 P06 P05 P04 P03/INT3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P72/SEG18 P73/SEG19 P74/SEG20 P75/SEG21 P76/SEG22 P77/SEG23 P80/SEG24 P81/SEG25 P82/SEG26 P83/SEG27 P90/RTO0 P91/RTO1 P92/BUZ/CLK P93/PWM0 VSS MODA X1 X0 P94/PWM1 HST RST P95/SCK P96/SO P97/SI (MQP-80C-P01) • Pin assignment on package top (only for piggyback/evaluation product) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 81 N.C. 89 A2 97 N.C. 105 OE/VPP 82 A15 90 A1 98 O4 106 N.C. 83 A12 91 A0 99 O5 107 A11 84 A7 92 N.C. 100 O6 108 A9 85 A6 93 O1 101 O7 109 A8 86 A5 94 O2 102 O8 110 A13 87 A4 95 O3 103 CE 111 A14 88 A3 96 VSS 104 A10 112 VCC N.C.: Internally connected. Do not use. (Only for piggyback/evaluation product) 6 DS07-12526-2E MB89920 Series ■ PIN DESCRIPTION Pin no. Pin name 17 X1 18 X0 16 Circuit type Function A Clock oscillator pins MODA B Operation mode selection input pin Connect this pin to VSS (GND). 20 HST B Hardware standby input pin 21 RST C Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 11, 12 P90/RTO0, P91/RTO1 D General-purpose I/O ports A pull-up resistor option is provided. Also serve as an output compare data output. 13 P92/BUZ/CLK D General-purpose I/O port Also serves as a buzzer/clock output. 14 P93/PWM0 D General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit PWM output. 19 P94/PWM1 D General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit PWM output. 22 P95/SCK E General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O (SCK) for the serial I/O. The SCK input is a hysteresis input. The output type can be switched between N-ch open-drain and CMOS. 23 P96/SO D General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output (SO) for the serial I/O. The output type can be switched between N-ch open-drain and CMOS. 24 P97/SI E General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input (SI) for the serial I/O. 25 P32/UCK E General-purpose I/O port A pull-up resistor option is provided. Also serves as a UART clock I/O (UCK). The UCK input is hysteresis input. The output type can be switched between N-ch open-drain and CMOS. 26 P31/UO D General-purpose I/O port A pull-up resistor option is provided. Also serves as a UART data output (UO). The output type can be switched between N-ch open-drain and CMOS. (Continued) DS07-12526-2E 7 MB89920 Series (Continued) Pin no. 27 Circuit type Function P30/UI E P27 to P24 D 32 P23/RTI1 E 33, 34 P22, P21 D 35 P20/RTI0 E General-purpose I/O port A pull-up resistor option is provided. Also serves as an input capture data input. 36 to 39 P07 to P04 D General-purpose I/O ports A pull-up resistor options is provided. 40 to 43 P03/INT3 to P00/INT0 E General-purpose I/O ports A pull-up resistor options is provided. Also serve as an external interrupt input (INT0 to INT3). 44 to 51 P17/AN7 to P10/AN0 G CMOS I/O ports Also serve as an A/D converter analog input. P45/V2, P44/V1 F LCD driving power supply pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD driving power supply. 59 to 62 P43/COM3 to P40/COM0 F LCD common output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD common output. 63 to 70 P50/SEG0 to P57/SEG7 F LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. 71 to 78 P60/SEG8 to P67/SEG15 F LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. 79, 80 P70/SEG16, P71/SEG17 F LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. 1 to 6 P72/SEG18 to P77/SEG23 F LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. 7 to 10 P80/SEG24 to P83/SEG27 F LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. 52 AVSS ⎯ A/D converter power supply (GND) pin 53 AVR ⎯ A/D converter reference power supply pin 54 AVCC ⎯ A/D converter power supply pin 55 VCC ⎯ Power supply pin 56 V3 ⎯ LCD driving power supply pin 15 VSS ⎯ Power supply (GND) pin 28 to 31 57, 58 8 Pin name General-purpose I/O port A pull-up resistor option is provided. Also serves as a UART data input (UI). General-purpose I/O ports A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. Also serves as an input capture data input. General-purpose I/O ports A pull-up resistor option is provided. DS07-12526-2E MB89920 Series • External EPROM pins (the MB89PV920 only) Pin no. Pin name I/O Function 82 83 84 85 86 87 88 89 90 91 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 93 94 95 O1 O2 O3 I Data input pins 96 VSS O Power supply (GND) pin 98 99 100 101 102 O4 O5 O6 O7 O8 I Data input pins 103 CE O ROM chip enable pin Outputs “H” during standby. 104 A10 O Address output pin 105 OE/VPP O ROM output enable pin Outputs “L” at all times. 107 108 109 A11 A9 A8 O Address output pins 110 A13 O Address output pin 111 A14 O Address output pin 112 VCC O EPROM power supply pin 81 92 97 106 N.C. — Internally connected pins Be sure to leave them open. DS07-12526-2E 9 MB89920 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks A • At an oscillation feedback resistor of approximately 1 MΩ (1 to 8 MHz) X1 X0 N-ch Standby control signal B • CMOS input C • At an output pull-up resistor of approximately 50 KΩ (5.0 V) • Hysteresis input R P-ch N-ch D • CMOS output • CMOS input • Pull-up resistor optional R P-ch P-ch N-ch E R P-ch P-ch • • • • CMOS output CMOS input Hysteresis input (peripheral input) Pull-up resistor optional N-ch (Continued) 10 DS07-12526-2E MB89920 Series (Continued) Type Circuit F N-ch Remarks • N-ch open-drain I/O • Also serves as LCD controller/driver common/ segment output. P-ch N-ch P-ch N-ch G P-ch • CMOS I/O • Analog input N-ch Analog input DS07-12526-2E 11 MB89920 Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D Converter Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 12 DS07-12526-2E MB89920 Series ■ PROGRAMMING TO THE EPROM ON THE MB89P928 The MB89P928 is an OTPROM version of the MB89920 series. 1. Features • 48-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C1001A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in the EPROM mode is diagrammed below. Address Normal operating mode EPROM mode (Corresponding addresses on the EPROM programmer) 0000H 0000H I/O 0080H 0100H 0200H Vacancy Register (Read value undefined) RAM 0480H 0FE4H Option area Not available 1000H Vacancy (Read value undefined) 4000H 4000H Program area (EPROM) ROM FFFFH FFFFH Vacancy (Read value undefined) 1FFFFH DS07-12526-2E 13 MB89920 Series 3.Programming to the PROM In EPROM mode, the MB89P928 functions equivalent to the MBM27C1001A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C1001A. (2) Load program data into the EPROM programmer at 0FE4H to FFFFH. (3) Program with the EPROM programmer. 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150 °C, 48 h Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 14 DS07-12526-2E MB89920 Series 6. PROM Option Bit Map Bit 7 Bit 6 Bit 5 Vacancy Vacancy Vacancy Readable Readable Readable P07 Pull-up 1: No 0: Yes P06 Pull-up 1: No 0: Yes P27 Pull-up 0FECH 1: No 0: Yes 0FF0H 0FF4H • Bit 2 Bit 1 Bit 0 Reset pin output Power-on reset Vacancy Vacancy 1: Yes 0: No 1: Yes 0: No Readable Readable P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes P26 Pull-up 1: No 0: Yes P25 Pull-up 1: No 0: Yes P24 Pull-up 1: No 0: Yes P23 Pull-up 1: No 0: Yes P22 Pull-up 1: No 0: Yes P21 Pull-up 1: No 0: Yes P20 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable Readable P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P97 Pull-up 1: No 0: Yes P96 Pull-up 1: No 0: Yes P95 Pull-up 1: No 0: Yes P94 Pull-up 1: No 0: Yes P93 Pull-up 1: No 0: Yes P92 Pull-up 1: No 0: Yes P91 Pull-up 1: No 0: Yes P90 Pull-up 1: No 0: Yes Vacancy Vacancy Low-voltage detection WDT/lowvoltage voltage control 1: Register 00: — 01: 3.3 V 0: Option 11: 4.0 V EPROM 10: 3.6 V Low-voltage Low-voltage Watchdog timer (WDT) detection reset 1: Yes 0: No 1: Automatic 0: Prohibited 1: Automatic 0: Prohibited 0FF8H Readable 0FFCH Bit 3 Oscillation stabilization time 1: Crystal 0: Ceramic 0FE4H 0FE8H Bit 4 Readable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable Readable Readable Readable Readable The initial value of each bit is “1”. Notes: • Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. • Write the same value as each option register to the 3-byte vacant address that follows above option registers. Example: In the case of 0FE4H, write the same value to 0FE5H, 0FE6H and 0FF7H. • This optional information is taken into the OTPROM while the oscillation is being reset. Therefore, if the hardware state is initially shifted to standby state after the power supply is turned on, the optional information will not be valid during the transition (in a state of the initial value 1). After the hardware standby state is cleared, the oscillation starts and the optional information becomes valid. Note that if the hardware is shifted to the standby or stop state in the course of a normal operation (oscillation), the contents of the optional register are valid since the option data has already been taken into the OTPROM. DS07-12526-2E 15 MB89920 Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C512-20TV 2. Memory Space Memory space in each mode is diagrammed below. Address Normal operating mode Corresponding addresses on the EPROM programmer 0000H 0000H I/O 0080H Not available RAM 0480H Not available 4000H 4000H PROM 48 KB FFFFH EPROM 48 KB FFFFH 3. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 4000H to FFFFH. (3) Program to 4000H to FFFFH with the EPROM programmer. 16 DS07-12526-2E MB89920 Series ■ BLOCK DIAGRAM X0 X1 Operating mode control Oscillator Clock control HST MODA Time-base timer Watchdog timer CMOS I/O port Reset circuit RST P91/RTO1 P90/RTO0 Output compare Low-voltage detection 16-bit free run counter RAM F2MC-8L Input capture P23/RTI1 P20/RTI0 UART P32/UCK P31/UO P30/UI Serial I/O P95/SCK P96/SO P97/SI CPU P80/SEG24 to P83/SEG27 P70/SEG16 to P77/SEG23 P60/SEG8 to P67/SEG15 P50/SEG0 to P57/SEG7 4 N-ch open-drain I/O port 8 8 28 8 LCD controller /driver V3 P44/V1, P45/V2 2 2 P40/COM0 to P43/COM3 4 4 Internal bus ROM 2-channel 8-bit PWM timer 8-bit timer #2 P94/PWM1 8-bit timer #1 P93/PWM0 AVR 10-bit A/D converter 8 8 P10/AN0 to P17/AN7 N-ch open-drain I/O port P21, P22 P24 to P27 P04 to P07 P00/INT0 to P03/INT3 DS07-12526-2E 6 4 4 CMOS I/O port Buzzer/clock output P92/BUZ/CLK CMOS I/O port 4 External interrupt CMOS I/O port 17 MB89920 Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89920 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89920 series is structured as illustrated below. Memory Space MB89925 MB89923 0000H 0080H 0100H 0000H I/O RAM 0080H 0100H Register MB89P928 0000H I/O RAM 0080H 0100H Register 0180H 0200H MB89PV920 0000H I/O RAM 0080H 0100H Register I/O RAM Register 0200H 0200H 0480H 0480H 0280H Not available Not available Not available Not available 4000H 4000H C000H Program ROM E000H Program ROM ROM ROM FFFFH 18 FFFFH FFFFH FFFFH DS07-12526-2E MB89920 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits FFFDH : Program counter PC A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register bit PS 15 14 13 12 10 9 8 Vacancy Vacancy Vacancy RP RP DS07-12526-2E 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR 19 MB89920 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 20 DS07-12526-2E MB89920 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89925. Up to a total of 16 banks can be used on the MB89923. The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area DS07-12526-2E 21 MB89920 Series ■ I/O MAP Address Read/write Register Register description 00H (R/W) PDR0 Port 0 data register XXXX XXXXB 01H (W) DDR0 Port 0 data direction register 0000 0000 02H (R/W) PDR1 Port 1 data register XXXX XXXXB 03H (W) DDR1 Port 1 data direction register 0000 0000 B B 04H Vacancy 05H Vacancy 06H Vacancy 07H Vacancy Intial value B 08H (R/W) STBC Standby control register 0001 XXXX 09H (R/W) WDTE Watchdog timer control register XXXX XXXXB 0AH (R/W) TBCR Time-base timer control register XXX0 0000 B 0BH (R/W) LVRC Low-voltage detection reset control register 0X11 X00X B 0CH (R/W) PDR3 Port 3 data/peripheral I/O control register 0000 –XXX B 0DH (W) DDR3 Port 3 data direction register –––– –000 B 0EH (R/W) PDR4 Port 4 data register ––11 1111 B 0FH (R/W) PDR5 Port 5 data register 1111 1111 B 10H (R/W) PDR6 Port 6 data register 1111 1111 B 11H (R/W) PDR7 Port 7 data register 1111 1111 B 12H (R/W) PDR8 Port 8 data register –––– 1111 B 13H (R/W) PDR9 Port 9 data register XXXX XXXXB 14H (W) DDR9 Port 9 data direction register 0000 0000 15H (R/W) PDR2 Port 2 data register XXXX XXXXB 16H (R/W) DDR2 Port 2 data direction register 0000 0000 B 17H (R/W) BUZR Buzzer control register XXXX 0000 B 18H (R/W) ADC1 AD converter control register 1 0000 0000 B 19H (R/W) ADC2 AD converter control register 2 X000 0001 B 1AH (R/W) ADCH AD converter data register “H” –––– ––XX B 1BH (R/W) ADCL AD converter data register “L” XXXX XXXXB 1CH (R/W) SMR Serial mode register 0000 0000 1DH (R/W) SDR Serial data register XXXX XXXXB 1EH 1FH B B Vacancy (W) –: Unused X: Undefined ICR1 Port 1 input control register 0000 0000 B (Continued) Note: Do not use vacancies 22 DS07-12526-2E MB89920 Series Address Read/write Register Register description 20H (R/W) CNTR1 PWM timer control register 1 0000 0000 B 21H (R/W) CNTR2 PWM timer control register 2 0000 0000 B 22H (R/W) CNTR3 PWM timer control register 3 000X 0000 B 23H (W) COMR2 PWM timer compare register 2 XXXX XXXXB 24H (W) COMR1 PWM timer compare register 1 XXXX XXXXB 25H Vacancy 26H Vacancy 27H Vacancy Initial value 28H (R/W) TMCR Timer control register 00XX 0000 B 29H (R) TCHR Timer count register (H) 0000 0000 B 2AH (R) TCLR Timer count register (L) 0000 0000 B 2BH (R/W) OPCR Output control register 0000 0000 B 2CH (R/W) CPR0H Output compare register 0 (H) 0000 0000 B 2DH (R/W) CPR0L Output compare register 0 (L) 0000 0000 B 2EH (R/W) CPR1H Output compare register 1 (H) 0000 0000 B 2FH (R/W) CPR1L Output compare register 1 (L) 0000 0000 B 30H (R/W) ICCR Input capture control register X000 X000 B 31H (R/W) ICIC Input capture interrupt control register X000 0X00 B 32H (R) ICR0H Input capture register 0 (H) XXXX XXXXB 33H (R) ICR0L Input capture register 0 (L) XXXX XXXXB 34H (R) ICR1H Input capture register 1 (H) XXXX XXXXB 35H (R) ICR1L Input capture register 1 (L) XXXX XXXXB 36H Vacancy 37H Vacancy 38H (R/W) EIC1 External interrupt control register 1 0000 0000 B 39H (R/W) EIC2 External interrupt control register 2 0000 0000 B 3AH Vacancy 3BH Vacancy 3CH Vacancy 3DH Vacancy 3EH Vacancy 3FH Vacancy –: Unused X: Undefined (Continued) Note: Do not use vacancies DS07-12526-2E 23 MB89920 Series (Continued) Address Read/write Register 40H (R/W) USMR UART mode register 0000 0000 B 41H (R/W) USCR UART control register 0000 0000 B 42H (R/W) USTR UART status register 0000 1XXX B 43H (R) (W) RXDR TXDR UART receiver data register UART transmitter data register XXXX XXXXB XXXX XXXXB 44H 45H Register description Initial value Vacancy (R/W) RRDR Baud rate generator/reload data register 46H Vacancy 47H Vacancy 48 to 5FH Vacancy XXXX XXXXB 60 to 6DH (R/W) VRAM Display data RAM XXXX XXXXB 70H (R/W) LCR1 LCD controller/driver control register 1 0000 0000 B 71H (R/W) LCR2 LCD controller/driver control register 2 000– –––– B 72H (R/W) LCR3 LCD controller/driver control register 3 0000 0000 B 73 to 7BH Vacancy 7CH (W) ILR1 Interrupt level setting register 1 1111 1111 B 7DH (W) ILR2 Interrupt level setting register 2 1111 1111 B 7EH (W) ILR3 Interrupt level setting register 3 1111 1111 B 7FH Vacancy –: Unused X: Undefined Note: Do not use vacancies 24 DS07-12526-2E MB89920 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC VSS – 0.3 VSS + 7.0 V *1 AVCC VSS – 0.3 VCC + 0.3 V *1 AVR VSS – 0.3 VSS + 7.0 V AVR must not exceed AVCC + 0.3 V. LCD power supply voltage V1 to V3 VSS – 0.3 VSS + 7.0 V V1 ≤ V2 ≤ V3 *2 Input voltage VI1 VSS – 0.3 VCC + 0.3 V VO1 VSS – 0.3 VCC + 0.3 V P00 to P07, P10 to P17, P20 to P27, P30 to P32, P90 to P97 VO2 VSS – 0.3 VSS + 7.0 V P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83 Must not exceed “V3 + 0.3 V” “L” level maximum output current IOL ⎯ 20 mA Peak value “L” level average output current IOLAV ⎯ 4 mA Average value “L” level total maximum output current ∑IOL ⎯ 100 mA Peak value “L” level total average output current ∑IOLAV ⎯ 40 mA Average value “H” level maximum output current IOH ⎯ –20 mA Peak value “H” level average output current IOHAV ⎯ –4 mA Average value “H” level total maximum output current ∑IOH ⎯ –50 mA Peak value “H” level total average output current ∑IOHAV ⎯ –20 mA Average value Power consumption PD ⎯ 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage Output voltage *1: Use AVCC and VCC set at the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. *2: VCC must not exceed V3. Unless LCD is used, the same setting must be executed. Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DS07-12526-2E 25 MB89920 Series 2. Recommended Operating Conditions (VSS = 0.0 V) Value Symbol Parameter Power supply voltage VCC Unit Remarks 6.0 V Normal operation assurance range 2.7*1 6.0 V MB89PV920/P928 1.5 6.0 V Retains the RAM state in stop mode Min. Max. 2.2*1 A/D converter reference input voltage AVR 3.0 AVCC V LCD power supply voltage V1 to V3 VSS VSS + 6.0 V Operating temperature TA –40 +85 °C V1 ≤ V2 ≤ V3*2 *1: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics”. *2: VCC must not exceed V3. Figure 1 Operating Voltage vs. Clock Operating Frequency 6 Analog accuracy assured in the AVCC = 3.5 V to 6.0 V range 5 Operating voltage (V) Operation assurance range 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Clock operating frequency (at an instruction cycle of 4/FC) (MHz) 4.0 2.0 0.8 0.5 Minimum execution time (instruction cycle) (µs) Note: The shaded area is assured only for the MB89923/925. Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 26 DS07-12526-2E MB89920 Series 3. DC Characteristics (VCC = 5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Condition VIH P00 to P07, P10 to P17, P20 to P27, P30 to P32, P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83, P90 to P97 Value Unit Remarks Min. Typ. Max. — 0.7 VCC — VCC + 0.3 V VIHS RST, MODA, HST P00 to P03, P20, P23, P30, P32, P95, P97 — 0.8 VCC — VCC + 0.3 V VIL P00 to P07, P10 to P17, P20 to P27, P30 to P32, P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83, P90 to P97 — VSS − 0.3 — 0.3 VCC V VILS RST, MODA, HST P00 to P03, P20, P23, P30, P32, P95, P97 — VSS − 0.3 — 0.2 VCC V VD P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83*1 — VSS − 0.3 — VSS + 6.0 V VOH1 P00 to P07, P10 to P17, P30 to P32, P90 to P97 IOH = –2.0 mA 4.0 — — V VOH2 P20 to P27 IOH = –5.0 mA 2.4 — — V VOL1 P00 to P07, P10 to P17, P30 to P32, P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83, P90 to P97 IOL = 4.0 mA — — 0.4 V VOL2 P20 to P27 IOL = 5.0 mA — — 0.4 V VOL3 RST IOL = 4.0 mA — — 0.4 V Input leakage current (Hi-Z output leakage current) ILI1 P00 to P07, P10 to P17, P20 to P27, P30 to P32, P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83, P90 to P97, MODA 0.45 V < VI < VCC — — ±5 µA Without pullup resistor Pull-up resistance RPULU P00 to P07, P20 to P27, P30 to P32, P90 to P97 VI = 0.0 V 25 50 100 kΩ With pull-up resistor “H” level input voltage “L” level input voltage Open-drain output pin application voltage “H” level output voltage “L” level output voltage Peripheral input of the port 0, 2, 3, and 9 Peripheral input of the port 0, 2, 3, and 9 (Continued) DS07-12526-2E 27 MB89920 Series (Continued) (VCC = 5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Unit Max. VCC = 5.0 V — 12 20 mA tinst = 0.5 µs VCC = 5.0 V — 3 7 mA Sleep mode tinst = 0.5 µs ICCH TA = +25°C — — 1 µA Stop mode IA when A/D conversion is activated — 6 8 mA when A/D conversion is stopped TA = +25°C — — 1 µA 200 300 450 kΩ VCC AVCC IAH RLCD Between V3 and VSS COM0 to 3 output RVCOM impedance COM0 to COM3 V1 to V3 = 5.0 V — — 2.5 kΩ SEG0 to 27 output impedance RVSEG SEG0 to SEG27 V1 to V3 = 5.0 V — — 15 kΩ ILCDL V1 to V3, COM0 to COM3, SEG0 to SEG27 V1 to V3 = 5.0 V — — ±1 µA Other than AVCC, AVSS, VCC, and VSS f = 1 MHz — 10 — pF LCD controller/ driver leakage current Remarks Typ. ICCS LCD divided resistance Value Min. ICC Power supply current*2 Condition Input capacitance CIN *1: VD must not exceed V3. *2: The measurement conditions of power supply current are as follows: the external clock and TA = +25°C. In the case of the MB89PV920, the current consumed by the connected EPROM and ICE is not included. Note: For pins which serve as the LCD and ports (P40 to P45, P50 to P57, P60 to P67, P70 to P77, and P80 to P83), see the port parameter when these pins are used as ports and the LCD parameter when they are used as LCD pins. 28 DS07-12526-2E MB89920 Series 5. AC Characteristics (1) Reset Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width Value Condition tZLZH — Min. Max. 48 txCYL — Unit Remarks ns tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition — Value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC DS07-12526-2E 0.2 V 0.2 V 0.2 V 29 MB89920 Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Pin Value Condition Min. Max. Unit Remarks Clock frequency FC X0, X1 1 8 MHz Clock cycle time tXCYL X0, X1 125 1000 ns Input clock pulse width PWH PWL X0 20 — ns External clock Input clock rising/falling time tCR tCF X0 — 10 ns External clock — X0 and X1 Timing and Conditions tXCYL PWH PWL tCF tCR 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Clock Conditions When a crystal or ceramic resonator is used X0 When an external clock is used X1 X0 FC C1 X1 Open C2 (4) Instruction Cycle Parameter Symbol Instruction cycle tinst (minimum execution time) 30 Value (typical) Unit 4/FC µs Remarks (4/FC) tinst = 0.5 µs when operating at FC = 8 MHz DS07-12526-2E MB89920 Series (5) Serial I/O Timing (AVCC = VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Condition Serial clock cycle time tSCYC SCK SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK SCK ↑ → valid SI hold time tSHIX SCK, SI Serial clock “H” pulse width tSHSL SCK Serial clock “L” pulse width tSLSH SCK Internal shift clock mode External shift clock mode Value Unit Min. Max. 2 tinst* — µs –200 200 ns 1/2 tinst* — µs 1/2 tinst* — µs 1 tinst* — µs 1 tinst* — µs 0 200 ns SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK 1/2 tinst* — µs SCK ↑ → valid SI hold time tSHIX SCK, SI 1/2 tinst* — µs Remarks * : For information on tinst, see “(4) Instruction Cycle”. Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SO 0.8 V tIVSH tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC SI External Shift Clock Mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SO 0.8 V tIVSH tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC SI DS07-12526-2E 31 MB89920 Series (6) Peripheral Input Timing (VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Symbol Parameter Value Pin Min. Max. Unit Peripheral input “H” pulse width 1 tILIH1 INT0 to INT3, RTI0, RTI1 2 tinst* — — Peripheral input “L” pulse width 1 tIHIL1 INT0 to INT3, RTI0, RTI1 2 tinst* — — Remarks * : For information on tinst, see “(4) Instruction Cycle”. tIHIL1 RTI0, RTI1 INT0 to INT3 0.8 VCC 0.2 VCC 32 tILIH1 0.8 V CC 0.2 VCC DS07-12526-2E MB89920 Series (7) A/D Converter Electrical Characteristics (AVCC = VCC = +3.5 V to +6.0 V, FC = 8 MHZ, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Condition Resolution Linearity error — Differential linearity error — Differential total error Zero transition voltage VOT AN0 to AN7 Full-scale transition voltage AN0 to AN7 VFST AVCC = AVR = VCC Interchannel disparity — A/D mode conversion time Analog port input current VAIN Analog input voltage — Reference voltage Reference voltage supply current DS07-12526-2E IR — AN0 to AN7 Source oscillation at 8 MHz Value Unit Min. Typ. Max. — — 10 bit — — ±2.0 LSB — — ±1.5 LSB — — ±3.0 LSB AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB V AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB V — — 4 LSB — — 16.5 µs — — 10 µA AN0 to AN7 — 0.0 — AVR V AVR — 0.0 — AVCC V — 200 ⎯ µA AVR AVR = 5.0 V 33 MB89920 Series 6. A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter. • Linearity error The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics • Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error The difference between theoretical and actual conversion values, caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise. Theoreticall I/O characteristics Total error VFST 3FF 3FF 3FE 3FE 3FD 1.5 LSB Digital output Digital output 3FD 004 003 Actual conversion value {1 LSB × N + 0.5 LSB} 004 VNT 003 VOT 002 Actual conversion value 002 1 LSB Theoretical value 001 001 0.5 LSB AVSS AVR Analog input 1 LSB = VFST − VOT 1022 AVSS AVR Analog input (V) Total error of digital output N = VNT − {1 LSB × N + 0.5 LSB} 1 LSB (Continued) 34 DS07-12526-2E MB89920 Series (Continued) Zero transition error Full-scale transition error 004 Theoretical value Actual conversion value 3FF Actual conversion value Digital output Digital output 003 002 Theoretical value 3FE VFST (Actual measured value) 3FD Actual conversion value Actual conversion value 001 3FC VOT (Actual measured value) AVSS 3FF AVR Analog input Linearity error Differential linearity error Theoretical value Actual conversion value 3FE N+1 {1 LSB × N + VOT} Actual conversion value VNT 004 003 VFST (Actual measured value) V(N + 1)T N N -1 Actual conversion value 002 Digital output 3FD Digital output AVSS AVR Analog input VNT Actual conversion value Theoretical value N-2 001 VOT (Actual measured value) AVSS AVR Analog input Linearity error of digital output N = AVR Analog input VNT - {1 LSB × N + VOT} 1 LSB DS07-12526-2E AVSS Differential linearity error of digital output N = V(N+1)T - VNT 1 LSB -1 35 MB89920 Series 7. Notes on A/D Converter • The smaller | AVR – AVSS |, the greater the error would become relatively. • The output impedance of the external circuit for the analog input must satisfy the following conditions: Output impedance of the external circuit < Approx. 10 kΩ If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 7.5 µs at 8 MHz oscillation). An analog input equivalent circuit is shown below. Sample & hold circuit R ≤ 10 kΩ is recommended. . C =. 60 pF AN . R =. 3 kΩ Comparator ( * ) Analog channel selector *: If R > 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. Close for approx. 15 instruction cycles after activating A/D conversion. Microcontroller’s internal circuit Since the A/D converter contains sample & hold circuit, the level of the analog input pin might not stabilize within the sampling period after A/D activation, resulting in inaccurate A/D conversion values, if the input impedance to the analog pin is too high. Be sure to maintain an appropriate input impedance to the analog pin. It is recommended to keep the input impedance to the analog pin not exceed 10 kΩ. If it exceeds 10 kΩ, it is recommended to connect a capacitor of approx. 0.1 µF for the analog input pin. Except for the sampling period after A/D activation, the input leakage current of the analog input pin is less than 10 µA. 36 DS07-12526-2E MB89920 Series 8. Low-voltage Detection Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Value Condition Unit Min. Max. VDL1 3.00 3.60 V VDL2 3.30 3.90 V VDL3 3.70 4.30 V VDH1 3.10 3.80 V VDH2 3.40 4.10 V VDH3 3.80 4.50 V Hysteresis width ∆V 0.10 — V Reset ignore time tL 0.3 — µs Reset sense time tLW 16 tXCYL — ns Reset detection deley time tD — 2.0 µs Voltage regulation (V∆/t∆) VCR — 0.10 V/µs Voltage detected at power supply voltage drop Voltage detected at power supply voltage rise Remarks *1 *1: VDH and VDL can be set for the MB89923 and MB89925 by mask options; for the MB89PV920 and MB89P928 by registers. Power supply voltage VCC VDH* VDL* tD tOSC tOSC tD RUN RESET tOSC oscillation stabilization time 218/FCH = 32.8 ms or 214/FCH = 2.05 ms (f = 8 MHz) (due to option setting) Power supply voltage VCC less than tL over than tLW VDH* VDL* time RUN RESET DS07-12526-2E Not reset Reset time 37 MB89920 Series ■ MASK OPTIONS Part number MB89923 MB89925 MB89P928 MB89PV920 Specifying procedure Specify when ordering masking Set with EPROM programmer Setting not possible P00 to P07, P20 to P27, P00 to P07, P20 to P27, P30 to P32, P90 to P97 P30 to P32, P90 to P97 : Selectable by pin : Can be set per pin Selectable Can be set With power-on reset Selectable Can be set Crystal oscillator (32.8 ms/8 MHZ) No. 1 2 Pull-up resistors P00 to P07, P20 to P27, P30 to P32, P90 to P97 Power-on reset Power-on reset provided No power-on reset No pull-up resistor Oscillation stabilization time slection (at 8 MHZ) 3 38 Cystal oscillator (32.8 ms/8MHZ) Ceramic oscillator (2.05 ms/8 MHZ) 4 Reset pin output Reset output provided No reset output Selectable Can be set With reset output 5 Watchdog timer Activation prohibited Automatic activation Selectable Can be set Inactive by default (Can be activated by software) 6 Low-voltage detection reset circuit Activation prohibited Automatic activation Selectable Can be set Inactive by default (Can be activated by software) 7 Low-voltage detection reset output Output disabled Output enabled Selectable Can be set Inactive by default (Can be activated by software) 8 Low-voltage detection voltage 3.3 V ± 0.3 V 3.6 V ± 0.3 V 4.0 V ± 0.3 V Selectable Can be set Register setting 9 Low-voltage detection reset/watchdog timer function selection Register setting valid Option setting valid Selectable Can be set Fixed to register setting DS07-12526-2E MB89920 Series ■ ORDERING INFORMATION Part number MB89923PF MB89925PF MB89P928PF MB89PV920CF DS07-12526-2E Package Remarks 80-pin Plastic QFP (FPT-80P-M06) 80-pin Ceramic MQFP (MQP-80C-P01) 39 MB89920 Series ■ PACKAGE DIMENSIONS 80-pin plastic QFP Lead pitch 0.80 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP80-14×20-0.80 (FPT-80P-M06) 80-pin plastic QFP (FPT-80P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 64 41 40 65 0.10(.004) 17.90±0.40 (.705±.016) * 14.00±0.20 (.551±.008) INDEX Details of "A" part 25 80 0.25(.010) +0.30 3.05 –0.20 +.012 .120 –.008 (Mounting height) 1 24 0.80(.031) 0.37±0.05 (.015±.002) 0.16(.006) 0~8° M 0.17±0.06 (.007±.002) "A" C 2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) +0.10 0.30 –0.25 +.004 .012 –.010 (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 40 DS07-12526-2E MB89920 Series (Continued) 80-pin ceramic MQFP Lead pitch 0.8 mm Lead shape Straight Motherboard material Ceramic Mounted package material Plastic (MQP-80C-P01) 80-pin ceramic MQFP (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP +0.40 1.20 –0.20 +.016 .047 –.008 1.27±0.13 (.050±.005) INDEX AREA 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010) 1.00(.040)TYP 4.50(.177) TYP 0.30(.012) TYP 18.40(.724) REF INDEX 1.27±0.13 (.050±.005) 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 0.15±0.05 8.70(.343) (.006±.002) MAX C 1994-2008 FUJITSU MICROELECTRONICS LIMITED M80001SC-4-3 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ DS07-12526-2E 41 MB89920 Series ■ MAIN CHANGES IN THIS EDITION Page 5, 6 Section PIN ASSIGNMENT Change Results Changed the pin name of pin 13. P92/CLK → P92/BUZ/CLK Changed the pin name of pin 86 to pin 91. AD7 to AD0 → A7 to A0 6 PIN DESCRIPTION Changed a pin no.. 7 to 11 → 7 to 10 14 ■ PROGRAMMING TO THE EPROM ON THE MB89P928 Deleted the “6. EPROM Programmer Socket Adapter”. 16 ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE Deleted the “2. Programming Socket Adapter”. 17 ■ BLOCK DIAGRAM Changed a pin name in bottom right corner. 29 ■ ELECTRICAL CHARACTERISTICS 4. AC. Characteristics (1) Reset Timing Changed the Value Min. 48 tHCYL → 48 tXCYL 33 ■ ELECTRICAL CHARACTERISTICS 5. A/D Converter Electrical Characteristics Changed the unit of “Zero transition voltage” and “Full-scale transition voltage” mV → V ⎯ ■ INSTRUCTIONS (136 INSTRUCTIONS) Deleted the “INSTRUCTIONS (136 INSTRUCTIONS)” ⎯ ■ INSTRUCTION MAP Deleted the “INSTRUCTION MAP” 8 The vertical lines marked in the left side of the page show the changes. 42 DS07-12526-2E MB89920 Series MEMO DS07-12526-2E 43 MB89920 Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. 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