FUJITSU SEMICONDUCTOR DATA SHEET DS07-12519-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89660 Series MB89663/665/P665/W665 ■ DESCRIPTION The MB89660 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as timers, a UART, a serial interface, an 8-bit A/D converter, an input capture, an output compare, and an external interrupt. The MB89660 series is applicable to a wide range of applications from welfare products to industrial equipment. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • Package expansion QFP package SDIP package (Continued) ■ PACKAGE 64-pin Plastic SH-DIP (DIP-64P-M01) 64-pin Plastic QFP (FPT-64P-M06) 64-pin Ceramic SH-DIP (DIP-64C-A06) MB89660 Series (Continued) • F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • Three types of timers 8-bit PWM timer 8/16-bit timer/counter 20-bit time-base timer • Functions that permit communications with a variety of devices UART which permits selection of synchronous/asynchronous communications A serial interface that permits selection of the transfer direction • 8-bit A/D converter: 8 channels Sense mode function capable of performing compare operation in 5 µs Activation by external input possible • Real-time control Input capture: 2 channels Output compare: 2 channels • External interrupt: 4 channels Two channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). • Low power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) Hardware standby mode (Wake-up from this mode and activation by pin input only.) 2 MB89660 Series ■ PRODUCT LINEUP Part number Parameter Classification MB89663 MB89665 Mass production products (mask ROM products) ROM size 8 K × 8 bits (internal mask ROM) RAM size 256 × 8 bits MB89W665 MB89P665 EPROM product One-time PROM product, also used for evaluation 16 K × 8 bits 16 K × 8 bits (internal mask ROM) (internal PROM, programming with general-purpose EPROM programmer) 16 K × 8 bits (internal PROM, programming with general-purpose EPROM programmer) 512 × 8 bits CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1,8, 16 bits 0.4 µs/10 MHz 3.6 µs/10 MHz Ports Output ports (CMOS): Output ports (N-ch open-drain): I/O ports (CMOS): Total: 8 8 (All also serve as peripherals.) 36 (19 ports also serve as peripherals.) 52 8-bit PWM timer 8/16-bit timer/ counter UART 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs, 6.4 µs, 25.6 µs) 8-bit resolution PWM operation (conversion cycle: 102 µs, 1.6 ms, 6.6 ms) Independent 8-bit reload timer/counter operation: 2 channels Single 16-bit event counter (cascade connection): 1 channel One clock selectable from four transfer clocks (one external shift clock, three internal clocks: 0.8 µs, 3.2 µs, 12.8 µs) 8 bits Full-duplex double buffer Synchronous and asynchronous data transfer 8-bit serial I/O 8 bits LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs) 8-bit A/D converter 8-bit resolution × 8 channels A/D conversion mode (conversion time: 18 µs at 10 MHz) Sense mode (conversion time: 5 µs at 10 MHz) Continuous activation by an external activation or an internal timer capable Reference voltage input Real-time I/O 16-bit timer: operating clock cycle (0.4 µs, 0.8 µs, 1.6 µs, 3.2 µs) overflow interrupt Input capture: 16 bits × 2 channels (External trigger edge selectability) Output compare: 16 bits × 2 channels (Continued) 3 MB89660 Series (Continued) Part number Parameter MB89665 MB89663 External interrupt MB89W665 MB89P665 4 channels (edge selection, interrupt vector, source flag) Rising edge/falling edge/both edges selectability Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) (Wake-up from hardware standby mode is not possible) Standby mode Sleep mode, stop mode, and hardware standby mode Process CMOS Operating voltage* 2.2 V to 6.0 V 2.7 V to 6.0 V * : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB89663 MB89665 MB89P665 × DIP-64P-M01 × DIP-64C-A06 × FPT-64P-M06 : Available MB89W665 × : Not available Note: For more information about each package, see section “■ Package Dimensions.” 4 MB89660 Series ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTPROM (one-time PROM) product (also used for evaluation), verify its differences from the product that will actually be used: Take particular care on the following points: • On the MB89663, register bank from 16 to 32 cannot be used. • On the MB89P665, address BFF0H to BFF6H comprise the option setting area, option settings can be read by reading these addresses. • The stack area, etc., is used. 2. Current Consumption • When operated at low speed, the product with an OTPROM or an EPROM will consume more current than the product with a mask ROM. • However, the current comsumption in sleep/stop modes is the same. (For more information, see sections “■ Electrical Characteristics” and “■ Example Characteristics.” 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following points: • On the MB89P665, a pull-up resistor must be selected in a group of four pins for P54 to P57. • For all products, P50 to P57 must be set to without a pull-up resistor when an A/D converter is used. 5 MB89660 Series ■ PIN ASSIGNMENT (Top view) P36/RTO1 P37/ADST P40/SCK1 P41/SO1 P42/SI1 P43/SCK2 P44/SO2 P45/SI2 P46/PTO P47 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 HST RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC P35/RTO0 P34/RTI1 P33/RTI0 P32/TO2 P31/TO1 P30/EC VSS P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 (DIP-64P-M01) (DIP-64C-A06) P45/SI2 P46/PTO P47 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 P61/INT1 P62/INT2 P63/INT3 RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 HST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 P44/SO2 P43/SCK2 P42/SI1 P41/SO1 P40/SCK1 P37/ADST P36/RTO1 VCC P35/RTO0 P34/RTI1 P33/RTI0 P32/TO2 P31/TO1 (Top view) (FPT-64P-M06) 6 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/EC VSS P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 MB89660 Series ■ PIN DESCRIPTION Pin no. DIP *1 *2 QFP Pin name 30 23 X0 31 24 X1 28 21 MOD0 29 22 MOD1 27 20 26 19 56 to 49 Circuit type Function A Crystal oscillator pins B Operating mode selection pins Connect directly to VCC or VSS. A pull-down resistor is selectable as an option for mask ROM products. RST C Reset I/O pin This port is an N-ch open-drain output type with pull-up resistor and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. HST G Hardware standby input pin Connect directly to VCC when hardware standby is not used. 49 to 42 P00 to P07 D General-purpose I/O ports 48 to 41 41 to 34 P10 to P17 40 to 33 33 to 26 P20 to P27 F General-purpose output ports 58 51 P30/EC E General-purpose I/O port Also serves as an external clock input for an 8/16-bit timer/counter. This pin is a hysteresis input type and with a noise canceller. 59 52 P31/TO1 E General-purpose high-current I/O port Also serves as an 8/16-bit timer/counter output. This pin is a hysteresis input type and with a noise canceller. 60 53 P32/TO2 E General-purpose I/O port Also serves as an 8/16-bit timer/counter output. This pin is a hysteresis input type and with a noise canceller. 61 54 P33/RTI0 E 62 55 P34/RTI1 General-purpose I/O ports Also serve as the data input for the input capture. This pin is a hysteresis input type and with a noise canceller. 63 56 P35/RTO0 E 1 58 P36/RTO1 General-purpose I/O ports Also serve as the data output for the output compare. This pin is a hysteresis input type and with a noise canceller. 2 59 P37/ADST E General-purpose heavy-current I/O port Also serves as the external activation input for the A/D converter. This pin is a hysteresis input type and with a noise canceller. *1: DIP-64P-M01, DIP-64C-A06 *2: FPT-64P-M06 (Continued) 7 MB89660 Series (Continued) Pin no. Pin name Function QFP*2 3 60 P40/SCK1 E General-purpose I/O port Also serves as the clock I/O for the UART. This pin is a hysteresis input type and with a noise canceller. 4 61 P41/SO1 E General-purpose I/O port Also serves as the data output for the UART. This pin is a hysteresis input type and with a noise canceller. 5 62 P42/SI1 E General-purpose I/O port Also serves as the data input for the UART. This pin is a hysteresis input type and with a noise canceller. 6 63 P43/SCK2 E General-purpose I/O port Also serves as the clock I/O for the 8-bit serial I/O interface. This pin is a hysteresis input type and with a noise canceller. 7 64 P44/SO2 E General-purpose I/O port Also serves as the data output for the 8-bit serial I/O interface. This pin is a hysteresis input type and with a noise canceller. 8 1 P45/SI2 E General-purpose I/O port Also serves as the data input for the 8-bit serial I/O interface. This pin is a hysteresis input type and with a noise canceller. 9 2 P46/PTO E General-purpose I/O port Also serves as a toggle output for an 8-bit PWM timer. This pin is a hysteresis input type and with a noise canceller. 10 3 P47 E General-purpose I/O port This pin is a hysteresis input type and with a noise canceller. 11 to 18 4 to 11 P50/AN0 to P57/AN7 H N-ch open-drain output-only ports Also serve as the analog input for the A/D converter. 22 to 25 15 to 18 P60/INT0 to P63/INT3 E General-purpose I/O ports These pins also serve as an external interrupt input. These pins are a hysteresis input type and with a noise canceller. 64 57 VCC — Power supply pin 32 57 25 50 VSS — Power supply (GND) pins 19 12 AVCC — A/D converter power supply pin 20 13 AVR — A/D converter reference voltage input pin 21 14 AVSS — A/D converter power supply pin Use this pin at the same voltage as VSS. *1: DIP-64P-M01, DIP-64C-A06 *2: FPT-64P-M06 8 Circuit type DIP*1 MB89660 Series ■ I/O CIRCUIT TYPE Type A Circuit Remarks • External clock input selection versions of crystal or ceramic oscillation type • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V X1 X0 Standby control signal B • CMOS input • Built-in pull-down resistor (mask ROM products only) C R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input N-ch D • CMOS output • CMOS input • Pull-up resistor optional R P-ch P-ch N-ch E • CMOS output • Hysteresis input • Pull-up resistor optional R P-ch P-ch N-ch F • CMOS output P-ch N-ch (Continued) 9 MB89660 Series (Continued) Type Circuit Remarks G • Hysteresis input H • N-ch open-drain output • Analog input • Pull-up resistor optional R P-ch P-ch N-ch Analog input 10 MB89660 Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- or high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “ ■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D Converters Connect to be AVCC = VCC and AVSS = AVR = VSS if the A/D converters are not in use. 4. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency(50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 5. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 11 MB89660 Series ■ PROGRAMMING TO THE EPROM ON THE MB89P665 The MB89P665 is an OTPROM version of the MB89660 series. 1. Features • 16-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 16-Kbyte PROM, option area is diagrammed below. Address Single chip 0000H EPROM mode (Corresponding addresses on the EPROM programmer) I/O 0080H RAM 0280H Not available 0000H Vacancy (Read value FFH) 3FF0H BFF0H Option area Not available BFF7H 3FF7H Vacancy (Read value FFH) Not availble C000H FFFFH 12 4000H PROM EPROM 16 KB 16 KB 7FFFH MB89660 Series 3. Programming to the PROM In EPROM mode, the MB89P665A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode). Load option data into addresses 3FF0H to 3FF6H of the EPROM programmer. (For information about each corresponding option, see “8. Setting OTPROM Options.”) (3) Program with the EPROM programmer. 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 13 MB89660 Series 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. Erasure Procedure In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity of 12000 µW/cm2 for 15 to 21 minuites. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance. 7. EPROM Programmer Socket Adapter Package Compatible socket adapter FPT-64P-M06 ROM-64QF-28DP-8L DIP-64P-M01 ROM-64SD-28DP-8L Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Connect the adapter jumper pin to VSS when using. 14 MB89660 Series 8. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map Bit 7 Vacancy 3FF0H Bit 6 Vacancy Bit 5 Bit 4 Vacancy Oscillation Readable and Readable and Readable and stabilization time writable writable writable 1: Crystal 0: Ceramic Bit 3 Bit 2 Reset pin output Power-on reset 1: Yes 0: No 1: Yes 0: No Bit 1 Vacancy Bit 0 Vacancy Readable and Readable and writable writable 3FF1H P07 Pull-up 1: No 1: Yes P06 Pull-up 1: No 1: Yes P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes 3FF2H P17 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes 3FF3H P37 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes 3FF4H P47 Pull-up 1: No 0: Yes P46 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes P53 Pull-up 1: No 0: Yes P52 Pull-up 1: No 0: Yes P51 Pull-up 1: No 0: Yes P50 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes 3FF5H P57 to P54 Pull-up Readable and Readable and Readable and 1: No writable writable writable 0: Yes Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy 3FF6H Readable and Readable and Readable and Readable and writable writable writable writable Note: • Set each bit to erase. • Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. 15 MB89660 Series ■ BLOCK DIAGRAM 21-bit time-base timer Clock controller 8-bit PWM timer Reset circuit (WDT) 8-bit serial I/O Hardware standby 8 P00 to P07 8 P10 to P17 Port 0 and port 1 HST P47 P46/PTO P45/SI2 P44/SO2 P43/SCK2 Port 4 RST Oscillator Internal bus X0 X1 P42/SI1 UART P41/SO1 P40/SCK1 CMOS I/O port CMOS I/O port CMOS I/O port P37/ADST P36/RTO1 P35/RTO0 Port 3 8 P20 to P27 Port 2 Output compare 16-bit timer CMOS output port P34/RTI1 P33/RTI0 Input capture Real-time I/O P32/TO2 8/16-bit timer/counter P31/TO1 P30/EC RAM 8 8-bit A/D converter Port 5 N-ch open-drain output port F2MC-8L CPU 8 ROM 4 16 CMOS I/O port Port 6 AVR AVCC AVSS External interrupt Other pins VCC, VSS × 2 MOD0, MOD1 P50/AN0 to P57/AN7 4 P60/INT0 to P63/INT3 MB89660 Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89660 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89660 series is structured as illustrated below. Memory Space MB89663 0000H MB89665 MB89W665 MB89P665 0000H I/O 0080H I/O 0080H RAM 256 B 0100H RAM 512 B 0100H Register 0180H Register 0200H 0280H Not available Not available C000H ROM* 16 KB E000H ROM 8 KB FFFFH FFFFH *: When the MB89P665 is used for evaluation, the internal ROM cannot be used. 17 MB89660 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits FFFDH : Program counter PC A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 12 10 9 8 Vacancy Vacancy Vacancy RP RP 18 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR MB89660 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 19 MB89660 Series The following general-purpose registers are provided: General-purpose registers: an 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 16 banks can be used on the MB89663 and a total of 32 banks can be used on the MB89665/P665/W665. The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 20 MB89660 Series ■ I/O MAP Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Vacancy 06H Vacancy 07H Vacancy 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBTC Watch interrupt control register Vacancy 0BH 0CH (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (W) DDR4 Port 4 data direction register 10H (R/W) PDR5 Port 5 data register 11H Vacancy 12H (R/W) PDR6 Port 6 data register 13H (W) DDR6 Port 6 data direction register 14H Vacancy 15H (R/W) ADC1 A/D converter control register 1 16H (R/W) ADC2 A/D converter control register 2 17H (R/W) ADCD A/D converter data register 18H (R/W) T2CR 8/16-bit timer 2 control register 19H (R/W) T1CR 8/16-bit timer 1 control register 1AH (R/W) T2DR 8/16-bit timer 2 data register 1BH (R/W) T1DR 8/16-bit timer 1 data register 1CH (R/W) CNTR PWM control register 1DH (W) COMR PWM compare register 1EH Vacancy 1FH Vacancy (Continued) 21 MB89660 Series (Continued) Address Read/write Register name 20H (R/W) SMC UART serial mode control register 21H (R/W) SRC UART serial rate control register 22H (R/W) SSD UART serial status/data register 23H (R/W) SIDR/SODR 24H (R/W) SMR Serial mode register 25H (R/W) SDR Serial data register 26H (R/W) EIC1 External interrupt control register 1 27H (R/W) EIC2 External interrupt control register 2 28H (R/W) TMCR Timer control register 29H (R) TCHR Timer count register (H) 2AH (R) TCLR Timer count register (L) 2BH (R/W) OPCR Output control register 2CH (R/W) CPR0H Output compare register 0 (H) 2DH (R/W) CPR0L Output compare register 0 (L) 2EH (R/W) CPR1H Output compare register 1 (H) 2FH (R/W) CPR1L Output compare register 1 (L) 30H (R/W) ICCR Input capture control register 31H (R/W) ICIC Input capture interrupt control register 32H (R) ICR0H Input capture register 0 (H) 33H (R) ICR0L Input capture register 0 (L) 34H (R) ICR1H Input capture register 1 (H) 35H (R) ICR1L Input capture register 1 (L) UART serial data register 36H Vacancy 37H Vacancy 38H Vacancy 7CH (W) ILR1 Interrupt level setting register 1 7DH (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Note: Do not use vacancies. 22 Register description Vacancy MB89660 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC AVCC VSS – 0.3 VSS + 7.0 V * AVR VSS – 0.3 VSS + 7.0 V AVR must not exceed AVCC + 0.3 V Input voltage VI VSS – 0.3 VCC + 0.3 V Output voltage VO VSS – 0.3 VCC + 0.3 V “L” level maximum output current IOL — 20 mA “L” level average output current IOLAV — 4 mA “L” level total maximum output current ΣIOL — 100 mA “L” level total average output current ΣIOLAV — 40 mA “H” level maximum output current IOH — –20 mA “H” level average output current IOHAV — –4 mA “H” level total maximum output current ΣIOH — –50 mA “H” level total average output current ΣIOHAV — –20 mA Power consumption PD — 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) * : Use AVCC and VCC set at the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 23 MB89660 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Value Symbol Operating temperature Remarks Max. 2.2* 6.0* V Normal operation assurance range* MB89663/665 2.7* 6.0* V Normal operation assurance range* MB89P665 1.5 6.0 V Retains the RAM state in stop mode AVR 0.0 AVCC V TA –40 +85 °C VCC AVCC Power supply voltage Unit Min. * : These values vary with the operating frequency and analog assurance range. See Figure. 1 and “5. A/D Converter Electrical Characteristics.” 6 5 Analog accuracy assured in the AVCC = VCC = 3.5 to 6.0 V range Operating voltage (V) Operation assurance range 4 3 2 1 1 2 3 4 5 6 7 8 9 10 Main clock operating frequency (MHz) Note: The shaded area is assured only for the MB89663/665. Figure 1 24 Operating Voltage vs. Main Clock Operating Frequency (MHz) MB89660 Series 3. DC characteristics Parameter Pin Symbol (AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Typ. Max. VIH P00 to P07, P10 to P17 — 0.7 VCC — VCC + 0.3 V VIHS RST, HST P30 to P37, P40 to P47, P60 to P63 — 0.8 VCC — VCC + 0.3 V VIL P00 to P07, P10 to P17 — VSS – 0.3 — 0.3 VCC V VILS RST, HST P30 to P37, P40 to P47, P60 to P63 — VSS – 0.3 — 0.2 VCC V VD P50 to P57 — VSS – 0.3 — VCC + 0.3 V VOH1 P00 to P07, P10 to P17, P20 to P27, P30, P32 to P36, P40 to P47, P60 to P63 IOH = –2.0 mA 2.4 — — V VOH2 P31, P37 IOH = –15 mA 2.4 — — V VOL1 P00 to P07, P10 to P17, P20 to P27, P30, P32 to P36, P40 to P47, P50 to P57, P60 to P63 IOL = +1.8 mA — — 0.4 V VOL2 P31, P37 IOL = +12 mA — — 0.4 V VOL3 RST IOL = +4.0 mA — — 0.4 V Input leakage current (Hi-z output leakage current) ILI1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P63 0.45 V < VI < VCC — — ±5 µA Pull-up resistance RPULU RST, option selection pin VI = 0.0 V 25 50 100 kΩ “H” level input voltage “L” level input voltage*1 Open-drain output pin application voltage “H” level output voltage “L” level output voltage Without pull-up resistor (Continued) 25 MB89660 Series (Continued) (AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Pull-down resistance Pin Symbol Remarks Max. 5 20 60 kΩ Mask ROM products only — 15 18 mA MB89663/665 — 17 20 mA MB89P665/ W665 FC = 10 MHz tinst*3 = 0.4 µs Sleep mode — 6 8 mA ICCH TA = +25°C tinst*3 = 0.4 µs Stop mode — — 10 µA IA FC = 10 MHz, when A/D conversion is activated — 2.5 4.5 mA FC = 10 MHz, TA = +25°C, when A/D conversion is stopped — — 5 µA — 10 — pF RPULD MOD0, MOD1 VI = +5.0 mA FC = 10 MHz tinst*3 = 0.4 µs Normal mode VCC AVCC IAH CIN Other than AVCC, AVSS, VCC, f = 1 MHz and VSS *1: Fix MOD0 and MOD1 to VSS. *2: The power supply current is measured at the external clock. *3: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 26 Unit Typ. ICCS Input capacitance Value Min. ICC Power supply current Condition Also applicable to the hardware standby mode. MB89660 Series 4. AC Characteristics (1) Reset Timing, Hardware Standby Timing Parameter Symbol RST “L” pulse width tZLZH HST “L” pulse width tHLHH (VCC = +5.0 V±10%, AVSS =VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Max. — 16 tXCYL — ns 16 tXCYL — ns * : tXCYL is the oscillation cycle (1/FC) to input to the X0 pin. tZLZH RST 0.2 VCC 0.2 VCC tHLHH HST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Power supply rising time Power supply cut-off time Symbol Condition tR — tOFF Values Unit Min. Max. — 50 ms 1 — ms Remarks Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC 0.2 V 0.2 V 0.2 V 27 MB89660 Series (3) Clock Timing Parameter Symbol Pin Condition Min. (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Unit Remarks Typ. Max. Clock frequency FC X0, X1 — 1 — 10 MHz Clock cycle time tXCYL X0, X1 — 100 — 1000 ns Input clock pulse width PWH PWL X0 — 20 — — ns External clock Input clock rising/ falling time tCR tCF X0 — — — 10 ns External clock X0 and X1 Timing and Conditions tXCYL PWL PWH tCF tCR 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC When a crystal or ceramic resonator is used X0 0.2 VCC When an external clock is used X1 X0 X1 Open (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) 28 Symbol tinst Value (typical) 4/FC Unit Remarks µs When operating at FC = 10 MHz MB89660 Series (5) Recommended Resonator Manufacturers Sample Application of Piezoelectric Resonator (FAR series) X0 X1 FAR* C1 C2 *: Fujitsu Acoustic Resonator C1 = C2 = 20 pF±8 pF (built-in FAR) FAR part number (built-in capacitor type) Frequency Initial deviation of FAR frequency (TA = +25°C) Temperature characteristic of FAR frequency (TA = –20°C to +60°C) FAR-C4CB-08000-M02 8.00 MHz ±0.5% ±0.5% FAR-C4CB-10000-M02 10.00 MHz ±0.5% ±0.5% Inquiry: FUJITSU LIMITED 29 MB89660 Series Sample Application of Ceramic Resonator X0 X1 * C1 Resonator manufacturer* Kyocera Corporation Murata Mfg. Co., Ltd. Resonator C2 Frequency C1 (pF) C2 (pF) R (kΩ) KBR-7.68MWS 7.68 MHz 33 33 — KBR-8.0MWS 8.0 MHz 33 33 — CSA8.00MTZ 8.0 MHz 30 30 — Inquiry: Kyocera Corporation • AVX Corporation North American Sales Headquarters: TEL 1-803-448-9411 • AVX Limited European Sales Headquarters: TEL 44-1252-770000 • AVX/Kyocera H.K. Ltd. Asian Sales Headquarters: TEL 852-363-3303 Murata Mfg. Co., Ltd. • Murata Electronics North America, Inc.: TEL 1-404-436-1300 • Murata Europe Management GmbH: TEL 49-911-66870 • Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233 30 MB89660 Series (6) Serial I/O Timing and UART Timing Parameter Symbol Pin (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Max. Serial clock cycle time tSCYC SCK1, SCK2 SCK1 ↓ → SO1 time SCK2 ↓ → SO2 time tSLOV SCK1, SO1 SCK2, SO2 Valid SI1 → SCK1 ↑ Valid SI1 → SCK1 ↑ tIVSH SI1, SCK1 SI2, SCK2 SCK1 ↑ → valid SI1 hold time SCK2 ↑ → valid SI2 hold time tSHIX SCK1, SI1 SCK2, SI2 Internal shift clock mode 2 tinst* — µs –200 200 ns 1/2 tinst* — µs 1/2 tinst* — µs Serial clock “H” pulse width tSHSL SCK1, SCK2 1 tinst* — µs Serial clock “L” pulse width tSLSH SCK1, SCK2 1 tinst* — µs SCK1 ↓ → SO1 time SCK2 ↓ → SO2 time tSLOV SCK1, SO1 SCK2, SO2 0 200 ns Valid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑ tIVSH SI1, SCK1 SI2, SCK2 1/2 tinst* — µs SCK1 ↑ → valid SI1 hold time SCK2 ↑ → valid SI2 hold time tSHIX SCK1, SI1 SCK2, SI2 1/2 tinst* — µs External shift clock mode * : For information on tinst, see “(4) Instruction Cycle.” 31 MB89660 Series Serial I/O Timing and UART Timing (Internal Shift Clock Mode) tSCYC SCK1 SCK2 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SO1 SO2 0.8 V tIVSH SI1 SI2 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Serial I/O Timing and UART Timing (External Shift Clock Mode) tSLSH SCK1 SCK2 tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV SO1 SO2 2.4 V 0.8 V tIVSH SI1 SI2 32 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB89660 Series (7) Peripheral Input Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Peripheral input “H” pulse width 1 tILIH1 Peripheral input “L” pulse width 1 tIHIL1 Peripheral input “H” pulse width 2 tILIH2 Peripheral input “L” pulse width 2 tIHIL2 Peripheral input “H” pulse width 3 tILIH3 Peripheral input “L” pulse width 3 tIHIL3 Peripheral input “H” pulse width 3 tILIH3 Peripheral input “L” pulse width 3 tIHIL3 Pin RTI0, 1 INT0 to INT3 Value Condition Min. — Max. Unit — µs — µs — µs — µs — µs — µs — µs — µs Remarks 2 tinst* — — EC 1 tinst* — 32 tinst* A/D mode ADST Sense mode 8 tinst* * : For information on tinst, see “(4) Instruction cycle.” tIHIL1 INT0 to 3 RTI0, 1 tILIH1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tIHIL2 tILIH2 0.8 VCC 0.8 VCC EC 0.2 VCC 0.2 VCC tIHIL3 tILIH3 0.8 VCC ADST 0.2 VCC 0.8 VCC 0.2 VCC 33 MB89660 Series (8) Noise Filter (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Condition Value Min. Max. Noise filter width 1 tINF1 P30 to P37, P40 to P47, P60 to P63 During port operation 15 — ns Noise filter width 2 tINF2 P60 to P63 During external interrupt 60 — ns tINF 1, tINF 1, 2 0.8 VCC 0.2 VCC Input waveform 34 Unit 0.2 VCC 2 0.8 VCC Remarks MB89660 Series 5. A/D Converter Electrical Characteristics Parameter Symbol (AVCC = VCC = +3.5 V to 6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Pin Condition Unit Remarks Min. Typ. Max. Resolution Total error Linearity error — — — 8 bit — — ±2.0 LSB — — ±1.0 LSB — — ±0.9 LSB AVSS – 1.5 LSB AVSS+ 0.5 LSB AVSS+ 2.5 LSB mV AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB mV — — 1 LSB — 44 tisnt* — µs — 12 tinst* — µs — — 10 µA 0 — AVR V 0 — AVCC V AVR = 5.0 V when A/D conversion is activated — 150 — µA AVR = 5.0 V when A/D conversion is stopped — — 5 µA — Differential linearity error Zero transition voltage Full-scale transition voltage AVR = AVCC VOT — VFST Interchannel disparity A/D mode conversion time — Sense mode conversion time Analog port input circuit Analog input voltage Reference voltage IAIN — AN0 to AN7 — IR AVR Reference voltage supply current IRH * : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” (1) A/D Glossary • Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 8, analog voltage can be divided into 28 = 256. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values 35 MB89660 Series Digital output 1111 1111 Theoretical conversion value 1111 1110 Actual conversion value (1 LSB × N + VOT) 1 LSB = AVR 256 Linearity error = Differential linearity error = V( N + 1 ) T − VNT − 1 1 LSB Linearity error Total error = 0000 0000 0000 VNT − (1 LSB × N + VOT) 1 LSB VNT − (1 LSB × N + 1 LSB) 1 LSB 0010 0001 0000 VOT VNT V( N+I )T VFST Analog input (2) Precautions • Input impedance of analog input pins The A/D converter used for the MB89660 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low. If a higher accurancy is required, set the output impedance in this series to 2 kΩ or less. When the impedance cannot be kept low, the following two methods are recommended. One is to activate the A/D converter continuously for obtaining the pseudo long sampling time by using software. The other is to connect the external capacitor of approx. 0.1 µs to the analog input pin. Analog Input Equivalent Circuit Sample hold circuit . C =. 33 pF Analog input pin Comparator . R =. 6 kΩ If the output impedance of the external circuit is high, it is recommended to connect an external capacitor of approx. 0.1 µF. Closes for 8 instruction cycles after activating A/D conversion. Analog channel selector • Error The smaller the | AVR – AVSS |, the greater the error would become relatively. 36 MB89660 Series ■ EXAMPLES CHARACTERISTICS (1) “L” Level Output Voltage P00 to P07, P10 to P17,P20 to P27, P30, P32 to P36, P40 to P47, P50 to P57, P60 to P63 VOL vs. IOL VOL (V) VCC = 2.5 V TA = +25°C 0.5 VCC = 3.0 V 0.4 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.3 0.2 (2) “H” Level Output Voltage P00 to P07, P10 to P17, P20 to P27, P30, P32 to P36, P40 to P47, P60 to P63 VCC - VOH VS. IOH VDD - VOH(V) 1.0 0.9 TA = +25°C VCC = 2.5 V 0.8 0.7 VCC = 3.0 V 0.6 0.5 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.4 0.3 0.2 0.1 0.1 0 (3) 1 2 3 4 5 6 7 8 9 10 IOL (mA) (4) “L” Level Output Voltage P31, P37 VOL2 vs. IOL2 VOL2(V) 0.0 0.0 –0.5 –1.0 TA = +25°C –2.0 –3.0 IOH(mA) VCC - VOH2 vs. IOH2 3.0 TA = +25°C VCC = 3.0 V VCC = 4.0 V VCC = 3.0 V VCC = 4.0 V 0.4 –2.5 “H” Level Output Voltage P31, P37 VDD - VOH2(V) 0.6 –1.5 2.0 VCC = 5.0 V VCC = 5.0 V VCC = 6.0 V VCC = 6.0 V 1.0 0.2 0 0 0 –5 –10 –15 –20 IOL2(mA) 0 –5 –10 –15 –20 IOH2(mA) 37 MB89660 Series (5) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) VIN(V) 5.0 4.5 (6) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN(V) 5.0 4.5 VIN vs. VCC TA = +25°C 4.0 TA = +25°C 3.5 4.0 3.0 3.5 2.5 3.0 2.0 2.5 1.5 2.0 1.0 1.5 0.5 1.0 0.0 VIHS VILS 0 0.0 0 1 2 3 4 5 6 1 2 3 4 5 6 7 VCC(V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 0.5 (7) VIN vs. VCC 7 VCC(V) Power Supply Current (External Clock) ICC(mA) 16 ICCS(mA) 5 ICC vs. VCC ICCS vs. VCC TA = +25°C TA = +25°C FC = 10 MHz 14 FC = 10 MHz 4 12 FC = 8 MHz 10 FC = 8 MHz 3 8 FC = 4 MHz 6 4 38 FC = 4 MHz 1 FC = 1 MHz 2 0 2 FC = 1 MHz 1 2 3 4 5 6 7 VCC(v) 0 1 2 3 4 5 6 7 VCC(v) MB89660 Series (8) Pull-up Resistance RPULU vs. VCC RPULU (kΩ) 1000 TA = +25°C 100 1 1 2 3 4 5 6 VCC(V) 39 MB89660 Series ■ INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • Transfer • Arithmetic operation • Branch • Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri × (×) (( × )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH prior to the instruction executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 40 MB89660 Series Table 2 Mnemonic Transfer Instructions (48 instructions) ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Note During byte transfer to A, T ← A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 41 MB89660 Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A (Continued) 42 MB89660 Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ # Operation 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 43 L 44 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 9 A B C D E F A SUBC A XCH A, T XOR A AND A OR A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 rel CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 8 A A SETC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP CMPW CMP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A 7 F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX E 6 D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP C 5 B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 A A DIVU SETI 9 4 8 RORC 7 3 6 ROLC A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89660 Series ■ INSTRUCTION MAP MB89660 Series ■ MASK OPTIONS Part number MB89663 MB89665 MB89P665 MB89W665 Specifying procedure Specify when ordering masking Set with EPROM programmer No. 1 Power-on reset selection With power-on reset Without power-on reset Selectable Setting possible 2 Selection of the oscillation stabilization time Crystal oscillator (26.2 ms/10 MHz) Ceramic oscillator (1.64 ms/10 MHz) Selectable Setting possible 3 Reset pin output With reset output Without reset output Selectable Setting possible 4 Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P63 Can be selected per pin. (P50 to P57 are available for without pull-up resistors when an A/D converter is used.) Can be set per pin. (P54 to P57 must have the same setting) ■ ORDERING INFORMATION Part number Package MB89663P-SH MB89665P-SH MB89P665P-SH 64-pin Plastic SH-DIP (DIP-64P-M01) MB89663PF MB89665PF MB89P665PF 64-pin Plastic SH-DIP (FPT-64P-M06) MB89W665C-SH Remarks 64-pin Ceramic SH-DIP (DIP-64C-A06) 45 MB89660 Series ■ PACKAGE DIMENSIONS 64-pin Plastic SH-DIP (DIP-64P-M01) +0.22 58.00 –0.55 +.008 2.283 –.022 INDEX-1 17.00±0.25 (.669±.010) INDEX-2 5.65(.222)MAX 0.25±0.05 (.010±.002) 3.00(.118)MIN +0.50 0.45±0.10 (.018±.004) 1.00 –0 +.020 .039 –0 0.51(.020)MIN 15°MAX 19.05(.750) TYP 1.778±0.18 (.070±.007) 1.778(.070) MAX C 55.118(2.170)REF 1994 FUJITSU LIMITED D64001S-3C-4 64-pin Plastic QFP (FPT-64P-M06) Dimensions in mm (inches) 24.70±0.40(.972±.016) 3.35(.132)MAX 20.00±0.20(.787±.008) 51 0.05(.002)MIN (STAND OFF) 33 52 32 14.00±0.20 (.551±.008) 18.70±0.40 (.736±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) INDEX 64 20 "A" LEAD No. 1 19 0.40±0.10 (.016±.004) 1.00(.0394) TYP 0.15±0.05(.006±.002) 0.20(.008) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 18.00(.709)REF 22.30±0.40(.878±.016) C 46 1994 FUJITSU LIMITED F64013S-3C-2 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX 0 10° 1.20±0.20 (.047±.008) Dimensions in mm (inches) MB89660 Series 64-pin Ceramic SH-DIP (DIP-64C-A06) 56.90±0.56 (2.240±.022) 8.89(.350) DIA TYP R1.27(.050) REF 18.75±0.25 (.738±.010) INDEX AREA 1.27±0.25 (.050±.010) 5.84(.230)MAX 0.25±0.05 (.010±.004) 3.40±0.36 (.134±.014) 1.45(.057) MAX C 1994 FUJITSU LIMITED D64006SC-1-2 1.778±0.180 (.070±.007) 0.90±0.10 (.0355±.0040) +0.13 0.46 –0.08 +.005 .018 –.003 19.05±0.25 (.750±.010) 0°~9° 55.118(2.170)REF Dimensions in mm (inches) 47 MB89660 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F9602 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.