The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR DATA SHEET DS07–12627–7E 8-bit Microcontrollers CMOS New 8FX MB95260H/270H/280H Series MB95F262H/F262K/F263H/F263K/F264H/F264K MB95F272H/F272K/F273H/F273K/F274H/F274K MB95F282H/F282K/F283H/F283K/F284H/F284K ■ DESCRIPTION MB95260H/270H/280H are series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of these series contain a variety of peripheral resources. ■ FEATURES • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instructions • Bit manipulation instructions, etc. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. • Clock (main OSC clock and sub-OSC clock are only available on MB95F262H/F262K/F263H/F263K/F264H/ F264K/F282H/F282K/F283H/F283K/F284H/F284K) • Selectable main clock source Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) Main CR clock (1/8/10 MHz ±3%, maximum machine clock frequency: 10 MHz) • Selectable subclock source Sub-OSC clock (32.768 kHz) External clock (32.768 kHz) Sub CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz) • Timer • 8/16-bit composite timer • Time-base timer • Watch prescaler • LIN-UART (only available on MB95F262H/F262K/F263H/F263K/F264H/F264K/F282H/F282K/F283H/ F283K/F284H/F284K) • Full duplex double buffer • Capable of clock-synchronized serial data transfer and clock-asynchronized serial data transfer (Continued) Copyright©2008-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.6 MB95260H/270H/280H Series (Continued) • External interrupt • Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) • Can be used to wake up the device from different low power consumption (standby) modes • 8/10-bit A/D converter • 8-bit or 10-bit resolution can be selected. • Low power consumption (standby) modes • Stop mode • Sleep mode • Watch mode • Time-base timer mode • I/O port (Max: 17) (MB95F262K/F263K/F264K) • General-purpose I/O ports (Max): CMOS I/O: 15, N-ch open drain: 2 • I/O port (Max: 16) (MB95F262H/F263H/F264H) • General-purpose I/O ports (Max): CMOS I/O: 15, N-ch open drain: 1 • I/O port (Max: 5) (MB95F272K/F273K/F274K) • General-purpose I/O ports (Max): CMOS I/O: 3, N-ch open drain: 2 • I/O port (Max: 4) (MB95F272H/F273H/F274H) • General-purpose I/O ports (Max): CMOS I/O: 3, N-ch open drain: 1 • I/O port (Max: 13) (MB95F282K/F283K/F284K) • General-purpose I/O ports (Max): CMOS I/O: 11, N-ch open drain: 2 • I/O port (Max: 12) (MB95F282H/F283H/F284H) • General-purpose I/O ports (Max): CMOS I/O: 11, N-ch open drain: 1 • On-chip debug • 1-wire serial control • Serial writing supported (asynchronous mode) • Hardware/software watchdog timer • Built-in hardware watchdog timer • Built-in software watchdog timer • Power-on reset • A power-on reset is generated when the power is switched on. • Low-voltage detection reset circuit • Built-in low-voltage detector • Clock supervisor counter • Built-in clock supervisor counter function • Programmable port input voltage level • CMOS input level / hysteresis input level • Dual operation Flash memory • The program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. • Flash memory security function • Protects the content of the Flash memory 2 DS07–12627–7E MB95260H/270H/280H Series ■ PRODUCT LINE-UP • MB95260H Series Part number MB95F262H MB95F263H MB95F264H MB95F262K MB95F263K MB95F264K Parameter Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Power-on reset Yes Low-voltage No Yes detection reset Reset input Dedicated Selected by software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 17 • I/O ports (Max) : 16 General• CMOS I/O : 15 • CMOS I/O : 15 purpose I/O • N-ch open drain: 1 • N-ch open drain: 2 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ software Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer • The sub CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace three bytes of data. • A wide range of communication speed can be selected by a dedicated reload timer. • It has a full duplex double buffer. LIN-UART • Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is enabled. • The LIN function can be used as a LIN master or a LIN slave. 6 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. 2 channels • The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel". 8/16-bit • composite timer It has built-in timer function, PWC function, PWM function and input capture function. • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. 6 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from the standby mode. • 1-wire serial control On-chip debug • It supports serial writing. (asynchronous mode) (Continued) DS07–12627–7E 3 MB95260H/270H/280H Series (Continued) Part number MB95F262H MB95F263H MB95F264H MB95F262K MB95F263K MB95F264K Parameter Watch prescaler Eight different time intervals can be selected. • It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/ erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Number of program/erase cycles: 100000 • Data retention time: 20 years • Flash security feature for protecting the content of the Flash memory Standby mode Sleep mode, stop mode, watch mode, time-base timer mode DIP-24P-M07 LCC-32P-M19 Package FPT-20P-M09 FPT-20P-M10 4 DS07–12627–7E MB95260H/270H/280H Series • MB95270H Series Part number MB95F272H MB95F273H MB95F274H MB95F272K MB95F273K MB95F274K Parameter Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Power-on reset Yes Low-voltage No Yes detection reset Reset input Dedicated Selected by software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 4 • I/O ports (Max) : 5 General• CMOS I/O :3 • CMOS I/O :3 purpose I/O • N-ch open drain: 2 • N-ch open drain: 1 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ Main oscillation clock at 10 MHz: 105 ms (Min) software watchdog timer • The sub-internal CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace three bytes of data. LIN-UART No LIN-UART 2 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. 1 channel • The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel". 8/16-bit • composite timer It has built-in timer function, PWC function, PWM function and input capture function. • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. 2 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from standby modes. • 1-wire serial control On-chip debug • It supports serial writing. (asynchronous mode) Watch prescaler Eight different time intervals can be selected. • It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/ erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Number of program/erase cycles: 100000 • Data retention time: 20 years • Flash security feature for protecting the content of the Flash memory Standby mode Sleep mode, stop mode, watch mode, time-base timer mode Package DS07–12627–7E DIP-8P-M03 FPT-8P-M08 5 MB95260H/270H/280H Series • MB95280H Series Part number MB95F282H MB95F283H MB95F284H MB95F282K MB95F283K MB95F284K Parameter Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Flash memory 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes Power-on reset Yes Low-voltage No Yes detection reset Reset input Dedicated Selected by software • Number of basic instructions : 136 • Instruction bit length : 8 bits • Instruction length : 1 to 3 bytes CPU functions • Data bit length : 1, 8 and 16 bits • Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz) • Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) • I/O ports (Max) : 12 • I/O ports (Max) : 13 General• CMOS I/O : 11 • CMOS I/O : 11 purpose I/O • N-ch open drain: 1 • N-ch open drain: 2 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ software Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer • The sub-internal CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace three bytes of data. • A wide range of communication speed can be selected by a dedicated reload timer. • It has a full duplex double buffer. LIN-UART • Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is enabled. • The LIN function can be used as a LIN master or a LIN slave. 5 channels 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. 1 channel • The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel". 8/16-bit • composite timer It has built-in timer function, PWC function, PWM function and input capture function. • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. 6 channels External • Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt • It can be used to wake up the device from standby modes. • 1-wire serial control On-chip debug • It supports serial writing. (asynchronous mode) (Continued) 6 DS07–12627–7E MB95260H/270H/280H Series (Continued) Part number MB95F282H MB95F283H MB95F284H MB95F282K MB95F283K MB95F284K Parameter Watch prescaler Eight different time intervals can be selected. • It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/ erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory • Number of program/erase cycles: 100000 • Data retention time: 20 years • Flash security feature for protecting the content of the Flash memory Standby mode Sleep mode, stop mode, watch mode, time-base timer mode LCC-32P-M19 Package DIP-16P-M06 FPT-16P-M06 DS07–12627–7E 7 MB95260H/270H/280H Series ■ PACKAGES AND CORRESPONDING PRODUCTS Part number MB95F MB95F MB95F MB95F MB95F MB95F MB95F MB95F MB95F MB95F MB95F MB95F 262H 262K 263H 263K 264H 264K 272H 272K 273H 273K 274H 274K Package DIP-24P-M07 O O O O O O X X X X X X FPT-20P-M09 O O O O O O X X X X X X FPT-20P-M10 O O O O O O X X X X X X DIP-16P-M06 X X X X X X X X X X X X FPT-16P-M06 X X X X X X X X X X X X DIP-8P-M03 X X X X X X O O O O O O FPT-8P-M08 X X X X X X O O O O O O LCC-32P-M19 O O O O O O X X X X X X Part number MB95F MB95F MB95F MB95F MB95F MB95F 282H 282K 283H 283K 284H 284K Package DIP-24P-M07 X X X X X X FPT-20P-M09 X X X X X X FPT-20P-M10 X X X X X X DIP-16P-M06 O O O O O O FPT-16P-M06 O O O O O O DIP-8P-M03 X X X X X X FPT-8P-M08 X X X X X X LCC-32P-M19 O O O O O O O: Available X: Unavailable 8 DS07–12627–7E MB95260H/270H/280H Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION • Current consumption When using the on-chip debug function, take account of the current consumption of flash erase/write. For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSION”. • Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”. • On-chip debug function The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. In addition, if the Flash memory data has to be updated, the PF2/RST pin must also be connected to the same evaluation tool. DS07–12627–7E 9 MB95260H/270H/280H Series NC NC NC NC NC NC NC NC ■ PIN ASSIGNMENT 32 31 30 29 28 27 26 25 X1/PF1 X0/PF0 Vss X1A/PG2 X0A/PG1 Vcc C RST/PF2 1 24 2 23 (TOP VIEW) 32 pins 3 5 21 P06/INT06/TO01 P05/INT05/AN05/TO00 20 P04/INT04/AN04/SIN/EC0 19 P03/INT03/AN03/SOT P02/INT02/AN02/SCK 22 4 LCC-32P-M19 6 7 The number of usable pins is 20.18 17 8 X0/PF0 NC X1/PF1 Vss X1A/PG2 X0A/PG1 Vcc C RST/PF2 TO10/P62 NC TO11/P63 1 2 3 4 5 6 7 8 9 10 11 12 X0/PF0 X1/PF1 Vss X1A/PG2 X0A/PG1 Vcc C RST/PF2 TO10/P62 TO11/P63 1 2 3 4 5 6 7 8 9 10 P01/AN01 P64/EC1 P00/AN00 NC NC NC 11 12 13 14 15 16 NC TO11/P63 TO10/P62 9 10 P07/INT07 P12/EC0/DBG (TOP VIEW) 24 pins DIP-24P-M07 The number of usable pins is 20. (TOP VIEW) 20 pins FPT-20P-M09 FPT-20P-M10 24 23 22 21 20 19 18 17 16 15 14 13 P12/EC0/DBG NC P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/AN01 P00/AN00 NC P64/EC1 20 19 18 17 16 15 14 13 12 11 P12/EC0/DBG P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/AN01 P00/AN00 P64/EC1 (Continued) 10 DS07–12627–7E MB95260H/270H/280H Series NC NC NC NC NC NC NC NC (Continued) 32 31 30 29 28 27 26 25 X1/PF1 X0/PF0 Vss X1A/PG2 X0A/PG1 Vcc C RST/PF2 1 24 (TOP VIEW) 32 pins 2 3 5 LCC-32P-M19 6 7 The number of usable pins is 16. 8 1 2 3 4 5 6 7 8 Vss Vcc C RST/PF2 1 2 3 4 P06/INT06/TO01 P05/INT05/AN05/TO00 20 P04/INT04/AN04/SIN/EC0 19 18 P03/INT03/AN03/SOT P02/INT02/AN02/SCK 17 P01/AN01 NC NC NC NC NC 11 12 13 14 15 16 NC NC NC X0/PF0 X1/PF1 Vss X1A/PG2 X0A/PG1 Vcc RST/PF2 C P07/INT07 P12/EC0/DBG 21 22 4 9 10 DS07–12627–7E 23 (TOP VIEW) 16 pins DIP-16P-M06 FPT-16P-M06 (TOP VIEW) 8 pins DIP-8P-M03 / FPT-8P-M08 16 15 14 13 12 11 10 9 8 7 6 5 P12/EC0/DBG P07/INT07 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P01/AN01 P02/INT02/AN02/SCK P12/EC0/DBG P06/INT06/TO01 P05/AN05/TO00 P04/INT04/AN04/EC0 11 MB95260H/270H/280H Series ■ PIN DESCRIPTION (MB95260H Series, 32 pins) Pin no. 1 2 3 4 5 Pin name PF1 X1 PF0 X0 Vss PG2 X1A PG1 X0A I/O circuit type* B B ⎯ C C Function General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin 6 Vcc ⎯ Power supply pin 7 C ⎯ Capacitor connection pin PF2 8 9 RST P63 General-purpose I/O port A D TO11 10 P62 Reset pin This is a dedicated reset pin in MB95F262H/F263H/F264H. General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin D TO10 General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin 11 NC ⎯ It is an internally connected pin. Always leave it unconnected. 12 NC ⎯ It is an internally connected pin. Always leave it unconnected. 13 NC ⎯ It is an internally connected pin. Always leave it unconnected. 14 NC ⎯ It is an internally connected pin. Always leave it unconnected. 15 16 17 P00 AN00 P64 EC1 P01 AN01 E D E P02 18 19 INT02 AN02 General-purpose I/O port A/D converter analog input pin General-purpose I/O port 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port E External interrupt input pin A/D converter analog input pin SCK LIN-UART clock I/O pin P03 General-purpose I/O port INT03 AN03 SOT E External interrupt input pin A/D converter analog input pin LIN-UART data output pin (Continued) 12 DS07–12627–7E MB95260H/270H/280H Series (Continued) Pin no. Pin name General-purpose I/O port INT04 External interrupt input pin AN04 F LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port High-current pin INT05 E A/D converter analog input pin TO00 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin G TO01 EC0 General-purpose I/O port H DBG P07 INT07 External interrupt input pin 8/16-bit composite timer ch. 0 output pin P12 24 External interrupt input pin AN05 INT06 23 A/D converter analog input pin SIN P06 22 Function P04 20 21 I/O circuit type* 8/16-bit composite timer ch. 0 clock input pin DBG input pin G General-purpose I/O port External interrupt input pin 25 NC ⎯ It is an internally connected pin. Always leave it unconnected. 26 NC ⎯ It is an internally connected pin. Always leave it unconnected. 27 NC ⎯ It is an internally connected pin. Always leave it unconnected. 28 NC ⎯ It is an internally connected pin. Always leave it unconnected. 29 NC ⎯ It is an internally connected pin. Always leave it unconnected. 30 NC ⎯ It is an internally connected pin. Always leave it unconnected. 31 NC ⎯ It is an internally connected pin. Always leave it unconnected. 32 NC ⎯ It is an internally connected pin. Always leave it unconnected. *: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. DS07–12627–7E 13 MB95260H/270H/280H Series ■ PIN DESCRIPTION (MB95260H Series, 24 pins) Pin no. 1 2 3 4 5 6 Pin name PF0 X0 NC PF1 X1 VSS PG2 X1A PG1 X0A I/O circuit type* B — B — C C Function General-purpose I/O port Main clock input oscillation pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin 7 VCC — Power supply pin 8 C — Capacitor connection pin PF2 9 10 RST P62 General-purpose I/O port A D TO10 11 12 NC P63 14 15 16 P64 EC1 NC P00 AN00 P01 AN01 — It is an internally connected pin. Always leave it unconnected. D General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin D — E E P02 17 INT02 AN02 SCK General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin TO11 13 Reset pin This is a dedicated reset pin in MB95F262H/F263H/F264H. General-purpose I/O port 8/16-bit composite timer ch. 1 clock input pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port E External interrupt input pin A/D converter analog input pin LIN-UART clock I/O pin (Continued) 14 DS07–12627–7E MB95260H/270H/280H Series (Continued) Pin no. Pin name I/O circuit type* P03 18 19 20 INT03 AN03 General-purpose I/O port E 23 P04 General-purpose I/O port INT04 External interrupt input pin AN04 F A/D converter analog input pin SIN LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port High-current pin INT05 E External interrupt input pin AN05 A/D converter analog input pin TO00 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin INT06 G P07 INT07 NC EC0 DBG External interrupt input pin 8/16-bit composite timer ch. 0 output pin G — P12 24 A/D converter analog input pin LIN-UART data output pin TO01 22 External interrupt input pin SOT P06 21 Function General-purpose I/O port External interrupt input pin It is an internally connected pin. Always leave it unconnected. General-purpose I/O port H 8/16-bit composite timer ch. 0 clock input pin DBG input pin *: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. DS07–12627–7E 15 MB95260H/270H/280H Series ■ PIN DESCRIPTION (MB95260H Series, 20 pins) Pin no. 1 2 3 4 5 Pin name PF0 X0 PF1 X1 VSS PG2 X1A PG1 X0A I/O circuit type* B B — C C Function General-purpose I/O port Main clock input oscillation pin General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin 6 VCC — Power supply pin 7 C — Capacitor connection pin PF2 8 9 RST P62 General-purpose I/O port A D TO10 10 P63 12 13 P64 EC1 P00 AN00 P01 AN01 D 15 INT02 AN02 General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin D E E P02 14 General-purpose I/O port High-current pin 8/16-bit composite timer ch. 1 output pin TO11 11 Reset pin This is a dedicated reset pin in MB95F262H/F263H/F264H. General-purpose I/O port 8/16-bit composite timer ch. 1 clock input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port A/D converter analog input pin General-purpose I/O port E External interrupt input pin A/D converter analog input pin SCK LIN-UART clock I/O pin P03 General-purpose I/O port INT03 AN03 SOT E External interrupt input pin A/D converter analog input pin LIN-UART data output pin (Continued) 16 DS07–12627–7E MB95260H/270H/280H Series (Continued) Pin no. Pin name 16 17 I/O circuit type* P04 General-purpose I/O port INT04 External interrupt input pin AN04 F LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port High-current pin INT05 E A/D converter analog input pin TO00 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin INT06 G P07 INT07 EC0 DBG External interrupt input pin 8/16-bit composite timer ch. 0 output pin G P12 20 External interrupt input pin AN05 TO01 19 A/D converter analog input pin SIN P06 18 Function General-purpose I/O port External interrupt input pin General-purpose I/O port H 8/16-bit composite timer ch. 0 clock input pin DBG input pin *: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. DS07–12627–7E 17 MB95260H/270H/280H Series ■ PIN DESCRIPTION (MB95270H Series, 8 pins) s Pin no. Pin name I/O circuit type* 1 VSS — Power supply pin (GND) 2 VCC — Power supply pin 3 C — Capacitor connection pin PF2 4 RST General-purpose I/O port A P04 5 6 INT04 AN04 F External interrupt input pin A/D converter analog input pin EC0 8/16-bit composite timer ch. 0 clock input pin P05 General-purpose I/O port High-current pin AN05 E INT06 General-purpose I/O port High-current pin G TO01 DBG External interrupt input pin 8/16-bit composite timer ch. 0 output pin P12 EC0 A/D converter analog input pin 8/16-bit composite timer ch. 0 output pin P06 8 Reset pin This pin is a dedicated reset pin in MB95F272H/F273H/F274H. General-purpose I/O port TO00 7 Function General-purpose I/O port H 8/16-bit composite timer ch. 0 clock input pin DBG input pin *: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. 18 DS07–12627–7E MB95260H/270H/280H Series ■ PIN DESCRIPTION (MB95280H Series, 32 pins) Pin no. Pin name PF1 1 X1 PF0 2 X0 3 Vss PG2 4 X1A PG1 5 X0A I/O circuit type* B B ⎯ C C Function General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin 6 Vcc ⎯ Power supply pin 7 C ⎯ Capacitor connection pin PF2 8 RST General-purpose I/O port A Reset pin This is a dedicated reset pin in MB95F282H/F283H/F284H. 9 NC ⎯ It is an internally connected pin. Always leave it unconnected. 10 NC ⎯ It is an internally connected pin. Always leave it unconnected. 11 NC ⎯ It is an internally connected pin. Always leave it unconnected. 12 NC ⎯ It is an internally connected pin. Always leave it unconnected. 13 NC ⎯ It is an internally connected pin. Always leave it unconnected. 14 NC ⎯ It is an internally connected pin. Always leave it unconnected. 15 NC ⎯ It is an internally connected pin. Always leave it unconnected. 16 NC ⎯ It is an internally connected pin. Always leave it unconnected. 17 P01 AN01 E P02 18 19 20 INT02 AN02 General-purpose I/O port A/D converter analog input pin General-purpose I/O port E External interrupt input pin A/D converter analog input pin SCK LIN-UART clock I/O pin P03 General-purpose I/O port INT03 AN03 E External interrupt input pin A/D converter analog input pin SOT LIN-UART data output pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 F A/D converter analog input pin SIN LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin (Continued) DS07–12627–7E 19 MB95260H/270H/280H Series (Continued) Pin no. Pin name I/O circuit type* General-purpose I/O port High-current pin P05 21 INT05 E A/D converter analog input pin TO00 8/16-bit composite timer ch. 0 output pin General-purpose I/O port High-current pin INT06 G TO01 EC0 General-purpose I/O port H DBG 24 P07 INT07 External interrupt input pin 8/16-bit composite timer ch. 0 output pin P12 23 External interrupt input pin AN05 P06 22 Function 8/16-bit composite timer ch. 0 clock input pin DBG input pin G General-purpose I/O port External interrupt input pin 25 NC ⎯ It is an internally connected pin. Always leave it unconnected. 26 NC ⎯ It is an internally connected pin. Always leave it unconnected. 27 NC ⎯ It is an internally connected pin. Always leave it unconnected. 28 NC ⎯ It is an internally connected pin. Always leave it unconnected. 29 NC ⎯ It is an internally connected pin. Always leave it unconnected. 30 NC ⎯ It is an internally connected pin. Always leave it unconnected. 31 NC ⎯ It is an internally connected pin. Always leave it unconnected. 32 NC ⎯ It is an internally connected pin. Always leave it unconnected. *: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. 20 DS07–12627–7E MB95260H/270H/280H Series ■ PIN DESCRIPTION (MB95280H Series, 16 pins) Pin no. Pin name 1 2 3 4 5 6 PF0 X0 PF1 X1 VSS PG2 X1A PG1 X0A VCC I/O circuit type* B B — C C — PF2 7 8 RST C INT02 AN02 P01 AN01 12 INT03 AN03 General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND) General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin Reset pin This pin is a dedicated reset pin in MB95F282H/F283H/F284H. — Capacitor connection pin General-purpose I/O port E External interrupt input pin A/D converter analog input pin LIN-UART clock I/O pin E P03 11 Main clock input oscillation pin A SCK 10 General-purpose I/O port General-purpose I/O port P02 9 Function General-purpose I/O port A/D converter analog input pin General-purpose I/O port E External interrupt input pin A/D converter analog input pin SOT LIN-UART data output pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 F A/D converter analog input pin SIN LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin (Continued) DS07–12627–7E 21 MB95260H/270H/280H Series (Continued) Pin no. Pin name I/O circuit type* General-purpose I/O port High-current pin P05 13 INT05 E A/D converter analog input pin TO00 8/16-bit composite timer ch. 0 clock input pin General-purpose I/O port High-current pin INT06 G TO01 15 P07 INT07 EC0 DBG External interrupt input pin 8/16-bit composite timer ch. 0 clock input pin G P12 16 External interrupt input pin AN05 P06 14 Function General-purpose I/O port External interrupt input pin General-purpose I/O port H 8/16-bit composite timer ch. 0 clock input pin DBG input pin *: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. 22 DS07–12627–7E MB95260H/270H/280H Series ■ I/O CIRCUIT TYPE Type Circuit A Remarks Reset input / Hysteresis input Reset output / Digital output • N-ch open drain output • Hysteresis input • Reset output N-ch B P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input Clock input • Oscillation circuit • High-speed side • Feedback resistance: approx. 1 MΩ • CMOS output • Hysteresis input X1 X0 Standby control / Port select P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input C Port select R Pull-up control P-ch P-ch Digital output N-ch Digital output Standby control Hysteresis input • Oscillation circuit • Low-speed side • Feedback resistance: approx.10 MΩ • CMOS output • Hysteresis input • Pull-up control available Clock input X1A X0A Standby control / Port select Port select R Pull-up control Digital output P-ch Digital output N-ch Digital output Standby control Hysteresis input (Continued) DS07–12627–7E 23 MB95260H/270H/280H Series (Continued) Type Circuit D Remarks P-ch Digital output • CMOS output • Hysteresis input Digital output N-ch Standby control Hysteresis input E Pull-up control R P-ch • CMOS output • Hysteresis input • Pull-up control available Digital output P-ch Digital output N-ch Analog input A/D control Standby control Hysteresis input F Pull-up control R P-ch Digital output P-ch • • • • CMOS output Hysteresis input CMOS input Pull-up control available Digital output N-ch Analog input A/D control Standby control Hysteresis input CMOS input G Pull-up control R P-ch • Hysteresis input • CMOS output • Pull-up control available Digital output P-ch Digital output N-ch Standby control Hysteresis input H Standby control Hysteresis input • N-ch open drain output • Hysteresis input Digital output N-ch 24 DS07–12627–7E MB95260H/270H/280H Series ■ NOTES ON DEVICE HANDLING • Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in “1. Absolute Maximum Ratings” of “■ ELECTRICAL CHARACTERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. • Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. • Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. ■ PIN CONNECTION • Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. • Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. • DBG pin Connect the DBG pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board. The DBG pin should not stay at “L” level after power-on until the reset output is released. • RST pin Connect the RST pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board. The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST pin can be enabled by the RSTOE bit of the SYSC register, and the reset input function and the general purpose I/O function can be selected by the RSTEN bit of the SYSC register. DS07–12627–7E 25 MB95260H/270H/280H Series • C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG/RST/C pins connection diagram DBG C RST Cs 26 DS07–12627–7E MB95260H/270H/280H Series ■ BLOCK DIAGRAM (MB95260H Series) F2MC-8FX CPU PF2*1/RST*2 Flash with security function (20/12/8 Kbyte) Reset with LVD PF1/X1*2 RAM (496/240 bytes) PF0/X0*2 PG2/X1A*2 Oscillator circuit CR oscillator Interrupt controller PG1/X0A*2 (P05*3/TO00) 8/16-bit composite timer (0) Clock control (P06*3/TO01) P12*1/EC0, (P04/EC0) (P12/DBG) On-chip debug P02/INT02 to P07/INT07 External interrupt Internal Bus (P00/AN00 to P05*3/AN05) Wild register 8/10-bit A/D converter (P62*3/TO10) 8/16-bit composite timer (1) (P02/SCK) (P03/SOT) (P63*3/TO11) P64/EC1 LIN-UART (P04/SIN) C Port VCC *1: PF2 and P12 are N-ch open drain pins. VSS *2: Software option Port *3: P05, P06, P62 and P63 are high-current ports. Note: Pins in parentheses indicate that functions of those pins are shared among different resources. DS07–12627–7E 27 MB95260H/270H/280H Series ■ BLOCK DIAGRAM (MB95270H Series) F2MC-8FX CPU PF2*1/RST*2 Flash with security function (20/12/8 Kbyte) Reset with LVD RAM (496/240 bytes) CR oscillator Interrupt controller (P05*3/TO00) 8/16-bit composite timer (0) Clock control (P06*3/TO01) P12*1/EC0, (P04/EC0) (P12/DBG) On-chip debug P04/INT04, P06*3/INT06 External interrupt Internal Bus P05*3/AN05, (P04/AN04) Wild register 8/10-bit A/D converter C Port VCC *1: PF2 and P12 are N-ch open drain pins. VSS *2: Software option Port *3: P05 and P06 are high-current ports. Note: Pins in parentheses indicate that functions of those pins are shared among different resources. 28 DS07–12627–7E MB95260H/270H/280H Series ■ BLOCK DIAGRAM (MB95280H Series) F2MC-8FX CPU PF2*1/RST*2 Flash with security function (20/12/8 Kbyte) Reset with LVD PF1/X1*2 RAM (496/240 bytes) PF0/X0*2 PG2/X1A*2 Oscillator circuit CR oscillator Interrupt controller PG1/X0A*2 (P05*3/TO00) 8/16-bit composite timer (0) Clock control (P06*3/TO01) P12*1/EC0, (P04/EC0) (P12/DBG) On-chip debug P02/INT02 to P07/INT07 External interrupt Internal Bus (P01/AN01 to P05*3/AN05) Wild register 8/10-bit A/D converter (P02/SCK) (P03/SOT) LIN-UART (P04/SIN) C Port VCC *1: PF2 and P12 are N-ch open drain pins. VSS *2: Software option Port *3: P05 and P06 are high-current ports. Note: Pins in parentheses indicate that functions of those pins are shared among different resources. DS07–12627–7E 29 MB95260H/270H/280H Series ■ CPU CORE • Memory Space The memory space of the MB95260H/270H/280H Series is 64 Kbyte in size, and consists of an I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95260H/270H/280H Series are shown below. • Memory Maps MB95F262H/F262K/F272H/ F272K/F282H/F282K 0000H MB95F263H/F263K/F273H/ F273K/F283H/F283K 0000H I/O area 0080H 0090H 0100H 0180H Access prohibited RAM 240 bytes Register Access prohibited 0F80H 0080H 0090H 0100H Flash 4 Kbyte Access prohibited F000H FFFFH 30 Access prohibited Flash 4 Kbyte I/O area 0080H 0090H 0100H 0F80H C000H Access prohibited Extension I/O area 1000H Access prohibited B000H Access prohibited RAM 496 bytes Register 0200H 0280H Extension I/O area 1000H Access prohibited C000H Access prohibited RAM 496 bytes Register 0200H 0280H Extension I/O area B000H 0000H I/O area 0F80H 1000H MB95F264H/F264K/F274H/ F274K/F284H/F284K Flash 4 Kbyte Access prohibited B000H Access prohibited Flash 20 Kbyte E000H Flash 8 Kbyte FFFFH FFFFH DS07–12627–7E MB95260H/270H/280H Series ■ I/O MAP (MB95260H Series) Address Register abbreviation Register name R/W Initial value 0000H PDR0 Port 0 data register R/W 00000000B 0001H DDR0 Port 0 direction register R/W 00000000B 0002H PDR1 Port 1 data register R/W 00000000B 0003H DDR1 Port 1 direction register R/W 00000000B 0004H — — — 0005H WATR R/W 11111111B 0006H — — — 0007H SYCC R/W 0000X011B 00000XXXB (Disabled) Oscillation stabilization wait time setting register (Disabled) System clock control register 0008H STBC Standby control register R/W 0009H RSRR Reset source register R/W 000XXXXXB 000AH TBTC Time-base timer control register R/W 00000000B 000BH WPCR Watch prescaler control register R/W 00000000B 000CH WDTC Watchdog timer control register R/W 00XX0000B 000DH SYCC2 System clock control register 2 R/W XX100011B 000EH to 0015H — — — 0016H PDR6 Port 6 data register R/W 00000000B 0017H DDR6 Port 6 direction register R/W 00000000B 0018H to 0027H — — — 0028H PDRF Port F data register R/W 00000000B 0029H DDRF Port F direction register R/W 00000000B 002AH PDRG Port G data register R/W 00000000B 002BH DDRG Port G direction register R/W 00000000B 002CH PUL0 Port 0 pull-up register R/W 00000000B 002DH to 0034H — — — (Disabled) (Disabled) (Disabled) 0035H PULG Port G pull-up register R/W 00000000B 0036H T01CR1 8/16-bit composite timer 01 status control register 1 ch. 0 R/W 00000000B 0037H T00CR1 8/16-bit composite timer 00 status control register 1 ch. 0 R/W 00000000B 0038H T11CR1 8/16-bit composite timer 11 status control register 1 ch. 1 R/W 00000000B 0039H T10CR1 8/16-bit composite timer 10 status control register 1 ch. 1 R/W 00000000B 003AH to 0048H — — — 0049H EIC10 R/W 00000000B (Disabled) External interrupt circuit control register ch. 2/ch. 3 (Continued) DS07–12627–7E 31 MB95260H/270H/280H Series Address Register abbreviation 004AH EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 00000000B 004BH EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 00000000B 004CH to 004FH — — — 0050H SCR LIN-UART serial control register R/W 00000000B 0051H SMR LIN-UART serial mode register R/W 00000000B 0052H SSR LIN-UART serial status register R/W 00001000B 0053H RDR/TDR LIN-UART receive/transmit data register R/W 00000000B 0054H ESCR LIN-UART extended status control register R/W 00000100B 0055H ECCR LIN-UART extended communication control register R/W 000000XXB 0056H to 006BH — — — 006CH ADC1 8/10-bit A/D converter control register 1 R/W 00000000B 006DH ADC2 8/10-bit A/D converter control register 2 R/W 00000000B 006EH ADDH 8/10-bit A/D converter data register upper R/W 00000000B 006FH ADDL 8/10-bit A/D converter data register lower R/W 00000000B 0070H — — — 0071H FSR2 Flash memory status register 2 R/W 00000000B 0072H FSR Flash memory status register R/W 000X0000B 0073H SWRE0 Flash memory sector write control register 0 R/W 00000000B 0074H FSR3 R 0000XXXXB 0075H — — — 0076H WREN Wild register address compare enable register R/W 00000000B 0077H WROR Wild register data test setting register R/W 00000000B 0078H — — — 0079H ILR0 Interrupt level setting register 0 R/W 11111111B 007AH ILR1 Interrupt level setting register 1 R/W 11111111B 007BH ILR2 Interrupt level setting register 2 R/W 11111111B 007CH ILR3 Interrupt level setting register 3 R/W 11111111B 007DH ILR4 Interrupt level setting register 4 R/W 11111111B 007EH ILR5 Interrupt level setting register 5 R/W 11111111B 007FH — — — 0F80H WRARH0 R/W 00000000B Register name (Disabled) (Disabled) (Disabled) Flash memory status register 3 (Disabled) Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) Wild register address setting register (Upper) ch. 0 R/W Initial value (Continued) 32 DS07–12627–7E MB95260H/270H/280H Series Address Register abbreviation 0F81H WRARL0 Wild register address setting register (Lower) ch. 0 R/W 00000000B 0F82H WRDR0 Wild register data setting register ch. 0 R/W 00000000B 0F83H WRARH1 Wild register address setting register (Upper) ch. 1 R/W 00000000B 0F84H WRARL1 Wild register address setting register (Lower) ch. 1 R/W 00000000B 0F85H WRDR1 Wild register data setting register ch. 1 R/W 00000000B 0F86H WRARH2 Wild register address setting register (Upper) ch. 2 R/W 00000000B 0F87H WRARL2 Wild register address setting register (Lower) ch. 2 R/W 00000000B 0F88H WRDR2 Wild register data setting register ch. 2 R/W 00000000B 0F89H to 0F91H — — — 0F92H T01CR0 8/16-bit composite timer 01 status control register 0 ch. 0 R/W 00000000B 0F93H T00CR0 8/16-bit composite timer 00 status control register 0 ch. 0 R/W 00000000B 0F94H T01DR 8/16-bit composite timer 01 data register ch. 0 R/W 00000000B 0F95H T00DR 8/16-bit composite timer 00 data register ch. 0 R/W 00000000B 0F96H TMCR0 8/16-bit composite timer 00/01 timer mode control register ch. 0 R/W 00000000B 0F97H T11CR0 8/16-bit composite timer 11 status control register 0 ch. 1 R/W 00000000B 0F98H T10CR0 8/16-bit composite timer 10 status control register 0 ch. 1 R/W 00000000B 0F99H T11DR 8/16-bit composite timer 11 data register ch. 1 R/W 00000000B 0F9AH T10DR 8/16-bit composite timer 10 data register ch. 1 R/W 00000000B 0F9BH TMCR1 8/16-bit composite timer 10/11 timer mode control register ch. 1 R/W 00000000B 0F9CH to 0FBBH — — — 0FBCH BGR1 LIN-UART baud rate generator register 1 R/W 00000000B 0FBDH BGR0 LIN-UART baud rate generator register 0 R/W 00000000B 0FBEH to 0FC2H — — — 0FC3H AIDRL R/W 00000000B 0FC4H to 0FE3H — — — 0FE4H CRTH Main CR clock trimming register (Upper) R/W 1XXXXXXXB 0FE5H CRTL Main CR clock trimming register (Lower) R/W 000XXXXXB Register name (Disabled) (Disabled) (Disabled) A/D input disable register (Lower) (Disabled) R/W Initial value (Continued) DS07–12627–7E 33 MB95260H/270H/280H Series (Continued) Address Register abbreviation Register name 0FE6H, 0FE7H — (Disabled) 0FE8H SYSC 0FE9H R/W Initial value — — System configuration register R/W 11000011B CMCR Clock monitoring control register R/W 00000000B 0FEAH CMDR Clock monitoring data register R/W 00000000B 0FEBH WDTH Watchdog timer selection ID register (Upper) R/W XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register (Lower) R/W XXXXXXXXB 0FEDH — 0FEEH ILSR 0FEFH to 0FFFH — (Disabled) Input level select register (Disabled) — — R/W 00000000B — — • R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. 34 DS07–12627–7E MB95260H/270H/280H Series ■ I/O MAP (MB95270H Series) Address Register abbreviation Register name R/W Initial value 0000H PDR0 Port 0 data register R/W 00000000B 0001H DDR0 Port 0 direction register R/W 00000000B 0002H PDR1 Port 1 data register R/W 00000000B 0003H DDR1 Port 1 direction register R/W 00000000B 0004H — — — 0005H WATR R/W 11111111B 0006H — — — 0007H SYCC R/W 0000X011B 00000XXXB (Disabled) Oscillation stabilization wait time setting register (Disabled) System clock control register 0008H STBC Standby control register R/W 0009H RSRR Reset source register R/W 000XXXXXB 000AH TBTC Time-base timer control register R/W 00000000B 000BH WPCR Watch prescaler control register R/W 00000000B 000CH WDTC Watchdog timer control register R/W 00XX0000B 000DH SYCC2 System clock control register 2 R/W XX100011B 000EH to 0015H — (Disabled) — — 0016H — (Disabled) — — 0017H — (Disabled) — — 0018H to 0027H — (Disabled) — — 0028H PDRF Port F data register R/W 00000000B 0029H DDRF Port F direction register R/W 00000000B 002AH — (Disabled) — — 002BH — (Disabled) — — 002CH PUL0 R/W 00000000B 002DH to 0034H — — — Port 0 pull-up register (Disabled) 0035H — — — 0036H T01CR1 8/16-bit composite timer 01 status control register 1 ch. 0 R/W 00000000B 0037H T00CR1 8/16-bit composite timer 00 status control register 1 ch. 0 R/W 00000000B 0038H — (Disabled) — — 0039H — (Disabled) — — 003AH to 0048H — (Disabled) — — 0049H — (Disabled) — — (Disabled) (Continued) DS07–12627–7E 35 MB95260H/270H/280H Series Address Register abbreviation 004AH EIC20 External interrupt circuit control register ch. 4 R/W 00000000B 004BH EIC30 External interrupt circuit control register ch. 6 R/W 00000000B 004CH to 004FH — (Disabled) — — 0050H — (Disabled) — — 0051H — (Disabled) — — 0052H — (Disabled) — — 0053H — (Disabled) — — 0054H — (Disabled) — — 0055H — (Disabled) — — 0056H to 006BH — (Disabled) — — 006CH ADC1 8/10-bit A/D converter control register 1 R/W 00000000B 006DH ADC2 8/10-bit A/D converter control register 2 R/W 00000000B 006EH ADDH 8/10-bit A/D converter data register upper R/W 00000000B 006FH ADDL 8/10-bit A/D converter data register lower R/W 00000000B Register name (Disabled) R/W Initial value 0070H — — — 0071H FSR2 Flash memory status register 2 R/W 00000000B 0072H FSR Flash memory status register R/W 000X0000B 0073H SWRE0 Flash memory sector write control register 0 R/W 00000000B 0074H FSR3 R 0000XXXXB 0075H — — — 0076H WREN Wild register address compare enable register R/W 00000000B 0077H WROR Wild register data test setting register R/W 00000000B 0078H — — — 0079H ILR0 Interrupt level setting register 0 R/W 11111111B 007AH ILR1 Interrupt level setting register 1 R/W 11111111B 007BH — (Disabled) — — 007CH — (Disabled) — — 007DH ILR4 Interrupt level setting register 4 R/W 11111111B 007EH ILR5 Interrupt level setting register 5 R/W 11111111B 007FH — — — 0F80H WRARH0 Wild register address setting register (Upper) ch. 0 R/W 00000000B 0F81H WRARL0 Wild register address setting register (Lower) ch. 0 R/W 00000000B 0F82H WRDR0 Wild register data setting register ch. 0 R/W 00000000B Flash memory status register 3 (Disabled) Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) (Continued) 36 DS07–12627–7E MB95260H/270H/280H Series Address Register abbreviation 0F83H WRARH1 Wild register address setting register (Upper) ch. 1 R/W 00000000B 0F84H WRARL1 Wild register address setting register (Lower) ch. 1 R/W 00000000B 0F85H WRDR1 Wild register data setting register ch. 1 R/W 00000000B 0F86H WRARH2 Wild register address setting register (Upper) ch. 2 R/W 00000000B 0F87H WRARL2 Wild register address setting register (Lower) ch. 2 R/W 00000000B 0F88H WRDR2 Wild register data setting register ch. 2 R/W 00000000B 0F89H to 0F91H — — — 0F92H T01CR0 8/16-bit composite timer 01 status control register 0 ch. 0 R/W 00000000B 0F93H T00CR0 8/16-bit composite timer 00 status control register 0 ch. 0 R/W 00000000B 0F94H T01DR 8/16-bit composite timer 01 data register ch. 0 R/W 00000000B 0F95H T00DR 8/16-bit composite timer 00 data register ch. 0 R/W 00000000B 0F96H TMCR0 8/16-bit composite timer 00/01 timer mode control register ch. 0 R/W 00000000B 0F97H — (Disabled) — — 0F98H — (Disabled) — — 0F99H — (Disabled) — — 0F9AH — (Disabled) — — 0F9BH — (Disabled) — — 0F9CH to 0FBBH — (Disabled) — — 0FBCH — (Disabled) — — 0FBDH — (Disabled) — — 0FBEH to 0FC2H — (Disabled) — — 0FC3H AIDRL R/W 00000000B 0FC4H to 0FE3H — — — 0FE4H CRTH Main CR clock trimming register (Upper) R/W 1XXXXXXXB 0FE5H CRTL Main CR clock trimming register (Lower) R/W 000XXXXXB 0FE6H, 0FE7H — 0FE8H SYSC Register name (Disabled) A/D input disable register (Lower) (Disabled) (Disabled) System configuration register R/W Initial value — — R/W 11000011B (Continued) DS07–12627–7E 37 MB95260H/270H/280H Series (Continued) Address Register abbreviation 0FE9H CMCR Clock monitoring control register R/W 00000000B 0FEAH CMDR Clock monitoring data register R/W 00000000B 0FEBH WDTH Watchdog timer selection ID register (Upper) R/W XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register (Lower) R/W XXXXXXXXB 0FEDH — 0FEEH ILSR 0FEFH to 0FFFH — Register name (Disabled) Input level select register (Disabled) R/W Initial value — — R/W 00000000B — — • R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. 38 DS07–12627–7E MB95260H/270H/280H Series ■ I/O MAP (MB95280H Series) Address Register abbreviation Register name R/W Initial value 0000H PDR0 Port 0 data register R/W 00000000B 0001H DDR0 Port 0 direction register R/W 00000000B 0002H PDR1 Port 1 data register R/W 00000000B 0003H DDR1 Port 1 direction register R/W 00000000B 0004H — — — 0005H WATR R/W 11111111B 0006H — — — 0007H SYCC R/W 0000X011B 00000XXXB (Disabled) Oscillation stabilization wait time setting register (Disabled) System clock control register 0008H STBC Standby control register R/W 0009H RSRR Reset source register R/W 000XXXXXB 000AH TBTC Time-base timer control register R/W 00000000B 000BH WPCR Watch prescaler control register R/W 00000000B 000CH WDTC Watchdog timer control register R/W 00XX0000B 000DH SYCC2 System clock control register 2 R/W XX100011B 000EH to 0015H — (Disabled) — — 0016H — (Disabled) — — 0017H — (Disabled) — — 0018H to 0027H — (Disabled) — — 0028H PDRF Port F data register R/W 00000000B 0029H DDRF Port F direction register R/W 00000000B 002AH PDRG Port G data register R/W 00000000B 002BH DDRG Port G direction register R/W 00000000B 002CH PUL0 Port 0 pull-up register R/W 00000000B 002DH to 0034H — — — (Disabled) 0035H PULG Port G pull-up register R/W 00000000B 0036H T01CR1 8/16-bit composite timer 01 status control register 1 ch. 0 R/W 00000000B 0037H T00CR1 8/16-bit composite timer 00 status control register 1 ch. 0 R/W 00000000B 0038H — (Disabled) — — 0039H — (Disabled) — — 003AH to 0048H — (Disabled) — — 0049H EIC10 R/W 00000000B External interrupt circuit control register ch. 2/ch. 3 (Continued) DS07–12627–7E 39 MB95260H/270H/280H Series Address Register abbreviation 004AH EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 00000000B 004BH EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 00000000B 004CH to 004FH — — — 0050H SCR LIN-UART serial control register R/W 00000000B 0051H SMR LIN-UART serial mode register R/W 00000000B 0052H SSR LIN-UART serial status register R/W 00001000B 0053H RDR/TDR LIN-UART receive/transmit data register R/W 00000000B 0054H ESCR LIN-UART extended status control register R/W 00000100B 0055H ECCR LIN-UART extended communication control register R/W 000000XXB 0056H to 006BH — — — 006CH ADC1 8/10-bit A/D converter control register 1 R/W 00000000B 006DH ADC2 8/10-bit A/D converter control register 2 R/W 00000000B 006EH ADDH 8/10-bit A/D converter data register upper R/W 00000000B 006FH ADDL 8/10-bit A/D converter data register lower R/W 00000000B 0070H — — — 0071H FSR2 Flash memory status register 2 R/W 00000000B 0072H FSR Flash memory status register R/W 000X0000B 0073H SWRE0 Flash memory sector write control register 0 R/W 00000000B 0074H FSR3 R 0000XXXXB 0075H — ⎯ — 0076H WREN Wild register address compare enable register R/W 00000000B 0077H WROR Wild register data test setting register R/W 00000000B 0078H — ⎯ — 0079H ILR0 Interrupt level setting register 0 R/W 11111111B 007AH ILR1 Interrupt level setting register 1 R/W 11111111B 007BH ILR2 Interrupt level setting register 2 R/W 11111111B 007CH ILR3 Interrupt level setting register 3 R/W 11111111B 007DH ILR4 Interrupt level setting register 4 R/W 11111111B 007EH ILR5 Interrupt level setting register 5 R/W 11111111B 007FH — — — Register name (Disabled) (Disabled) (Disabled) Flash memory status register 3 (Disabled) Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) R/W Initial value (Continued) 40 DS07–12627–7E MB95260H/270H/280H Series Address Register abbreviation 0F80H WRARH0 Wild register address setting register (Upper) ch. 0 R/W 00000000B 0F81H WRARL0 Wild register address setting register (Lower) ch. 0 R/W 00000000B 0F82H WRDR0 Wild register data setting register ch. 0 R/W 00000000B 0F83H WRARH1 Wild register address setting register (Upper) ch. 1 R/W 00000000B 0F84H WRARL1 Wild register address setting register (Lower) ch. 1 R/W 00000000B 0F85H WRDR1 Wild register data setting register ch. 1 R/W 00000000B 0F86H WRARH2 Wild register address setting register (Upper) ch. 2 R/W 00000000B 0F87H WRARL2 Wild register address setting register (Lower) ch. 2 R/W 00000000B 0F88H WRDR2 Wild register data setting register ch. 2 R/W 00000000B 0F89H to 0F91H — — — 0F92H T01CR0 8/16-bit composite timer 01 status control register 0 ch. 0 R/W 00000000B 0F93H T00CR0 8/16-bit composite timer 00 status control register 0 ch. 0 R/W 00000000B 0F94H T01DR 8/16-bit composite timer 01 data register ch. 0 R/W 00000000B 0F95H T00DR 8/16-bit composite timer 00 data register ch. 0 R/W 00000000B 0F96H TMCR0 8/16-bit composite timer 00/01 timer mode control register ch. 0 R/W 00000000B 0F97H — (Disabled) — — 0F98H — (Disabled) — — 0F99H — (Disabled) — — 0F9AH — (Disabled) — — 0F9BH — (Disabled) — — 0F9CH to 0FBBH — (Disabled) — — 0FBCH BGR1 LIN-UART baud rate generator register 1 R/W 00000000B 0FBDH BGR0 LIN-UART baud rate generator register 0 R/W 00000000B 0FBEH to 0FC2H — — — 0FC3H AIDRL R/W 00000000B 0FC4H to 0FE3H — — — 0FE4H CRTH Main CR clock trimming register (Upper) R/W 1XXXXXXXB 0FE5H CRTL Main CR clock trimming register (Lower) R/W 000XXXXXB Register name (Disabled) (Disabled) A/D input disable register (Lower) (Disabled) R/W Initial value (Continued) DS07–12627–7E 41 MB95260H/270H/280H Series (Continued) Address Register abbreviation Register name 0FE6H, 0FE7H — (Disabled) 0FE8H SYSC 0FE9H R/W Initial value — — System configuration register R/W 11000011B CMCR Clock monitoring control register R/W 00000000B 0FEAH CMDR Clock monitoring data register R/W 00000000B 0FEBH WDTH Watchdog timer selection ID register (Upper) R/W XXXXXXXXB 0FECH WDTL Watchdog timer selection ID register (Lower) R/W XXXXXXXXB 0FEDH — 0FEEH ILSR 0FEFH to 0FFFH — (Disabled) Input level select register (Disabled) — — R/W 00000000B — — • R/W access symbols R/W : Readable / Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. 42 DS07–12627–7E MB95260H/270H/280H Series ■ INTERRUPT SOURCE TABLE (MB95260H Series) Vector table address Priority order of interrupt sourcBit name of interrupt level es of the same setting register level (occurring simultaneously) Interrupt request number Upper Lower External interrupt ch. 4 IRQ00 FFFAH FFFBH L00 [1:0] External interrupt ch. 5 IRQ01 FFF8H FFF9H L01 [1:0] IRQ02 FFF6H FFF7H L02 [1:0] IRQ03 FFF4H FFF5H L03 [1:0] IRQ04 FFF2H FFF3H L04 [1:0] 8/16-bit composite timer ch. 0 (Lower) IRQ05 FFF0H FFF1H L05 [1:0] 8/16-bit composite timer ch. 0 (Upper) IRQ06 FFEEH FFEFH L06 [1:0] LIN-UART (reception) IRQ07 FFECH FFEDH L07 [1:0] LIN-UART (transmission) IRQ08 FFEAH FFEBH L08 [1:0] — IRQ09 FFE8H FFE9H L09 [1:0] — IRQ10 FFE6H FFE7H L10 [1:0] — IRQ11 FFE4H FFE5H L11 [1:0] — IRQ12 FFE2H FFE3H L12 [1:0] — IRQ13 FFE0H FFE1H L13 [1:0] IRQ14 FFDEH FFDFH L14 [1:0] — IRQ15 FFDCH FFDDH L15 [1:0] — IRQ16 FFDAH FFDBH L16 [1:0] — IRQ17 FFD8H FFD9H L17 [1:0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1:0] Time-base timer IRQ19 FFD4H FFD5H L19 [1:0] Watch prescaler IRQ20 FFD2H FFD3H L20 [1:0] IRQ21 FFD0H FFD1H L21 [1:0] 8/16-bit composite timer ch. 1 (Lower) IRQ22 FFCEH FFCFH L22 [1:0] Flash memory IRQ23 FFCCH FFCDH L23 [1:0] Interrupt source External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 — 8/16-bit composite timer ch. 1 (Upper) — DS07–12627–7E High Low 43 MB95260H/270H/280H Series ■ INTERRUPT SOURCE TABLE (MB95270H Series) Vector table address Priority order of interrupt sourcBit name of interrupt level es of the same setting register level (occurring simultaneously) Interrupt request number Upper Lower IRQ00 FFFAH FFFBH L00 [1:0] IRQ01 FFF8H FFF9H L01 [1:0] IRQ02 FFF6H FFF7H L02 [1:0] IRQ03 FFF4H FFF5H L03 [1:0] IRQ04 FFF2H FFF3H L04 [1:0] 8/16-bit composite timer ch. 0 (Lower) IRQ05 FFF0H FFF1H L05 [1:0] 8/16-bit composite timer ch. 0 (Upper) IRQ06 FFEEH FFEFH L06 [1:0] — IRQ07 FFECH FFEDH L07 [1:0] — IRQ08 FFEAH FFEBH L08 [1:0] — IRQ09 FFE8H FFE9H L09 [1:0] — IRQ10 FFE6H FFE7H L10 [1:0] — IRQ11 FFE4H FFE5H L11 [1:0] — IRQ12 FFE2H FFE3H L12 [1:0] — IRQ13 FFE0H FFE1H L13 [1:0] — IRQ14 FFDEH FFDFH L14 [1:0] — IRQ15 FFDCH FFDDH L15 [1:0] — IRQ16 FFDAH FFDBH L16 [1:0] — IRQ17 FFD8H FFD9H L17 [1:0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1:0] Time-base timer IRQ19 FFD4H FFD5H L19 [1:0] Watch prescaler IRQ20 FFD2H FFD3H L20 [1:0] — IRQ21 FFD0H FFD1H L21 [1:0] — IRQ22 FFCEH FFCFH L22 [1:0] IRQ23 FFCCH FFCDH L23 [1:0] Interrupt source External interrupt ch. 4 — — External interrupt ch. 6 — — — Flash memory 44 High Low DS07–12627–7E MB95260H/270H/280H Series ■ INTERRUPT SOURCE TABLE (MB95280H Series) Vector table address Priority order of interrupt sourcBit name of interrupt level es of the same setting register level (occurring simultaneously) Interrupt request number Upper Lower External interrupt ch. 4 IRQ00 FFFAH FFFBH L00 [1:0] External interrupt ch. 5 IRQ01 FFF8H FFF9H L01 [1:0] IRQ02 FFF6H FFF7H L02 [1:0] IRQ03 FFF4H FFF5H L03 [1:0] IRQ04 FFF2H FFF3H L04 [1:0] 8/16-bit composite timer ch. 0 (Lower) IRQ05 FFF0H FFF1H L05 [1:0] 8/16-bit composite timer ch. 0 (Upper) IRQ06 FFEEH FFEFH L06 [1:0] LIN-UART (reception) IRQ07 FFECH FFEDH L07 [1:0] LIN-UART (transmission) IRQ08 FFEAH FFEBH L08 [1:0] — IRQ09 FFE8H FFE9H L09 [1:0] — IRQ10 FFE6H FFE7H L10 [1:0] — IRQ11 FFE4H FFE5H L11 [1:0] — IRQ12 FFE2H FFE3H L12 [1:0] — IRQ13 FFE0H FFE1H L13 [1:0] — IRQ14 FFDEH FFDFH L14 [1:0] — IRQ15 FFDCH FFDDH L15 [1:0] — IRQ16 FFDAH FFDBH L16 [1:0] — IRQ17 FFD8H FFD9H L17 [1:0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1:0] Time-base timer IRQ19 FFD4H FFD5H L19 [1:0] Watch prescaler IRQ20 FFD2H FFD3H L20 [1:0] — IRQ21 FFD0H FFD1H L21 [1:0] — IRQ22 FFCEH FFCFH L22 [1:0] IRQ23 FFCCH FFCDH L23 [1:0] Interrupt source External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 — Flash memory DS07–12627–7E High Low 45 MB95260H/270H/280H Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Power supply voltage*1 Input voltage*1 Output voltage* 1 Maximum clamp current Total maximum clamp current “L” level maximum output current Rating VCC VSS − 0.3 VSS + 6 V VI VSS − 0.3 VSS + 6 V *2 VO VSS − 0.3 VSS + 6 V *2 ICLAMP −2 +2 mA Applicable to specific pins*3 Σ|ICLAMP| — 20 mA Applicable to specific pins*3 IOL1 IOL2 “L” level average current — “H” level maximum output current 15 — 12 — 100 ΣIOLAV — 50 IOH1 IOH2 mA mA ΣIOL — − 15 − 15 — mA mA mA −8 IOHAV2 Other than P05, P06, P62 and P63*4 P05, P06, P62 and P63*4 Other than P05, P06, P62 and P63*4 Average output current= operating current × operating ratio (1 pin) P05, P06, P62 and P63*4 Average output current= operating current × operating ratio (1 pin) mA −4 IOHAV1 “H” level average current “H” level total maximum output current 15 4 IOLAV2 “L” level total average output current Remarks Max IOLAV1 “L” level total maximum output current Unit Min Total average output current= operating current × operating ratio (Total number of pins) Other than P05, P06, P62 and P63*4 P05, P06, P62 and P63*4 Other than P05, P06, P62 and P63*4 Average output current= operating current × operating ratio (1 pin) P05, P06, P62 and P63*4 Average output current= operating current × operating ratio (1 pin) ΣIOH — − 100 mA ΣIOHAV — − 50 Total average output current= mA operating current × operating ratio (Total number of pins) Power consumption Pd — 320 mW Operating temperature TA − 40 + 85 °C Tstg − 55 + 150 °C “H” level total average output current Storage temperature (Continued) 46 DS07–12627–7E MB95260H/270H/280H Series (Continued) *1: These parameters are based on the condition that VSS is 0.0 V. *2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. *3: Applicable to the following pins: P00 to P07, P62 to P64, PG1, PG2, PF0, PF1 (P00, P62, P63 and P64 are only available on MB95F262H/F262K/F263H/F263K/F264H/F264K. P01, P02, P03, P07, PG1, PG2, PF0 and PF1 are only available on MB95F262H/F262K/F263H/F263K/F264H/F264K/F282H/F282K/F283H/ F283K/F284H/F284K.) • Use under recommended operating conditions. • Use with DC voltage (current). • The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. • The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. • When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. • If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. • If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. • Do not leave the HV (High Voltage) input pin unconnected. • Example of a recommended circuit: • Input/Output equivalent circuit Protective diode VCC P-ch Limiting resistor HV(High Voltage) input (0 V to 16 V) N-ch R *4: P62 and P63 are only available on MB95F262H/F262K/F263H/F263K/F264H/F264K. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. WARNING: DS07–12627–7E 47 MB95260H/270H/280H Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Power supply voltage VCC Smoothing capacitor CS Operating temperature TA Value Min Max 2.4*1*2 5.5*1 2.3 5.5 2.9 5.5 2.3 5.5 0.022 1 -40 + 85 +5 + 35 Unit Remarks In normal operation V Other than on-chip debug Hold condition in stop mode mode In normal operation Hold condition in stop mode On-chip debug mode µF *3 °C Other than on-chip debug mode On-chip debug mode *1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: The value is 2.88 V when the low-voltage detection reset is used. *3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG / RST / C pins connection diagram * DBG C RST Cs *: Since the DBG pin becomes a communication pin in on-chip debug mode, set a pull-up resistor value suiting the input/output specifications of P12/DBG. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. WARNING: 48 DS07–12627–7E MB95260H/270H/280H Series 3. DC Characteristics (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol "H" level input voltage “L” level input voltage Open-drain output application voltage “H” level output voltage “L” level output voltage Input capacitance Condition Value Min Typ Max Unit Remarks VIHI P04 *1 0.7 VCC — VCC + 0.3 V When CMOS input level (hysteresis input) is selected VIHS P00 to P07, P12, P62 to P64, PF0, PF1, PG1, PG2 *1 0.8 VCC — VCC + 0.3 V Hysteresis input VIHM PF2 — 0.7 VCC — VCC + 0.3 V Hysteresis input VIL P04 *1 VSS − 0.3 — 0.3 VCC V When CMOS input level (hysteresis input) is selected VILS P00 to P07, P12, P62 to P64, PF0, PF1, PG1, PG2 *1 VSS − 0.3 — 0.2 VCC V Hysteresis input VILM PF2 — VSS − 0.3 — 0.3 VCC V Hysteresis input VD PF2, P12 — VSS − 0.3 — VSS + 5.5 V VOH1 Output pins other than P05, IOH = − 4 mA P06, P12, P62, P63, PF2*2 VCC − 0.5 — — V VOH2 P05, P06, P62, IOH = − 8 mA P63*2 VCC − 0.5 — — V VOL1 Output pins other than P05, IOL = 4 mA P06, P62, P63*2 — — 0.4 V VOL2 P05, P06, P62, IOL = 12 mA P63*2 — — 0.4 V ILI All input pins 0.0 V < VI < VCC −5 — +5 When pull-up µA resistance is disabled RPULL P00 to P07, PG1, PG2*3*4 VI = 0 V 25 50 100 When pull-up kΩ resistance is enabled — 5 15 pF Input leak current (Hi-Z output leak current) Pull-up resistance Pin name CIN Other than VCC f = 1 MHz and VSS (Continued) DS07–12627–7E 49 MB95260H/270H/280H Series (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Pin name Condition Value Min — VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) ICC Typ 13 Max Unit Remarks 17 Except during Flash memory mA programming and erasing — 33.5 39.5 During Flash memory mA programming and erasing — 15 21 mA At A/D conversion — 5.5 9 mA ICCL VCC VCC = 5.5 V (External clock FCL = 32 kHz operation) FMPL = 16 kHz Subclock mode (divided by 2) TA = + 25°C — 65 153 µA ICCLS VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = + 25°C — 10 84 µA ICCT VCC = 5.5 V FCL = 32 kHz Watch mode Main stop mode TA = + 25°C — 5 30 µA VCC = 5.5 V FCRH = 10 MHz FMP = 10 MHz Main CR clock mode — 8.6 — mA VCC = 5.5 V Sub-CR clock mode (divided by 2) TA = + 25°C — 110 410 µA VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) ICCS Power supply current*4 ICCMCR VCC ICCSCR (Continued) 50 DS07–12627–7E MB95260H/270H/280H Series (Continued) Parameter Symbol Pin name (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Value Condition Unit Remarks Min Typ Max VCC = 5.5 V FCH = 32 MHz Time-base timer VCC mode (External clock TA = + 25°C operation) VCC = 5.5 V Substop mode TA = + 25°C — 1.1 3 mA — 3.5 22.5 µA ILVD Current consumption for low-voltage detection circuit only — 37 54 µA ICRH Current consumption for the main CR oscillator — 0.5 0.6 mA Current consumption for the sub-CR oscillator oscillating at 100 kHz — 20 72 µA ICCTS ICCH Power supply current*4 ICRL VCC Main stop mode for single external clock selection *1: The input level of P04 can be switched between “CMOS input level” and “hysteresis input level”. The input level selection register (ILSR) is used to switch between the two input levels. *2: P62 and P63 are only available on MB95F262H/F262K/F263H/F263K/F264H/F264K. *3: P00 is only available on MB95F262H/F262K/F263H/F263K/F264H/F264K. P01, P02, P03, P07, PG1 and PG2 are only available on MB95F262H/F262K/F263H/F263K/F264H/F264K/F282H/F282K/F283H/F283K/ F284H/F284K. *4: • The power supply current is determined by the external clock. When the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. • See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL. • See "4. AC Characteristics: (2) Source Clock / Machine Clock" for FMP and FMPL. DS07–12627–7E 51 MB95260H/270H/280H Series 4. AC Characteristics (1) Clock Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Pin name Condition X0, X1 FCH X0 X0, X1 Clock frequency ⎯ FCRH FCL X0A, X1A tHCYL tLCYL Remarks Typ — 1 — X1 : open 1 — 12 *1 1 — 32.5 9.7 10 10.3 7.76 8 8.24 MHz When the main CR clock is 2 MHz used* 0.97 1 1.03 MHz 9.55 10 10.45 MHz 7.64 8 8.36 0.955 1 1.045 MHz 9.5 10 10.5 7.6 8 8.4 MHz When the main CR clock is 2 MHz used* 0.95 1 1.05 MHz 9.7 10 10.3 MHz 7.76 8 8.24 When the main CR clock is MHz used*3 0.97 1 1.03 MHz 9.5 10 10.5 7.6 8 8.4 MHz When the main CR clock is 3 MHz used* 0.95 1 1.05 MHz — 32.768 — kHz When the sub oscillation circuit is used — 32.768 — kHz When the sub-external clock is used — Max Unit Min 16.25 MHz When the main oscillation circuit is used MHz When the main external clock MHz is used 3.3 V ≤ Vcc ≤ 5.5 V(-40 °C ≤ TA ≤ + 40 °C) 2.4 V ≤ Vcc < 3.3 V(0 °C ≤ TA ≤ + 40 °C) When the main CR clock is MHz used*2 — 3.3 V ≤ Vcc ≤ 5.5 V ( + 40 °C < TA ≤ + 85 °C) 2.4 V ≤ Vcc < 3.3 V (-40 °C ≤ TA < 0 °C, + 40 °C < TA ≤ + 85 °C) 2.4 V ≤ Vcc ≤ 5.5 V(0 °C ≤ TA ≤ + 40 °C) 2.4 V ≤ Vcc ≤ 5.5 V (-40 °C ≤ TA < 0 °C, + 40 °C < TA ≤ + 85 °C) ⎯ — 50 100 200 X0, X1 — 61.5 — 1000 ns X1 : open 83.4 — 1000 ns X0, X1 *1 30.8 — 1000 ns When the external clock is used X0A, X1A — — 30.5 — µs When the subclock is used FCRL Clock cycle time Value X0 kHz When the sub CR clock is used When the main oscillation circuit is used (Continued) 52 DS07–12627–7E MB95260H/270H/280H Series (Continued) Parameter (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to + 85°C) Symbol Pin name Condition Input clock pulse width Input clock rise time and fall time CR oscillation start time Value Unit Remarks Min Typ Max X1 : open 33.4 — — ns X0, X1 *1 12.4 — — ns X0A — — 15.2 — µs X1 : open — — 5 ns X0, X1 *1 — — 5 ns tCRHWK — — — — 80 µs When the main CR clock is used tCRLWK — — — — 10 µs When the sub CR clock is used tWH1 tWL1 tWH2 tWL2 tCR tCF X0 X0 When the external clock is used, the duty ratio should range between 40% and 60%. When the external clock is used *1: The external clock signal is input to X0 and the inverted external clock signal to X1. *2: These specifications are not applicable to the following products: MB95F272HPH, MB95F272KPH, MB95F273HPH, MB95F273KPH, MB95F274HPH, MB95F274KPH, MB95F282HPH, MB95F282KPH, MB95F283HPH, MB95F283KPH, MB95F284HPH and MB95F284KPH. *3: These specifications are only applicable to the following products: MB95F272HPH, MB95F272KPH, MB95F273HPH, MB95F273KPH, MB95F274HPH, MB95F274KPH, MB95F282HPH, MB95F282KPH, MB95F283HPH, MB95F283KPH, MB95F284HPH and MB95F284KPH. DS07–12627–7E 53 MB95260H/270H/280H Series • Input waveform generated when an external clock (main clock) is used tHCYL tWH1 tWL1 tCR X0, X1 tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC • Figure of main clock input port external connection When a crystal oscillator or a ceramic oscillator is used X0 When an external clock is used When an external clock (X1 is open) is used X0 X1 X1 X0 X1 Open FCH FCH FCH • Input waveform generated when an external clock (subclock) is used tLCYL tWH2 tCR X0A tWL2 tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC • Figure of subclock input port external connection When a crystal oscillator or a ceramic oscillator is used X0A X1A FCL When an external clock is used X0A X1A Open FCL 54 DS07–12627–7E MB95260H/270H/280H Series (2) Source Clock / Machine Clock (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Source clock cycle time*1 tSCLK Pin name — FSP Source clock frequency — FSPL Machine clock cycle time*2 (minimum instruction execution time) tMCLK — FMPL Unit Remarks Min Typ Max 61.5 — 2000 ns When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 100 — 1000 ns When the main CR clock is used Min: FCRH = 10 MHz Max: FCRH = 1 MHz — 61 — µs When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 — 20 — µs When the sub CR clock is used FCRL = 100 kHz, divided by 2 0.5 ⎯ 16.25 1 ⎯ 10 MHz When the main CR clock is used — 16.384 — kHz When the sub-oscillation clock is used — 50 — kHz 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 100 — 16000 ns When the main CR clock is used Min: FSP = 10 MHz Max: FSP = 1 MHz, divided by 16 61 — 976.5 µs When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 0.031 — 16.25 0.0625 — 10 1.024 — 16.384 3.125 — 50 MHz When the main oscillation clock is used — FMP Machine clock frequency Value When the sub-CR clock is used FCRL = 100 kHz, divided by 2 MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the sub-oscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz *1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (SYCC : DIV1 and DIV0) . This source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (SYCC : DIV1 and DIV0). In addition, a source clock can be selected from the following. • Main clock divided by 2 • Main CR clock • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 DS07–12627–7E 55 MB95260H/270H/280H Series • Schematic diagram of the clock generation block Divided by 2 FCH (main oscillation) FCRH (Main CR clock) FCL (sub-oscillation) FCRL (SubCR clock) Divided by 2 Division circuit × 1 × 1/4 × 1/8 ×1/16 SCLK (source clock) Divided by 2 MCLK (machine clock) Machine clock division ratio select bits (SYCC : DIV1, DIV0) Clock mode select bits (SYCC2: RCS1, RCS0) • Operating voltage - Operating frequency (When TA = -40°C to + 85°C) MB95260H/270H/280H (without the on-chip debug function) 5.5 Operating voltage (V) 5.0 A/D converter operation range 4.0 3.5 3.0 2.4 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) • Operating voltage - Operating frequency (When TA = -40°C to + 85°C) MB95260H/270H/280H (with the on-chip debug function) 5.5 Operating voltage (V) 5.0 A/D converter operation range 4.0 3.5 2.9 3.0 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP) 56 DS07–12627–7E MB95260H/270H/280H Series (3) External Reset (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol RST “L” level pulse width tRSTL Value Unit Remarks Min Max 2 tMCLK*1 — ns In normal operation Oscillation time of the oscillator*2 + 100 — µs In stop mode, subclock mode, sub-sleep mode, watch mode, and power-on 100 — µs In time-base timer mode *1 : See “(2) Source Clock / Machine Clock” for tMCLK. *2 : The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several µs and several ms. • In normal operation tRSTL RST 0.2 VCC 0.2 VCC • In stop mode, subclock mode, subsleep mode, watch mode and power-on tRSTL RST X0 0.2 VCC 0.2 VCC 90% of amplitude Internal operating clock Oscillation time of oscillator Internal reset DS07–12627–7E 100 μs Oscillation stabilization wait time Execute instruction 57 MB95260H/270H/280H Series (4) Power-on Reset (VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Condition Power supply rising time tR Power supply cutoff time tOFF tR Value Unit Min Max — — 50 ms — 1 — ms Remarks Wait time until power-on tOFF 2.5 V VCC 0.2 V 0.2 V 0.2 V Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below. VCC 2.3 V Set the slope of rising to a value below 30 mV/ms. Hold condition in stop mode VSS 58 DS07–12627–7E MB95260H/270H/280H Series (5) Peripheral Input Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Peripheral input “H” pulse width tILIH Peripheral input “L” pulse width tIHIL Value Pin name INT02 to INT07*2,*3, EC0*2, EC1*4 Unit Min Max 2 tMCLK*1 — ns 2 tMCLK*1 — ns *1: See “(2) Source Clock / Machine Clock” for tMCLK. *2: INT04, INT06 and EC0 are available in all products. *3: INT02, INT03, INT05 and INT07 are only available on MB95F262H/F262K/F263H/F263K/F264H/F264K/ F282H/F282K/F283H/F283K/F284H/F284K. *4: EC1 is only available on MB95F262H/F262K/F263H/F263K/F264H/F264K. tILIH INT02 to INT07*2, *3, EC0*2, EC1*4 DS07–12627–7E 0.8 VCC tIHIL 0.8 VCC 0.2 VCC 0.2 VCC 59 MB95260H/270H/280H Series (6) LIN-UART Timing (only available on MB95F262H/F262K/F263H/F263K/F264H/F264K/F282H/F282K/ F283H/F283K/F284H/F284K) Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0) (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK ↓→ SOT delay time tSLOVI SCK, SOT Valid SIN → SCK ↑ tIVSHI SCK, SIN SCK ↑→ valid SIN hold time tSHIXI SCK, SIN Value Condition Unit Min Max 5 tMCLK*3 — ns + 95 ns — ns — ns Internal clock − 95 operation output pin: 3 CL = 80 pF + 1 TTL tMCLK* + 190 0 Serial clock “L” pulse width tSLSH SCK 3t * − tR — ns Serial clock “H” pulse width tSHSL SCK tMCLK*3 + 95 — ns SCK ↓→ SOT delay time tSLOVE SCK, SOT — 2 tMCLK*3 + 95 ns Valid SIN → SCK ↑ tIVSHE SCK, SIN 190 — ns * + 95 — ns SCK ↑→ valid SIN hold time tSHIXE SCK, SIN MCLK 3 External clock operation output pin: CL = 80 pF + 1 TTL MCLK 3 t SCK fall time tF SCK — 10 ns SCK rise time tR SCK — 10 ns *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “(2) Source Clock / Machine Clock” for tMCLK. 60 DS07–12627–7E MB95260H/270H/280H Series • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOVI 2.4 V SOT 0.8 V tIVSHI tSHIXI 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.8 VCC 0.8 VCC SCK 0.2 VCC tF 0.2 VCC tR tSLOVE 2.4 V SOT 0.8 V tIVSHE tSHIXE 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC DS07–12627–7E 61 MB95260H/270H/280H Series Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK ↑→ SOT delay time tSHOVI SCK, SOT Valid SIN → SCK ↓ tIVSLI SCK, SIN SCK ↓→ valid SIN hold time tSLIXI SCK, SIN Value Condition Unit Min Max 5 tMCLK*3 — ns + 95 ns — ns — ns Internal clock − 95 operation output pin: 3 CL = 80 pF + 1 TTL tMCLK* + 190 0 Serial clock “H” pulse width tSHSL SCK 3t * − tR — ns Serial clock “L” pulse width tSLSH SCK tMCLK*3 + 95 — ns SCK ↑→ SOT delay time tSHOVE SCK, SOT — 2 tMCLK*3 + 95 ns Valid SIN → SCK ↓ tIVSLE SCK, SIN 190 — ns * + 95 — ns SCK ↓→ valid SIN hold time tSLIXE SCK, SIN MCLK 3 External clock operation output pin: CL = 80 pF + 1 TTL MCLK 3 t SCK fall time tF SCK — 10 ns SCK rise time tR SCK — 10 ns *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “(2) Source Clock / Machine Clock” for tMCLK. 62 DS07–12627–7E MB95260H/270H/280H Series • Internal shift clock mode tSCYC 2.4 V 2.4 V SCK 0.8 V tSHOVI 2.4 V SOT 0.8 V tIVSLI tSLIXI 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC • External shift clock mode tSHSL 0.8 VCC tSLSH 0.8 VCC SCK 0.2 VCC tR tF 0.2 VCC 0.2 VCC tSHOVE 2.4 V SOT 0.8 V tIVSLE tSLIXE 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC DS07–12627–7E 63 MB95260H/270H/280H Series Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK ↑→ SOT delay time tSHOVI SCK, SOT Valid SIN → SCK ↓ tIVSLI SCK, SIN SCK ↓→ valid SIN hold time tSLIXI SCK, SIN SOT → SCK ↓ delay time tSOVLI SCK, SOT Value Condition Unit Min Max 5 tMCLK*3 — ns + 95 ns — ns — ns 4 tMCLK*3 ns − 95 Internal clock operation output pin: tMCLK*3 + 190 CL = 80 pF + 1 TTL 0 — *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: See “(2) Source Clock / Machine Clock” for tMCLK. tSCYC 2.4 V SCK 0.8 V SOT 2.4 V 2.4 V 0.8 V 0.8 V tIVSLI SIN 64 0.8 V tSHOVI tSOVLI tSLIXI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC DS07–12627–7E MB95260H/270H/280H Series Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK ↓→ SOT delay time tSLOVI SCK, SOT Valid SIN → SCK ↑ tIVSHI SCK, SIN SCK ↑→ valid SIN hold time tSHIXI SCK, SIN SOT → SCK ↑ delay time tSOVHI Value Condition Unit Min Max 5 tMCLK*3 — ns + 95 ns — ns — ns − 95 Internal clock operating output pin: tMCLK*3 + 190 CL = 80 pF + 1 TTL 0 SCK, SOT — 4t MCLK 3 * ns *1:There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: See “(2) Source Clock / Machine Clock” for tMCLK. tSCYC 2.4 V SCK 2.4 V 0.8 V tSOVHI SOT 2.4 V 0.8 V 0.8 V tIVSHI SIN DS07–12627–7E tSLOVI 2.4 V tSHIXI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 65 MB95260H/270H/280H Series (7) Low-voltage Detection (VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Value Min Typ Max Unit Remarks Release voltage VDL+ 2.52 2.7 2.88 V At power supply rise Detection voltage VDL− 2.42 2.6 2.78 V At power supply fall Hysteresis width VHYS 70 100 — mV Power supply start voltage Voff — — 2.3 V Power supply end voltage Von 4.9 — — V Power supply voltage change time (at power supply rise) tr 3000 — — µs Slope of power supply that the reset release signal generates within the rating (VDL+) Power supply voltage change time (at power supply fall) tf 300 — — µs Slope of power supply that the reset detection signal generates within the rating (VDL-) Reset release delay time td1 — — 300 µs Reset detection delay time td2 — — 20 µs VCC Von Voff time tf tr VDL+ VHYS VDL- Internal reset signal time td2 66 td1 DS07–12627–7E MB95260H/270H/280H Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = -40°C to + 85°C) Parameter Symbol Resolution Total error Linearity error — Differential linear error Value Unit Min Typ Max — — 10 bit −3 — +3 LSB − 2.5 — + 2.5 LSB − 1.9 — + 1.9 LSB Remarks Zero transition voltage VOT VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB V Full-scale transition voltage VFST VCC − 4.5 LSB VCC − 2 LSB VCC + 0.5 LSB V 0.9 — 16500 µs 4.5 V ≤ VCC ≤ 5.5 V 1.8 — 16500 µs 4.0 V ≤ VCC < 4.5 V 0.6 — ∞ µs 4.5 V ≤ VCC ≤ 5.5 V, with external impedance < 5.4 kΩ 1.2 — ∞ µs 4.0 V ≤ VCC < 4.5 V, with external impedance < 2.4 kΩ Compare time Sampling time — — Analog input current IAIN − 0.3 — + 0.3 µA Analog input voltage VAIN VSS — VCC V DS07–12627–7E 67 MB95260H/270H/280H Series (2) Notes on Using the A/D Converter • External impedance of analog input and its sampling time • The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit Analog input Comparator R C During sampling: ON 4.5 V < VCC < 5.5 V : R ~ ~ 1.95 kΩ (Max), C ~ ~ 17 pF (Max) 4.0 V < VCC < 4.5 V : R ~ ~ 8.98 kΩ (Max), C ~ ~ 17 pF (Max) Note: The values are reference values. • Relationship between external impedance and minimum sampling time [External impedance = 0 kΩ to 20 kΩ] [External impedance = 0 kΩ to 100 kΩ] 20 External impedance [kΩ] External impedance [kΩ] 100 90 80 70 60 (VCC > 4.5 V) 50 (VCC > 4.0 V) 40 30 20 10 18 16 14 12 (VCC > 4.5 V) 10 (VCC > 4.0 V) 8 6 4 2 0 0 0 2 4 6 8 10 12 Minimum sampling time [μs] 14 0 1 2 3 4 Minimum sampling time [μs] • A/D conversion error As |VCC−VSS| decreases, the A/D conversion error increases proportionately. 68 DS07–12627–7E MB95260H/270H/280H Series (3) Definitions of A/D Converter Terms • Resolution It indicates the level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit: LSB) It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device. • Differential linear error (unit: LSB) It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value. • Total error (unit: LSB) It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. Ideal I/O characteristics 3FFH Total error 3FFH VFST 3FEH 3FEH 2 LSB 004H 003H 3FDH Digital output Digital output 3FDH VOT Actual conversion characteristic {1 LSB × (N-1) + 0.5 LSB} 004H VNT 003H 1 LSB 002H 002H 001H 001H Actual conversion characteristic Ideal characteristic 0.5 LSB VSS Analog input 1 LSB = VCC VCC - VSS (V) 1024 VSS Analog input VCC VNT - {1 LSB × (N - 1) + 0.5 LSB} Total error of = [LSB] digital output N 1 LSB N : A/D converter digital output value VNT : Voltage at which the digital output transits from (N - 1)H to NH (Continued) DS07–12627–7E 69 MB95260H/270H/280H Series (Continued) Zero transition error Full-scale transition error 004H Ideal characteristic Actual conversion characteristic 3FFH Actual conversion characteristic Digital output Digital output 003H 002H Actual conversion characteristic Ideal characteristic 3FEH VFST (measurement value) 3FDH Actual conversion characteristic 001H 3FCH VOT (measurement value) VSS VCC Analog input VSS Linearity error 3FEH Ideal characteristic Actual conversion characteristic (N + 1)H Actual conversion characteristic {1 LSB × N + VOT} 3FDH Digital output Differential linearity error VFST (measurement value) VNT 004H Actual conversion characteristic 003H 002H Digital output 3FFH VCC Analog input V(N+1)T NH VNT (N - 1)H Ideal characteristic Actual conversion characteristic (N - 2)H 001H VOT (measurement value) VSS Analog input VCC VNT - {1 LSB × N + VOT} Linearity error = of digital output N 1 LSB N VSS VCC Analog input Differential linear error V(N+1)T - VNT = - 1 of digital output N 1 LSB : A/D converter digital output value VNT : Voltage at which the digital output transits from (N - 1)H to NH VOT (ideal value) = VSS + 0.5 LSB [V] VFST (ideal value) = VCC - 2 LSB [V] 70 DS07–12627–7E MB95260H/270H/280H Series 6. Flash Memory Program/Erase Characteristics Parameter Value Unit Remarks Min Typ Max Sector erase time (2 Kbyte sector) — 0.2*1 0.5*2 s The time of writing 00H prior to erasure is excluded. Sector erase time (16 Kbyte sector) — 0.5*1 7.5*2 s The time of writing 00H prior to erasure is excluded. Byte writing time — 21 6100*2 µs System-level overhead is excluded. 100000 — — cycle Power supply voltage at program/erase 3.0 — 5.5 V Flash memory data retention time 20*3 — — Program/erase cycle year Average TA = + 85°C *1: TA = + 25 °C, VCC = 5.0 V, 100000 cycles *2: TA = + 85 °C, VCC = 3.0 V, 100000 cycles *3: This value is converted from the result of a technology reliability assessment. (The value is converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature being + 85°C) . DS07–12627–7E 71 MB95260H/270H/280H Series ■ SAMPLE CHARACTERISTICS • Power supply current temperature 20 20 15 15 Icc [mA] Icc [mA] Icc − TA Icc − Vcc TA = + 25 °C FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Vcc = 5.5 V FMP = 10, 16 MHz (divided by 2) Main clock mode with the external clock operating Main clock mode with the external clock operating FMP = 16 MHz 10 FMP = 10 MHz FMP = 8 MHz 5 FMP = 16 MHz 10 FMP = 10 MHz 5 FMP = 4 MHz FMP = 2 MHz 0 2 3 4 5 Vcc [V] 6 0 −50 7 20 20 15 15 10 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 5 0 2 3 4 5 Vcc [V] 6 +100 +150 10 FMP = 16 MHz 5 FMP = 10MHz 0 −50 7 ICCL − Vcc TA = + 25 °C FMPL = 16 kHz (divided by 2) Subclock mode with the external clock operating 100 100 75 75 50 0 +50 TA [°C] +100 +150 ICCL − TA Vcc = 5.5 V FMPL = 16 kHz (divided by 2) Subclock mode with the external clock operating Icc L [μA] Icc L [μA] +50 TA [°C] Iccs − TA Vcc = 5.5 V FMP = 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating ICCS [mA] ICCS [mA] Iccs − Vcc TA = + 25 °C FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating 0 50 25 25 0 0 2 3 4 5 Vcc [V] 6 7 −50 0 +50 TA [°C] +100 +150 (Continued) 72 DS07–12627–7E MB95260H/270H/280H Series ICCLS − TA Vcc = 5.5 V FMPL = 16 kHz (divided by 2) Subsleep mode with the external clock operating 80 80 70 70 60 60 Icc LS [μA] Icc LS [μA] ICCLS − Vcc TA = + 25 °C FMPL = 16 kHz (divided by 2) Subsleep mode with the external clock operating 50 40 30 20 20 10 10 2 3 4 Vcc [V] 5 6 0 −50 7 ICCT − Vcc TA = + 25 °C FMPL = 16 kHz (divided by 2) Watch mode with the external clock operating 0 +50 TA [°C] +100 +150 ICCT − TA Vcc = 5.5 V FMPL = 16 kHz (divided by 2) Watch mode with the external clock operating 20 20 16 16 Icc T [μA] Icc T [μA] 40 30 0 12 12 8 8 4 4 0 −50 0 2 3 4 5 Vcc [V] 6 7 ICTS − Vcc TA = + 25 °C FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating 1.4 1.4 1.2 1.2 1 1 0.8 FMP = 16 MHz 0.6 FMP = 10 MHz FMP = 8 MHz 0.4 0 +50 TA [°C] +100 +150 ICTS − TA Vcc = 5.5 V FMP = 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating ICTS [mA] ICTS [mA] 50 FMP = 16 MHz 0.8 0.6 FMP = 10 MHz 0.4 FMP = 4 MHz 0.2 FMP = 2 MHz 0 2 3 4 Vcc [V] 5 6 7 0.2 0 −50 0 +50 TA [°C] +100 +150 (Continued) DS07–12627–7E 73 MB95260H/270H/280H Series (Continued) ICCH − TA Vcc = 5.5 V FMPL = (stop) Substop mode with the external clock stopping 20 20 16 16 12 12 Icc H [μA] Icc H [ A] ICCH − Vcc TA = + 25 °C FMPL = (stop) Substop mode with the external clock stopping 8 4 4 0 −50 0 2 3 4 Vcc [V] 5 6 7 ICCMCR − Vcc TA = + 25 °C FMP = 1, 8, 10 MHz (no division) Main clock mode with the main CR clock operating 0 +50 TA [°C] 20 20 15 15 FMP = 10 MHz FMP = 8 MHz FMP = 10 MHz FMP = 8 MHz 5 FMP = 1 MHz FMP = 1 MHz 0 2 3 4 Vcc [V] 5 6 0 −50 7 ICCSCR − Vcc TA = + 25 °C FMPL = 50 kHz (divided by 2) Subclock mode with the sub-CR clock operating 0 +50 TA [°C] +100 +150 ICCSCR − TA Vcc = 5.5 V FMPL = 50 kHz (divided by 2) Subclock mode with the sub-CR clock operating 200 200 150 150 ICCSCR [μA] ICCSCR [μA] +150 10 10 5 100 100 50 50 0 0 2 74 +100 ICCMCR − TA Vcc = 5.5 V FMP = 1, 8, 10 MHz (no division) Main clock mode with the main CR clock operating ICCMCR [mA] ICCMCR [mA] 8 3 4 5 Vcc [V] 6 7 −50 0 +50 TA [°C] +100 +150 DS07–12627–7E MB95260H/270H/280H Series • Input voltage VIHS - VCC and VILS - VCC TA=+25°C 5 5 4 4 VIHI 3 VIHS/VILS[V] VIHI/VILI[V] VIHI - VCC and VILI - VCC TA=+25°C VILI 2 1 VIHS 3 VILS 2 1 0 0 2 3 4 5 6 7 2 3 VCC[V] 4 5 6 7 VCC[V] VIHM - VCC and VILM - VCC TA=+25°C 5 VIHM/VILM[V] 4 3 VIHM VILM 2 1 0 2 3 4 5 6 7 VCC[V] DS07–12627–7E 75 MB95260H/270H/280H Series • Output voltage (Vcc − VOH2) − IOH TA = + 25 °C 1 1 0.8 0.8 Vcc - VOH2 [V] Vcc - VOH1 [V] (Vcc − VOH1) − IOH TA = + 25 °C 0.6 0.4 0.2 0.6 0.4 0.2 0 0 −2 0 −4 −6 IOH [mA] −8 −10 −2 0 −4 −6 −8 IOH [mA] Vcc = 2.4 V Vcc = 2.7 V Vcc = 3.5 V Vcc = 4.5 V Vcc = 5.0 V Vcc = 5.5 V Vcc = 2.4 V Vcc = 2.7 V Vcc = 3.5 V Vcc = 4.5 V Vcc = 5.0 V Vcc = 5.5 V VOL1 − IOL TA = + 25 °C VOL2 − IOL TA = + 25 °C −10 −12 0.6 1 VOL2 [V] VOL1 [V] 0.8 0.6 0.4 0.4 0.2 0.2 0 0 0 2 4 6 IOL [mA] 8 Vcc = 2.4 V Vcc = 2.7 V Vcc = 3.5 V Vcc = 4.5 V Vcc = 5.0 V Vcc = 5.5 V 76 10 0 2 4 6 8 IOL [mA] 10 12 Vcc = 2.4 V Vcc = 2.7 V Vcc = 3.5 V Vcc = 4.5 V Vcc = 5.0 V Vcc = 5.5 V DS07–12627–7E MB95260H/270H/280H Series • Pull-up RPULL-Vcc TA = + 25 °C 250 RPULL [kΩ] 200 150 100 50 0 2 DS07–12627–7E 3 4 VCC [V] 5 6 77 MB95260H/270H/280H Series ■ MASK OPTIONS No. Part Number MB95F262H MB95F263H MB95F264H MB95F272H MB95F273H MB95F274H MB95F282H MB95F283H MB95F284H Selectable/Fixed MB95F262K MB95F263K MB95F264K MB95F272K MB95F273K MB95F274K MB95F282K MB95F283K MB95F284K Fixed 1 Low-voltage detection reset Without low-voltage detection reset 2 Reset 78 With dedicated reset input With low-voltage detection reset Without dedicated reset input DS07–12627–7E MB95260H/270H/280H Series ■ ORDERING INFORMATION Part Number MB95F262HWQN-G-SNE1 MB95F262HWQN-G-SNERE1 MB95F262KWQN-G-SNE1 MB95F262KWQN-G-SNERE1 MB95F263HWQN-G-SNE1 MB95F263HWQN-G-SNERE1 MB95F263KWQN-G-SNE1 MB95F263KWQN-G-SNERE1 MB95F264HWQN-G-SNE1 MB95F264HWQN-G-SNERE1 MB95F264KWQN-G-SNE1 MB95F264KWQN-G-SNERE1 MB95F262HP-G-SH-SNE2 MB95F262KP-G-SH-SNE2 MB95F263HP-G-SH-SNE2 MB95F263KP-G-SH-SNE2 MB95F264HP-G-SH-SNE2 MB95F264KP-G-SH-SNE2 MB95F262HPF-G-SNE2 MB95F262KPF-G-SNE2 MB95F263HPF-G-SNE2 MB95F263KPF-G-SNE2 MB95F264HPF-G-SNE2 MB95F264KPF-G-SNE2 MB95F262HPFT-G-SNE2 MB95F262KPFT-G-SNE2 MB95F263HPFT-G-SNE2 MB95F263KPFT-G-SNE2 MB95F264HPFT-G-SNE2 MB95F264KPFT-G-SNE2 MB95F282HWQN-G-SNE1 MB95F282HWQN-G-SNERE1 MB95F282KWQN-G-SNE1 MB95F282KWQN-G-SNERE1 MB95F283HWQN-G-SNE1 MB95F283HWQN-G-SNERE1 MB95F283KWQN-G-SNE1 MB95F283KWQN-G-SNERE1 MB95F284HWQN-G-SNE1 MB95F284HWQN-G-SNERE1 MB95F284KWQN-G-SNE1 MB95F284KWQN-G-SNERE1 MB95F282HPH-G-SNE2 MB95F282KPH-G-SNE2 MB95F283HPH-G-SNE2 MB95F283KPH-G-SNE2 MB95F284HPH-G-SNE2 MB95F284KPH-G-SNE2 Package 32-pin plastic QFN (LCC-32P-M19) 24-pin plastic SDIP (DIP-24P-M07) 20-pin plastic SOP (FPT-20P-M09) 20-pin plastic TSSOP (FPT-20P-M10) 32-pin plastic QFN (LCC-32P-M19) 16-pin plastic DIP (DIP-16P-M06) (Continued) DS07–12627–7E 79 MB95260H/270H/280H Series (Continued) Part Number MB95F282HPF-G-SNE1 MB95F282KPF-G-SNE1 MB95F283HPF-G-SNE1 MB95F283KPF-G-SNE1 MB95F284HPF-G-SNE1 MB95F284KPF-G-SNE1 MB95F272HPH-G-SNE2 MB95F272KPH-G-SNE2 MB95F273HPH-G-SNE2 MB95F273KPH-G-SNE2 MB95F274HPH-G-SNE2 MB95F274KPH-G-SNE2 MB95F272HPF-G-SNE2 MB95F272KPF-G-SNE2 MB95F273HPF-G-SNE2 MB95F273KPF-G-SNE2 MB95F274HPF-G-SNE2 MB95F274KPF-G-SNE2 80 Package 16-pin plastic SOP (FPT-16P-M06) 8-pin plastic DIP (DIP-8P-M03) 8-pin plastic SOP (FPT-8P-M08) DS07–12627–7E MB95260H/270H/280H Series ■ PACKAGE DIMENSION 24-pin plastic SDIP Lead pitch 1.778 mm Package width × package length 6.40 mm × 22.86 mm Sealing method Plastic mold Mounting height 4.80 mm Max (DIP-24P-M07) 24-pin plastic SDIP (DIP-24P-M07) Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion. #22.86±0.10(.900±.004) 24 13 BTM E-MARK INDEX 6.40±0.10 (.252±.004) 1 7.62(.300) TYP. 12 0.50(.020) MIN 4.80(.189)MAX +0.10 +0.20 0.25 –0.04 +.008 +.004 3.00 –0.30 .118 –.012 1.778(.070) C .010 –.002 1.00±0.10 (.039±.004) +0.09 0.43 –0.04 +.004 .017 –.002 2008-2010 FUJITSU SEMICONDUCTOR LIMITED D24066S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07–12627–7E 81 MB95260H/270H/280H Series 32-pin plastic QFN Lead pitch 0.50 mm Package width × package length 5.00 mm × 5.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.06 g (LCC-32P-M19) 32-pin plastic QFN (LCC-32P-M19) 3.50±0.10 (.138±.004) 5.00±0.10 (.197±.004) 5.00±0.10 (.197±.004) 3.50±0.10 (.138±.004) INDEX AREA 0.25 (.010 (3-R0.20) ((3-R.008)) 0.50(.020) +0.05 –0.07 +.002 –.003 ) 0.40±0.05 (.016±.002) 1PIN CORNER (C0.30(C.012)) (TYP) 0.75±0.05 (.030±.002) 0.02 (.001 C +0.03 –0.02 +.001 –.001 (0.20(.008)) ) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 82 DS07–12627–7E MB95260H/270H/280H Series 20-pin plastic SOP Lead pitch 1.27 mm Package width × package length 7.50 mm × 12.70 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 2.65 mm Max (FPT-20P-M09) 20-pin plastic SOP (FPT-20P-M09) Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion. 0.25 #12.70±0.10(.500±.004) +0.07 –0.02 +.003 .010 –.001 20 11 BTM E-MARK +0.40 #7.50±0.10 10.2 –0.20 (.295±.004) .402 +.016 –.008 INDEX Details of "A" part +0.13 2.52 –0.17 (Mounting height) +.005 .099 –.007 1 "A" 10 1.27(.050) 0.40 .016 +0.09 –0.05 +.004 –.002 0.25(.010) M 0~8° +0.47 0.80 –0.30 +.019 .031 –.012 0.20±0.10 (.008±.004) (Stand off) 0.10(.004) C 2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07–12627–7E 83 MB95260H/270H/280H Series 20-pin plastic TSSOP Lead pitch 0.65 mm Package width × package length 4.40 mm × 6.50 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm MAX Weight 0.08 g (FPT-20P-M10) 20-pin plastic TSSOP (FPT-20P-M10) Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion. +0.05 0.14 –0.04 #6.50±0.10(.256±.004) +.002 .006 –.002 11 20 BTM E-MARK #4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part LEAD No. 1 1.20(.047) (Mounting height) MAX 10 0.65(.026) "A" 0.24±0.04 (.009±.002) 0~8° 0.60±0.15 (.024±.006) 0.10(.004) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F20031S-c-1-2 0.10±0.05 (.004±.002) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 84 DS07–12627–7E MB95260H/270H/280H Series 16-pin plastic DIP Lead pitch 2.54 mm Sealing method Plastic mold (DIP-16P-M06) 16-pin plastic DIP (DIP-16P-M06) 19.55 .770 +0.20 –0.30 +.008 –.012 INDEX 6.35±0.25 (.250±.010) 7.62(.300) TYP. 0.50(.020) MIN 4.36(.172)MAX 0.25±0.05 (.010±.002) 3.00(.118)MIN 1.52 –0 MAX .060 –0 +.012 +0.30 0.99 –0 +.012 .039 –0 C +0.30 1.27(.050) 0.46±0.08 (.018±.003) 2.54(.100) TYP. 2006-2010 FUJITSU SEMICONDUCTOR LIMITED D16125S-c-1-3 15° MAX Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07–12627–7E 85 MB95260H/270H/280H Series 16-pin plastic SOP (FPT-16P-M06) 16-pin plastic SOP (FPT-16P-M06) Lead pitch 1.27 mm Package width × package length 5.3 × 10.15 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 2.25 mm MAX Weight 0.20 g Code (Reference) P-SOP16-5.3×10.15-1.27 Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +0.25 +.010 +0.03 *110.15 –0.20 .400 –.008 0.17 –0.04 +.001 16 .007 –.002 9 *2 5.30±0.30 7.80±0.40 (.209±.012) (.307±.016) INDEX Details of "A" part +0.25 2.00 –0.15 +.010 .079 –.006 1 "A" 8 1.27(.050) 0.47±0.08 (.019±.003) 0.13(.005) (Mounting height) 0.25(.010) 0~8° M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) +0.10 0.10 –0.05 +.004 .004 –.002 (Stand off) 0.10(.004) C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F16015S-c-4-9 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 86 DS07–12627–7E MB95260H/270H/280H Series 8-pin plastic DIP Lead pitch 2.54 mm Sealing method Plastic mold (DIP-8P-M03) 8-pin plastic DIP (DIP-8P-M03) 9.40 .370 8 +0.40 –0.30 +.016 –.012 5 INDEX 6.35±0.25 (.250±.010) 1 4 7.62(.300) TYP. 4.36(.172)MAX 0.50(.020) MIN 0.25±0.05 (.010±.002) 3.00(.118)MIN +0.35 0.46±0.08 (.018±.003) 0.89 –0.30 +.014 .035 –.012 +0.30 0.99 –0 +.012 .039 –0 C +0.30 1.52 –0 15° MAX +.012 .060 –0 2.54(.100) TYP. 2006-2010 FUJITSU SEMICONDUCTOR LIMITED D08008S-c-1-4 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07–12627–7E 87 MB95260H/270H/280H Series (Continued) 8-pin plastic SOP Lead pitch 1.27 mm Package width × package length 5.30 mm × 5.24 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 2.10 mm Max (FPT-8P-M08) 8-pin plastic SOP (FPT-8P-M08) Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) # : These dimensions do not include resin protrusion. #5.24±0.10 (.206±.004) 8 5 "A" BTM E-MARK #5.30±0.10 (.209±.004) INDEX 7.80 .307 +0.45 –0.10 +.018 –.004 Details of "A" part 2.10(.083) MAX (Mounting height) 1 1.27(.050) 4 0.43±0.05 (.017±.002) 0.20±0.05 (.008±.002) 0~8° +0.15 0.10 –0.05 +.006 .004 –.002 (Stand off) C 2008-2010 FUJITSU SEMICONDUCTOR LIMITED F08016S-c-1-2 +0.10 0.75 –0.20 +.004 .030 –.008 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 88 DS07–12627–7E MB95260H/270H/280H Series ■ MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section 1 — Details Changed the family name. F2MC-8FX → New 8FX 2 ■ FEATURES Added “• Power-on reset”. 3 ■ PRODUCT LINE-UP • MB95260H Series Added the parameter “Power-on reset”. 5 ■ PRODUCT LINE-UP • MB95270H Series Added the parameter “Power-on reset”. 6 ■ PRODUCT LINE-UP • MB95280H Series Added the parameter “Power-on reset”. 10 ■ PIN ASSIGNMENT Deleted the HCLK1 pin and the HCLK2 pin. 11 Deleted the HCLK1 pin and the HCLK2 pin. 13 ■ PIN DESCRIPTION (MB95260H Series, 32 pins) Deleted the HCLK1 pin and the HCLK2 pin. 15 ■ PIN DESCRIPTION (MB95260H Series, 24 pins) Deleted the HCLK1 pin and the HCLK2 pin. 17 ■ PIN DESCRIPTION (MB95260H Series, 20 pins) Deleted the HCLK1 pin and the HCLK2 pin. 18 ■ PIN DESCRIPTION (MB95270H Series, 8 pins) Deleted the HCLK1 pin and the HCLK2 pin. 19 ■ PIN DESCRIPTION (MB95280H Series, 32 pins) Deleted the HCLK1 pin. 20 21 22 ■ PIN DESCRIPTION (MB95280H Series, 16 pins) Deleted the HCLK2 pin. Deleted the HCLK1 pin. Deleted the HCLK2 pin. 27 ■ BLOCK DIAGRAM (MB95260H Series) Deleted the HCLK1 pin and the HCLK2 pin. 28 ■ BLOCK DIAGRAM (MB95270H Series) Deleted the HCLK1 pin and the HCLK2 pin. 29 ■ BLOCK DIAGRAM (MB95280H Series) Deleted the HCLK1 pin and the HCLK2 pin. 52, 53 ■ ELECTRICAL CHARACTERISTICS Deleted all information about the HCLK1 pin and the HCLK2 4. AC Characteristics pin in the table. (1) Clock Timing Deleted the HCLK1 pin and the HCLK2 pin in the “• Input waveform generated when an external clock (main clock) is used”. 54 Deleted the external connection diagram for the HCLK1 pin and the HCLK2 pin in “• Figure of main clock input port external connection”. DS07–12627–7E 89 MB95260H/270H/280H Series MEMO 90 DS07–12627–7E MB95260H/270H/280H Series MEMO DS07–12627–7E 91 MB95260H/270H/280H Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department