LatticeEC Standard Evaluation Board User's Guide - Revision B

LatticeEC™ Standard Evaluation Board – Revision B
User’s Guide
April 2007
ebug10_01.4
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Introduction
The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user
designs, including designs requiring PCI. The information in this document pertains only to boards marked as 'Rev
B'. This marking is located on the front of the board, beneath the Lattice logo.
Features
• Required voltages supplied by PCI or one external 5V DC supply
• ispVM® System programming support
• SPI3 Flash device included for low cost, non-volatile configuration storage
• PCI edge connector (120-pin) for 32-bit PCI interface
• Large Prototyping Area with access to over 290 I/O pins
• Optional SMA/SMB connectors (up to six) for high-speed clock and data interfacing
Figure 1. LatticeEC Standard Evaluation Board
Electrical, Mechanical and Environmental Specifications
The nominal board dimensions are 7 inches by 3.9 inches. The environmental specifications are as follows:
• Operating temperature: 0ºC to 55ºC
• Storage temperature: -40ºC to 75ºC
• Humidity: < 95% without condensation
• VDC input (+/- 10%) up to 4A, or 3.3V input from PCI backplane
Additional Resources
Additional resources related to this board can be downloaded from the web at www.latticesemi.com/boards. Click
on the appropriate evaluation board, then see the blue “Resources” box on the right of the screen for items such as:
updated documentation, software, sample designs, IP evaluation bitstreams, and more.
2
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Table 1. Embedded Functions
Description
Source
LatticeEC Pin
Notes
33.33MHz clock
On-Board Oscillator
V1/AB10
3.3V TTL Output
The 3.3V oscillator socket accepts both full-size and half-size oscillators and can route to different clock inputs,
depending on its position within the socket. The 16-pin socket will allow connection to PLL clock pin V1 when the
bottom of the oscillator is aligned to socket pins 8 and 9. When the top of the oscillator is aligned to socket pins 1
and 16, the clock is provided to primary clock pin AB10.
LatticeEC Device
This board features a LatticeEC FPGA with a 1.2V DC core. It can accommodate all pin-compatible LatticeEC
devices in plastic 484-ball fpBGA (1mm pitch) packages. A complete description of this device can be found in the
LatticeECP/EC Family Data Sheet on the Lattice web site at www.latticesemi.com.
Programming Headers
Four programming headers are provided on the evaluation board, providing access to the LatticeEC JTAG port or
the SPI Flash device. Both 1x10 and 2x5 formats are available for compatibility with all Lattice download cables.
The pinouts for the headers are provided in Tables 2 and 3.
Note: An ispDOWNLOAD® cable is included with each ispLEVER®-Base or ispLEVER-Advanced design tool shipment. Cables may also be purchased separately from Lattice.
Table 2. JTAG Programming Headers
Function
JP1 (1x10)
JP2 (2x5)
VCC (3.3V)
1
6
TDO
2
7
TDI
3
5
TMS
6
3
TCK
8
1
INITN
10
8
GND
7, 9
2, 4
Note: When using a 1x8 download cable, connect to the
1x10 header by justifying the alignment to pin 1 (VCC).
Table 3. Flash Programming Headers
Function
JP4 (1x10)
JP3 (2x5)
VCC (3.3V)
1
6
SFLASH_Q
2
7
SFLASH_D
3
5
SFLASH_S_N
4
10
SFLASH_C
8
1
GND
7, 9
2, 4
Note: When using a 1x8 download cable, connect to the
1x10 header by justifying the alignment to pin 1 (VCC).
3
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Power Setup
For stand-alone board operation (i.e. outside of a PCI backplane), the evaluation board may be supplied with a single 5V DC power supply. On-board regulators will provide the necessary supply voltages.
The on-board regulators supply 3.3V, 1.2V, and an adjustable voltage. The adjustable voltage is set by the potentiometer R9 at the upper right corner of the board and can be set to a value between 1.22V and 3.25V.
5V DC power may be applied using the power jack at J31 using an AC adapter such as the Condor Electronics S5V0-4A0-U11-206IP, or similar. Requirements for the power jack are listed in Table 4.
Table 4. Power Jack J31 Specifications
Positive Center
Polarity
Inside Diameter
0.1” (2.5mm)
Outside Diameter
0.218” (5.5mm)
Current Capacity
Up to 4A
When the evaluation board is inserted into a PCI backplane, all on-board power will be derived from the PCI 3.3V
power rail. When plugged into the PCI slot, the on-board 3.3V regulator (U4) will be disabled automatically, allowing
3.3V to be supplied directly from the PCI host system.
Power can also be supplied directly for each individual supply rail using banana jack connectors. To enable this
mode of operation, the appropriate jumpers must be removed. All power sources must be regulated to the specifications in Table 5. No special power sequencing is required for the evaluation board.
Note: A single 3.3V supply can also be used to supply all three required voltages to the LatticeEC Standard Evaluation Board. This can be achieved by disabling the 3.3V on-board regulator through the installation of jumper J29.
3.3V power can then be supplied directly to banana jack J22, providing power to the remaining regulators.
Table 5. Individual Control of Supplies
Supply
Jack
Jumper
Requirement
3.3V
J22
J26
3.3V +/- 0.3V
1.2V
J23
J27
1.2V +/- 5%
VCC_ADJ
J21
J25
User-defined1
Note: If the user-defined adjustable voltage is used for any of the LatticeEC
sysIO™ banks, it must be set to a supported voltage between 1.2V DC and 3.3V
DC.
The jumpers listed in Table 6 allow the user to select the voltage (VCCIO) applied to each of the eight I/O banks of
the LatticeEC device. Certain restrictions apply depending on which features of the board are being used.
Table 6. sysIO Bank Settings
sysIO Bank
Jumper
0
J9
1
J12
2
J15
3
J16
4
J14
5
J10
6
J8
7
J7
Settings
1-2 -> VCC_1.2v
3-4 -> VCC_3.3v
5-6 -> VCC_ADJ
4
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Table 7. sysIO Bank Considerations
Bank
Setting
1
0
Any
1
Any1
2
Any1
3
3.3V if SPI configuration mode selected, otherwise any
4
3.3V when PCI interface used, otherwise any
5
3.3V when PCI interface used, otherwise any
6
Any1
7
Any1
1. “Any” refers to any supported voltage between 1.2V and 3.3V.
The following tables detail the various standards supported by the LatticeEC FPGA Input/Output (sysIO) structures. More information can be found in Lattice technical note number TN1056, LatticeECP/EC sysIO Usage
Guide, available on the Lattice web site at www.latticesemi.com.
Table 8. Mixed Voltage Support
Input sysIO Standards
VCCIO
1.2V
1.2V
Yes
1.5V
Yes
1.8V
Yes
2.5V
Yes
3.3V
Yes
1.5V
1.8V
Yes
Yes
2.5V
Output sysIO Standards
3.3V
1.2V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.5V
1.8V
2.5V
3.3V
Yes
Yes
Yes
Yes
For example, if VCCIO is 3.3V then signals from devices powered by 1.2V, 2.5V or 3.3V can be input and the thresholds will be correct (assuming the user has selected the desired input level using ispLEVER software). Output levels are tied directly to VCCIO.
5
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Table 9. sysIO Standards Supported per Bank
Description
Top Side
Banks 0-1
Right Side
Banks 2-3
Bottom Side
Banks 4-5
Left Side
Banks 6-7
Types of I/O Buffers
Single-ended
Single-ended and
Differential
Single-ended
Single-ended and
Differential
Output Standards
Supported
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18_I, II, III
HSTL15 Class I, III
HSTL18 Class I, II, III
HSTL15 Class I, III
HSTL18 Class I, II, III
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D Class I, II
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I, III,
HSTL18D Class I, III
HSTL15D Class I, III
HSTL18D Class I, III
HSTL15D Class I, III
HSTL18D Class I, III
HSTL15D Class I, III
HSTL18D Class I, III
PCI33
LVDS25E1
LVPECL1
BLVDS1
RSDS1
PCI33
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
PCI33
LVDS25E1
LVPECL1
BLVDS1
RSDS1
PCI33
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
Clock Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
PCI Support
PCI33 with clamp
PCI33 no clamp
PCI33 with clamp
LVDS Output Buffers
LVDS (3.5mA) Buffers
PCI no clamp
LVDS (3.5mA) Buffers
1. These differential standards are implemented by using complementary LVCMOS driver with external resistor pack.
PCI
The LatticeEC Evaluation Board is designed to interface directly to PCI 2.2 compatible systems using the PCI edge
connector. All necessary signals required for 32-bit PCI operation are provided to the connector, as shown in
Tables 10 and 11.
Table 10. PCI Connections – Solder Side
J32
Description
LatticeEC Pin
sysIO Bank
6
PCI_INTA_N
AB5
5
7
PCI_INTC_N
AB6
5
15
PCI_RST_N
AB7
5
17
PCI_GNT_N
Y8
5
20
PCI_AD30
AB9
5
22
PCI_AD28
Y9
5
23
PCI_AD26
V9
5
25
PCI_AD24
AA10
5
6
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Table 10. PCI Connections – Solder Side (Continued)
J32
Description
LatticeEC Pin
sysIO Bank
26
PCI_IDSEL
W10
5
28
PCI_AD22
U10
5
29
PCI_AD20
AA11
5
31
PCI_AD18
W11
5
32
PCI_AD16
AB12
4
34
PCI_FRAME_N
Y12
4
36
PCI_TRDY_N
V12
5
38
PCI_STOP_N
AA13
4
43
PCI_PAR
U13
4
44
PCI_AD15
AA14
4
46
PCI_AD13
W14
4
47
PCI_AD11
U14
4
49
PCI_AD9
AA15
4
52
PCI_CBE0_N
AA16
4
54
PCI_AD6
V15
4
55
PCI_AD4
AA17
4
57
PCI_AD2
AA18
4
58
PCI_AD0
AB19
4
Description
LatticeEC Pin
sysIO Bank
7
PCI_INTB_N
AA6
5
8
PCI_INTD_N
AA7
5
9
PCI_PRSNT1_N
Y7
5
11
PCI_PRSNT2_N
W8
5
Table 11. PCI Connections - Component Side
J3
16
PCI_CLK
U20
3
18
PCI_REQ_N
AB8
5
20
PCI_AD31
AA8
5
21
PCI_AD29
AA9
5
23
PCI_AD27
W9
5
24
PCI_AD25
U9
5
26
PCI_CBE3_N
Y10
5
27
PCI_AD23
V10
5
29
PCI_AD21
AB11
5
30
PCI_AD19
Y11
5
32
PCI_AD17
V11
5
33
PCI_CBE2_N
AA12
4
35
PCI_IRDY_N
W12
4
37
PCI_DEVSEL_N
AB13
4
40
PCI_PERR_N
W13
4
42
PCI_SERR_N
V13
4
44
PCI_CBE1_N
AB14
4
45
PCI_AD14
Y14
4
7
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Table 11. PCI Connections - Component Side (Continued)
J3
Description
LatticeEC Pin
sysIO Bank
47
PCI_AD12
V14
4
48
PCI_AD10
AB15
4
52
PCI_AD8
Y15
4
53
PCI_AD7
W15
4
55
PCI_AD5
AB16
4
56
PCI_AD3
AB17
4
58
PCI_AD1
AB18
4
Prototype Area
For general purpose I/Os, numerous test points are provided for direct access. The test points are labeled according to the associated I/O pin location, and are listed in Table .
Table 12. LatticeEC Pins Accessible at Test Points
A3 (0)
B20 (1)
D13 (1)
F6 (0)
H5 (7)
M3 (6)
R21 (3)
W6 (5)
A4 (0)
B21 (2)
D14 (1)
F7 (0)
H6 (7)
M4 (6)
R22 (3)
W7 (5)
A6 (0)
B22 (2)
D15 (1)
F8 (0)
H17 (2)
M5 (6)
T1 (6)
W16 (4)
A7 (0)
C1 (7)
D16 (1)
F9 (0)
H18 (2)
M18 (3)
T2 (6)
W17 (4)
A8 (0)
C2 (7)
D17 (1)
F10 (0)
H19 (2)
M19 (3)
T3 (6)
W18 (4)
A9 (0)
C3 (7)
D18 (1)
F11 (1)
H20 (2)
M20 (3)
T6 (5)
W19 (3)
A10 (0)
C4 (0)
D19 (2)
F12 (1)
H21 (2)
M21 (3)
T17 (4)
W20 (3)
A11 (0)
C5 (0)
D20 (2)
F13 (1)
H22 (2)
M22 (3)
T18 (3)
W21 (3)
2
3
1
A12 (1)
C6 (0)
D21 (2)
F14 (1)
J1 (7)
N1 (6)
T20 (3)
W22 (3)
A13 (1)
C7 (0)
D22 (2)
F15 (1)
J21 (7)
N22 (6)
T22 (3)
Y1 (6)
A14 (1)
C8 (0)
E1 (7)
F16 (1)
J3 (7)
N3 (6)
U3 (6)
Y2 (6)
A15 (1)
C9 (0)
E2 (7)
F17 (1)
J4 (7)
N4 (6)
U4 (6)
Y3 (6)
A16 (1)
C10 (0)
E3 (7)
F18 (2)
J5 (7)
N5 (6)
U6 (5)
Y4 (5)
A17 (1)
C11 (0)
E4 (7)
F19 (2)
J18 (2)
N18 (3)
U7 (5)
Y5 (5)
A18 (1)
C12 (1)
E5 (7)
F20 (2)
J19 (2)
N19 (3)
U8 (5)
Y6 (5)
A194 (1)
C13 (1)
E6 (0)
F21 (2)
J20 (2)
N20 (3)
U15 (4)
Y16 (4)
A20 (1)
C14 (1)
E7 (0)
F22 (2)
K11 (7)
N21 (3)
U16 (4)
Y17 (4)
E8 (0)
1
G1 (7)
K21 (7)
N22 (3)
U17 (4)
Y18 (4)
1
2
3
AA1 (6)
C15 (1)
AA2 (6)
C16 (1)
E9 (0)
G2 (7)
K3 (7)
P1 (6)
U21 (3)
Y19 (4)
B1 (7)
C17 (1)
E10 (0)
G3 (7)
K4 (7)
P22 (6)
U22 (3)
Y20 (3)
B2 (7)
C18 (1)
E11 (0)
G4 (7)
K5 (7)
P3 (6)
V2 (6)
Y215 (3)
B3 (0)
C19 (1)
E12 (0)
G5 (7)
K18 (2)
P4 (6)
V3 (6)
Y22 (3)
B4 (0)
C20 (2)
E13 (1)
G6 (0)
K19 (2)
P5 (6)
V4 (6)
AA3 (5)
B5 (0)
C21 (2)
E14 (1)
G9 (0)
K20 (2)
P18 (3)
V6 (5)
AA4 (5)
B7 (0)
C22 (2)
E15 (1)
G10 (0)
K21 (3)
P19 (3)
V7 (5)
AA5 (5)
B8 (0)
D1 (7)
E16 (1)
G13 (1)
K22 (3)
P20 (3)
V8 (5)
AA19 (4)
B9 (0)
D2 (7)
E17 (1)
G14 (1)
L12 (6)
P21 (3)
V16 (4)
AA20 (4)
B10 (0)
D3 (7)
E18 (2)
G17 (1)
L22 (6)
P22 (3)
V17 (4)
AA21 (3)
B11 (0)
D4 (7)
E19 (2)
G18 (2)
L4 (6)
R1 (6)
V19 (3)
AA22 (3)
B12 (1)
D5 (0)
E20 (2)
G19 (2)
L5 (6)
R2 (6)
V20 (3)
AB3 (5)
R3 (6)
3
AB4 (5)
B13 (1)
D6 (0)
E21 (2)
G20 (2)
L18 (2)
8
V21 (3)
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Table 12. LatticeEC Pins Accessible at Test Points (Continued)
B14 (1)
D7 (0)
E22 (2)
G21 (2)
L19 (2)
R4 (6)
V223 (3)
AB20 (4)
B15 (1)
D8 (0)
F1 (7)
G22 (2)
L20 (3)
R5 (6)
W1 (6)
AB21 (3)
1
B16 (1)
D9 (0)
F2 (7)
H1 (7)
L21 (3)
R6 (6)
W2 (6)
B17 (1)
D10 (0)
F3 (7)
H21 (7)
L22 (3)
R17 (3)
W3 (6)
2
R18 (3)
W4 (6)
R19 (3)
W5 (5)
B18 (1)
D11 (0)
F4 (7)
H3 (7)
M1 (6)
B19 (1)
D12 (1)
F5 (7)
H4 (7)
M22 (6)
Note: sysIO Bank indicated in parenthesis.
1. Also connected to LEDs. See Table 15 for more information.
2. Also connected to SW1. See Table 13 for more information.
3. Also connected to SPI configuration signals. See Figures 11 and 12.
4. Also connected to momentary switch SW2.
5. Also connected to J34.
Switches
Switch 1 (SW1) on the left side of the board is an eight-switch block that is part of the prototyping area. The pull-up
resistors associated with SW1 are wired to 3.3V but any I/O voltage up to 3.3V may be used. A switch in the down
position produces a low (0), while the up position produces a high (1).
Table 13. SW1 Connections
Switch
I/O Ball
sysIO Bank
SW1(1)
L1
6
SW1(2)
L2
6
SW1(3)
M1
6
SW1(4)
M2
6
SW1(5)
N1
6
SW1(6)
N2
6
SW1(7)
P1
6
SW1(8)
P2
6
SW2 is a momentary switch that the user can define for any purpose, such as a global reset. SW2 is wired to I/O
ball A19 (bank 1) and applies a low logic level when depressed.
SW3 is a momentary switch that, when pressed, forces the FPGA to start its programming cycle.
Jumpers
A jumper installed on J34 provides a connection between the configuration clock (CCLK) and a general-purpose
I/O. This connection is provided for programming the SPI Flash device via the ispJTAG™ interface. For more information, please refer to Lattice technical note number TN1078, SPI Serial Flash Programming Using ispJTAG on
LatticeECP/EC FPGAs.
The headers at J28, J29, and J30 (not installed) allow the user to disable the voltage regulators. J28 is used to disable the adjustable voltage, J29 for 3.3V, and J30 for 1.2V. Installing the jumper disables the regulator.
The jumpers at J25, J26, and J27 disconnect the regulators from the rest of the board. These jumpers are removed
if the user is supplying the voltage with an external supply. For normal operation, install all of these jumpers. The
jumpers must be installed horizontally. See Table 5 for more information.
The jumpers at J20 determine which type of device the FPGA expects to receive programming information from
and whether the FPGA will be master or slave during the transfer. Table 14 lists the possible configuration modes.
Installing the jumper produces a low (0), removing the jumper produces a high (1).
9
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Table 14. LatticeEC Configuration Mode Settings
CFG2
CFG1
CFG0
Configuration Mode
0
0
0
SPI3 Flash
0
0
1
SPIX Flash
1
0
0
Master Serial
1
0
1
Slave Serial
1
1
0
Master Parallel
1
1
1
Slave Parallel
X
X
X
ispJTAG (always available)
LEDs
Eight user-definable LEDs are provided on the upper left side of the board above SW1. These LEDs are each wired
to a separate general purpose I/O as defined in the Table 15. The current limiting resistors associated with these
LEDs are wired to 3.3V but it is safe to use any FPGA I/O voltage. The LED will light when its associated I/O pin is
driven low.
Table 15. LED Connections
LED
I/O Ball
sysIO Bank
D1
G1
7
D2
G2
7
D3
H1
7
D4
H2
7
D5
J1
7
D6
J2
7
D7
K1
7
D8
K2
7
Miscellaneous
Pads are provided in six locations to allow the user to install SMA or SMB style connectors. This allows a highspeed interface for clocks or general purpose I/O. Table 16 indicates the I/O pin connections to each SMA connector pad. The dimensions on the pads are such that any standard SMA or SMB connector with dimensions similar to
the Molex 73391-0060 are compatible.
Table 16. SMA Connections
Location
I/O Ball
sysIO Bank
J1
AA2
6
GP I/O (T)
Description
J4
AA1
6
GP I/O (C)
J5
B6
0
GP I/O (T)
J2
A5
0
GP I/O (C)
J18
J21
2
PCLKT, GP I/O
J19
J22
2
PCLKC, GP I/O
Note: T and C can be used as a differential pair.
10
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Download Procedure
Requirements:
• PC with ispVM System v.14.2 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable).
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (pDS4102-DL2, HW7265-DL3, HW-USB-1A, etc.)
JTAG Download
The LatticeEC device can be configured easily via its JTAG port. The device is SRAM-based, so it must remain
powered on to retain its configuration when programmed in this fashion.
1. Connect the ispDOWNLOAD cable to the appropriate header. JP1 is used for the 1x10 cable, while JP2 is used
for the 2x5 version.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any
other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP/EC FPGA
device and render the board inoperable.
2. Connect the LatticeEC Evaluation Board to an external 5V supply.
3. When using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (VCC).
4. Start the ispVM System software.
5. Press the ‘SCAN’ button located in the toolbar. The LatticeEC device should be automatically detected. The
resulting screen should be similar to Figure 2.
Figure 2. ispVM System Interface
11
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
6. Double-click the device to open the device information dialog, as shown in Figure 3. In the device information
dialog, click the Browse button located under ‘Data File’. Locate the desired bitstream file (.bit). Click OK to
both dialog boxes.
Figure 3. Device Information Dialog
7. Click the green ‘GO’ button. This will begin the download process into the device.
8. Upon successful download, the device will be operational.
SPI Flash Download
For non-volatile storage of configuration memory, the LatticeEC device features an interface compatible with lowcost SPI3 Flash memory devices. ispVM System has the capability to program the SPI3 Flash device directly. During the LatticeEC power-up cycle, the data stored in the SPI3 Flash device is automatically read into configuration
memory.
1. Install all three jumpers at J20 (000). This enables SPI3 mode by setting the CFG pins of the LatticeEC device.
Note: If the SPI3 Flash and the LatticeEC devices are blank, remove all three jumpers from J20. This configures the device in Slave Parallel mode, preventing the CCLK output from toggling. After the Flash device is programmed, the jumpers should be reinstalled.
2. Connect the ispDOWNLOAD cable to the appropriate header. JP4 is used for the 1x10 cable, while JP3 is used
for the 2x5 version.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any
12
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP/EC FPGA
device and render the board inoperable.
When using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (VCC).
3. Connect the evaluation board to an external 5V supply.
4. Start the ispVM System software.
5. Create a new chain file (File->New).
6. Insert a new device into the chain (Edit->Add Device).
7. In the resulting Device Information dialog, press the ‘Select’ button (see Figure 4).
Figure 4. Device Selection Dialog
8. Use the pull-down menu in the ‘Device Family’ field to choose the device ‘FPGA Loader’. Press OK. The resulting dialog should resemble Figure 5.
Figure 5. FPGA Loader Setup
9. Choose the ‘Flash Device’ page and press the ‘Select’ button.
13
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
10. Select the ‘SPI Serial Flash’ family and choose the device SPI-M25P80, as shown in Figure 6. Press OK.
Note: It may be necessary to select an alternate SPI3 Flash device, as the part number is subject to change.
Figure 6. SPI Device Selection
11. Choose the ‘Configuration Data Setup’ page, as shown in Figure 7.
Figure 7. Configuration Data Setup Page
12. Click the ‘Browse’ button near the top of the window. Browse to the desired bitstream (.bit) file, created by
ispLEVER.
13. Press OK to exit the FPGA Loader setup.
14. Click the green ‘GO’ button. This will begin the download process into the Flash device.
15. Once the operation is complete, press SW3, which forces the LatticeEC device to reconfigure. The data should
then automatically transfer from the Flash to the FPGA.
Note: If the mode was set to Slave Parallel (all jumpers removed) from Step 1, reinstall all three jumpers before
depressing SW3 to enable SPI3 configuration mode.
14
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Lattice Semiconductor
Ordering Information
Description
Ordering Part Number
LatticeEC6 Evaluation Board - Standard
China RoHS Environment-Friendly
Use Period (EFUP)
LFEC6E-L-EV
LatticeEC20 Evaluation Board - Standard
LFEC20E-L-EV
LatticeECP20 Evaluation Board - Standard
LFECP20E-L-EV
10
ispLEVER (HDL) (Base) with Lattice EC6 Development Kit LS-EC6-BASE-PC-N
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
—
—
Change Summary
March 2007
01.3
Added Ordering Information section.
April 2007
01.4
Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
Previous Lattice releases.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
15
16
A
B
C
D
5
(Sheet 6)
5
Prototyping
Support
4
4
3
(Sheet 2)
32-Bit PCI
Bank 4
Bank 3
Bank 2
Bank 1
FPGA
Bank 5
Bank 6
Bank 7
Bank 0
Prototyping
Support
(Sheet 3)
3
2
Monday, November 22, 2004
Document Number
Sheet
1
1
of
8
B
Joseph Hsin R e v
Lattice Semiconductor Corporation
LatticeEC Evaluation Board 484 fpBGA
Date:
Size
A
Title
1
Prototyping (Sheet 4)
Support
2
A
B
C
D
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Appendix A. Schematics
Figure 8. Evaluation Board Block Diagram
A
B
C
VCC_1.2V
VCC_3.3V
VCC_ADJ
TP_W7
TP_U8
TP_W7
TP_U8
OSC_PCLK
VCC_1.2V
VCC_3.3V
VCC_ADJ
[6]
AA4
AB4
TP_AA4
TP_AB4
T_AA4
T_AB4
5
1
3
5
CON6A
J10
2
4
6
OSC_PCLK
TP_T10
Y5
Y4
TP_Y5
TP_Y4
TP_Y5
TP_Y4
No Connect
AA5
W6
TP_AA5
TP_W6
T_AA5
TP_W6
TP_T9
Y6
V6
TP_Y6
TP_V6
TP_Y6
TP_V6
No Connect
AA3
AB3
TP_AA3
TP_AB3
T_AA3
T_AB3
P C I_TRDY_N
PCI_REQ_N
PCI_CBE3_N
PCI_INTC_N
PCI_RST_N
PCI_INTD_N
PCI_INTB_N
PCI_INTA_N
PCI_IDSEL
PCI_GNT_N
W5
U6
TP_W5
TP_U6
TP_W5
TP_U6
PCI_AD28
V11
V12
PCI_AD19
PCI_AD20
PCI_AD17
C46
0.1uF
R9
R10
R11
T11
AB10
AB11
Y11
AA11
PCI_AD24
PCI_AD29
PCI_AD21
AB8
AB9
AA10
AA9
PCI_AD30
Y10
W11
AB6
AB7
AA8
AA7
AA6
AB5
V10
T10
W10
U10
PCI_AD18
PCI_AD31
PCI_AD23
PCI_AD22
V9
T9
Y8
Y9
PCI_AD26
W9
U9
PCI_AD27
PCI_AD25
W7
U8
Y7
W8
V8
U7
TP_V8
TP_U7
TP_V8
TP_U7
PCI_PRSNT1_N
PCI_PRSNT2_N
V7
T6
TP_V7
TP_T6
TP_V7
TP_T6
C56
0.1uF
FPGA_484
VCCO5
VCCO5
VCCO5
VCCO5
PB33A / PCLKT5_0
PB33B / PCLKC5_0
PB32A / VREF2_5
PB32B / VREF1_5
PB31A
PB31B
PB30A / BDQS30
PB30B
PB29A
PB29B
PB28A
PB28B
PB27A
PB27B
PB26A
PB26B
PB25A
PB25B
PB24A
PB24B
PB23A
PB23B
PB22A / BDQS22
PB22B
PB21A
PB21B
PB20A
PB20B
PB19A
PB19B
PB18A
PB18B
PB17A
PB17B
PB16A
PB16B
PB15A
PB15B
C58
0.1uF
4
C43
0.1uF
(2 of 5)
C55
0.1uF
AA12
AB12
R12
R13
R14
T12
T17
U17
Y18
W18
AA20
Y19
Y16
W17
AB20
AA19
Y17
V17
V16
U16
W16
U15
AB19
AA18
AB18
AA17
AB17
AA16
AB16
AA15
AB14
AB15
V15
T14
Y15
W15
AA14
Y14
C73
0.1uF
PCI_AD0
PCI_AD2
PCI_AD1
PCI_AD4
C61
0.1uF
PCI_AD3
PCI_CBE0_N
PCI_AD5
PCI_AD9
PCI_CBE1_N
PCI_AD10
PCI_AD6
PCI_AD8
PCI_AD7
PCI_AD15
PCI_AD14
PCI_STOP_N
PCI_DEVSEL_N
PCI_LOCK_N
PCI_AD12
Y13
V14
AA13
AB13
PCI_AD13
PCI_AD11
W14
U14
PCI_SERR_N
PCI_PERR_N
PCI_PAR
PCI_CBE2_N
PCI_AD16
W13
U13
T13
V13
P CI_ IRDY_N
W12
U12
C51
0.1uF
VCCO4
VCCO4
VCCO4
VCCO4
PB57A
PB57B
PB56A
PB56B
PB55A
PB55B
BDQS54 / PB54A
PB54B
PB53A
PB53B
PB52A
PB52B
PB51A
PB51B
PB50A
PB50B
PB49A
PB49B
PB48A
PB48B
PB47A
PB47B
BDQS46 / PB46A
PB46B
PB45A
PB45B
PB44A
PB44B
PB43A
PB43B
PB42A
PB42B
PB41A
SPID1 / D6 / PB41B
LFEC20E(fpBGA484)
PB14A / BDQS14
PB14B
PB13A
PB13B
PB12A
PB12B
PB11A
PB11B
PB10A
PB10B
PB40A
SPID2 / D5 / PB40B
PB39A
SPID3 / D4 / PB39B
BDQS38 / PB38A
SPID4 / D3 / PB38B
SPID5 / D2 / PB37A
SPID6 / D1 / PB37B
VREF2_4 / PB36A
SPID7/ D0 / PB36B
VREF1_4 / PB35A
CSN / PB35B
PCI_FRAME_N
1
3
5
3
C70
0.1uF
TP_T17
TP_U17
TP_Y18
TP_W18
T_AA20
TP_Y19
TP_Y16
TP_W17
T_AB20
T_AA19
TP_Y17
TP_V17
TP_V16
TP_U16
TP_W16
TP_U15
No Connect
No Connect
No Connect
No Connect
CON6A
J14
C60
0.1uF
2
4
6
TP_T17
TP_U17
TP_Y18
TP_W18
TP_AA20
TP_Y19
TP_Y16
TP_W17
TP_AB20
TP_AA19
TP_Y17
TP_V17
TP_V16
TP_U16
TP_W16
TP_U15
TP_T14
TP_T13
TP_U12
TP_U11
PCI_3.3V
PCI_TMS
C74
0.1uF
VCC_1.2V
VCC_3.3V
VCC_ADJ
C68
0.1uF
VCC_1.2V
VCC_3.3V
VCC_ADJ
[5]
[5] PCI_TDO
PCI_TCK
[7]
[5]
PCI_TDO
PCI_TCK
PCI_3.3V
PCI_TMS
+
PCI_TDI
PCI_TDI
[4]
PCI_CLK
PCI_CLK
J32
PCI EDGE CONN Solder Side
[5]
2
J3
PCI EDGE CONN Component Side
C1
47uF Size D
PC I_CLK
Y12
U11
PC I_REQ_N
BANK4
P CI_AD30
P CI_AD31
P CI_AD29
WRITEN / PB34A
CS1N / PB34B
P CI_AD28
P CI_AD26
P CI_AD27
P CI_AD25
BANK5
PC I_IDSEL
PC I_CBE3_N
P CI_AD23
U1B
P CI_AD22
P CI_AD20
P CI_AD21
P CI_AD19
D
PCI_PRSNT2_N
PCI_RST_N
2
PCI_IRD Y_N
3
P CI_DEVSEL_N
PCI_INTA_N
PC I_INTC_N
PCI_INTB_N
PC I_INTD_N
PCI_PRSNT1_N
P CI_AD18
P CI_AD16
P CI_AD17
PC I_CBE2_N
4
PC I_LOCK_N
PCI _PERR_N
5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
PCI _SERR_N
1
2
3
4
5
6
7
8
9
10
11
TRST#
+12V
TMS
TDI
+5V_5
INTA#
INTC#
+5V_8
Reserved_9
+VIO_10
Reserved_11
1
2
3
4
5
6
7
8
9
10
11
-12V
TCK
Ground_3
TDO
+5V_5
+5V_7
INTB#
INTD#
PRSNT1#
Reserved_10
PRSNT2#
P CI_AD15
PC I_PAR
[7]
PC I_AD9
P CI_AD13
P CI_AD11
J33
CON3
PCI_GND_57
R37
0
PCI_STOP_N
PC I_CBE0_N
PCI_VIO
C115
0.01
R38
5K
PCI_VIO
C3
47uF Size D
1
Monday, November 22, 2004
32-Bit PCI
Document Number
Sheet
2
of
8
B
ev
Lattice Semiconductor Corporation
Date
Size
C
Title
+
1
PC I_AD1
PCI_ TRDY_N
P CI_FRAME_N
P CI_AD24
PCI_GNT_N
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PC I_CBE1_N
P CI_AD14
PC I_AD6
PC I_AD4
PC I_AD5
PC I_AD3
3.3VAUX
RST#
+VIO_16
GNT#
Ground_18
PME#
AD[30]
+3.3V_21
AD[28]
AD[26]
Ground_24
AD[24]
IDSEL
+3.3V_27
AD[22]
AD[20]
Ground_30
AD[18]
AD[16]
+3.3V_33
FRAME#
Ground_35
TRDY#
Ground_37
STOP#
+3.3V_39
Reserved_40
Reserved_41
Ground_42
PAR
AD[15]
+3.3V_45
AD[13]
AD[11]
Ground_48
AD[09]
1
2
3
P CI_AD12
P CI_AD10
PCI_M66EN
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Reserved_14
Ground_15
CLK
Ground_17
REQ#
+VIO_19
AD[31]
AD[29]
Ground_22
AD[27]
AD[25]
+3.3V_25
C/BE#[3]
AD[23]
Ground_28
AD[21]
AD[19]
+3.3V_31
AD[17]
C/BE#[2]
Ground_34
IRDY#
+3.3V_36
DEVSEL#
Ground_38
LOCK#
PERR#
+3.3V_41
SERR#
+3.3V_43
C/BE#[1]
AD[14]
Ground_46
AD[12]
AD[10]
M66EN
PC I_AD8
PC I_AD7
1
2
PC I_AD2
PC I_AD0
52
53
54
55
56
57
58
59
60
61
62
C/BE#[0]
+3.3V_53
AD[06]
AD[04]
Ground_56
AD[02]
AD[00]
+VIO_59
REQ64#
+5V_61
+5V_62
52
53
54
55
56
57
58
59
60
61
62
17
AD[08]
AD[07]
+3.3V_54
AD[05]
AD[03]
Ground_57
AD[01]
+VIO_59
ACK64#
+5V_61
+5V_62
A
B
C
D
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Figure 9. 32-Bit PCI Interface
A
B
C
1
2
D
5
C2
1.0uF
D9
LED 0603 Red
R36
100
R20
220
VCC_3.3V
VCC_1.2V
VCC_3.3V
VCC_ADJ
VCC_1.2V
VCC_3.3V
VCC_ADJ
4
SW2
SW PUSHBUTTON Panasonic EVQP2H02B
GSRN(A19)
TP_A19
4
1
3
5
G13
E13
D14
F14
C13
E14
B13
A13
B14
C14
C15
D15
E15
G14
A14
A15
TP_G13
TP_E13
TP_D14
TP_F14
TP_C13
TP_E14
TP_B13
TP_A13
TP_B14
TP_C14
TP_C15
TP_D15
TP_E15
TP_G14
TP_A14
TP_A15
TP_G13
TP_E13
TP_D14
TP_F14
TP_C13
TP_E14
TP_B13
TP_A13
TP_B14
TP_C14
TP_C15
TP_D15
TP_E15
TP_G14
TP_A14
TP_A15
2
4
6
B12
A12
TP_B12
TP_A12
TP_B12
TP_A12
A18
B17
TP_A18
TP_B17
TP_A18
TP_B17
C16
D17
TP_C16
TP_D17
TP_B20
TP_C19
TP_C18
TP_D18
TP_F17
TP_G17
TP_C16
TP_D17
TP_B20
TP_C19
TP_C18
TP_D18
TP_F17
TP_G17
1
2
CON2
J13
CON6A
J12
A20
B19
TP_A20
TP_B19
TP_A20
TP_B19
C71
0.1uF
G12
H12
H13
H14
F17
G17
C18
D18
B20
C19
C17
E17
E16
F16
TP_E16
TP_F16
TP_E16
TP_F16
TP_C17
TP_E17
D16
F15
TP_D16
TP_F15
TP_D16
TP_F15
TP_C17
TP_E17
A19
B18
TP_A19
TP_B18
TP_A19
TP_B18
A17
B16
TP_A17
TP_B16
TP_A17
TP_B16
A16
B15
D13
F13
TP_D13
TP_F13
TP_D13
TP_F13
TP_A16
TP_B15
D12
F12
TP_D12
TP_F12
TP_D12
TP_F12
TP_A16
TP_B15
C12
F11
TP_C12
TP_F11
TP_C12
TP_F11
BANK1
U1 D
C72
0.1uF
FPGA_484
VCCO1
VCCO1
VCCO1
VCCO1
PT57A
PT57B
PT56A
PT56B
PT55A
PT55B
PT54A / TDQS54
PT54B
PT53A
PT53B
PT52A
PT52B
PT51A
PT51B
PT50A
PT50B
PT49A
PT49B
PT48A
PT48B
PT47A
PT47B
C62
0.1uF
3
C64
0.1uF
(4 of 5)
C63
0.1uF
G11
H9
H10
H11
A10
A11
E11
E12
C11
B11
B10
B9
A8
A9
C10
D11
A6
A7
B8
B7
B6
A5
E10
G10
D10
F10
E9
G9
C8
C9
D9
F9
D7
F8
C7
D8
B4
A4
C5
C4
B5
D6
C6
E6
B3
A3
D5
F6
E8
F7
E7
G6
C59
0.1uF
VCCO0
VCCO0
VCCO0
VCCO0
PCLKT0_0 / PT33A
PCLKC0_0 / PT33B
VREF2_0 / PT32A
VREF1_0 / PT32B
PT31A
PT31B
TDQS30 / PT30A
PT30B
PT29A
PT29B
PT28A
PT28B
PT27A
PT27B
PT26A
PT26B
PT25A
PT25B
PT24A
PT24B
PT23A
PT23B
TDQS22 / PT22A
PT22B
PT21A
PT21B
PT20A
PT20B
PT19A
PT19B
PT18A
PT18B
PT17A
PT17B
PT16A
PT16B
PT15A
PT15B
TDQS14 / PT14A
PT14B
PT13A
PT13B
PT12A
PT12B
PT11A
PT11B
PT10A
PT10B
BANK0
LFEC20E(fpBGA484)
PT46A / TDQS46
PT46B
PT45A
PT45B
PT44A
PT44B
PT43A
PT43B
PT42A
PT42B
PT41A
PT41B
PT40A
PT40B
PT39A
PT39B
PT38A / TDQS38
PT38B
PT37A
PT37B
PT36A
PT36B
PT35A / VREF1_1
PT35B / VREF2_1
PT34A
PT34B
3
C48
0.1uF
C57
0.1uF
TP_A10
TP_A11
TP_E11
TP_E12
TP_C11
TP_B11
TP_B10
TP_B9
TP_A8
TP_A9
TP_C10
TP_D11
TP_A6
TP_A7
TP_B8
TP_B7
TP_E10
TP_G10
TP_D10
TP_F10
TP_E9
TP_G9
TP_C8
TP_C9
TP_D9
TP_F9
TP_D7
TP_F8
TP_C7
TP_D8
TP_B4
TP_A4
TP_C5
TP_C4
TP_B5
TP_D6
TP_C6
TP_E6
TP_B3
TP_A3
TP_D5
TP_F6
TP_E8
TP_F7
TP_E7
TP_G6
C47
0.1uF
TP_A10
TP_A11
TP_E11
TP_E12
TP_C11
TP_B11
TP_B10
TP_B9
TP_A8
TP_A9
TP_C10
TP_D11
TP_A6
TP_A7
TP_B8
TP_B7
TP_E10
TP_G10
TP_D10
TP_F10
TP_E9
TP_G9
TP_C8
TP_C9
TP_D9
TP_F9
TP_D7
TP_F8
TP_C7
TP_D8
TP_B4
TP_A4
TP_C5
TP_C4
TP_B5
TP_D6
TP_C6
TP_E6
TP_B3
TP_A3
TP_D5
TP_F6
TP_E8
TP_F7
TP_E7
TP_G6
2
2
C44
0.1uF
1
2
5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
CON6A
J9
C45
0.1uF
2
4
6
1
18
2
1
3
5
C52
0.1uF
VCC_1.2V
VCC_3.3V
VCC_ADJ
SMA_B6
SMA_A5
S
J2
S
J5
N(A5)
P(B6)
1
Monday, November 22, 2004
Sheet
Prototyping Support
Document Number
3
of
8
B
ev
Lattice Semiconductor Corporation
Date
Size
C
Title
VCC_1.2V
VCC_3.3V
VCC_ADJ
1
1
1
A
B
C
D
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Figure 10. Prototyping Support
A
B
C
D
5
VCC_1.2V
VCC_3.3V
VCC_ADJ
5
VCC_1.2V
VCC_3.3V
VCC_ADJ
1
3
5
CON6A
J16
2
4
6
[5]
[2]
[5]
[5]
[5]
TP_Y21
PCI_CLK
CSSPIN
SISPI
SPID0
4
TP_Y21
PCI_CLK
CSSPIN
SISPI
SPID0
4
TP_R22
TP_R21
TP_R22
TP_R21
W22
V21
Y22
W21
U20
V20
AA22
Y21
V19
W19
AB21
AA21
Y20
W20
TP_W22
TP_V21
TP_Y22
TP_W21
TP_V20
TP_AA22
TP_Y21
TP_V19
TP_W19
TP_AB21
TP_AA21
TP_Y20
TP_W20
TP_W22
TP_V21
TP_Y22
TP_W21
TP_V20
T_AA22
TP_Y21
TP_V19
TP_W19
T_AB21
T_AA21
TP_Y20
TP_W20
C111
0.1uF
M15
M16
N15
P15
V22
U21
TP_V22
TP_U21
TP_V22
TP_U21
R17
T18
R22
R21
TP_N20
TP_P20
TP_N20
TP_P20
TP_R17
TP_T18
N20
P20
TP_P18
TP_P19
TP_P18
TP_P19
TP_R17
TP_T18
P18
P19
TP_P22
TP_P21
TP_P22
TP_P21
R18
R19
P22
P21
TP_N22
TP_N21
TP_N22
TP_N21
TP_R18
TP_R19
N22
N21
TP_N18
TP_N19
TP_N18
TP_N19
TP_R18
TP_R19
N18
N19
TP_L20
TP_M21
TP_L20
TP_M21
T22
U22
L20
M21
TP_M20
TP_L21
TP_M20
TP_L21
TP_T22
TP_U22
M20
L21
TP_M19
TP_M18
TP_M19
TP_M18
TP_T22
TP_U22
M19
M18
TP_L22
TP_M22
TP_L22
TP_M22
K21
K22
L22
M22
TP_K21
TP_K22
TP_K21
TP_K22
1
2
PR45A / RDQS45
PR45B
C108
0.1uF
FPGA_484
VCCO3
VCCO3
VCCO3
VCCO3
PR48A / VREF1_3
PR48B / VREF2_3
PR47A
PR47B
C109
0.1uF
PR44A / RLM0_PLLT_IN_A
PR44B / RLM0_PLLC_IN_A
PR46A
PR46B
RUM0_PLLT_IN_A / PR8A
RUM0_PLLC_IN_A / PR8B
3
PR7A
PR7B
RDQS6 / PR6A
PR6B
PR5A
PR5B
PR4A
PR4B
PR3A
PR3B
VREF2_2 / PR2A
VREF1_2 / PR2B
BANK2
C69
0.1uF
C67
0.1uF
D19
E19
J15
K15
L15
L16
J21
J22
H21
H22
L18
L19
J20
K20
K18
K19
F22
G22
E22
F21
D22
E21
G20
G21
H19
J18
H20
J19
H18
H17
C22
D21
G18
G19
F19
F20
D20
E20
C20
C21
E18
F18
B21
B22
C110
0.1uF
VCCO2
VCCO2
VCCO2
VCCO2
PCLKT2_0 / PR22A
PCLKC2_0 / PR22B
PR21A
PR21B
PR20A
PR20B
RDQS19 / PR19A
PR19B
PR18A
PR18B
PR17A
PR17B
PR16A
PR16B
PR15A
PR15B
PR14A
PR14B
PR13A
PR13B
PR12A
PR12B
PR11A
PR11B
RUM0_PLLT_FB_A / PR9A
RUM0_PLLC_FB_A / PR9B
(3 of 5)
PR43A / RLM0_PLLT_FB_A
PR43B / RLM0_PLLC_FB_A
PR42A / DOUT / CSOB
PR42B / DI / CSSPIN
PR41A / D7 / SPID0
PR41B / BUSY / SISPI
PR37A
PR37B
3
LFEC20E(fpBGA484)
PR36A / RDQS36
PR36B
PR35A
PR35B
PR34A
PR34B
PR33A
PR33B
PR32A
PR32B
PR31A
PR31B
PR30A
PR30B
PR29A
PR29B
PR28A / RDQS28
PR28B
PR27A
PR27B
PR26A
PR26B
PR25A
PR25B
PR24A
PR24B
BANK3
U1C
1
2
1
2
1
2
1
2
1
2
1
2
C66
0.1uF
TP_H21
TP_H22
TP_L18
TP_L19
TP_J20
TP_K20
TP_K18
TP_K19
TP_F22
TP_G22
TP_E22
TP_F21
TP_D22
TP_E21
TP_G20
TP_G21
TP_H19
TP_J18
TP_H20
TP_J19
TP_H18
TP_H17
TP_C22
TP_D21
TP_G18
TP_G19
TP_F19
TP_F20
TP_D20
TP_E20
TP_C20
TP_C21
TP_E18
TP_F18
TP_B21
TP_B22
TP_D19
TP_E19
1
2
C106
0.1uF
1
2
C105
0.1uF
TP_H21
TP_H22
TP_L18
TP_L19
TP_J20
TP_K20
TP_K18
TP_K19
TP_F22
TP_G22
TP_E22
TP_F21
TP_D22
TP_E21
TP_G20
TP_G21
TP_H19
TP_J18
TP_H20
TP_J19
TP_H18
TP_H17
TP_C22
TP_D21
TP_G18
TP_G19
TP_F19
TP_F20
TP_D20
TP_E20
TP_C20
TP_C21
TP_E18
TP_F18
TP_B21
TP_B22
TP_D19
TP_E19
1
2
2
C107
0.1uF
SMA_J21
SMA_J22
2
1
2
19
S
J19
S
J18
C65
0.1uF
1
1
1
2
C104
0.1uF
2
4
6
CON2
J17
1
2
CON6A
J15
N(J22)
P(J21)
VCC_1.2V
VCC_3.3V
VCC_ADJ
VCC_1.2V
VCC_3.3V
V CC_ADJ
1
Monday, November 22, 2004
heet
Prototyping Support
Document Number
4
of
8
B
ev
Lattice Semiconductor Corporation
Date
Size
C
Title
1
3
5
1
A
B
C
D
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Figure 11. Prototyping Support
A
B
C
D
VCC_3.3V
VCC_1.2V
10K
R23
SF0_W_N
Hardware Setup
TDO
Q
TDI
D
ISPEN_N
/S
DONE
TMS
TCK
C
INITN
5
V C CJ
IN ITN
U6
VCC
/HOLD
C
D
SPI Serial FLASH
/S
Q
/W
VSS
2
4
6
8
10
8
7
6
5
HEADER 5X2
1
3
5
7
9
JP3
SPID0
SFLASH_C
SFLASH_D
VCC_3.3V
[4]
VCC_3.3V
SFLASH_S_N
V C CJ
C102
0.1uF
C35
0.1uF
VCC_3.3V
1
2
3
4
VCC
/HOLD
C
D
8
7
6
5
SFLASH_C
SFLASH_D
VCC_3.3V
C21
0.1uF
C22
0.1uF
C27
0.1uF
C24
0.1uF
C34
0.1uF
C28
0.1uF
C95
0.1uF
C83
0.1uF
10K
R19
C96
0.1uF
C33
0.1uF
SPI Serial FLASH STMicro M25P80-VMW6T
/S
Q
/W
VSS
U2
for different size or vender
Optional SPI Serial FLASH
1
2
3
4
SFLASH_D
SFLASH_Q
SFLASH_C
SFLASH_S_N
SFLASH_Q_1
C36
0.1uF
2
4
6
8
10
HEADER 5X2
1
3
5
7
9
2x5 SPI Flash Programming Header
TCK
TMS
TDI
TDO
JP2
2x5 Download Cable Header
SFLASH_S_N
SFLASH_Q_2
C23
0.1uF
FPGA Loader
Download Cable Header
input
TDO
output
TDI
ISPEN_N
DONE
TMS
output
output
TCK
INITN
input
JTAG
1
2
1
2
IN ITN
TCK
TMS
V C CJ
TDO
TDI
4
C100
0.1uF
C84
0.1uF
C32
0.1uF
C85
0.1uF
SF0_HLD_N
SFLASH_S_N
SPID0
SFLASH_D
SFLASH_C
HEADER 10
1
2
3
4
5
6
7
8
9
10
JP4
C98
0.1uF
C82
0.1uF
10K
R22
SFLASH_Q_2
SFLASH_Q
SFLASH_C
C97
0.1uF
C79
0.1uF
VCC_3.3V
J11
CON3
CSSPIN
SISPI
CCLK
C30
0.1uF
C80
0.1uF
SFLASH_Q_1
V C CJ
VCC_3.3V
SFLASH_Q
SFLASH_D
SFLASH_S_N
Header
VCC_3.3V
1x10 SPI Flash Programming
HEADER 10
1
2
3
4
5
6
7
8
9
10
JP1
1x10 Download Cable Header
4
3
2
1
C39
0.1uF
C99
0.1uF
C31
0.1uF
C86
0.1uF
[6], [7]
[7]
TDO
TDI
TMS
TCK
3
C81
0.1uF
C87
0.1uF
VCC_3.3V
VCC_1.2V
[4]
[4]
CSSPIN
SISPI
3
8
7
6
5
1
2
3
4
C38
0.1uF
C88
0.1uF
L3
U2
U1
U5
T4
T5
C37
0.1uF
C101
0.1uF
G7
G8
G15
G16
H7
H16
R7
R16
T7
T8
T15
T16
J6
J7
J16
J17
K6
K7
K16
K17
L6
L17
M6
M17
N6
N7
N16
N17
P6
P7
P16
P17
R18
10K 1% YAGEO 0402
XRES
V C CJ
33 CTS 741X083
RN1
PCI_TCK
PCI_TMS
PCI_TDI
PCI_TDO
[2]
[2]
[2]
[2]
(5 of 5)
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
A22
AB1
AB22
H8
H15
J9
J10
J11
J12
J13
J14
K9
K10
K11
K12
K13
K14
L9
L10
L11
L12
L13
L14
M9
M10
M11
M12
M13
M14
N9
N10
N11
N12
N13
N14
P9
P10
P11
P12
P13
P14
R8
R15
V18
R20
T21
T20
T19
U19
U18
CFG0
CFG1
CFG2
CFG2
CFG1
CFG0
10K
10K
10K
PROGRAMN
DONE
INITN
CCLK
R28
R27
R26
LFEC20E(fpBGA484)
FPGA_484
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
XRES
VCCJ
TDO
TDI
TMS
TCK
U1E
PCI_TCK
PCI_TMS
PCI_TDI
PCI_TDO
VCC_3.3V
VCC_3.3V
VCC_3.3V
2
PROGRAMN
DONE
IN ITN
CCLK
2
4
6
TP_T20
CON6A
J20
1
3
5
R25
10K
0 (ON)
0 (ON)
1 (OFF)
1 (OFF)
X
1 (OFF)
1 (OFF)
1 (OFF)
X
SPIX Flash
TP_Y21
TP_Y21
[4]
PROGRAM
Date
Size
C
Title
VCC_3.3V
C41
0.1uF
C77
0.1uF
C103
0.1uF
C91
0.1uF
C42
0.1uF
C93
0.1uF
C76
0.1uF
C19
0.1uF
C26
0.1uF
C78
0.1uF
C94
0.1uF
C18
0.1uF
C17
0.1uF
C75
0.1uF
C92
0.1uF
C90
0.1uF
1
Monday, November 22, 2004
heet
5
of
8
JTAG
and FPGA Programming
Document Number
C40
0.1uF
C29
0.1uF
C89
0.1uF
C20
0.1uF
FLASH programmer SoftIP
D11
LED 0603 Green
R24
220
VCC_3.3V
ispJTAG
Slave Parallel
Master Parallel
Slave Serial
Master Serial
SW3
SW PUSHBUTTON Panasonic EVQP2H02B
X
1 (OFF)
0 (ON)
1 (OFF)
SPI3 Flash
Configuration Mode
Short this if using SPI Serial
CON2
J34
1 (OFF)
0 (ON)
0 (ON)
1 (OFF)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
1
C FG0
C FG1
C FG2
IN ITN
VCC_3.3V
D10
LED 0603 Yellow
R21
220
VCC_3.3V
1
2
5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
20
2
B
ev
A
B
C
D
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Figure 12. JTAG and FPGA Programming
A
B
C
5
220
220
R7
R8
VCC_1.2V
VCC_3.3V
V CC_ADJ
220
R6
220
R4
220
220
R3
R5
220
220
R2
R1
VCC_3.3V
LED_G1
LED(G1)
LED_G2
LED(G2)
LED_H1
LED(H1)
LED_H2
LED(H2)
LED_J1
LED(J1)
LED_J2
LED(J2)
LED_K1
LED(K1)
LED_K2
VCC_1.2V
VCC_3.3V
VCC_ADJ
1
3
5
1
2
CON2
J6
CON6A
J7
LED(K2)
LED 0603 Green
D8
LED 0603 Green
D7
LED 0603 Green
D6
LED 0603 Green
D5
LED 0603 Green
D4
LED 0603 Green
D3
LED 0603 Green
D2
LED 0603 Green
D1
VCC_3.3V
2
4
6
LED_J1
LED_K1
TP_J1
TP_K1
TP_K3
TP_K2
TP_J1
TP_K1
TP_K3
TP_K2
TP_J2
TP_H1
TP_K4
TP_K5
LED_K2
LED_J2
LED_H1
TP_K4
TP_K5
TP_J2
TP_H1
TP_J4
TP_J3
TP_H2
TP_G1
LED_H2
LED_G1
TP_J4
TP_J3
TP_H3
TP_G2
LED_G2
TP_H2
TP_G1
TP_E1
TP_D1
TP_E1
TP_D1
TP_H3
TP_G2
TP_F2
TP_F1
C49
0.1uF
J8
K8
L7
L8
J1
K1
K3
K2
K4
K5
J2
H1
J4
J3
H2
G1
H3
G2
E1
D1
F2
F1
J5
H5
TP_J5
TP_H5
TP_J5
TP_H5
TP_F2
TP_F1
G3
H4
TP_G3
TP_H4
G5
H6
TP_G5
TP_H6
TP_G5
TP_H6
TP_G3
TP_H4
F3
E2
B1
C1
TP_F3
TP_E2
TP_F3
TP_E2
TP_B1
TP_C1
F4
G4
TP_F4
TP_G4
TP_F4
TP_G4
TP_B1
TP_C1
D3
C2
TP_D3
TP_C2
TP_D3
TP_C2
E3
D2
E5
F5
TP_E5
TP_F5
TP_E5
TP_F5
TP_E3
TP_D2
C3
B2
TP_C3
TP_B2
TP_C3
TP_B2
TP_E3
TP_D2
D4
E4
TP_D4
TP_E4
TP_D4
TP_E4
4
4
BANK7
U1A
C10
0.1uF
FPGA_484
VCCO7
VCCO7
VCCO7
VCCO7
PL22A / PCLKT7_0
PL22B / PCLKC7_0
PL21A
PL21B
PL20A
PL20B
C11
0.1uF
LLM0_PLLT_IN_A / PL41A
LLM0_PLLC_IN_A / PL41B
PL37A
PL37B
LDQS36 / PL36A
PL36B
PL35A
PL35B
PL34A
PL34B
C12
0.1uF
C53
0.1uF
3
M7
M8
N8
P8
W3
Y3
W4
V4
AA1
AA2
Y1
Y2
W1
W2
U4
V5
U3
V3
V1
V2
R3
T3
T1
T2
R5
R4
R1
R2
P3
P4
R6
P5
P1
P2
N1
N2
N5
N4
N3
M3
M1
M2
M4
M5
L2
L1
L4
L5
C13
0.1uF
VCCO6
VCCO6
VCCO6
VCCO6
VREF1_6 / PL48A
VREF2_6 / PL48B
PL47A
PL47B
PL46A
PL46B
LDQS45 / PL45A
PL45B
PL44A
PL44B
PL43A
PL43B
LLM0_PLLT_FB_A / PL42A
LLM0_PLLC_FB_A / PL42B
(1 of 5)
PL33A
PL33B
PL32A
PL32B
PL31A
PL31B
PL30A
PL30B
PL29A
PL29B
LDQS28 / PL28A
PL28B
PL27A
PL27B
PL26A
PL26B
PL25A
PL25B
PL24A
PL24B
BANK6
LFEC20E(fpBGA484)
PL19A / LDQS19
PL19B
PL18A
PL18B
PL17A
PL17B
PL16A
PL16B
PL15A
PL15B
PL14A
PL14B
PL13A
PL13B
PL12A
PL12B
PL11A
PL11B
PL9A / LUM0_PLLT_FB_A
PL9B / LUM0_PLLC_FB_A
PL8A / LUM0_PLLT_IN_A
PL8B / LUM0_PLLC_IN_A
PL7A
PL7B
PL6A / LDQS6
PL6B
PL5A
PL5B
PL4A
PL4B
PL3A
PL3B
PL2A / VREF2_7
PL2B / VREF1_7
3
C14
0.1uF
TP_R3
TP_T3
TP_T1
TP_T2
TP_R5
TP_R4
TP_R1
TP_R2
TP_P3
TP_P4
TP_R6
TP_P5
TP_P1
TP_P2
TP_N1
TP_N2
TP_N5
TP_N4
TP_N3
TP_M3
TP_M1
TP_M2
TP_M4
TP_M5
TP_L2
TP_L1
TP_L4
TP_L5
TP_U4
TP_V5
TP_W1
TP_W2
TP_Y1
TP_Y2
TP_W4
TP_V4
TP_W3
TP_Y3
TP_U4
TP_V5
TP_W1
TP_W2
TP_Y1
TP_Y2
TP_W4
TP_V4
TP_W3
TP_Y3
C25
0.1uF
TP_U3
TP_V3
C16
0.1uF
TP_V2
TP_U3
TP_V3
TP_R3
TP_T3
TP_T1
TP_T2
TP_R5
TP_R4
TP_R1
TP_R2
TP_P3
TP_P4
TP_R6
TP_P5
TP_P1
TP_P2
TP_N1
TP_N2
TP_N5
TP_N4
TP_N3
TP_M3
TP_M1
TP_M2
TP_M4
TP_M5
TP_L2
TP_L1
TP_V2
SW_P1
SW_P2
SW_N1
SW_N2
SW_M1
SW_M2
SW_L2
SW_L1
TP_L4
TP_L5
2
4
6
C50
0.1uF
CON6A
J8
1
3
5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC_3.3V
10K
R12
10K
R13
10K
R14
OSC_PLLCLK
C54
0.1uF
2
C15
0.1uF
VCC_1.2V
VCC_3.3V
VCC_ADJ
VCC_1.2V
VCC_3.3V
VCC_ADJ
SMA_AA1
SMA_AA2
OSC_PLLCLK
(33.33 MHz OSC Installed)
1
1
J1
S
J4
S
OSC_PCLK
OSC1(V1)
OSC_PCLK
10K
R16
10K
R17
VCC_3.3V
ON
VCC_3.3V
SW1
SW DIP-8 CTS 194-8MST
1
[2]
1
Monday, November 22, 2004
Sheet
Prototyping Support
Document Number
6
of
8
B
ev
Lattice Semiconductor Corporation
Date:
Size
C
Title
N(AA2)
P(AA1)
1
2
3
4
5
6
7
8
(L1)(L2)(M1)(M2)(N1)(N2)(P1)(P2)
10K
R15
OSC2(AB10)
10K
R11
Oscillator Socket
DIPSOC-8x2
Y1
SW_L1
SW_L2
SW_M1
SW_M2
SW_N1
SW_N2
SW_P1
SW_P2
10K
R10
2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
D
5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
21
2
A
B
C
D
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Figure 13. Prototyping Support
A
B
C
D
J31
1
2
3
5
PW R JACK Switchcraft RAPC722
+5VDC
V CC_IN
CON2
J30
1
2
C9
4.7uF Size B
PCI_3.3V
J24
BANANA JACK, BLACK, SPC 845-B
D12
1N5820
V CC_IN
1N5820
D14
1N5820
D13
1
2
5
1
S
[2]
1
2
EN
VIN
U5
4
1.2V
disable
R34
10K
PCI_3.3V
4
FB
VOUT
5
4
TPS78601KTT
GND
3
PWR_1.2V
VCC_1.2V
R35
30.1K 1% YAGEO 0402
[5]
VCC_1.2V
3
+
3
C8
2.2uF Size B
J27
CON4A
+
C114
47uF Size D
J23
BANANA JACK, RED, SPC 845-R
S
1
3
1
4
2
[2]
V CC_IN
V CC_IN
1
2
1
1
2
CON2
J29
1
2
C7
4.7uF Size B
CON2
J28
C5
4.7uF Size B
PCI_GND_57
2
1
2
EN
VIN
U3
1
2
EN
VIN
2
3.3V
disable
R33
10K
U4
ADJ
disable
R31
10K
2
5
4
FB
VOUT
5
4
TPS78601KTT
FB
VOUT
TPS78601KTT
[5]
2
VCC_ADJ
VCC_ADJ
VCC_3.3V
VCC_3.3V
C4
2.2uF Size B
+
C112
47uF Size D
+
C6
2.2uF Size B
J26
CON4A
+
C113
47uF Size D
PCI_3.3V
J22
BANANA JACK, RED, SPC 845-R
+
J25
CON4A
J21
BANANA JACK, RED, SPC 845-R
1
1
Monday, November 22, 2004
Power
Document Number
heet
7
of
8
B
ev
Lattice Semiconductor Corporation
Date
Size
C
Title
R30
30.1K 1% YAGEO 0402
R32
51K 1% YAGEO 0402
PWR_3.3V
[5],[6]
R29
30.1K 1% YAGEO 0402
R9
50K POT Murata PVG5H503A01
PW R_ADJ
3
1
S
1
3
1
4
2
S
1
3
1
GND
3
GND
3
22
4
2
A
B
C
D
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Figure 14. Power
23
4
3
2
Lattice Semiconductor Corporation
Date
Friday, January 21, 2005
1
heet
Mechanical Drawing
Document Number
8
of
8
B
ev
A
A
Size
C
B
B
5
Title
1
C
2
C
3
D
4
D
5
Lattice Semiconductor
LatticeEC Standard Evaluation Board – Revision B
User’s Guide
Figure 15. Mechanical Drawing