The following document contains information on Cypress products. Although the document is marked with the name “Spansion”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. Continuity of Ordering Part Numbers Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress (NASDAQ: CY) delivers high-performance, high-quality solutions at the heart of today’s most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. With a broad, differentiated product portfolio that includes ® NOR flash memories, F-RAM™ and SRAM, Traveo™ microcontrollers, the industry’s only PSoC ® programmable system-on-chip solutions, analog and PMIC Power Management ICs, CapSense ® capacitive touch-sensing controllers, and Wireless BLE Bluetooth Low-Energy and USB connectivity solutions, Cypress is committed to providing its customers worldwide with consistent innovation, bestin-class support and exceptional system value. MB91570 Series 32-bit Microcontroller MB91F575B/F575BS/F575BH/F575BHS/F575C/ F575CS/F575CH/F575CHS MB91F577B/F577BS/F577BH/F577BHS/F577CS/ F577CH/F577CHS MB91F578C(M)/F578CS(M)/F578CH(M)/F578CHS(M) MB91F579C(M)/F579CS(M)/F579CH(M)/F579CHS(M) Data Sheet (Full Production) Publication Number MB91F577_DS705-00009 CONFIDENTIAL Revision 3.0 Issue Date June 19, 2015 D a t a S h e e t 2 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 MB91570 Series 32-bit Microcontroller MB91F575B/F575BS/F575BH/F575BHS/F575C/ F575CS/F575CH/F575CHS MB91F577B/F577BS/F577BH/F577BHS/F577CS/ F577CH/F577CHS MB91F578C(M)/F578CS(M)/F578CH(M)/F578CHS(M) MB91F579C(M)/F579CS(M)/F579CH(M)/F579CHS(M) Data Sheet (Full Production) DESCRIPTION This series is Spansion 32-bit microcontroller designed for automotive and industrial control applications. It contains the FR81S CPU that is compatible with the FR family. The FR81S has a high level performance among the Spansion FR family by enhancing CPU instruction pipeline and load store processing, and improving internal bus transfer. It is best suited for application control for automotive. Note: FR is a line of products of Spansion Inc. Spansion provides information facilitating product development via the following website. The website contains information useful for customers. http://www.spansion.com/Support/microcontrollers/ Publication Number MB91F577_DS705-00009 Revision 3.0 Issue Date June 19, 2015 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. CONFIDENTIAL D a t a S h e e t FEATURES FR81S CPU Core ・ 32-bit RISC, load/store architecture, 5-stage pipeline ・ Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied ( PLL clock multiplication system )) ・ General-purpose register : 32-bit ×16 sets ・ 16-bit fixed length instructions ( basic instruction ), 1 instruction per cycle ・ Instructions appropriate to embedded applications ・ Memory-to-memory transfer instruction ・ Bit processing instruction ・ Barrel shift instruction etc. ・ High-level language support instructions ・ Function entry/exit instructions ・ Register content multi-load and store instructions ・ Bit search instructions ・ Logical 1 detection, 0 detection, and change-point detection ・ Branch instructions with delay slot ・ Decrease overhead during branch process ・ Register interlock function ・ Easy assembler writing ・ Built-in multiplier and instruction level support ・ Signed 32-bit multiplication : 5 cycles ・ Signed 16-bit multiplication : 3 cycles ・ Interrupt ( PC/PS saving ) ・ 6 cycles ( 16 priority levels ) ・ The Harvard architecture allows simultaneous execution of program and data access. ・ Instruction compatibility with the FR family ・ Built-in memory protection function ( MPU ) ・ Eight protection areas can be specified commonly for instructions and the data. ・ Control access privilege in both privilege mode and user mode. ・ Built-in FPU (floating point arithmetic) ・ IEEE754 compliant ・ Floating-point register 32-bit × 16 sets Peripheral Functions ・ Clock generation (equipped with SSCG function) ・ Main oscillation (4MHz) ・ Sub oscillation (32kHz ) or no sub oscillation ・ PLL multiplication rate : 1 to 20 times ・ Built-in Program flash memory capacity ・ MB91F575 : 512 + 64KB ・ MB91F577 : 1024 + 64KB ・ MB91F578 : 1536 + 64KB ・ MB91F579 : 2048 + 64KB ・ Built-in Data flash memory (WorkFlash) capacity 64KB ・ Built-in RAM capacity ・ Main RAM MB91F575 : 40KB MB91F577 : 64KB MB91F578 : 96KB MB91F579 : 128KB ・ Backup RAM MB91F575/7 : 8KB MB91F578/9 : 16KB 2 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t ・ General-purpose ports [LQFP-144] ・ 111 (none sub oscillation ), 109 (with sub oscillation ) ・ Included I2C pseudo open drain ports : 4 ・ P057 : Input only [LQFP-208] ・ 159 (none sub oscillation ), 157 (with sub oscillation ) ・ Included I2C pseudo open drain ports : 4 ・ P057 : Input only ・ External bus interface ・ 22-bit address, 16-bit data ・ 23 pins of 9-bit address, 8-bit data, ASX, CS0X, CS1X, RDX, WR0X, and WR1X can select 5V/3.3V by the VCCE power supply ・ DMA Controller ・ Up to 16 channels can be started simultaneously. ・ 2 transfer factors ( Internal peripheral request and software ) ・ A/D converter (successive approximation type) ・ 8/10-bit resolution : 40 channels ・ Conversion time : 3μs ・ D/A converter (R-2R type) ・ 8-bit resolution : 2 channels ・ External interrupt input: 16 channels ・ Level ("H" / "L"), or edge detection ( rising or falling ) enabled ・ LIN-UART ・ 6 channels, ch.2 to ch.7 ・ Selectable from UART, synchronous mode or LIN-UART mode ・ LIN protocol Revision 2.1 supported (LIN-UART). ・ SPI( Serial Peripheral Interface ) supported ( synchronous mode ) ・ Full-duplex double buffering system ・ LIN synch break detection ( linked to the input capture ) ・ Built-in dedicated baud rate generator ・ DMA transfer support ・ Multi-function serial communication (built-in transmission/reception FIFO memory ) : 4 channels < UART (Asynchronous serial interface) > ・ Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO memory ・ Parity or no parity is selectable. ・ Built-in dedicated baud rate generator ・ The external clock can be used as the transfer clock ・ Parity, frame, and overrun error detect functions provided ・ DMA transfer support <CSIO (Synchronous serial interface) > ・ Full-duplex double buffering system, 16-byte transmission FIFO, memory, 16-byte reception FIFO memory ・ SPI supported; master and slave systems supported; 5 to 9-bit data length can be set. ・ Built-in dedicated baud rate generator (Master operation) ・ The external clock can be entered. (Slave operation) ・ Overrun error detection function is provided ・ DMA transfer support <LIN-UART (Asynchronous Serial Interface for LIN) > ・ Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO memory ・ LIN protocol revision 2.1 supported ・ Master and slave systems supported ・ Framing error and overrun error detection ・ LIN synch break generation and detection; LIN synch delimiter generation June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 3 D a t a S h e e t ・ Built-in dedicated baud rate generator ・ The external clock can be adjusted by the reload counter ・ DMA transfer support < I2C > ・ Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO memory ・ Standard mode ( Max. 100kbps ) / high-speed mode ( Max. 400kbps ) supported ・ DMA transfer supported ( for transmission only ) ・ I2C supporting I/O ( for ch.0 and ch.1 only ) ・ CAN Controller (C-CAN) : 3 channels ・ Transfer speed : Up to 1Mbps ・ 64-transmission/reception message buffering : 1 channel, 32-transmission/reception message buffering : 2 channels ・ PPG : 16-bit × 24 channels ・ Reload timer : 16-bit × 7 channels(3 channels are for regular timer interrupt generation. ) ・ Free-run timer : 32-bit × 6 channels (Can select each channel for input capture, output compare) ・ Input capture : 32-bit × 12 channels (linked to the free-run timer) ・ Output compare : 32-bit × 12 channels (linked to the free-run timer) ・ Sound generator : 5 channels ・ Frequency and amplitude sequencers provided ・ Stepping motor controller : 6 channels ・ 8/10-bit PWM ・ High current output supported (4 lines × 6 channels) Can refer back electromotive force using pin-shared A/D converter ・ LCD controller ・ Common output : 4 , Segment output : 32 ・ Duty drive (SEG0 to SEG31) and static drive (ST0 to ST8) can be switched. ・ Each of COM0 to COM3, SEG0 to SEG31, V0, V1, V2, and V3 pins for duty drive can be switched to the general-purpose port. (The SEG23 to SEG31 pins can be switched to static driving.) ・ V0, V1, V2 and V3 pin can be used as the general-purpose port. But V3 pin cannot be used as an output pin. ・ Each of ST0 to ST8 pins for static drive can be switched to the general-purpose port, or it can be switched to the segment output of duty drive. ・ MB91F575/7: The amplitude of the SEG0 to SEG22 output is determined by the VCC5 power supply pin or by the V3 pin even if VCCE pin is supplied to 3.3V. ・ MB91F578/9: The voltage VCCE or less can be supplied to V3 pin. It is prohibited that VCC5 being chosen as LCDC reference voltage by software. ・ Up/Down counter: 2 channels ・ 8/16-bit up/down counter ・ Real-time clock (RTC) (for day, hours, minutes, seconds) ・ Main oscillation / sub oscillation frequency can be selected for the operation clock ・ Calibration: A hardware watchdog of the CR oscillation drive and real-time clock (RTC) of the sub clock drive ・ The CR oscillation frequency can be trimmed ・ The main clock to sub clock ratio can be corrected by setting the real-time clock prescaler ・ Clock Supervisor ・ Monitoring abnormality (damage of crystal etc.) of sub oscillation ( 32kHz ) (dual clock products) and main oscillation ( 4 MHz ) ・ When abnormality is detected, it switches to the CR clock. ・ Base timer : 2 channels ・ 16-bit timer ・ Any of four PWM/PPG/PWC/reload timer functions can be selected and used. ・ As for the functions of PWC and reload timer, 2 channels of cascade mode can be used as 32-bit timer. ・ CRC generation 4 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t ・ HS-SPI Note: In this series, the HS-SPI function is prohibited ・ E2PROM and the flash device of the Single/Dual/Quad-SPI protocol can be connected. ・ The power supply of 5V/3.3V supplied to the VCCE power supply pin is used. ・ Maximum 16MHz (Maximum 8 MHz at the slave.) ・ Watchdog timer ・ Hardware watchdog ・ Software watchdog ・ NMI ・ Interrupt controller ・ Interrupt request batch read ・ Multiple interrupts from peripherals can be read by a series of registers. ・ I/O relocation ・ Peripheral function pins can be reassigned. ・ Low-power consumption mode ・ Sleep / Stop / Watch / Sub RUN mode ・ Stop (power shutdown) / Watch (power shutdown) mode ・ Power on reset ・ Low-voltage detection reset (external low-voltage detection) ・ Low-voltage detection reset (internal low-voltage detection) ・ Device Package : ・ LQFP-144 for MB91F575/7/8/9 ・ LQFP-208 for MB91F578/9 ・ CMOS 90nm Technology ・ Power supplies ・ 5V Power supply ・ The internal 1.2V is generated from 5V with the voltage step-down regulator. ・ I/O port uses the power supply of 5V/3.3V supplied to the VCCE power supply pin. ・ LQFP-144: P010 to P017, P020 to P027, and P030 to P036 ・ LQFP-208: P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, and P190 to P197 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 5 D a t a S h e e t PRODUCT LINEUP Product Item MB91F575B(S)/C(S) MB91F575BH(S)/CH(S) System Clock On chip PLL Clock multiple method Minimum instruction execution time Around 12.5ns (80MHz) Sub clock Yes(Non-S series) No(S series) FLASH Capacity (Program) 512 + 64KB FLASH Capacity (Work) 64KB RAM 40KB + 8KB BI-ROM 4KB GDC None External BUS I/F Address : 22-bit Data :16-bit (Part of the External BUS I/F pins can select the power supply 5V or 3.3V) DMA Controller 16 channels Base Timer(16bit) 2 channels Free-run Timer(32bit) 6 channels Input capture(32bit) 12 channels Output Compare(32bit) 12 channels Reload Timer(16bit) 7 channels PPG timer(16bit) 24 channels Up/down Counter 2 channels Clock Supervisor Yes D/A converter 2 channels External Interrupt 16 channels A/D converter (8bit/10bit) 40 channels LIN-UART 6 channels Multi-Function serial communication 4 channels*1 HS-SPI Yes Up to 16MHz Note: In this series, the HS-SPI function is prohibited. LCD Controller 32seg × 4com(Static drive 8seg × 1com) CAN 64msg × 1 channel / 32msg × 2 channels 6 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Product Item MB91F575B(S)/C(S) MB91F575BH(S)/CH(S) Stepping Motor Controller 6 channels Sound Generator 5 channels Software Watchdog Yes Hardware Watchdog Yes Clock supervisor Initial value "ON" Initial value "OFF" CRC generation Yes Low-voltage detection reset (External low-voltage detection) Yes Low-voltage detection reset (Internal low-voltage detection) Yes Package LQFP-144 Others Flash Products On Chip Debug Yes 2 *1: I C only supported by ch.0 and ch.1. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 7 D a t a S h e e t Product Item MB91F577B(S)/C(S) MB91F577BH(S)/CH(S) System Clock On chip PLL Clock multiple method Minimum instruction execution time Around 12.5ns (80MHz) Sub clock Yes(Non-S series) No(S series) FLASH Capacity (Program) 1024 + 64KB FLASH Capacity (Work) 64KB RAM 64KB + 8KB BI-ROM 4KB GDC None External BUS I/F Address : 22-bit Data :16-bit (Part of the External BUS I/F pins can select the power supply 5V or 3.3V) DMA Controller 16 channels Base Timer(16bit) 2 channels Free-run Timer(32bit) 6 channels Input capture(32bit) 12 channels Output Compare(32bit) 12 channels Reload Timer(16bit) 7 channels PPG timer(16bit) 24 channels Up/down Counter 2 channels Clock Supervisor Yes D/A converter 2 channels External Interrupt 16 channels A/D converter (8bit/10bit) 40 channels LIN-UART 6 channels Multi-Function serial communication 4 channels*1 HS-SPI Yes Up to 16MHz Note: In this series, the HS-SPI function is prohibited. LCD Controller 32seg × 4com(Static drive 8seg × 1com) CAN 64msg × 1 channel / 32msg × 2 channels Stepping Motor Controller 6 channels 8 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Product Item MB91F577B(S)/C(S) MB91F577BH(S)/CH(S) Sound Generator 5 channels Software Watchdog Yes Hardware Watchdog Yes Clock supervisor Initial value "ON" Initial value "OFF" CRC generation Yes Low-voltage detection reset (External low-voltage detection) Yes Low-voltage detection reset (Internal low-voltage detection) Yes Package LQFP-144 Others Flash Products On Chip Debug Yes 2 *1: I C only supported by ch.0 and ch.1. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 9 D a t a S h e e t Product Item MB91F 578C(S)(M) MB91F 578CH(S)(M) MB91F 579C(S)(M) System Clock On chip PLL Clock multiple method Minimum instruction execution time Around 12.5ns (80MHz) Sub clock Yes(Non-S series) No(S series) FLASH Capacity (Program) 1536 + 64KB FLASH Capacity (Work) RAM MB91F 579CH(S)(M) 2048 + 64KB 64KB 96KB + 16KB 128KB + 16KB BI-ROM 4KB GDC None External BUS I/F Address : 22-bit Data :16-bit (Part of the External BUS I/F pins can select the power supply 5V or 3.3V) DMA Controller 16 channels Base Timer(16bit) 2 channels Free-run Timer(32bit) 6 channels Input capture(32bit) 12 channels Output Compare(32bit) 12 channels Reload Timer(16bit) 7 channels PPG timer(16bit) 24 channels Up/down Counter 2 channels Clock Supervisor Yes D/A converter 2 channels External Interrupt 16 channels A/D converter (8bit/10bit) 40 channels LIN-UART 6 channels Multi-Function serial communication 4 channels*1 HS-SPI No LCD Controller 32seg × 4com(Static drive 8seg × 1com) CAN 64msg × 1 channel / 32msg × 2 channels Stepping Motor Controller 6 channels Sound Generator 5 channels 10 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Product Item MB91F 578C(S)(M) MB91F 578CH(S)(M) MB91F 579C(S)(M) Software Watchdog Yes Hardware Watchdog Yes Clock supervisor Initial value "ON" Initial value "OFF" Initial value "ON" CRC generation Yes Low-voltage detection reset (External low-voltage detection) Yes Low-voltage detection reset (Internal low-voltage detection) Yes Package LQFP-144 LQFP-208 (with suffix "M") Others Flash Products On Chip Debug Yes MB91F 579CH(S)(M) Initial value "OFF" 2 *1: I C only supported by ch.0 and ch.1. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 11 D a t a S h e e t 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VSS P014/D28_0/SEG4/D20_1/INT12_1 P013/D27_0/SEG3/D19_1/INT11_1 P012/D26_0/SEG2/D18_1/INT10_1 P011/D25_0/SEG1/D17_1/INT9_1 P010/D24_0/SEG0/D16_1/INT8_1 P007/D23_0/TOT3_2/PPG7_0/D31_1/INT7_1 P006/D22_0/TOT2_2/PPG6_0/D30_1/INT6_1 P005/D21_0/SCK3_1/TOT1_2/PPG5_0/D29_1/INT5_1 P004/D20_0/SOT3_1/TOT0_2/PPG4_0/D28_1/INT4_1 P003/D19_0/SIN3_1/TIN3_2/PPG3_0/D27_1/INT3_1 P002/D18_0/SCK2_1/TIN2_2/PPG2_0/D26_1/INT2_1 P001/D17_0/SOT2_1/TIN1_2/PPG1_0/D25_1/INT1_1 P000/D16_0/SIN2_1/TIN0_2/PPG0_0/D24_1/INT0_1 C VSS VCC5 P134/TRG2/INT5_0/ICU5_0/PPG1_3 P133/SCK1_0/INT3_0/ICU4_0/TIOB1/PPG11_1/TRG5 P132/SOT1_0/INT2_0/ICU3_0/TIOB0 P131/TRG1/SIN1_0/INT4_0/ICU2_0/TIOA1 P130/SCK0_0/INT0_0/ICU1_0/TIOA0 P127/SOT0_0/OCU5_0 P126/TRG0/SIN0_0/INT1_0/OCU4_0 P125/OCU3_0/ICU0_0/PPG10_2 VSS X1 X0 MD2 MD1 MD0 P124/OCU2_0/ICU5_2/PPG9_2 P096/RX0/INT9_0 P095/TX0/PPG10_1 DEBUGIF VSS PIN ASSIGNMENT (LQFP-144) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TOP VIEW LQFP-144 VCC5 RSTX P113/RX2/INT11_0/PPG4_2 P112/TX2/PPG3_2 P111/RX1/INT10_0/PPG2_2 P110/TX1/PPG1_2/FRCK5_0 P091/SGA0/SIN2_0/INT12_0/TOT2_1/ICU2_1/PPG6_1 P092/SGO0/SCK2_0/INT13_0/TOT3_1/ICU0_1/PPG7_1 P093/SGA1/SOT2_0/INT14_0/ICU3_1/PPG8_1 P094/SGO1/SIN3_0/INT15_0/ICU1_1/PPG9_1 P097/WOT/SOT3_0/INT8_0/TIN0_0/ICU4_1/PPG0_1 NMIX P136/(X1A) P137/(X0A) VSS VCC5 P114/SCK3_0/TIN1_0/ICU5_1/SGA2/TRG3/AN32 P115/SIN4_0/TIN2_0/SGO2/FRCK4_0/AN33 P116/SOT4_0/TIN3_0/SGA3/FRCK3_0/AN34 P117/SCK4_0/TOT0_0/SGO3/TRG4/FRCK2_0/AN35 P120/FRCK1_0/SIN5_0/INT6_0/TOT1_0/PPG5_2/AN36 P121/FRCK0_0/SOT5_0/INT7_0/TOT2_0/PPG6_2/AN37 P122/OCU0_0/SCK5_0/TOT3_0/PPG7_2/AN38 P123/OCU1_0/PPG8_2/DAO0/AN39 AVCC AVRH AVSS/AVRL P107/AN7/PPG5_1/DAO1/ICU11_2/SGO4_1 P106/AN6/PPG4_1/ICU10_2/SGA4_1 P105/SCK5_1/AN5/TOT1_1/PPG3_1/ICU9_2 P104/SOT5_1/AN4/TOT0_1/PPG2_1/ICU8_2 P103/SIN5_1/AN3/TIN3_1/PPG1_1/ICU7_2 P102/SCK4_1/AN2/TIN2_1/PPG10_0/ICU6_2 P101/SOT4_1/AN1/TIN1_1/PPG9_0 P100/SIN4_1/AN0/TIN0_1/PPG8_0 P090/ADTG/PPG0_2 VSS P055/CS2X/V1/FRCK1_1 P056/CS3X/V2/FRCK2_1 P057/RDY/V3/FRCK3_1 DVCC DVSS P060/PWM1P0/AN8 P061/PWM1M0/AN9/SIN1_1 P062/PWM2P0/AN10/ZIN1_1/SOT1_1 P063/PWM2M0/AN11/BIN1_1/SCK1_1 P064/PWM1P1/AN12/AIN1_1/SIN0_1 P065/PWM1M1/AN13/ZIN0_1/SOT0_1 P066/PWM2P1/AN14/BIN0_1/SCK0_1 P067/PWM2M1/AN15/AIN0_1/SIN9_1 DVCC DVSS P070/PWM1P2/AN16/SOT9_1 P071/PWM1M2/AN17/SCK9_1 P072/PWM2P2/AN18/ICU11_1/SIN8_1 P073/PWM2M2/AN19/ICU10_1/SOT8_1 P074/PWM1P3/AN20/PPG12_1/ICU9_1/SCK8_1 P075/PWM1M3/AN21/PPG13_1/ICU8_1/SIN7_1 P076/PWM2P3/AN22/PPG14_1/ICU7_1/SOT7_1 P077/PWM2M3/AN23/PPG15_1/ICU6_1/SCK7_1 DVCC DVSS P080/PWM1P4/AN24/SIN6_0/PPG16_0/AIN0_2 P081/PWM1M4/AN25/SOT6_0/PPG17_0/BIN0_2 P082/PWM2P4/AN26/SCK6_0/PPG18_0/ZIN0_2 P083/PWM2M4/AN27/ICU0_2/PPG19_0 P084/PWM1P5/AN28/ICU1_2/PPG20_0 P085/PWM1M5/AN29/ICU2_2/PPG21_0 P086/PWM2P5/AN30/ICU3_2/PPG22_0 P087/PWM2M5/AN31/ICU4_2/PPG23_0 DVCC DVSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VCCE P015/D29_0/SEG5/D21_1/INT13_1 P016/D30_0/SEG6/D22_1/INT14_1 P017/D31_0/SEG7/D23_1/INT15_1 P020/ASX/SEG8/ICU6_0/OCU0_1 P021/CS0X/SEG9/ICU7_0/OCU1_1 P022/CS1X/SEG10/ICU8_0/OCU2_1 P023/RDX/SEG11/ICU9_0/OCU3_1 P024/WR0X/SEG12/ICU10_0/OCU11_0 P025/WR1X/SEG13/ICU11_0/OCU10_0 P026/A00/SEG14/SPI_CS3/SIN6_1/OCU9_0 P027/A01/SEG15/SPI_CS2/SOT6_1/OCU8_0 P030/A02/SEG16/SPI_CS1/SCK6_1 P031/A03/SEG17/SPI_CS0/SIN9_0 P032/A04/SEG18/SPI_SIO3/SOT9_0/OCU7_0 P033/A05/SEG19/SPI_SIO2/SCK9_0/OCU6_0 P034/A06/SEG20/SPI_SIO1/SIN8_0/OCU5_1 P035/A07/SEG21/SPI_SIO0/SOT8_0/OCU4_1 P036/A08/SEG22/PPG11_0/SPI_CLK/SCK8_0 VCCE VSS P037/A09/SEG23/ST0/PPG12_0/SIN7_0 P040/A10/SEG24/ST1/PPG13_0/SOT7_0 P041/A11/SEG25/ST2/PPG14_0/SCK7_0 P042/A12/SEG26/ST3/PPG15_0/AIN0_0 P043/A13/SEG27/ST4/BIN0_0/SGA4_0/OCU6_1 P044/A14/SEG28/ST5/ZIN0_0/SGO4_0/OCU7_1 P045/A15/SEG29/ST6/AIN1_0/SIN8_2 P046/A16/SEG30/ST7/BIN1_0/SOT8_2 P047/A17/SEG31/ST8/ZIN1_0/SCK8_2 P050/A18/COM0/OCU8_1 P051/A19/COM1/OCU9_1 P052/A20/COM2/OCU10_1 P053/A21/COM3/OCU11_1 P054/SYSCLK/V0/FRCK0_1 VCC5 12 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VSS P170/A02 P167/A01 P166/A00 P165/WR1X P164/WR0X P163/RDX P162/CS1X P161/CS0X P160/ASX P157/D31_0/D23_1 P156/D30_0/D22_1 P155/D29_0/D21_1 P154/D28_0/D20_1 P153/D27_0/D19_1 P152/D26_0/D18_1 P151/D25_0/D17_1 P150/D24_0/D16_1 P147/D23_0/D31_1 P146/D22_0/D30_1 P145/D21_0/D29_1 P144/D20_0/D28_1 P143/D19_0/D27_1 P142/D18_0/D26_1 P141/D17_0/D25_1 P140/D16_0/D24_1 C VSS VCC5 P134/TRG2/INT5_0/ICU5_0/PPG1_3 P133/SCK1_0/INT3_0/ICU4_0/TIOB1/TRG5/PPG11_1 P132/SOT1_0/INT2_0/ICU3_0/TIOB0 P131/TRG1/SIN1_0/INT4_0/ICU2_0/TIOA1 P130/SCK0_0/INT0_0/ICU1_0/TIOA0 P127/SOT0_0/OCU5_0 P126/TRG0/SIN0_0/INT1_0/OCU4_0 P125/OCU3_0/ICU0_0/PPG10_2 VSS X1 X0 MD2 MD1 MD0 Non connection Non connection Non connection Non connection P124/OCU2_0/ICU5_2/PPG9_2 P096/RX0/INT9_0 P095/TX0/PPG10_1 DEBUGIF VSS PIN ASSIGNMENT (LQFP-208) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 ○ TOP VIEW LQFP-208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VCC5 RSTX P113/RX2/INT11_0/PPG4_2 P112/TX2/PPG3_2 P111/RX1/INT10_0/PPG2_2 P110/TX1/PPG1_2/FRCK5_0 P091/SGA0/SIN2_0/INT12_0/TOT2_1/ICU2_1/PPG6_1 P092/SGO0/SCK2_0/INT13_0/TOT3_1/ICU0_1/PPG7_1 P093/SGA1/SOT2_0/INT14_0/ICU3_1/PPG8_1 P094/SGO1/SIN3_0/INT15_0/ICU1_1/PPG9_1 P097/WOT/SOT3_0/INT8_0/TIN0_0/ICU4_1/PPG0_1 Non connection P007/TOT3_2/PPG7_0/INT7_1 P006/TOT2_2/PPG6_0/INT6_1 P005/SCK3_1/TOT1_2/PPG5_0/INT5_1 P004/SOT3_1/TOT0_2/PPG4_0/INT4_1 NMIX P136/(X1A) P137/(X0A) VSS VCC5 P003/SIN3_1/TIN3_2/PPG3_0/INT3_1 P002/SCK2_1/TIN2_2/PPG2_0/INT2_1 P001/SOT2_1/TIN1_2/PPG1_0/INT1_1 P000/SIN2_1/TIN0_2/PPG0_0/INT0_1 P114/SCK3_0/TIN1_0/ICU5_1/SGA2/AN32/TRG3 P115/SIN4_0/TIN2_0/SGO2/FRCK4_0/AN33 P116/SOT4_0/TIN3_0/SGA3/FRCK3_0/AN34 P117/SCK4_0/TOT0_0/SGO3/FRCK2_0/AN35/TRG4 P120/FRCK1_0/SIN5_0/INT6_0/TOT1_0/PPG5_2/AN36 P121/FRCK0_0/SOT5_0/INT7_0/TOT2_0/PPG6_2/AN37 P122/OCU0_0/SCK5_0/TOT3_0/PPG7_2/AN38 P123/OCU1_0/PPG8_2/DAO0/AN39 Non connection AVCC AVRH AVSS/AVRL Non connection P107/AN7/PPG5_1/DAO1/ICU11_2/SGO4_1 P106/AN6/PPG4_1/ICU10_2/SGA4_1 Non connection P105/SCK5_1/AN5/TOT1_1/PPG3_1/ICU9_2 P104/SOT5_1/AN4/TOT0_1/PPG2_1/ICU8_2 Non connection P103/SIN5_1/AN3/TIN3_1/PPG1_1/ICU7_2 P102/SCK4_1/AN2/TIN2_1/PPG10_0/ICU6_2 Non connection P101/SOT4_1/AN1/TIN1_1/PPG9_0 Non connection P100/SIN4_1/AN0/TIN0_1/PPG8_0 P090/ADTG/PPG0_2 Non connection VSS P037/SEG23/ST0/PPG12_0/SIN7_0 P040/SEG24/ST1/PPG13_0/SOT7_0 P041/SEG25/ST2/PPG14_0/SCK7_0 VCC5 VSS P042/SEG26/ST3/PPG15_0/AIN0_0 P043/SEG27/ST4/BIN0_0/SGA4_0/OCU6_1 P044/SEG28/ST5/ZIN0_0/SGO4_0/OCU7_1 P045/SEG29/ST6/AIN1_0/SIN8_2 P046/SEG30/ST7/BIN1_0/SOT8_2 P047/SEG31/ST8/ZIN1_0/SCK8_2 P050/COM0/OCU8_1 P051/COM1/OCU9_1 P052/COM2/OCU10_1 P053/COM3/OCU11_1 P054/V0/FRCK0_1 P055/V1/FRCK1_1 P056/V2/FRCK2_1 P057/V3/FRCK3_1 DVCC DVSS P060/PWM1P0/AN8 P061/PWM1M0/AN9/SIN1_1 P062/PWM2P0/AN10/SOT1_1/ZIN1_1 P063/PWM2M0/AN11/SCK1_1/BIN1_1 P064/PWM1P1/AN12/SIN0_1/AIN1_1 P065/PWM1M1/AN13/SOT0_1/ZIN0_1 P066/PWM2P1/AN14/SCK0_1/BIN0_1 P067/PWM2M1/AN15/SIN9_1/AIN0_1 DVCC DVSS P070/PWM1P2/AN16/SOT9_1 P071/PWM1M2/AN17/SCK9_1 P072/PWM2P2/AN18/SIN8_1/ICU11_1 P073/PWM2M2/AN19/SOT8_1/ICU10_1 P074/PWM1P3/AN20/SCK8_1/ICU9_1/PPG12_1 P075/PWM1M3/AN21/SIN7_1/ICU8_1/PPG13_1 P076/PWM2P3/AN22/SOT7_1/ICU7_1/PPG14_1 P077/PWM2M3/AN23/SCK7_1/ICU6_1/PPG15_1 DVCC DVSS P080/PWM1P4/AN24/SIN6_0/PPG16_0/AIN0_2 P081/PWM1M4/AN25/SOT6_0/PPG17_0/BIN0_2 P082/PWM2P4/AN26/SCK6_0/PPG18_0/ZIN0_2 P083/PWM2M4/AN27/ICU0_2/PPG19_0 P084/PWM1P5/AN28/ICU1_2/PPG20_0 P085/PWM1M5/AN29/ICU2_2/PPG21_0 P086/PWM2P5/AN30/ICU3_2/PPG22_0 P087/PWM2M5/AN31/ICU4_2/PPG23_0 DVCC DVSS 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 VCCE P171/A03 P172/A04 P173/A05 P174/A06 P175/A07 P176/A08 P177/A09 P180/A10 P181/A11 P182/A12 P183/A13 P184/A14 P185/A15 P186/A16 P187/A17 P190/A18 P191/A19 P192/A20 P193/A21 VCCE VSS P194/SYSCLK P195/CS2X P196/CS3X P197/RDY VCC5 VSS P010/SEG0/INT8_1 P011/SEG1/INT9_1 P012/SEG2/INT10_1 P013/SEG3/INT11_1 P014/SEG4/INT12_1 P015/SEG5/INT13_1 P016/SEG6/INT14_1 P017/SEG7/INT15_1 P020/SEG8/ICU6_0/OCU0_1 P021/SEG9/ICU7_0/OCU1_1 P022/SEG10/ICU8_0/OCU2_1 P023/SEG11/ICU9_0/OCU3_1 P024/SEG12/ICU10_0/OCU11_0 P025/SEG13/ICU11_0/OCU10_0 P026/SEG14/SIN6_1/OCU9_0 P027/SEG15/SOT6_1/OCU8_0 P030/SEG16/SCK6_1 P031/SEG17/SIN9_0 P032/SEG18/SOT9_0/OCU7_0 P033/SEG19/SCK9_0/OCU6_0 P034/SEG20/SIN8_0/OCU5_1 P035/SEG21/SOT8_0/OCU4_1 P036/SEG22/PPG11_0/SCK8_0 VCC5 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 13 D a t a S h e e t PIN DESCRIPTION (LQFP-144) Pin Number 2 3 4 5 6 7 8 9 10 14 CONFIDENTIAL Pin Name P015 D29_0 SEG5 D21_1 INT13_1 P016 D30_0 SEG6 D22_1 INT14_1 P017 D31_0 SEG7 D23_1 INT15_1 P020 ASX SEG8 ICU6_0 OCU0_1 P021 CS0X SEG9 ICU7_0 OCU1_1 P022 CS1X SEG10 ICU8_0 OCU2_1 P023 RDX SEG11 ICU9_0 OCU3_1 P024 WR0X SEG12 ICU10_0 OCU11_0 P025 WR1X SEG13 ICU11_0 OCU10_0 I/O Circuit Type H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 Function Description General-Purpose I/O Port External Bus Data I/O pin LCDC Segment(Duty)Output pin External Bus Data I/O pin External Interrupt Request Input pin ch.13 relocation 1 General-Purpose I/O Port External Bus Data I/O pin LCDC Segment(Duty)Output pin External Bus Data I/O pin External Interrupt Request Input pin ch.14 relocation 1 General-Purpose I/O Port External Bus Data I/O pin LCDC Segment(Duty)Output pin External Bus Data I/O pin External Interrupt Request Input pin ch.15 relocation 1 General-Purpose I/O Port External Bus Address-Strobe Output pin LCDC Segment(Duty)Output pin Input Capture Input pin ch.6 relocation 0 Output Compare Output pin ch.0 relocation 1 General-Purpose I/O Port External Bus Chip-Select 0 Output pin LCDC Segment(Duty)Output pin Input Capture Input pin ch.7 relocation 0 Output Compare Output pin ch.1 relocation 1 General-Purpose I/O Port External Bus Chip-Select 1 Output pin LCDC Segment(Duty)Output pin Input Capture Input pin ch.8 relocation 0 Output Compare Output pin ch.2 relocation 1 General-Purpose I/O Port External Bus Read-Strobe Output pin LCDC Segment(Duty)Output pin Input Capture Input pin ch.9 relocation 0 Output Compare Output pin ch.3 relocation 1 General-Purpose I/O Port External Bus Write-Strobe 0 Output pin LCDC Segment(Duty)Output pin Input Capture Input pin ch.10 relocation 0 Output Compare Output pin ch.11 relocation 0 General-Purpose I/O Port External Bus Write-Strobe 1 Output pin LCDC Segment(Duty)Output pin Input Capture Input pin ch.11 relocation 0 Output Compare Output pin ch.10 relocation 0 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 11 12 13 14 15 16 17 18 Pin Name P026 A00 SEG14 SPI_CS3 SIN6_1 OCU9_0 P027 A01 SEG15 SPI_CS2 SOT6_1 OCU8_0 P030 A02 SEG16 SPI_CS1 SCK6_1 P031 A03 SEG17 SPI_CS0 SIN9_0 P032 A04 SEG18 SPI_SIO3 SOT9_0 OCU7_0 P033 A05 SEG19 SPI_SIO2 SCK9_0 OCU6_0 P034 A06 SEG20 SPI_SIO1 SIN8_0 OCU5_1 P035 A07 SEG21 SPI_SIO0 SOT8_0 OCU4_1 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL I/O Circuit Type H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 H/I4*1 Function Description General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin HS_SPI SSEL3 Output pin (Not supported) LIN_UART Serial Input pin ch.6 relocation 1 Output Compare Output pin ch.9 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin HS_SPI SSEL2 Output pin (Not supported) LIN_UART Serial Output pin ch.6 relocation 1 Output Compare Output pin ch.8 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin HS_SPI SSEL1 Output pin (Not supported) LIN_UART Serial Clock I/O pin ch.6 relocation 1 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin HS_SPI SSEL0 I/O pin (Not supported) Multi-function Serial Input pin ch.9 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin HS_SPI SDATA3 I/O pin (Not supported) Multi-function Serial Output pin ch.9 relocation 0 Output Compare Output pin ch.7 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin HS_SPI SDATA2 I/O pin (Not supported) Multi-function Serial Clock I/O pin ch.9 relocation 0 Output Compare Output pin ch.6 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin HS_SPI SDATA1 I/O pin (Not supported) Multi-function Serial Input pin ch.8 relocation 0 Output Compare Output pin ch.5 relocation 1 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin HS_SPI SDATA0 I/O pin (Not supported) Multi-function Serial Output pin ch.8 relocation 0 Output Compare Output pin ch.4 relocation 1 15 D a t a S h e e t Pin Number 19 22 23 24 25 26 27 16 CONFIDENTIAL Pin Name P036 A08 SEG22 PPG11_0 SPI_CLK SCK8_0 P037 A09 SEG23 ST0 PPG12_0 SIN7_0 P040 A10 SEG24 ST1 PPG13_0 SOT7_0 P041 A11 SEG25 ST2 PPG14_0 SCK7_0 P042 A12 SEG26 ST3 PPG15_0 AIN0_0 P043 A13 SEG27 ST4 BIN0_0 SGA4_0 OCU6_1 P044 A14 SEG28 ST5 ZIN0_0 SGO4_0 OCU7_1 I/O Circuit Type H/I4*1 I I I I I I Function Description General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin PPG Output pin ch.11 relocation 0 HS_SPI SCLK I/O pin (Not supported) Multi-function Serial Clock I/O pin ch.8 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin PPG Output pin ch.12 relocation 0 LIN_UART Serial Input pin ch.7 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin PPG Output pin ch.13 relocation 0 LIN_UART Serial Output pin ch.7 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin PPG Output pin ch.14 relocation 0 LIN_UART Serial Clock I/O pin ch.7 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin PPG Output pin ch.15 relocation 0 Up/down Counter AIN Input pin ch.0 relocation 0 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter BIN Input pin ch.0 relocation 0 Sound Generator SGA Output pin ch.4 relocation 0 Output Compare Output pin ch.6 relocation 1 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter ZIN Input pin ch.0 relocation 0 Sound Generator SGO Output pin ch.4 relocation 0 Output Compare Output pin ch.7 relocation 1 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 28 29 30 31 32 33 34 35 38 39 Pin Name P045 A15 SEG29 ST6 AIN1_0 SIN8_2 P046 A16 SEG30 ST7 BIN1_0 SOT8_2 P047 A17 SEG31 ST8 ZIN1_0 SCK8_2 P050 A18 COM0 OCU8_1 P051 A19 COM1 OCU9_1 P052 A20 COM2 OCU10_1 P053 A21 COM3 OCU11_1 P054 SYSCLK V0 FRCK0_1 P055 CS2X V1 FRCK1_1 P056 CS3X V2 FRCK2_1 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL I/O Circuit Type I I I I I I I I2 I2 I2 Function Description General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter AIN Input pin ch.1 relocation 0 Multi-function Serial Input pin ch.8 relocation 2 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter BIN Input pin ch.1 relocation 0 Multi-function Serial Output pin ch.8 relocation 2 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter ZIN Input pin ch.1 relocation 0 Multi-function Serial Clock I/O pin ch.8 relocation 2 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Common Output pin Output Compare Output pin ch.8 relocation 1 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Common Output pin Output Compare Output pin ch.9 relocation 1 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Common Output pin Output Compare Output pin ch.10 relocation 1 General-Purpose I/O Port External Bus Address Output pin LCDC Segment(Duty)Common Output pin Output Compare Output pin ch.11 relocation 1 General-Purpose I/O Port External Bus Clock Output pin LCDC Reference Voltage V0 Input pin Free-Run Timer Clock Input pin ch.0 relocation 1 General-Purpose I/O Port External Bus Chip-Select 2 Output pin LCDC Reference Voltage V1 Input pin Free-Run Timer Clock Input pin ch.1 relocation 1 General-Purpose I/O Port External Bus Chip-Select 3 Output pin LCDC Reference Voltage V2 Input pin Free-Run Timer Clock Input pin ch.2 relocation 1 17 D a t a S h e e t Pin Number 40 43 44 45 46 47 48 49 50 53 18 CONFIDENTIAL Pin Name P057 RDY V3 FRCK3_1 P060 PWM1P0 AN8 P061 PWM1M0 AN9 SIN1_1 P062 PWM2P0 AN10 ZIN1_1 SOT1_1 P063 PWM2M0 AN11 BIN1_1 SCK1_1 P064 PWM1P1 AN12 AIN1_1 SIN0_1 P065 PWM1M1 AN13 ZIN0_1 SOT0_1 P066 PWM2P1 AN14 BIN0_1 SCK0_1 P067 PWM2M1 AN15 AIN0_1 SIN9_1 P070 PWM1P2 AN16 SOT9_1 I/O Circuit Type I3 K K K K K K K K K Function Description General-Purpose I/O Port (Input only. No output.) External Bus RDY Input pin LCDC Reference Voltage V3 Input pin Free-Run Timer Clock Input pin ch.3 relocation 1 General-Purpose I/O Port SMC Output pin ch.0 ADC Analog Input pin ch.8 General-Purpose I/O Port SMC Output pin ch.0 ADC Analog Input pin ch.9 Multi-function Serial Input pin ch.1 relocation 1 General-Purpose I/O Port SMC Output pin ch.0 ADC Analog Input pin ch.10 Up/down Counter ZIN Input pin ch.1 relocation 1 Multi-function Serial Output pin ch.1 relocation 1 General-Purpose I/O Port SMC Output pin ch.0 ADC Analog Input pin ch.11 Up/down Counter BIN Input pin ch.1 relocation 1 Multi-function Serial Clock I/O pin ch.1 relocation 1 General-Purpose I/O Port SMC Output pin ch.1 ADC Analog Input pin ch.12 Up/down Counter AIN Input pin ch.1 relocation 1 Multi-function Serial Input pin ch.0 relocation 1 General-Purpose I/O Port SMC Output pin ch.1 ADC Analog Input pin ch.13 Up/down Counter ZIN Input pin ch.0 relocation 1 Multi-function Serial Output pin ch.0 relocation 1 General-Purpose I/O Port SMC Output pin ch.1 ADC Analog Input pin ch.14 Up/down Counter BIN Input pin ch.0 relocation 1 Multi-function Serial Clock I/O pin ch.0 relocation 1 General-Purpose I/O Port SMC Output pin ch.1 ADC Analog Input pin ch.15 Up/down Counter AIN Input pin ch.0 relocation 1 Multi-function Serial Input pin ch.9 relocation 1 General-Purpose I/O Port SMC Output pin ch.2 ADC Analog Input pin ch.16 Multi-function Serial Output pin ch.9 relocation 1 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 54 55 56 57 58 59 60 63 Pin Name P071 PWM1M2 AN17 SCK9_1 P072 PWM2P2 AN18 ICU11_1 SIN8_1 P073 PWM2M2 AN19 ICU10_1 SOT8_1 P074 PWM1P3 AN20 PPG12_1 ICU9_1 SCK8_1 P075 PWM1M3 AN21 PPG13_1 ICU8_1 SIN7_1 P076 PWM2P3 AN22 PPG14_1 ICU7_1 SOT7_1 P077 PWM2M3 AN23 PPG15_1 ICU6_1 SCK7_1 P080 PWM1P4 AN24 SIN6_0 PPG16_0 AIN0_2 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL I/O Circuit Type K K K K K K K K Function Description General-Purpose I/O Port SMC Output pin ch.2 ADC Analog Input pin ch.17 Multi-function Serial Clock I/O pin ch.9 relocation 1 General-Purpose I/O Port SMC Output pin ch.2 ADC Analog Input pin ch.18 Input Capture Input pin ch.11 relocation 1 Multi-function Serial Input pin ch.8 relocation 1 General-Purpose I/O Port SMC Output pin ch.2 ADC Analog Input pin ch.19 Input Capture Input pin ch.10 relocation 1 Multi-function Serial Output pin ch.8 relocation 1 General-Purpose I/O Port SMC Output pin ch.3 ADC Analog Input pin ch.20 PPG Output pin ch.12 relocation 1 Input Capture Input pin ch.9 relocation 1 Multi-function Serial Clock I/O pin ch.8 relocation 1 General-Purpose I/O Port SMC Output pin ch.3 ADC Analog Input pin ch.21 PPG Output pin ch.13 relocation 1 Input Capture Input pin ch.8 relocation 1 LIN_UART Serial Input pin ch.7 relocation 1 General-Purpose I/O Port SMC Output pin ch.3 ADC Analog Input pin ch.22 PPG Output pin ch.14 relocation 1 Input Capture Input pin ch.7 relocation 1 LIN_UART Serial Output pin ch.7 relocation 1 General-Purpose I/O Port SMC Output pin ch.3 ADC Analog Input pin ch.23 PPG Output pin ch.15 relocation 1 Input Capture Input pin ch.6 relocation 1 LIN_UART Serial Clock I/O pin ch.7 relocation 1 General-Purpose I/O Port SMC Output pin ch.4 ADC Analog Input pin ch.24 LIN_UART Serial Input pin ch.6 relocation 0 PPG Output pin ch.16 relocation 0 Up/down Counter AIN Input pin ch.0 relocation 2 19 D a t a S h e e t Pin Number 64 65 66 67 68 69 70 Pin Name P081 PWM1M4 AN25 SOT6_0 PPG17_0 BIN0_2 P082 PWM2P4 AN26 SCK6_0 PPG18_0 ZIN0_2 P083 PWM2M4 AN27 ICU0_2 PPG19_0 P084 PWM1P5 AN28 ICU1_2 PPG20_0 P085 PWM1M5 AN29 ICU2_2 PPG21_0 P086 PWM2P5 AN30 ICU3_2 PPG22_0 P087 PWM2M5 AN31 ICU4_2 PPG23_0 I/O Circuit Type K K K K K K K P090 73 74 20 CONFIDENTIAL ADTG PPG0_2 P100 SIN4_1 AN0 TIN0_1 PPG8_0 Function Description General-Purpose I/O Port SMC Output pin ch.4 ADC Analog Input pin ch.25 LIN_UART Serial Output pin ch.6 relocation 0 PPG Output pin ch.17 relocation 0 Up/down Counter BIN Input pin ch.0 relocation 2 General-Purpose I/O Port SMC Output pin ch.4 ADC Analog Input pin ch.26 LIN_UART Serial Clock I/O pin ch.6 relocation 0 PPG Output pin ch.18 relocation 0 Up/down Counter ZIN Input pin ch.0 relocation 2 General-Purpose I/O Port SMC Output pin ch.4 ADC Analog Input pin ch.27 Input Capture Input pin ch.0 relocation 2 PPG Output pin ch.19 relocation 0 General-Purpose I/O Port SMC Output pin ch.5 ADC Analog Input pin ch.28 Input Capture Input pin ch.1 relocation 2 PPG Output pin ch.20 relocation 0 General-Purpose I/O Port SMC Output pin ch.5 ADC Analog Input pin ch.29 Input Capture Input pin ch.2 relocation 2 PPG Output pin ch.21 relocation 0 General-Purpose I/O Port SMC Output pin ch.5 ADC Analog Input pin ch.30 Input Capture Input pin ch.3 relocation 2 PPG Output pin ch.22 relocation 0 General-Purpose I/O Port SMC Output pin ch.5 ADC Analog Input pin ch.31 Input Capture Input pin ch.4 relocation 2 PPG Output pin ch.23 relocation 0 General-Purpose I/O Port M J ADC External Trigger Input pin PPG Output pin ch.0 relocation 2 General-Purpose I/O Port LIN_UART Serial Input pin ch.4 relocation 1 ADC Analog Input pin ch.0 Reload Timer Event Input pin ch.0 relocation 1 PPG Output pin ch.8 relocation 0 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 75 76 77 78 79 80 81 85 Pin Name P101 SOT4_1 AN1 TIN1_1 PPG9_0 P102 SCK4_1 AN2 TIN2_1 PPG10_0 ICU6_2 P103 SIN5_1 AN3 TIN3_1 PPG1_1 ICU7_2 P104 SOT5_1 AN4 TOT0_1 PPG2_1 ICU8_2 P105 SCK5_1 AN5 TOT1_1 PPG3_1 ICU9_2 P106 AN6 PPG4_1 ICU10_2 SGA4_1 P107 AN7 PPG5_1 DAO1 ICU11_2 SGO4_1 P123 OCU1_0 PPG8_2 DAO0 AN39 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL I/O Circuit Type J J J J J J L L Function Description General-Purpose I/O Port LIN_UART Serial Output pin ch.4 relocation 1 ADC Analog Input pin ch.1 Reload Timer Event Input pin ch.1 relocation 1 PPG Output pin ch.9 relocation 0 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.4 relocation 1 ADC Analog Input pin ch.2 Reload Timer Event Input pin ch.2 relocation 1 PPG Output pin ch.10 relocation 0 Input Capture Input pin ch.6 relocation 2 General-Purpose I/O Port LIN_UART Serial Input pin ch.5 relocation 1 ADC Analog Input pin ch.3 Reload Timer Event Input pin ch.3 relocation 1 PPG Output pin ch.1 relocation 1 Input Capture Input pin ch.7 relocation 2 General-Purpose I/O Port LIN_UART Serial Output pin ch.5 relocation 1 ADC Analog Input pin ch.4 Reload Timer Output pin ch.0 relocation 1 PPG Output pin ch.2 relocation 1 Input Capture Input pin ch.8 relocation 2 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.5 relocation 1 ADC Analog Input pin ch.5 Reload Timer Output pin ch.1 relocation 1 PPG Output pin ch.3 relocation 1 Input Capture Input pin ch.9 relocation 2 General-Purpose I/O Port ADC Analog Input pin ch.6 PPG Output pin ch.4 relocation 1 Input Capture Input pin ch.10 relocation 2 Sound Generator SGA Output pin ch.4 relocation 1 General-Purpose I/O Port ADC Analog Input pin ch.7 PPG Output pin ch.5 relocation 1 DAC Output pin ch.1 Input Capture Input pin ch.11 relocation 2 Sound Generator SGO Output pin ch.4 relocation 1 General-Purpose I/O Port Output Compare Output pin ch.1 relocation 0 PPG Output pin ch.8 relocation 2 DAC Output pin ch.0 ADC Analog Input pin ch.39 21 D a t a S h e e t Pin Number 86 87 88 89 90 91 92 22 CONFIDENTIAL Pin Name P122 OCU0_0 SCK5_0 TOT3_0 PPG7_2 AN38 P121 FRCK0_0 SOT5_0 INT7_0 TOT2_0 PPG6_2 AN37 P120 FRCK1_0 SIN5_0 INT6_0 TOT1_0 PPG5_2 AN36 P117 SCK4_0 TOT0_0 SGO3 TRG4 FRCK2_0 AN35 P116 SOT4_0 TIN3_0 SGA3 FRCK3_0 AN34 P115 SIN4_0 TIN2_0 SGO2 FRCK4_0 AN33 P114 SCK3_0 TIN1_0 ICU5_1 SGA2 TRG3 AN32 I/O Circuit Type J J J J J J J Function Description General-Purpose I/O Port Output Compare Output pin ch.0 relocation 0 LIN_UART Serial Clock I/O pin ch.5 relocation 0 Reload Timer Output pin ch.3 relocation 0 PPG Output pin ch.7 relocation 2 ADC Analog Input pin ch.38 General-Purpose I/O Port Free-Run Timer Clock Input pin ch.0 relocation 0 LIN_UART Serial Output pin ch.5 relocation 0 External Interrupt Request Input pin ch.7 relocation 0 Reload Timer Output pin ch.2 relocation 0 PPG Output pin ch.6 relocation 2 ADC Analog Input pin ch.37 General-Purpose I/O Port Free-Run Timer Clock Input pin ch.1 relocation 0 LIN_UART Serial Input pin ch.5 relocation 0 External Interrupt Request Input pin ch.6 relocation 0 Reload Timer Output pin ch.1 relocation 0 PPG Output pin ch.5 relocation 2 ADC Analog Input pin ch.36 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.4 relocation 0 Reload Timer Output pin ch.0 relocation 0 Sound Generator SGO Output pin ch.3 PPG Trigger Input pin 4 (ch.16-ch.19) Free-Run Timer Clock Input pin ch.2 relocation 0 ADC Analog Input pin ch.35 General-Purpose I/O Port LIN_UART Serial Output pin ch.4 relocation 0 Reload Timer Event Input pin ch.3 relocation 0 Sound Generator SGA Output pin ch.3 Free-Run Timer Clock Input pin ch.3 relocation 0 ADC Analog Input pin ch.34 General-Purpose I/O Port LIN_UART Serial Input pin ch.4 relocation 0 Reload Timer Event Input pin ch.2 relocation 0 Sound Generator SGO Output pin ch.2 Free-Run Timer Clock Input pin ch.4 relocation 0 ADC Analog Input pin ch.33 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.3 relocation 0 Reload Timer Event Input pin ch.1 relocation 0 Input Capture Input pin ch.5 relocation 1 Sound Generator SGA Output pin ch.2 PPG Trigger Input pin 3 (ch.12-ch.15) ADC Analog Input pin ch.32 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 95 96 97 98 99 100 101 102 103 104 Pin Name P137 (X0A) P136 (X1A) NMIX P097 WOT SOT3_0 INT8_0 TIN0_0 ICU4_1 PPG0_1 P094 SGO1 SIN3_0 INT15_0 ICU1_1 PPG9_1 P093 SGA1 SOT2_0 INT14_0 ICU3_1 PPG8_1 P092 SGO0 SCK2_0 INT13_0 TOT3_1 ICU0_1 PPG7_1 P091 SGA0 SIN2_0 INT12_0 TOT2_1 ICU2_1 PPG6_1 P110 TX1 PPG1_2 FRCK5_0 P111 RX1 INT10_0 PPG2_2 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL I/O Circuit Type M (Y) M (Y) R M M M M M M M Function Description General-Purpose I/O Port Sub Clock oscillation Input pin (only dual clock product) General-Purpose I/O Port Sub Clock oscillation Output pin (only dual clock product) NMI Pin General-Purpose I/O Port RTC Overflow Output pin LIN_UART Serial Output pin ch.3 relocation 0 External Interrupt Request Input pin ch.8 relocation 0 Reload Timer Event Input pin ch.0 relocation 0 Input Capture Input pin ch.4 relocation 1 PPG Output pin ch.0 relocation 1 General-Purpose I/O Port Sound Generator SGO Output pin ch.1 LIN_UART Serial Input pin ch.3 relocation 0 External Interrupt Request Input pin ch.15 relocation 0 Input Capture Input pin ch.1 relocation 1 PPG Output pin ch.9 relocation 1 General-Purpose I/O Port Sound Generator SGA Output pin ch.1 LIN_UART Serial Output pin ch.2 relocation 0 External Interrupt Request Input pin ch.14 relocation 0 Input Capture Input pin ch.3 relocation 1 PPG Output pin ch.8 relocation 1 General-Purpose I/O Port Sound Generator SGO Output pin ch.0 LIN_UART Serial Clock I/O pin ch.2 relocation 0 External Interrupt Request Input pin ch.13 relocation 0 Reload Timer Output pin ch.3 relocation 1 Input Capture Input pin ch.0 relocation 1 PPG Output pin ch.7 relocation 1 General-Purpose I/O Port Sound Generator SGA Output pin ch.0 LIN_UART Serial Input pin ch.2 relocation 0 External Interrupt Request Input pin ch.12 relocation 0 Reload Timer Output pin ch.2 relocation 1 Input Capture Input pin ch.2 relocation 1 PPG Output pin ch.6 relocation 1 General-Purpose I/O Port CAN TX Data Output pin ch.1 PPG Output pin ch.1 relocation 2 Free-Run Timer Clock Input pin ch.5 relocation 0 General-Purpose I/O Port CAN RX Data Input pin ch.1 External Interrupt Request Input pin ch.10 relocation 0 PPG Output pin ch.2 relocation 2 23 D a t a S h e e t Pin Number 105 106 107 110 111 112 113 114 115 116 117 118 120 121 122 123 24 CONFIDENTIAL Pin Name P112 TX2 PPG3_2 P113 RX2 INT11_0 PPG4_2 RSTX DEBUGIF P095 TX0 PPG10_1 P096 RX0 INT9_0 P124 OCU2_0 ICU5_2 PPG9_2 MD0 MD1 MD2 X0 X1 P125 OCU3_0 ICU0_0 PPG10_2 P126 TRG0 SIN0_0 INT1_0 OCU4_0 P127 SOT0_0 OCU5_0 P130 SCK0_0 INT0_0 ICU1_0 TIOA0 I/O Circuit Type M M R B M M M A A R2 X X M M N N Function Description General-Purpose I/O Port CAN TX Data Output pin ch.2 PPG Output pin ch.3 relocation 2 General-Purpose I/O Port CAN RX Data Input pin ch.2 External Interrupt Request Input pin ch.11 relocation 0 PPG Output pin ch.4 relocation 2 Reset Pin DEBUG I/F pin General-Purpose I/O Port CAN TX Data Output pin ch.0 PPG Output pin ch.10 relocation 1 General-Purpose I/O Port CAN RX Data Input pin ch.0 External Interrupt Request Input pin ch.9 relocation 0 General-Purpose I/O Port Output Compare Output pin ch.2 relocation 0 Input Capture Input pin ch.5 relocation 2 PPG Output pin ch.9 relocation 2 Mode Pin 0 Mode Pin 1 Mode Pin 2 Main Clock oscillation Input pin Main Clock oscillation Output pin General-Purpose I/O Port Output Compare Output pin ch.3 relocation 0 Input Capture Input pin ch.0 relocation 0 PPG Output pin ch.10 relocation 2 General-Purpose I/O Port PPG Trigger Input pin 0 (ch.0-ch.3) Multi-function Serial Input pin ch.0 relocation 0 External Interrupt Request Input pin ch.1 relocation 0 Output Compare Output pin ch.4 relocation 0 General-Purpose I/O Port Multi-function Serial Output pin ch.0 relocation 0 Output Compare Output pin ch.5 relocation 0 General-Purpose I/O Port Multi-function Serial Clock I/O pin ch.0 relocation 0 External Interrupt Request Input pin ch.0 relocation 0 Input Capture Input pin ch.1 relocation 0 Base Timer Output pin ch.0 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 124 125 126 127 131 132 133 Pin Name P131 TRG1 SIN1_0 INT4_0 ICU2_0 TIOA1 P132 SOT1_0 INT2_0 ICU3_0 TIOB0 P133 SCK1_0 INT3_0 ICU4_0 TIOB1 PPG11_1 TRG5 P134 TRG2 INT5_0 ICU5_0 PPG1_3 P000 D16_0 SIN2_1 TIN0_2 PPG0_0 D24_1 INT0_1 P001 D17_0 SOT2_1 TIN1_2 PPG1_0 D25_1 INT1_1 P002 D18_0 SCK2_1 TIN2_2 PPG2_0 D26_1 INT2_1 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL I/O Circuit Type M N N M M M M Function Description General-Purpose I/O Port PPG Trigger Input pin 1 (ch.4-ch.7) Multi-function Serial Input pin ch.1 relocation 0 External Interrupt Request Input pin ch.4 relocation 0 Input Capture Input pin ch.2 relocation 0 Base Timer I/O pin ch.1 General-Purpose I/O Port Multi-function Serial Output pin ch.1 relocation 0 External Interrupt Request Input pin ch.2 relocation 0 Input Capture Input pin ch.3 relocation 0 Base Timer Input pin ch.0 General-Purpose I/O Port Multi-function Serial Clock I/O pin ch.1 relocation 0 External Interrupt Request Input pin ch.3 relocation 0 Input Capture Input pin ch.4 relocation 0 Base Timer Input pin ch.1 PPG Output pin ch.11 relocation 1 PPG Trigger Input pin 5 (ch.20-ch.23) General-Purpose I/O Port PPG Trigger Input pin 2 (ch.8-ch.11) External Interrupt Request Input pin ch.5 relocation 0 Input Capture Input pin ch.5 relocation 0 PPG Output pin ch.1 relocation 3 General-Purpose I/O Port External Bus Data I/O pin LIN_UART Serial Input pin ch.2 relocation 1 Reload Timer Event Input pin ch.0 relocation 2 PPG Output pin ch.0 relocation 0 External Bus Data I/O pin External Interrupt Request Input pin ch.0 relocation 1 General-Purpose I/O Port External Bus Data I/O pin LIN_UART Serial Output pin ch.2 relocation 1 Reload Timer Event Input pin ch.1 relocation 2 PPG Output pin ch.1 relocation 0 External Bus Data I/O pin External Interrupt Request Input pin ch.1 relocation 1 General-Purpose I/O Port External Bus Data I/O pin LIN_UART Serial Clock I/O pin ch.2 relocation 1 Reload Timer Event Input pin ch.2 relocation 2 PPG Output pin ch.2 relocation 0 External Bus Data I/O pin External Interrupt Request Input pin ch.2 relocation 1 25 D a t a S h e e t Pin Number 134 135 136 137 138 139 140 26 CONFIDENTIAL Pin Name P003 D19_0 SIN3_1 TIN3_2 PPG3_0 D27_1 INT3_1 P004 D20_0 SOT3_1 TOT0_2 PPG4_0 D28_1 INT4_1 P005 D21_0 SCK3_1 TOT1_2 PPG5_0 D29_1 INT5_1 P006 D22_0 TOT2_2 PPG6_0 D30_1 INT6_1 P007 D23_0 TOT3_2 PPG7_0 D31_1 INT7_1 P010 D24_0 SEG0 D16_1 INT8_1 P011 D25_0 SEG1 D17_1 INT9_1 I/O Circuit Type M M M M M H/I4*1 H/I4*1 Function Description General-Purpose I/O Port External Bus Data I/O pin LIN_UART Serial Input pin ch.3 relocation 1 Reload Timer Event Input pin ch.3 relocation 2 PPG Output pin ch.3 relocation 0 External Bus Data I/O pin External Interrupt Request Input pin ch.3 relocation 1 General-Purpose I/O Port External Bus Data I/O pin LIN_UART Serial Output pin ch.3 relocation 1 Reload Timer Output pin ch.0 relocation 2 PPG Output pin ch.4 relocation 0 External Bus Data I/O pin External Interrupt Request Input pin ch.4 relocation 1 General-Purpose I/O Port External Bus Data I/O pin LIN_UART Serial Clock I/O pin ch.3 relocation 1 Reload Timer Output pin ch.1 relocation 2 PPG Output pin ch.5 relocation 0 External Bus Data I/O pin External Interrupt Request Input pin ch.5 relocation 1 General-Purpose I/O Port External Bus Data I/O pin Reload Timer Output pin ch.2 relocation 2 PPG Output pin ch.6 relocation 0 External Bus Data I/O pin External Interrupt Request Input pin ch.6 relocation 1 General-Purpose I/O Port External Bus Data I/O pin Reload Timer Output pin ch.3 relocation 2 PPG Output pin ch.7 relocation 0 External Bus Data I/O pin External Interrupt Request Input pin ch.7 relocation 1 General-Purpose I/O Port External Bus Data I/O pin LCDC Segment(Duty)Output pin External Bus Data I/O pin External Interrupt Request Input pin ch.8 relocation 1 General-Purpose I/O Port External Bus Data I/O pin LCDC Segment(Duty)Output pin External Bus Data I/O pin External Interrupt Request Input pin ch.9 relocation 1 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number Pin Name I/O Circuit Type Function Description P012 General-Purpose I/O Port D26_0 External Bus Data I/O pin *1 141 SEG2 H/I4 LCDC Segment(Duty)Output pin D18_1 External Bus Data I/O pin INT10_1 External Interrupt Request Input pin ch.10 relocation 1 P013 General-Purpose I/O Port D27_0 External Bus Data I/O pin 142 SEG3 H/I4*1 LCDC Segment(Duty)Output pin D19_1 External Bus Data I/O pin INT11_1 External Interrupt Request Input pin ch.11 relocation 1 P014 General-Purpose I/O Port D28_0 External Bus Data I/O pin *1 143 SEG4 H/I4 LCDC Segment(Duty)Output pin D20_1 External Bus Data I/O pin INT12_1 External Interrupt Request Input pin ch.12 relocation 1 1 VCCE +3.3v/+5.0v Power Supply pin 20 VCCE +3.3v/+5.0v Power Supply pin 21 VSS GND pin 36 VCC5 +5.0v Power Supply pin 37 VSS GND pin 41 DVCC Power Supply pin for SMC high current 42 DVSS GND pin for SMC high current 51 DVCC Power Supply pin for SMC high current 52 DVSS GND pin for SMC high current 61 DVCC Power Supply pin for SMC high current 62 DVSS GND pin for SMC high current 71 DVCC Power Supply pin for SMC high current 72 DVSS GND pin for SMC high current 82 AVSS/AVRL ADC, DAC GND pin / Low Reference Voltage pin 83 AVRH ADC High Reference Voltage pin 84 AVCC ADC,DAC Analog Power Supply pin 93 VCC5 +5.0v Power Supply pin 94 VSS GND pin 108 VCC5 +5.0v Power Supply pin 109 VSS GND pin 119 VSS GND pin 128 VCC5 +5.0v Power Supply pin 129 VSS GND pin 130 C External Capacitance Connection Pin 144 VSS GND pin *1: I/O circuit type H is applied to MB91F575/7 and type I4 applied to MB91F578/9. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 27 D a t a S h e e t PIN DESCRIPTION (LQFP-208) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 28 CONFIDENTIAL Pin Name VCCE P171 A03 P172 A04 P173 A05 P174 A06 P175 A07 P176 A08 P177 A09 P180 A10 P181 A11 P182 A12 P183 A13 P184 A14 P185 A15 P186 A16 P187 A17 P190 A18 P191 A19 P192 A20 P193 A21 VCCE VSS P194 SYSCLK P195 CS2X P196 CS3X P197 RDY VCC5 VSS P010 SEG0 I/O Circuit Type M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 H Function Description +3.3v/+5.0v Power Supply pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin +3.3v/+5.0v Power Supply pin GND pin General-Purpose I/O Port External Bus Clock Output pin General-Purpose I/O Port External Bus Chip-Select 2 Output pin General-Purpose I/O Port External Bus Chip-Select 3 Output pin General-Purpose I/O Port External Bus RDY Input pin +5.0v Power Supply pin GND pin General-Purpose I/O Port LCDC Segment(Duty)Output pin MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin Name INT8_1 P011 SEG1 INT9_1 P012 SEG2 INT10_1 P013 SEG3 INT11_1 P014 SEG4 INT12_1 P015 SEG5 INT13_1 P016 SEG6 INT14_1 P017 SEG7 INT15_1 P020 SEG8 ICU6_0 OCU0_1 P021 SEG9 ICU7_0 OCU1_1 P022 SEG10 ICU8_0 OCU2_1 P023 SEG11 ICU9_0 OCU3_1 P024 SEG12 ICU10_0 OCU11_0 P025 SEG13 ICU11_0 OCU10_0 P026 SEG14 SIN6_1 OCU9_0 P027 SEG15 SOT6_1 OCU8_0 P030 I/O Circuit Type H June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL I I I I I I I I I I I I I I I I I Function Description External Interrupt Request Input pin ch.8 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin External Interrupt Request Input pin ch.9 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin External Interrupt Request Input pin ch.10 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin External Interrupt Request Input pin ch.11 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin External Interrupt Request Input pin ch.12 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin External Interrupt Request Input pin ch.13 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin External Interrupt Request Input pin ch.14 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin External Interrupt Request Input pin ch.15 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin Input Capture Input pin ch.6 relocation 0 Output Compare Output pin ch.0 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin Input Capture Input pin ch.7 relocation 0 Output Compare Output pin ch.1 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin Input Capture Input pin ch.8 relocation 0 Output Compare Output pin ch.2 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin Input Capture Input pin ch.9 relocation 0 Output Compare Output pin ch.3 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin Input Capture Input pin ch.10 relocation 0 Output Compare Output pin ch.11 relocation 0 General-Purpose I/O Port LCDC Segment(Duty)Output pin Input Capture Input pin ch.11 relocation 0 Output Compare Output pin ch.10 relocation 0 General-Purpose I/O Port LCDC Segment(Duty)Output pin LIN_UART Serial Input pin ch.6 relocation 1 Output Compare Output pin ch.9 relocation 0 General-Purpose I/O Port LCDC Segment(Duty)Output pin LIN_UART Serial Output pin ch.6 relocation 1 Output Compare Output pin ch.8 relocation 8 General-Purpose I/O Port 29 D a t a S h e e t Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 30 CONFIDENTIAL Pin Name SEG16 SCK6_1 P031 SEG17 SIN9_0 P032 SEG18 SOT9_0 OCU7_0 P033 SEG19 SCK9_0 OCU6_0 P034 SEG20 SIN8_0 OCU5_1 P035 SEG21 SOT8_0 OCU4_1 P036 SEG22 PPG11_0 SCK8_0 VCC5 VSS P037 SEG23 ST0 PPG12_0 SIN7_0 P040 SEG24 ST1 PPG13_0 SOT7_0 P041 SEG25 ST2 PPG14_0 SCK7_0 VCC5 VSS P042 SEG26 ST3 PPG15_0 AIN0_0 P043 SEG27 ST4 BIN0_0 SGA4_0 OCU6_1 I/O Circuit Type I I I I I I I - I I I - I I Function Description LCDC Segment(Duty)Output pin LIN_UART Serial Clock I/O pin ch.6 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin Multi-function Serial Input pin ch.9 relocation 0 General-Purpose I/O Port LCDC Segment(Duty)Output pin Multi-function Serial Output pin ch.9 relocation 0 Output Compare Output pin ch.7 relocation 7 General-Purpose I/O Port LCDC Segment(Duty)Output pin Multi-function Serial Clock I/O pin ch.9 relocation 0 Output Compare Output pin ch.6 relocation 6 General-Purpose I/O Port LCDC Segment(Duty)Output pin Multi-function Serial Input pin ch.8 relocation 0 Output Compare Output pin ch.5 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin Multi-function Serial Output pin ch.8 relocation 0 Output Compare Output pin ch.4 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin PPG Output pin ch.11 relocation 0 Multi-function Serial Clock I/O pin ch.8 relocation 0 +5.0v Power Supply pin GND pin General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin PPG Output pin ch.12 relocation 0 LIN_UART Serial Input pin ch.7 relocation 0 General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin PPG Output pin ch.13 relocation 0 LIN_UART Serial Output pin ch.7 relocation 0 General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin PPG Output pin ch.14 relocation 0 LIN_UART Serial Clock I/O pin ch.7 relocation 0 +5.0v Power Supply pin GND pin General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin PPG Output pin ch.15 relocation 0 Up/down Counter AIN Input pin ch.0 relocation 0 General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter BIN Input pin ch.0 relocation 0 Sound Generator SGA Output pin ch.4 relocation 0 Output Compare Output pin ch.6 relocation 1 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Pin Name P044 SEG28 ST5 ZIN0_0 SGO4_0 OCU7_1 P045 SEG29 ST6 AIN1_0 SIN8_2 P046 SEG30 ST7 BIN1_0 SOT8_2 P047 SEG31 ST8 ZIN1_0 SCK8_2 P050 COM0 OCU8_1 P051 COM1 OCU9_1 P052 COM2 OCU10_1 P053 COM3 OCU11_1 P054 V0 FRCK0_1 P055 V1 FRCK1_1 P056 V2 FRCK2_1 P057 V3 FRCK3_1 DVCC DVSS P060 PWM1P0 AN8 P061 PWM1M0 AN9 SIN1_1 P062 I/O Circuit Type June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL I I I I I I I I I2 I2 I2 I3 K K K Function Description General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter ZIN Input pin ch.0 relocation 0 Sound Generator SGO Output pin ch.4 relocation 0 Output Compare Output pin ch.7 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter AIN Input pin ch.1 relocation 0 Multi-function Serial Input pin ch.8 relocation 2 General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter BIN Input pin ch.1 relocation 0 Multi-function Serial Output pin ch.8 relocation 2 General-Purpose I/O Port LCDC Segment(Duty)Output pin LCDC Segment(Static)Output pin Up/down Counter ZIN Input pin ch.1 relocation 0 Multi-function Serial Clock I/O pin ch.8 relocation 2 General-Purpose I/O Port LCDC Segment(Duty)Common Output pin Output Compare Output pin ch.8 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Common Output pin Output Compare Output pin ch.9 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Common Output pin Output Compare Output pin ch.10 relocation 1 General-Purpose I/O Port LCDC Segment(Duty)Common Output pin Output Compare Output pin ch.11 relocation 1 General-Purpose I/O Port LCDC Reference Voltage V0 Input pin Free-Run Timer Clock Input pin ch.0 relocation 1 General-Purpose I/O Port LCDC Reference Voltage V1 Input pin Free-Run Timer Clock Input pin ch.1 relocation 1 General-Purpose I/O Port LCDC Reference Voltage V2 Input pin Free-Run Timer Clock Input pin ch.2 relocation 1 General-Purpose I/O Port LCDC Reference Voltage V3 Input pin Free-Run Timer Clock Input pin ch.3 relocation 1 Power Supply pin for SMC high current GND pin for SMC high current General-Purpose I/O Port SMC Output pin ch.0 ADC Analog Input pin ch.8 General-Purpose I/O Port SMC Output pin ch.0 ADC Analog Input pin ch.9 Multi-function Serial Input pin ch.1 relocation 1 General-Purpose I/O Port 31 D a t a S h e e t Pin Number 77 78 79 80 81 82 83 84 85 86 87 88 89 32 CONFIDENTIAL Pin Name PWM2P0 AN10 SOT1_1 ZIN1_1 P063 PWM2M0 AN11 SCK1_1 BIN1_1 P064 PWM1P1 AN12 SIN0_1 AIN1_1 P065 PWM1M1 AN13 SOT0_1 ZIN0_1 P066 PWM2P1 AN14 SCK0_1 BIN0_1 P067 PWM2M1 AN15 SIN9_1 AIN0_1 DVCC DVSS P070 PWM1P2 AN16 SOT9_1 P071 PWM1M2 AN17 SCK9_1 P072 PWM2P2 AN18 SIN8_1 ICU11_1 P073 PWM2M2 AN19 SOT8_1 ICU10_1 P074 PWM1P3 AN20 SCK8_1 ICU9_1 PPG12_1 I/O Circuit Type K K K K K K - K K K K K Function Description SMC Output pin ch.0 ADC Analog Input pin ch.10 Multi-function Serial Output pin ch.1 relocation 1 Up/down Counter ZIN Input pin ch.1 relocation 1 General-Purpose I/O Port SMC Output pin ch.0 ADC Analog Input pin ch.11 Multi-function Serial Clock I/O pin ch.1 relocation 1 Up/down Counter BIN Input pin ch.1 relocation 1 General-Purpose I/O Port SMC Output pin ch.1 ADC Analog Input pin ch.12 Multi-function Serial Input pin ch.0 relocation 1 Up/down Counter AIN Input pin ch.1 relocation 1 General-Purpose I/O Port SMC Output pin ch.1 ADC Analog Input pin ch.13 Multi-function Serial Output pin ch.0 relocation 1 Up/down Counter ZIN Input pin ch.0 relocation 1 General-Purpose I/O Port SMC Output pin ch.1 ADC Analog Input pin ch.14 Multi-function Serial Clock I/O pin ch.0 relocation 1 Up/down Counter BIN Input pin ch.0 relocation 1 General-Purpose I/O Port SMC Output pin ch.1 ADC Analog Input pin ch.15 Multi-function Serial Input pin ch.9 relocation 1 Up/down Counter AIN Input pin ch.0 relocation 1 Power Supply pin for SMC high current GND pin for SMC high current General-Purpose I/O Port SMC Output pin ch.2 ADC Analog Input pin ch.16 Multi-function Serial Output pin ch.9 relocation 1 General-Purpose I/O Port SMC Output pin ch.2 ADC Analog Input pin ch.17 Multi-function Serial Clock I/O pin ch.9 relocation 1 General-Purpose I/O Port SMC Output pin ch.2 ADC Analog Input pin ch.18 Multi-function Serial Input pin ch.8 relocation 1 Input Capture Input pin ch.11 relocation 1 General-Purpose I/O Port SMC Output pin ch.2 ADC Analog Input pin ch.19 Multi-function Serial Output pin ch.8 relocation 1 Input Capture Input pin ch.10 relocation 1 General-Purpose I/O Port SMC Output pin ch.3 ADC Analog Input pin ch.20 Multi-function Serial Clock I/O pin ch.8 relocation 1 Input Capture Input pin ch.9 relocation 1 PPG Output pin ch.12 relocation 1 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 90 91 92 93 94 95 96 97 98 99 100 101 Pin Name P075 PWM1M3 AN21 SIN7_1 ICU8_1 PPG13_1 P076 PWM2P3 AN22 SOT7_1 ICU7_1 PPG14_1 P077 PWM2M3 AN23 SCK7_1 ICU6_1 PPG15_1 DVCC DVSS P080 PWM1P4 AN24 SIN6_0 PPG16_0 AIN0_2 P081 PWM1M4 AN25 SOT6_0 PPG17_0 BIN0_2 P082 PWM2P4 AN26 SCK6_0 PPG18_0 ZIN0_2 P083 PWM2M4 AN27 ICU0_2 PPG19_0 P084 PWM1P5 AN28 ICU1_2 PPG20_0 P085 PWM1M5 AN29 ICU2_2 PPG21_0 P086 PWM2P5 I/O Circuit Type June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL K K K - K K K K K K K Function Description General-Purpose I/O Port SMC Output pin ch.3 ADC Analog Input pin ch.21 LIN_UART Serial Input pin ch.7 relocation 1 Input Capture Input pin ch.8 relocation 1 PPG Output pin ch.13 relocation 1 General-Purpose I/O Port SMC Output pin ch.3 ADC Analog Input pin ch.22 LIN_UART Serial Output pin ch.7 relocation 1 Input Capture Input pin ch.7 relocation 1 PPG Output pin ch.14 relocation 1 General-Purpose I/O Port SMC Output pin ch.3 ADC Analog Input pin ch.23 LIN_UART Serial Clock I/O pin ch.7 relocation 1 Input Capture Input pin ch.6 relocation 1 PPG Output pin ch.15 relocation 1 Power Supply pin for SMC high current GND pin for SMC high current General-Purpose I/O Port SMC Output pin ch.4 ADC Analog Input pin ch.24 LIN_UART Serial Input pin ch.6 relocation 0 PPG Output pin ch.16 relocation 0 Up/down Counter AIN Input pin ch.0 relocation 2 General-Purpose I/O Port SMC Output pin ch.4 ADC Analog Input pin ch.25 LIN_UART Serial Output pin ch.6 relocation 0 PPG Output pin ch.17 relocation 0 Up/down Counter BIN Input pin ch.0 relocation 2 General-Purpose I/O Port SMC Output pin ch.4 ADC Analog Input pin ch.26 LIN_UART Serial Clock I/O pin ch.6 relocation 0 PPG Output pin ch.18 relocation 0 Up/down Counter ZIN Input pin ch.0 relocation 2 General-Purpose I/O Port SMC Output pin ch.4 ADC Analog Input pin ch.27 Input Capture Input pin ch.0 relocation 2 PPG Output pin ch.19 relocation 0 General-Purpose I/O Port SMC Output pin ch.5 ADC Analog Input pin ch.28 Input Capture Input pin ch.1 relocation 2 PPG Output pin ch.20 relocation 0 General-Purpose I/O Port SMC Output pin ch.5 ADC Analog Input pin ch.29 Input Capture Input pin ch.2 relocation 2 PPG Output pin ch.21 relocation 0 General-Purpose I/O Port SMC Output pin ch.5 33 D a t a S h e e t Pin Number 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 34 CONFIDENTIAL Pin Name AN30 ICU3_2 PPG22_0 P087 PWM2M5 AN31 ICU4_2 PPG23_0 DVCC DVSS Non connection P090 ADTG PPG0_2 P100 SIN4_1 AN0 TIN0_1 PPG8_0 Non connection P101 SOT4_1 AN1 TIN1_1 PPG9_0 Non connection P102 SCK4_1 AN2 TIN2_1 PPG10_0 ICU6_2 P103 SIN5_1 AN3 TIN3_1 PPG1_1 ICU7_2 Non connection P104 SOT5_1 AN4 TOT0_1 PPG2_1 ICU8_2 P105 SCK5_1 AN5 TOT1_1 PPG3_1 ICU9_2 Non connection P106 AN6 PPG4_1 I/O Circuit Type K K M J - J - J J - J J J Function Description ADC Analog Input pin ch.30 Input Capture Input pin ch.3 relocation 2 PPG Output pin ch.22 relocation 0 General-Purpose I/O Port SMC Output pin ch.5 ADC Analog Input pin ch.31 Input Capture Input pin ch.4 relocation 2 PPG Output pin ch.23 relocation 0 Power Supply pin for SMC high current GND pin for SMC high current Non connection General-Purpose I/O Port ADC External Trigger Input pin PPG Output pin ch.0 relocation 2 General-Purpose I/O Port LIN_UART Serial Input pin ch.4 relocation 1 ADC Analog Input pin ch.0 Reload Timer Event Input pin ch.0 relocation 1 PPG Output pin ch.8 relocation 0 Non connection General-Purpose I/O Port LIN_UART Serial Output pin ch.4 relocation 1 ADC Analog Input pin ch.1 Reload Timer Event Input pin ch.1 relocation 1 PPG Output pin ch.9 relocation 0 Non connection General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.4 relocation 1 ADC Analog Input pin ch.2 Reload Timer Event Input pin ch.2 relocation 1 PPG Output pin ch.10 relocation 0 Input Capture Input pin ch.6 relocation 2 General-Purpose I/O Port LIN_UART Serial Input pin ch.5 relocation 1 ADC Analog Input pin ch.3 Reload Timer Event Input pin ch.3 relocation 1 PPG Output pin ch.1 relocation 1 Input Capture Input pin ch.7 relocation 2 Non connection General-Purpose I/O Port LIN_UART Serial Output pin ch.5 relocation 1 ADC Analog Input pin ch.4 Reload Timer Output pin ch.0 relocation 0 PPG Output pin ch.2 relocation 1 Input Capture Input pin ch.8 relocation 2 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.5 relocation 1 ADC Analog Input pin ch.5 Reload Timer Output pin ch.1 relocation 1 PPG Output pin ch.3 relocation 1 Input Capture Input pin ch.9 relocation 2 Non connection General-Purpose I/O Port ADC Analog Input pin ch.6 PPG Output pin ch.4 relocation 1 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Pin Name ICU10_2 SGA4_1 P107 AN7 PPG5_1 DAO1 ICU11_2 SGO4_1 Non connection AVSS AVRL AVRH AVCC Non connection P123 OCU1_0 PPG8_2 DAO0 AN39 P122 OCU0_0 SCK5_0 TOT3_0 PPG7_2 AN38 P121 FRCK0_0 SOT5_0 INT7_0 TOT2_0 PPG6_2 AN37 P120 FRCK1_0 SIN5_0 INT6_0 TOT1_0 PPG5_2 AN36 P117 SCK4_0 TOT0_0 SGO3 FRCK2_0 AN35 TRG4 P116 SOT4_0 TIN3_0 SGA3 FRCK3_0 AN34 P115 SIN4_0 TIN2_0 I/O Circuit Type June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL J L - L J J J J J J Function Description Input Capture Input pin ch.10 relocation 2 Sound Generator SGA Output pin ch.4 relocation 1 General-Purpose I/O Port ADC Analog Input pin ch.7 PPG Output pin ch.5 relocation 1 DAC Output pin ch.1 Input Capture Input pin ch.11 relocation 2 Sound Generator SGO Output pin ch.4 relocation 1 Non connection ADC, DAC GND pin ADC Low Reference Voltage pin ADC High Reference Voltage pin ADC,DAC Analog Power Supply pin Non connection General-Purpose I/O Port Output Compare Output pin ch.1 relocation 0 PPG Output pin ch.8 relocation 2 DAC Output pin ch.0 ADC Analog Input pin ch.39 General-Purpose I/O Port Output Compare Output pin ch.0 relocation 0 LIN_UART Serial Clock I/O pin ch.5 relocation 0 Reload Timer Output pin ch.3 relocation 0 PPG Output pin ch.7 relocation 2 ADC Analog Input pin ch.38 General-Purpose I/O Port Free-Run Timer Clock Input pin ch.0 relocation 0 LIN_UART Serial Output pin ch.5 relocation 0 External Interrupt Request Input pin ch.7 relocation 0 Reload Timer Output pin ch.2 relocation 0 PPG Output pin ch.6 relocation 2 ADC Analog Input pin ch.37 General-Purpose I/O Port Free-Run Timer Clock Input pin ch.1 relocation 0 LIN_UART Serial Input pin ch.5 relocation 0 External Interrupt Request Input pin ch.6 relocation 0 Reload Timer Output pin ch.1 relocation 0 PPG Output pin ch.5 relocation 2 ADC Analog Input pin ch.36 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.4 relocation 0 Reload Timer Output pin ch.0 relocation 0 Sound Generator SGO Output pin ch.3 Free-Run Timer Clock Input pin ch.2 relocation 0 ADC Analog Input pin ch.35 PPG Trigger Input pin 4 (ch.16-ch.19) General-Purpose I/O Port LIN_UART Serial Output pin ch.4 relocation 0 Reload Timer Event Input pin ch.3 relocation 0 Sound Generator SGA Output pin ch.3 Free-Run Timer Clock Input pin ch.3 relocation 0 ADC Analog Input pin ch.34 General-Purpose I/O Port LIN_UART Serial Input pin ch.4 relocation 0 Reload Timer Event Input pin ch.2 relocation 0 35 D a t a S h e e t Pin Number 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 36 CONFIDENTIAL Pin Name SGO2 FRCK4_0 AN33 P114 SCK3_0 TIN1_0 ICU5_1 SGA2 AN32 TRG3 P000 SIN2_1 TIN0_2 PPG0_0 INT0_1 P001 SOT2_1 TIN1_2 PPG1_0 INT1_1 P002 SCK2_1 TIN2_2 PPG2_0 INT2_1 P003 SIN3_1 TIN3_2 PPG3_0 INT3_1 VCC5 VSS P137 (X0A) P136 (X1A) NMIX P004 SOT3_1 TOT0_2 PPG4_0 INT4_1 P005 SCK3_1 TOT1_2 PPG5_0 INT5_1 P006 TOT2_2 PPG6_0 INT6_1 P007 TOT3_2 PPG7_0 INT7_1 I/O Circuit Type J J M M M M M(Y) M(Y) R M M M M Function Description Sound Generator SGO Output pin ch.2 Free-Run Timer Clock Input pin ch.4 relocation 0 ADC Analog Input pin ch.33 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.3 relocation 0 Reload Timer Event Input pin ch.1 relocation 0 Input Capture Input pin ch.5 relocation 1 Sound Generator SGA Output pin ch.2 ADC Analog Input pin ch.32 PPG Trigger Input pin 3 (ch.12-ch.15) General-Purpose I/O Port LIN_UART Serial Input pin ch.2 relocation 1 Reload Timer Event Input pin ch.0 relocation 2 PPG Output pin ch.0 relocation 0 External Interrupt Request Input pin ch.0 relocation 1 General-Purpose I/O Port LIN_UART Serial Output pin ch.2 relocation 1 Reload Timer Event Input pin ch.1 relocation 2 PPG Output pin ch.1 relocation 0 External Interrupt Request Input pin ch.1 relocation 1 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.2 relocation 1 Reload Timer Event Input pin ch.2 relocation 2 PPG Output pin ch.2 relocation 0 External Interrupt Request Input pin ch.2 relocation 1 General-Purpose I/O Port LIN_UART Serial Input pin ch.3 relocation 1 Reload Timer Event Input pin ch.3 relocation 2 PPG Output pin ch.3 relocation 0 External Interrupt Request Input pin ch.3 relocation 1 +5.0v Power Supply pin GND pin General-Purpose I/O Port Sub Clock oscillation Input pin (only dual clock product) General-Purpose I/O Port Sub Clock oscillation Output pin (only dual clock product) NMI Pin General-Purpose I/O Port LIN_UART Serial Output pin ch.3 relocation 1 Reload Timer Output pin ch.0 relocation 2 PPG Output pin ch.4 relocation 0 External Interrupt Request Input pin ch.4 relocation 1 General-Purpose I/O Port LIN_UART Serial Clock I/O pin ch.3 relocation 1 Reload Timer Output pin ch.1 relocation 2 PPG Output pin ch.5 relocation 0 External Interrupt Request Input pin ch.5 relocation 1 General-Purpose I/O Port Reload Timer Output pin ch.2 relocation 2 PPG Output pin ch.6 relocation 0 External Interrupt Request Input pin ch.6 relocation 1 General-Purpose I/O Port Reload Timer Output pin ch.3 relocation 2 PPG Output pin ch.7 relocation 0 External Interrupt Request Input pin ch.7 relocation 1 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 Pin Name Non connection P097 WOT SOT3_0 INT8_0 TIN0_0 ICU4_1 PPG0_1 P094 SGO1 SIN3_0 INT15_0 ICU1_1 PPG9_1 P093 SGA1 SOT2_0 INT14_0 ICU3_1 PPG8_1 P092 SGO0 SCK2_0 INT13_0 TOT3_1 ICU0_1 PPG7_1 P091 SGA0 SIN2_0 INT12_0 TOT2_1 ICU2_1 PPG6_1 P110 TX1 PPG1_2 FRCK5_0 P111 RX1 INT10_0 PPG2_2 P112 TX2 PPG3_2 P113 RX2 INT11_0 PPG4_2 RSTX VCC5 VSS DEBUGIF I/O Circuit Type - June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL M M M M M M M M M R B Function Description Non connection General-Purpose I/O Port RTC Overflow Output pin LIN_UART Serial Output pin ch.3 relocation 0 External Interrupt Request Input pin ch.8 relocation 0 Reload Timer Event Input pin ch.0 relocation 0 Input Capture Input pin ch.4 relocation 1 PPG Output pin ch.0 relocation 1 General-Purpose I/O Port Sound Generator SGO Output pin ch.1 LIN_UART Serial Input pin ch.3 relocation 0 External Interrupt Request Input pin ch.15 relocation 0 Input Capture Input pin ch.1 relocation 1 PPG Output pin ch.9 relocation 1 General-Purpose I/O Port Sound Generator SGA Output pin ch.1 LIN_UART Serial Output pin ch.2 relocation 0 External Interrupt Request Input pin ch.14 relocation 0 Input Capture Input pin ch.3 relocation 1 PPG Output pin ch.8 relocation 1 General-Purpose I/O Port Sound Generator SGO Output pin ch.0 LIN_UART Serial Clock I/O pin ch.0 relocation 0 External Interrupt Request Input pin ch.13 relocation 0 Reload Timer Output pin ch.3 relocation 1 Input Capture Input pin ch.0 relocation 1 PPG Output pin ch.7 relocation 1 General-Purpose I/O Port Sound Generator SGA Output pin ch.0 LIN_UART Serial Input pin ch.2 relocation 0 External Interrupt Request Input pin ch.12 relocation 0 Reload Timer Output pin ch.2 relocation 1 Input Capture Input pin ch.2 relocation 1 PPG Output pin ch.6 relocation 1 General-Purpose I/O Port CAN TX Data Output pin ch.1 PPG Output pin ch.1 relocation 2 Free-Run Timer Clock Input pin ch.5 relocation 0 General-Purpose I/O Port CAN RX Data Input pin ch.1 External Interrupt Request Input pin ch.10 relocation 0 PPG Output pin ch.2 relocation 2 General-Purpose I/O Port CAN TX Data Output pin ch.2 PPG Output pin ch.3 relocation 2 General-Purpose I/O Port CAN RX Data Input pin ch.2 External Interrupt Request Input pin ch.11 relocation 0 PPG Output pin ch.4 relocation 2 Reset Pin +5.0v Power Supply pin GND pin DEBUG I/F pin 37 D a t a S h e e t Pin Number 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 38 CONFIDENTIAL Pin Name P095 TX0 PPG10_1 P096 RX0 INT9_0 P124 OCU2_0 ICU5_2 PPG9_2 Non connection Non connection Non connection Non connection MD0 MD1 MD2 X0 X1 VSS P125 OCU3_0 ICU0_0 PPG10_2 P126 TRG0 SIN0_0 INT1_0 OCU4_0 P127 SOT0_0 OCU5_0 P130 SCK0_0 INT0_0 ICU1_0 TIOA0 P131 TRG1 SIN1_0 INT4_0 ICU2_0 TIOA1 P132 SOT1_0 INT2_0 ICU3_0 TIOB0 P133 SCK1_0 INT3_0 ICU4_0 TIOB1 TRG5 PPG11_1 I/O Circuit Type M M M A A R2 X X - M M N N M N N Function Description General-Purpose I/O Port CAN TX Data Output pin ch.0 PPG Output pin ch.10 relocation 1 General-Purpose I/O Port CAN RX Data Input pin ch.0 External Interrupt Request Input pin ch.9 relocation 0 General-Purpose I/O Port Output Compare Output pin ch.2 relocation 0 Input Capture Input pin ch.5 relocation 2 PPG Output pin ch.9 relocation 2 Non connection Non connection Non connection Non connection Mode Pin 0 Mode Pin 1 Mode Pin 2 Main Clock oscillation Input pin Main Clock oscillation Output pin GND pin General-Purpose I/O Port Output Compare Output pin ch.3 relocation 0 Input Capture Input pin ch.0 relocation 0 PPG Output pin ch.10 relocation 2 General-Purpose I/O Port PPG Trigger Input pin 0 (ch.0-ch.3) Multi-function Serial Input pin ch.0 relocation 0 External Interrupt Request Input pin ch.1 relocation 0 Output Compare Output pin ch.4 relocation 0 General-Purpose I/O Port Multi-function Serial Output pin ch.0 relocation 0 Output Compare Output pin ch.5 relocation 0 General-Purpose I/O Port Multi-function Serial Clock I/O pin ch.0 relocation 0 External Interrupt Request Input pin ch.0 relocation 0 Input Capture Input pin ch.1 relocation 0 Base Timer I/O pin ch.0 General-Purpose I/O Port PPG Trigger Input pin 1 (ch.4-ch.7) Multi-function Serial Input pin ch.1 relocation 0 External Interrupt Request Input pin ch.4 relocation 0 Input Capture Input pin ch.2 relocation 0 Base Timer I/O pin ch.1 General-Purpose I/O Port Multi-function Serial Output pin ch.1 relocation 0 External Interrupt Request Input pin ch.2 relocation 0 Input Capture Input pin ch.3 relocation 0 Base Timer I/O pin ch.0 General-Purpose I/O Port Multi-function Serial Clock I/O pin ch.1 relocation 0 External Interrupt Request Input pin ch.3 relocation 0 Input Capture Input pin ch.4 relocation 0 Base Timer I/O pin ch.1 PPG Trigger Input pin 5 (ch.20-ch.23) PPG Output pin ch.11 relocation 1 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Pin Number 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 Pin Name P134 TRG2 INT5_0 ICU5_0 PPG1_3 VCC5 VSS C P140 D16_0 D24_1 P141 D17_0 D25_1 P142 D18_0 D26_1 P143 D19_0 D27_1 P144 D20_0 D28_1 P145 D21_0 D29_1 P146 D22_0 D30_1 P147 D23_0 D31_1 P150 D24_0 D16_1 P151 D25_0 D17_1 P152 D26_0 D18_1 P153 D27_0 D19_1 P154 D28_0 D20_1 P155 D29_0 D21_1 P156 D30_0 D22_1 I/O Circuit Type June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL M M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 Function Description General-Purpose I/O Port PPG Trigger Input pin 2 (ch.8-ch.11) External Interrupt Request Input pin ch.5 relocation 0 Input Capture Input pin ch.5 relocation 0 PPG Output pin ch.1 relocation 3 +5.0v Power Supply pin GND pin External Capacitance Connection Pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin 39 D a t a S h e e t Pin Number 198 199 200 201 202 203 204 205 206 207 208 40 CONFIDENTIAL Pin Name P157 D31_0 D23_1 P160 ASX P161 CS0X P162 CS1X P163 RDX P164 WR0X P165 WR1X P166 A00 P167 A01 P170 A02 VSS I/O Circuit Type M2 M2 M2 M2 M2 M2 M2 M2 M2 M2 - Function Description General-Purpose I/O Port External Bus Data I/O pin External Bus Data I/O pin General-Purpose I/O Port External Bus Address-Strobe Output pin General-Purpose I/O Port External Bus Chip-Select 0 Output pin General-Purpose I/O Port External Bus Chip-Select 1 Output pin General-Purpose I/O Port External Bus Read-Strobe Output pin General-Purpose I/O Port External Bus Write-Strobe 0 Output pin General-Purpose I/O Port External Bus Write-Strobe 1 Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin General-Purpose I/O Port External Bus Address Output pin GND pin MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t I/O CIRCUIT TYPE Type Circuit Remarks H General-purpose I/O port with COM/SEG output and with against 3V pad power supply (5V tolerant). TTL input I IOH = -1/-2mA(@VCCE=5V), IOH = -0.5/-1/-2mA(@VCCE=3.3V), IOL = 1/2mA(@VCCE=5V), IOL = 0.5/1/2mA(@VCCE=3.3V) Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input General-purpose I/O port with COM/SEG output. IOH = -1/-2mA, IOL = 1/2mA Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input TTL input I2 General-purpose I/O port with LCDC reference voltage input IOH = -1/-2mA, IOL = 1/2mA Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input TTL input LCDC ref. voltage input June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 41 D a t a S h e e t Type Circuit Remarks I3 General-purpose input port with LCDC V3 input Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input TTL input I4 General-purpose I/O port with COM/SEG output. TTL input J IOH = -1/-2mA(@VCCE=5V), IOH = -0.5/-1mA(@VCCE=3.3V), IOL = 1/2mA(@VCCE=5V), IOL = 0.5/1mA(@VCCE=3.3V) Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input General-purpose I/O port with analog input. IOH = -1/-2mA, IOL = 1/2mA Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input TTL input Analog input 42 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Type Circuit Remarks K General-purpose I/O port with analog input and with high current capable for SMC. IOH = -1/-2/-30mA, IOL = 1/2/30mA Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input TTL input Analog input L General-purpose I/O port with analog input and with DAC output IOH = -1/-2mA, IOL = 1/2mA Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input TTL input M General-purpose I/O port. IOH = -1/-2mA, IOL = 1/2mA Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input TTL input June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 43 D a t a S h e e t Type Circuit Remarks M2 General-purpose I/O port. TTL input IOH = -1/-2mA(@VCCE=5V), IOH = -0.5/-1mA(@VCCE=3.3V), IOL = 1/2mA(@VCCE=5V), IOL = 0.5/1mA(@VCCE=3.3V) Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input General-purpose I/O port with I2C output N IOH = -1/-2/-3mA, IOL = 1/2/3mA Pull-up resistor control Pull-down resistor control Automotive level input TTL level input CMOS level hysteresis input CMOS level input TTL input A Mode pin B DEBUG I/F pin Digital output TTL input R CMOS level hysteresis input Pull-up resistor 50 kΩ Hysteresis input 44 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Type Circuit Remarks R2 Hysteresis input CMOS level hysteresis input Pull-down resistor 50KΩ X Main oscillation I/O Standby control Y Sub oscillation I/O Standby control June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 45 D a t a S h e e t HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high-voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-2Eb 46 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 47 D a t a S h e e t Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 48 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 49 D a t a S h e e t HANDLING DEVICES This section explains the latch-up prevention and the treatment of a pin. For latch-up prevention If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings is applied between VCC pin and VSS pin, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply current increases excessively and device elements may be damaged by heat. Take care to prevent any voltage from exceeding the maximum ratings in device application. Also, the analog power supply voltage (AVcc, AVRH), analog input ,and the power supply voltage to high-current output buffer pins (DVcc), the power supply voltage of external bus interface (VccE) must not be exceed the digital power supply voltage (Vcc5) when the power supply voltage to the analog system and high-current output buffer pins the power supply voltage of external bus interface (VccE) is turned on or off. In the correct power-on sequence, turn on the digital power supply voltage (Vcc5), analog power supply voltage (AVcc, AVRH), the power supply voltage of external bus interface (VccE), and the power supply voltage of high-current output buffer pins (DVcc) simultaneously. Or, turn on the digital power supply voltage (Vcc5), and then turn on analog power supply voltage (AVcc, AVRH), the power supply voltage of external bus interface (VccE), and the power supply voltage of high-current output buffer pins (DVcc). Treatment of unused pins If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch-up. Connect a 2kΩ resistor to each of unused pins for pull-up or pull-down connection. Also, if I/O pins are not used, they must be set to the output state for opening or they must be set to the input state and treated in the same way as for the input pins. 50 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Power supply pins The device is designed to ensure that if the device contains multiple VCC pin or VSS pin, the pins that should be at the same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these pins to an external power source or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. As shown in figure 1, all Vss power supply pins must be treated in the similar way. If multiple Vcc or Vss systems are connected, the device cannot operate correctly even within the guaranteed operating range. Figure -1 Power Supply Input Pins VCC VSS VCC VSS VSS VCC VCC VSS VSS VCC The power supply pins should be connected to VCC pin and VSS pin of this device at the low impedance from the power supply source. In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is recommended to use as a bypass capacitor between the VCC pin and the VSS pin. Crystal oscillation circuit An external noise to the X0 pin or X1 pin may cause a device malfunction. The printed circuit board must be designed to lay out the X0 pin and the X1 pin, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close position to the device. The printed circuit board artwork is recommended to surround the X0 pin and X1 pin by ground circuits. Mode pins (MD2, MD1, MD0) Connect the MD2, MD1and MD0 mode pin to the VCC pin or VSS pin directly. To prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode pin and VCC pin or VSS pin on the printed circuit board. Also, use the low-impedance pin connection. During power-on To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to have 50μs or longer (between 0.2V to 2.7V) during power-on. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 51 D a t a S h e e t Notes during PLL clock operation When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate at the free running frequency of the self-oscillator circuit built in the PLL clock. This operation is not guaranteed. Treatment of A/D converter power supply pins Connect the pins to have AVcc=AVRH=Vcc5 and AVss/AVRL=Vss even if the A/D converter is not used. Notes on using external clock An external clock is not supported. None of the external direct clock input can be used for both main clock and sub clock. Power-on sequence of A/D converter analog inputs Be sure to turn on the digital power supply voltage (Vcc) first, and then turn on the A/D converter power supply voltage (AVcc, AVRH, AVRL) and analog input voltage (AN0 to AN39). Also, turn off the A/D converter power supplies and analog inputs first, and then turn off the digital power supply voltage (Vcc5). When the AVRH pin voltage is turned on or off, it must not exceed AVcc. Even if a common analog input pin is used as an input port, its input voltage must not exceed AVcc. (However, the analog power supply voltage and digital power supply voltage can be turned on or off simultaneously.) Treatment of power supplies for high current output buffer pins (DVcc, DVss) Be sure to turn on the digital power supply voltage (Vcc) first, and then turn on the power supply voltage for high current output buffer pins (DVcc, DVss). Also, turn off the power supplies for high current output buffer pins first, and then turn off the digital power supply voltage (Vcc). Even if the high current output buffer pins are used as general-purpose ports, the power supply voltage of high current output buffer pins (DVcc, DVss) must be powered. (The power supplies of high current output buffer pins and the digital power supplies can be turned on or off simultaneously. Treatment of C pin This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to assure the internal stabilization of the device. For the standard values, see the "Recommended Operating Conditions" of the latest data sheet. Function Switching of a Multiplexed Port To switch between the port function and the multiplexed pin function, use the PFR (port function register). However, if a pin is also used for an external bus, its function is switched by the external bus setting. For details, see "I/O PORTS". 52 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Low-power Consumption Mode To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off), follow the procedure explained in the "Activating the sleep mode, watch mode, or stop mode" or the "Activating the watch mode (power-off) or stop mode(power-off)" of "POWER CONSUMPTION CONTROL" in Hardware Manual. Take the following notes when using a monitor debugger. Do not set a break point for the low-power consumption transition program. Do not execute an operation step for the low-power consumption transition program. Precautions when writing to registers including the status flag When writing a function control data in the register that has a status flag (especially, an interrupt request flag), taking care not to clear its status flag erroneously must be followed. The program must be written not to clear the flag to the status bit, and then to set the control bits to have the desired value. Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a single bit only.) By the Byte, Half-word, or Word access, writing data in the control bits and status flag simultaneously is done. During this time, take care not to clear other bits (in this case, the bits of status flag) erroneously. Note: These points can be ignored because the bit instructions to a register which supports RMW are already taken the points into consideration. Care must be taken when the bit instruction is used to a register which does not support RMW. No-connected-pin The product of LQFP-208 has some no-connected-pin which is not connected to any function on die. Pins are recommended to be pulled-up or pulled-down on the extern circuit. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 53 D a t a S h e e t BLOCK DIAGRAM FR81s CPU Core Regulator MPU Power On Reset Instruction Debug Interface D ata XBS Crossbar Switch Wild Register Flash ・MainFlash ・WorkFlash 64KB From Master To Slave On-Chip Bus Layer 2 From Master To Slave On-Chip Bus Layer 1 Ext-Bus I/F SPI_CS0-3, SPI_CLK, SPI_SIO0-3 On-Chip Bus RAM XBS CR OSC RAM ECC Control (XBS-RAM) Bus matster HS_SPI (1ch) DMAC CAN (3ch) Register Clock / Bus Bridge Peripheral Bridge RAM ECC Control RX0-2, TX0-2 Backup -RAM 16 32 Clock Bridge (PCLK1⇔PCLK2) Bus Performance Counter Mode Registers A SX,CS0X,CS1X , RDX,W R0X,WR1X, RDY ,SY SCLK 32- bit Peripheral B us MD 0,MD1,MD2,P 127 Ext-Bus Pins D16-31,A 00-21, CAN Prescaler RTC/WDT1 Calibration I/O Port Setting Registers SO T2-7,SIN2-7, SCK2-7 SOT 0/1/8/9,SIN 0/1/8/9, Clock Bridge (PCLK1⇔PCLK2) CRC Sound Generator (5ch) Lin-UART (6ch) SGO0-4,SGA 0-4 M ultifunction Serial Interface (4ch) Output Compare (12ch) Base Timer (2ch) TIOA 0-1,TIOB0-1 A IN0-1,BIN0-1,ZIN0-1 Up Down Counter (2ch) 16-bit Peripheral B us OCU0-11 Bus Bridge ( 32-bit ⇔ 16-bit) External Interrupt Request (16ch) RTC WOT Clock Supervisor V0-3, ST0-8, COM0-3, SEG0-31 LCD Controller TRG0-5,PPG0-23 A DTG,A N0-39 INT0-15, Hi-Z Controls f or Standby Mode Port I/O Input Capture (12ch) I/O Free Run Timer (6ch) ICU0-11 16- bit Peripheral B us Port SC K0/1/8/9 FRCK0-5 PPG(24ch) NMIX NMI AD Converter A DC enabled (A DER) DA O0-1 DA Converter Low Voltage Detection (External Power Supply) Low Voltage Detection (Internal Power Supply) PWM1M0-5, PWM1P0-5, PWM2M0-5, PWM2P0-5 TIN0-3,TOT0-3 Stepping Motor Controller (6ch) Clock Controls (Configuration Registers, Main Timer, Sub Timer, PLL Timer) Reload Timer (4ch : ch.0,1,2,3) Reload Timer (3ch : ch.4,5,6) Clock Controls (Divide Settings) Reset Controls Low Power Control Registers RS TX WatchdogTimer (SW and HW) DMA Request and Clear MUX Delayed Interrupt Interrupt Controller Interrupt Requests Batch Reading Note: In this series, the HS-SPI function is prohibited 54 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t MEMORY MAP Memory map MB91F575 0000 0000H I/O Area 0000 4000H BackUp RAM (8KB) 0000 6000H 0001 0000H I/O Area RAM (40KB) 0001 A000H Reserved 0007 0000H Flash memory (512+64)KB 0010 0000H Reserved 0033 0000H WorkFlash (64KB) 0034 0000H Reserved 1000 0000H HS_SPI MEM Area 2000 0000H HS_SPI CSR area HSSSWAP register 2000 0404H Reserved 8000 0000H External bus Area FFFF FFFFH June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 55 D a t a S h e e t Memory map MB91F577 0000 0000H I/O Area 0000 4000H 0000 6000H Backup RAM (8KB) I/O Area 0001 0000H RAM (64KB) 0002 0000H Reserved 0007 0000H Flash Memory (1024+64) KB 0018 0000H Reserved 0033 0000H 0034 0000H WorkFlash (64KB) Reserved 1000 0000H HS_SPI MEM Area 2000 0000H HS_SPI CSR Area, HSSSWAP register 2000 0404H Reserved 8000 0000H External bus area FFFF FFFFH 56 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Memory map MB91F578 0000 0000H 0000 4000H 0000 8000H I/O Area Backup RAM (16KB) I/O Area 0001 0000H RAM (96KB) 0002 8000H Reserved 0007 0000H Flash Memory (1536+64) KB 0020 0000H Reserved 0033 0000H 0034 0000H WorkFlash (64KB) Reserved 1000 0000H HS_SPI MEM Area 2000 0000H HS_SPI CSR Area, HSSSWAP register 2000 0404H Reserved 8000 0000H External bus area FFFF FFFFH June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 57 D a t a S h e e t Memory map MB91F579 0000 0000H 0000 4000H 0000 8000H I/O Area Backup RAM (16KB) I/O Area 0001 0000H RAM (128KB) 0003 0000H Reserved 0007 0000H Flash Memory (2048+64) KB 0028 0000H Reserved 0033 0000H 0034 0000H WorkFlash (64KB) Reserved 1000 0000H HS_SPI MEM Area 2000 0000H HS_SPI CSR Area, HSSSWAP register 2000 0404H Reserved 8000 0000H External bus area FFFF FFFFH 58 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t I/O MAP The following I/O map shows the relationship between memory space and registers for peripheral resources. Legend of I/O Map Read/Write attribute (R: Read W: Write) Address 000090 H Address offset value/ register name +0 +1 00009CH 0000A0 H +3 BT1PCSR/BT1PRLL[R /W] H 0000000000000000 Block BT1TMCR[R/W]B,H,W 00000000 00000000 BT1STC[R/W] B 00000000 000094 H 000098 H +2 BT1TMR[R] H 0000000000000000 BT1PDU T/BT1PRLH/BT1D TBF[R/W] H 0000000000000000 BTSEL[R /W] B ----000 0 Base timer 1 BTSS SR[W] B,H -------- ------11 ADERH [R/W]B, H, W 00000000 00000000 ADER L [R/W]B, H, W 00000000 00000000 0000A4 H ADC S1 [R/W] B, H,W 00000000 ADCS0 [R/W] B, H,W 00000000 ADCR1 [R] B, H,W ------XX ADCR 0 [R] B, H,W XXXXX XXX 0000A8 H ADCT1 [R/W] B, H,W 00010000 ADC T0 [R/W] B, H,W 00101100 ADSCH [R/W] B, H,W ---00000 ADECH [R/W] B, H,W ---00000 A/D converter Data access attribute B: Byte H: Half-word W: Word (Note) The access by the data access attribute not described is disabled. Initial register value after reset The initial register value after reset indicates as follows: "1": Initial value "1" "0": Initial value "0" "X": Initial value undefined "-": Reserved bit/Undefined bit "*": Initial value "0" or "1" according to the setting Note: It is prohibited to access addresses not described here. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 59 D a t a S h e e t Table: I/O Map Address +0 Address offset value / Register name +1 +2 +3 Block 000000H PDR00[R/W] B,H,W XXXXXXXX PDR01[R/W] B,H,W XXXXXXXX PDR02[R/W] B,H,W XXXXXXXX PDR03[R/W] B,H,W XXXXXXXX 000004H PDR04[R/W] B,H,W XXXXXXXX PDR05[R/W] B,H,W XXXXXXXX PDR06[R/W] B,H,W XXXXXXXX PDR07[R/W] B,H,W XXXXXXXX 000008H PDR08[R/W] B,H,W XXXXXXXX PDR09[R/W] B,H,W XXXXXXXX PDR10[R/W] B,H,W XXXXXXXX PDR11[R/W] B,H,W XXXXXXXX PDR12[R/W] B,H,W XXXXXXXX PDR16[R/W] B,H,W XXXXXXXX*4 PDR13[R/W] B,H,W XX-XXXXX PDR17[R/W] B,H,W XXXXXXXX*4 PDR14[R/W] B,H,W XXXXXXXX*4 PDR18[R/W] B,H,W XXXXXXXX*4 PDR15[R/W] B,H,W XXXXXXXX*4 PDR19[R/W] B,H,W XXXXXXXX*4 000014H to 000038H ― ― ― ― Reserved 00003CH WDTCR0[R/W] B,H,W -0--0000 WDTCPR0[W] B,H,W 00000000 WDTCR1[R] B,H,W ----0110 WDTCPR1[W] B,H,W 00000000 Watchdog timer [S] 000040H ― ― ― ― Reserved 000044H DICR [R/W] B -------0 ― ― ― Delayed interrupt 00000CH 000010H 000048H TMRLRA4 [R/W] H XXXXXXXX XXXXXXXX TMR4 [R] H XXXXXXXX XXXXXXXX 00004CH TMRLRB4 [R/W] H XXXXXXXX XXXXXXXX TMCSR4 [R/W] B, H,W 00000000 0-000000 000050H TMRLRA5 [R/W] H XXXXXXXX XXXXXXXX TMR5 [R] H XXXXXXXX XXXXXXXX 000054H TMRLRB5 [R/W] H XXXXXXXX XXXXXXXX TMCSR5 [R/W] B, H,W 00000000 0-000000 000058H TMRLRA6 [R/W] H XXXXXXXX XXXXXXXX TMR6 [R] H XXXXXXXX XXXXXXXX 00005CH TMRLRB6 [R/W] H XXXXXXXX XXXXXXXX TMCSR6 [R/W] B, H,W 00000000 0-000000 000060H TMRLRA0 [R/W] H XXXXXXXX XXXXXXXX TMR0 [R] H XXXXXXXX XXXXXXXX 000064H TMRLRB0 [R/W] H XXXXXXXX XXXXXXXX TMCSR0 [R/W] B, H,W 00000000 0-000000 000068H to 00007CH 60 CONFIDENTIAL ― ― ― ― Port data register *4:MB91F578/9 only Reload timer 4 Reload timer 5 Reload timer 6 Reload timer 0 Reserved MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address 000080H 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H +0 Address offset value / Register name +1 +2 BT0TMR[R] H 00000000 00000000 ― BT0STC[R/W] B 0000-000 BT0PCSR/BT0PRLL[R/W] H XXXXXXXX XXXXXXXX ― ― BT1TMR[R] H 00000000 00000000 ― BT1STC[R/W] B 0000-000 BT1PCSR/BT1PRLL[R/W] H 00000000 00000000 BTSEL01[R/W] B ----0000 Base timer 0 ― ― BT0PDUT/BT0PRLH/BT0DTBF[R/ W] H XXXXXXXX XXXXXXXX ― ― ― ― BTSSSR[W] B,H -------- ------11 ADCR1 [R] B, H,W ------XX ADCR0 [R] B, H,W XXXXXXXX 0000A8H ADCT1 [R/W] B, H,W 00010000 ADCT0 [R/W] B, H,W 00101100 ADSCH [R/W] B, H,W --000000 ADECH [R/W] B, H,W --000000 0000AC H ― EADERLL [R/W] B, H,W 00000000 EADCS [R] B, H,W --000000 ― 0000B0H SCR0/(IBCR0) [R/W] B,H,W 0--00000 SMR0 [R/W] B,H,W 000-0000 SSR0 [R/W] B,H,W 0-000011 ESCR0/(IBSR0) [R/W] B,H,W -0000000 BGR0 [R/W] H,W 00000000 00000000 0000B8H ― / (ISMK0) [R/W] B,H,W -------- *2 ― / (ISBA0) [R/W] B,H,W -------- *2 ― ― 0000BCH FCR10 [R/W] B,H,W ---00100 FCR00 [R/W] B,H,W -0000000 FBYTE20 [R/W] B,H,W 00000000 FBYTE10 [R/W] B,H,W 00000000 CONFIDENTIAL Base timer 1 Base timer 0,1 ADERL [R/W]B, H, W 00000000 00000000 ADCS0 [R/W] B, H,W 000----- June 19, 2015, MB91F577_DS705-00009-3v0-E Reserved BT1PDUT/BT1PRLH/BT1DTBF[R/ W] H 00000000 00000000 ADCS1 [R/W] B, H,W 0000000- RDR0/(TDR0)[R/W] B,H,W *1 -------0 00000000 Base timer 0 BT1TMCR[R/W]H -0000000 00000000 0000A4H 0000B4H Block BT0TMCR[R/W]H -0000000 00000000 ― ADERH [R/W]B, H, W 00000000 00000000 +3 A/D converter Multi-UART0 *1: Byte access is permitted only for access to lower 8 bits *2: Reserved because I2C mode is not set immediately after reset. 61 D a t a S h e e t Address 0000C0H 0000C4H +0 Address offset value / Register name +1 +2 SCR1/(IBCR1) [R/W] B,H,W 0--00000 SMR1 [R/W] B,H,W 000-0000 RDR1/(TDR1)[R/W] B,H,W *1 -------0 00000000 SSR1 [R/W] B,H,W 0-000011 +3 ESCR1/(IBSR1) [R/W] B,H,W -0000000 BGR1 [R/W] H,W 00000000 00000000 0000C8H ― / (ISMK1) [R/W] B,H,W -------- *2 ― / (ISBA1) [R/W] B,H,W -------- *2 ― ― 0000CCH FCR11 [R/W] B,H,W ---00100 FCR01 [R/W] B,H,W -0000000 FBYTE21 [R/W] B,H,W 00000000 FBYTE11 [R/W] B,H,W 00000000 0000D0H SCR2 [R/W] B, H, W 00000000 SMR2 [R/W] B, H, W 00000000 SSR2 [R/W] B, H, W 00001000 RDR2 /TDR2 [R/W] B, H, W 00000000 0000D4H ESCR2 [R/W] B, H, W 00000X00 ECCR2 [R/W] B, H, W -0000-XX 0000D8H SCR3 [R/W] B, H, W 00000000 SMR3 [R/W] B, H, W 00000000 0000DCH ESCR3 [R/W] B, H, W 00000X00 ECCR3 [R/W] B, H, W -0000-XX 0000E0H SCR4 [R/W] B, H, W 00000000 SMR4 [R/W] B, H, W 00000000 0000E4H ESCR4 [R/W] B, H, W 00000X00 ECCR4 [R/W] B, H, W -0000-XX 0000E8H SCR5 [R/W] B, H, W 00000000 SMR5 [R/W] B, H, W 00000000 0000ECH ESCR5 [R/W] B, H, W 00000X00 ECCR5 [R/W] B, H, W -0000-XX 0000F0H SCR6 [R/W] B, H, W 00000000 SMR6 [R/W] B, H, W 00000000 0000F4H ESCR6 [R/W] B, H, W 00000X00 ECCR6 [R/W] B, H, W -0000-XX 0000F8H SCR7 [R/W] B, H, W 00000000 SMR7 [R/W] B, H, W 00000000 0000FCH ESCR7 [R/W] B, H, W 00000X00 ECCR7 [R/W] B, H, W -0000-XX 62 CONFIDENTIAL Block Multi-UART1 *1: Byte access is permitted only for access to lower 8 bits *2: Reserved because I2C mode is not set immediately after reset. LIN-UART2 BGR2 [R/W] B, H, W -0000000 00000000 SSR3 [R/W] B, H, W 00001000 RDR3 /TDR3 [R/W] B, H, W 00000000 LIN-UART3 BGR3 [R/W] B, H, W -0000000 00000000 SSR4 [R/W] B, H, W 00001000 RDR4 /TDR4 [R/W] B, H, W 00000000 LIN-UART4 BGR4 [R/W] B, H, W -0000000 00000000 SSR5 [R/W] B, H, W 00001000 RDR5 /TDR5 [R/W] B, H, W 00000000 LIN-UART5 BGR5 [R/W] B, H, W -0000000 00000000 SSR6 [R/W] B, H, W 00001000 RDR6 /TDR6 [R/W] B, H, W 00000000 LIN-UART6 BGR6 [R/W] B, H, W -0000000 00000000 SSR7 [R/W] B, H, W 00001000 RDR7 /TDR7 [R/W] B, H, W 00000000 LIN-UART7 BGR7 [R/W] B, H, W -0000000 00000000 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 000100H TMRLRA1 [R/W] H XXXXXXXX XXXXXXXX TMR1 [R] H XXXXXXXX XXXXXXXX 000104H TMRLRB1 [R/W] H XXXXXXXX XXXXXXXX TMCSR1 [R/W] B, H,W 00000000 0-000000 000108H TMRLRA2 [R/W] H XXXXXXXX XXXXXXXX TMR2 [R] H XXXXXXXX XXXXXXXX 00010CH TMRLRB2 [R/W] H XXXXXXXX XXXXXXXX TMCSR2 [R/W] B, H,W 00000000 0-000000 000110H TMRLRA3 [R/W] H XXXXXXXX XXXXXXXX TMR3 [R] H XXXXXXXX XXXXXXXX 000114H TMRLRB3 [R/W] H XXXXXXXX XXXXXXXX TMCSR3 [R/W] B, H,W 00000000 0-000000 000118H to 00011CH ― ― ― 000120H OCCP6 [R/W] W 00000000 00000000 00000000 00000000 000124H OCCP7 [R/W] W 00000000 00000000 00000000 00000000 000128H OCFS67 [R/W] B, H, W ------11 ― OCSH67[R/W] B, H, W ---0--00 00012CH OCCP8 [R/W] W 00000000 00000000 00000000 00000000 000130H OCCP9 [R/W] W 00000000 00000000 00000000 00000000 000134H OCFS89 [R/W] B, H, W ------11 ― OCSH89[R/W] B, H, W ---0--00 000138H OCCP10 [R/W] W 00000000 00000000 00000000 00000000 00013CH OCCP11 [R/W] W 00000000 00000000 00000000 00000000 000140H OCFS1011 [R/W] B, H, W ------11 OCSH1011[R/W] ― B, H, W ---0--00 ― Block Reload timer 1 Reload timer 2 Reload timer 3 Reserved Output compare 6,7 OCSL67[R/W] B, H, W 0000--00 Output compare 8,9 OCSL89[R/W] B, H, W 0000--00 Output compare 10,11 OCSL1011[R/W] B, H, W 0000--00 000144H GCN13 [R/W] H 00110010 00010000 ― GCN23 [R/W] B ----0000 PPG12, 13, 14, 15 control 000148H GCN14 [R/W] H 00110010 00010000 ― GCN24 [R/W] B ----0000 PPG16, 17, 18, 19 control 00014CH GCN15 [R/W] H 00110010 00010000 ― GCN25 [R/W] B ----0000 PPG20, 21, 22, 23 control June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 63 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 000150H PTMR11 [R] H,W 11111111 11111111 PCSR11 [W] H,W XXXXXXXX XXXXXXXX 000154H PDUT11 [W] H,W XXXXXXXX XXXXXXXX PCN11 [R/W] B,H,W 0000000- 000000-0 000158H PTMR12 [R] H,W 11111111 11111111 PCSR12 [W] H,W XXXXXXXX XXXXXXXX PDUT12 [W] H,W XXXXXXXX XXXXXXXX PTMR13 [R] H,W 11111111 11111111 PDUT13 [W] H,W XXXXXXXX XXXXXXXX PTMR14 [R] H,W 11111111 11111111 PDUT14 [W] H,W XXXXXXXX XXXXXXXX PTMR15 [R] H,W 11111111 11111111 PDUT15 [W] H,W XXXXXXXX XXXXXXXX PTMR16 [R] H,W 11111111 11111111 PDUT16 [W] H,W XXXXXXXX XXXXXXXX PTMR17 [R] H,W 11111111 11111111 PDUT17 [W] H,W XXXXXXXX XXXXXXXX PTMR18 [R] H,W 11111111 11111111 PDUT18 [W] H,W XXXXXXXX XXXXXXXX PTMR19 [R] H,W 11111111 11111111 PDUT19 [W] H,W XXXXXXXX XXXXXXXX PTMR20 [R] H,W 11111111 11111111 PDUT20 [W] H,W XXXXXXXX XXXXXXXX PTMR21 [R] H,W 11111111 11111111 PDUT21 [W] H,W XXXXXXXX XXXXXXXX PTMR22 [R] H,W 11111111 11111111 PCN12 [R/W] B,H,W 0000000- 000000-0 PCSR13 [W] H,W XXXXXXXX XXXXXXXX PCN13 [R/W] B,H,W 0000000- 000000-0 PCSR14 [W] H,W XXXXXXXX XXXXXXXX PCN14 [R/W] B,H,W 0000000- 000000-0 PCSR15 [W] H,W XXXXXXXX XXXXXXXX PCN15 [R/W] B,H,W 0000000- 000000-0 PCSR16 [W] H,W XXXXXXXX XXXXXXXX PCN16 [R/W] B,H,W 0000000- 000000-0 PCSR17 [W] H,W XXXXXXXX XXXXXXXX PCN17 [R/W] B,H,W 0000000- 000000-0 PCSR18 [W] H,W XXXXXXXX XXXXXXXX PCN18 [R/W] B,H,W 0000000- 000000-0 PCSR19 [W] H,W XXXXXXXX XXXXXXXX PCN19 [R/W] B,H,W 0000000- 000000-0 PCSR20 [W] H,W XXXXXXXX XXXXXXXX PCN20 [R/W] B,H,W 0000000- 000000-0 PCSR21 [W] H,W XXXXXXXX XXXXXXXX PCN21 [R/W] B,H,W 0000000- 000000-0 PCSR22 [W] H,W XXXXXXXX XXXXXXXX PDUT22 [W] H,W XXXXXXXX XXXXXXXX PCN22 [R/W] B,H,W 0000000- 000000-0 Block PPG11 00015CH 000160H 000164H 000168H 00016CH 000170H 000174H 000178H 00017CH 000180H 000184H 000188H 00018CH 000190H 000194H 000198H 00019CH 0001A0H 0001A4H 0001A8H 0001ACH 64 CONFIDENTIAL PPG12 PPG13 PPG14 PPG15 PPG16 PPG17 PPG18 PPG19 PPG20 PPG21 PPG22 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 0001B0H PTMR23 [R] H,W 11111111 11111111 PCSR23 [W] H,W XXXXXXXX XXXXXXXX 0001B4H PDUT23 [W] H,W XXXXXXXX XXXXXXXX PCN23 [R/W] B,H,W 0000000- 000000-0 0001B8H to 0001FCH ― 000200H PWC20 [R/W] H,W ------XX XXXXXXXX ― PWC0 [R/W] B -00000-- 000204H ― 000208H PWC21 [R/W] H,W ------XX XXXXXXXX PWC1 [R/W] B -00000-- 00020CH ― 000210H PWC22 [R/W] H,W ------XX XXXXXXXX PWC2 [R/W] B -00000-- 000214H ― 000218H PWC23 [R/W] H,W ------XX XXXXXXXX PWC3 [R/W] B -00000-- 00021CH ― 000220H PWC24 [R/W] H,W ------XX XXXXXXXX PWC4 [R/W] B -00000-- 000224H ― 000228H PWC25 [R/W] H,W ------XX XXXXXXXX ― ― PWC10 [R/W] H,W ------XX XXXXXXXX PWS20 [R/W] PWS10 [R/W] B,H,W B,H,W -0000000 --000000 PWC11 [R/W] H,W ------XX XXXXXXXX PWS21 [R/W] B,H,W -0000000 PWS11 [R/W] B,H,W --000000 PWC12 [R/W] H,W ------XX XXXXXXXX PWS22 [R/W] PWS12 [R/W] B,H,W B,H,W -0000000 --000000 PWC13 [R/W] H,W ------XX XXXXXXXX PWS23 [R/W] B,H,W -0000000 PWS13 [R/W] B,H,W --000000 PWC14 [R/W] H,W ------XX XXXXXXXX PWS24 [R/W] B,H,W -0000000 PWS14 [R/W] B,H,W --000000 PWC15 [R/W] H,W ------XX XXXXXXXX PPG23 Reserved Stepping motor controller 0 Stepping motor controller 1 Stepping motor controller 2 Stepping motor controller3 Stepping motor controller 4 Stepping motor controller 5 00022CH ― PWC5 [R/W] B -00000-- PWS25 [R/W] B,H,W -0000000 000230H to 000238H ― ― ― ― Reserved 00023CH DACR0 [R/W] B,H,W -------0 DADR0 [R/W] B,H,W XXXXXXXX DACR1 [R/W] B,H,W -------0 DADR1 [R/W] B,H,W XXXXXXXX DA converter June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL PWS15 [R/W] B,H,W --000000 Block 65 D a t a S h e e t Address +0 000240H 000244H 000248H TCCSH0 [R/W]B,H,W 0-----00 00024CH 000250H 000254H TCCSH1 [R/W]B,H,W 0-----00 000258H ― Address offset value / Register name +1 +2 +3 CPCLR0 [R/W] W 11111111 11111111 11111111 11111111 TCDT0 [R/W] W 00000000 00000000 00000000 00000000 TCCSL0 [R/W]B,H,W ― -1-00000 CPCLR1 [R/W] W 11111111 11111111 11111111 11111111 TCDT1 [R/W] W 00000000 00000000 00000000 00000000 TCCSL1 [R/W]B,H,W ― -1-00000 ― Block Free-run timer 0 Free-run timer 1 ― ― Reserved 00025CH GCN10 [R/W] H 00110010 00010000 ― GCN20 [R/W] B ----0000 PPG0, 1, 2, 3 control 000260H GCN11 [R/W] H 00110010 00010000 ― GCN21 [R/W] B ----0000 PPG4, 5, 6, 7 control 000264H GCN12 [R/W] H 00110010 00010000 ― GCN22 [R/W] B ----0000 PPG8, 9, 10, 11 control ― PPGDIV [R/W] B ------00 000268H ― ― 00026CH PTMR0 [R] H,W 11111111 11111111 PCSR0 [W] H,W XXXXXXXX XXXXXXXX 000270H PDUT0 [W] H,W XXXXXXXX XXXXXXXX PCN0 [R/W] B, H,W 0000000- 000000-0 000274H PTMR1 [R] H,W 11111111 11111111 PCSR1 [W] H,W XXXXXXXX XXXXXXXX 000278H PDUT1 [W] H,W XXXXXXXX XXXXXXXX PCN1 [R/W] B,H,W 0000000- 000000-0 00027CH PTMR2 [R] H,W 11111111 11111111 PCSR2 [W] H,W XXXXXXXX XXXXXXXX 000280H PDUT2 [W] H,W XXXXXXXX XXXXXXXX PCN2 [R/W] B,H,W 0000000- 000000-0 000284H PTMR3 [R] H,W 11111111 11111111 PCSR3 [W] H,W XXXXXXXX XXXXXXXX 000288H PDUT3 [W] H,W XXXXXXXX XXXXXXXX PCN3 [R/W] B,H,W 0000000- 000000-0 00028CH PTMR4 [R] H,W 11111111 11111111 PCSR4 [W] H,W XXXXXXXX XXXXXXXX 000290H PDUT4 [W] H,W XXXXXXXX XXXXXXXX PCN4 [R/W] B,H,W 0000000- 000000-0 PPG0 PPG1 PPG2 PPG3 PPG4 66 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 000294H PTMR5 [R] H,W 11111111 11111111 PCSR5 [W] H,W XXXXXXXX XXXXXXXX 000298H PDUT5 [W] H,W XXXXXXXX XXXXXXXX PCN5 [R/W] B,H,W 0000000- 000000-0 00029CH PTMR6 [R] H,W 11111111 11111111 PCSR6 [W] H,W XXXXXXXX XXXXXXXX 0002A0H PDUT6 [W] H,W XXXXXXXX XXXXXXXX PCN6 [R/W] B,H,W 0000000- 000000-0 0002A4H PTMR7 [R] H,W 11111111 11111111 PCSR7 [W] H,W XXXXXXXX XXXXXXXX 0002A8H PDUT7 [W] H,W XXXXXXXX XXXXXXXX PCN7 [R/W] B,H,W 0000000- 000000-0 0002ACH PTMR8 [R] H,W 11111111 11111111 PCSR8 [W] H,W XXXXXXXX XXXXXXXX 0002B0H PDUT8 [W] H,W XXXXXXXX XXXXXXXX PCN8 [R/W] B,H,W 0000000- 000000-0 0002B4H PTMR9 [R] H,W 11111111 11111111 PCSR9 [W] H,W XXXXXXXX XXXXXXXX 0002B8H PDUT9 [W] H,W XXXXXXXX XXXXXXXX PCN9 [R/W] B,H,W 0000000- 000000-0 0002BCH PTMR10 [R] H,W 11111111 11111111 PCSR10 [W] H,W XXXXXXXX XXXXXXXX 0002C0H PDUT10 [W] H,W XXXXXXXX XXXXXXXX PCN10 [R/W] B,H,W 0000000- 000000-0 Block PPG5 PPG6 PPG7 0002C4H IPCP0 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0002C8H IPCP1 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0002CCH ICFS01 [R/W] B, H, W ------00 ― LSYNS0 [R/W] B,H,W --000000 IPCP2 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0002D4H IPCP3 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICFS23 [R/W] B, H, W ------00 ― ― IPCP4 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0002E0H IPCP5 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICFS45 [R/W] B, H, W ------00 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL ― ― PPG10 Input capture 0,1 Input capture 2,3 ICS23 [R/W] B, H, W 00000000 0002DCH 0002E4H PPG9 ICS01 [R/W] B, H, W 00000000 0002D0H 0002D8H PPG8 Input capture 4,5 ICS45 [R/W] B, H, W 00000000 67 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 0002E8H OCCP0 [R/W] W 00000000 00000000 00000000 00000000 0002ECH OCCP1 [R/W] W 00000000 00000000 00000000 00000000 0002F0H OCFS01 [R/W] B, H, W ------11 ― OCSH01[R/W] B, H, W ---0--00 +3 Output compare 0,1 OCSL01[R/W] B, H, W 0000--00 0002F4H OCCP2 [R/W] W 00000000 00000000 00000000 00000000 0002F8H OCCP3 [R/W] W 00000000 00000000 00000000 00000000 Output compare 2,3 0002FCH OCFS23 [R/W] B, H, W ------11 ― OCSH23[R/W] B, H, W ---0--00 OCSL23[R/W] B, H, W 0000--00 000300H to 00030CH ― ― ― ― 68 CONFIDENTIAL Block Reserved MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 000310H ― ― 000314H ― ― 000320H 000324H 000328H 00032CH ― ― ― ― ― ― ― DPVSR [R/W] H -------- 00000--0 DESR [R/W] H -------- 00000--0 MPU [S] (Only the CPU can access this area) PACR0 [R/W] H 000000-0 00000--0 PABR1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 ― ― PACR1 [R/W] H 000000-0 00000--0 PABR2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 ― ― PACR2 [R/W] H 000000-0 00000--0 PABR3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 ― June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL ― PABR0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000348H 00034CH ― DEAR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000340H 000344H ― ― 000338H 00033CH MPUCR [R/W] H 000000-0 ----0100 DPVAR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000330H 000334H Block ― 000318H 00031CH +3 ― PACR3 [R/W] H 000000-0 00000--0 69 D a t a S h e e t Address 000350H 000354H +0 ― ― ― ― ― ― ― 70 CONFIDENTIAL ― PACR8 [R/W] H 000000-0 00000--0 ― PACR9 [R/W] H 000000-0 00000--0 ― PACR10 [R/W] H 000000-0 00000--0 ― PACR11 [R/W] H 000000-0 00000--0 MPU [S] (Only product supporting MPU 12 channels or 16 channels) (Only the CPU can access this area) PABR12 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 ― ― PACR12 [R/W] H 000000-0 00000--0 PABR13 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000398H 00039CH PACR7 [R/W] H 000000-0 00000--0 PABR11 [R/W] ,W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000390H 000394H ― PABR10 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000388H 00038CH PACR6 [R/W] H 000000-0 00000--0 PABR9[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000380H 000384H ― MPU [S] (Only the CPU can access this area) PABR8 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000378H 00037CH PACR5 [R/W] H 000000-0 00000--0 PABR7 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000370H 000374H ― PABR6 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000368H 00036CH Block PABR5 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 000360H 000364H +3 PABR4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 PACR4 [R/W] H ― ― 000000-0 00000--0 000358H 00035CH Address offset value / Register name +1 +2 ― ― PACR13 [R/W] H 000000-0 00000--0 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +3 PABR14 [R/W]W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 0003A0H 0003A4H Address offset value / Register name +1 +2 +0 ― ― PACR14 [R/W] H 000000-0 00000--0 PABR15 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 0003A8H PACR15 [R/W] H 000000-0 00000--0 0003ACH ― ― 0003B0H to 0003FCH ― ― ― ― ICSEL0[R/W] B, H, W -----000 ICSEL4[R/W] B, H, W -------0 ICSEL8[R/W] B, H, W ------00 ICSEL1[R/W] B, H, W -----000 ICSEL5[R/W] B, H, W -------0 ICSEL9[R/W] B, H, W ------00 ICSEL2[R/W] B, H, W -------0 ICSEL6[R/W] B, H, W -----000 ICSEL10 [R/W]B, H, W ------00 ICSEL3[R/W] B, H, W -------0 ICSEL7[R/W] B, H, W -----000 ICSEL11[R/W] B, H, W ------00 00040CH ICSEL12[R/W] B, H, W ------00 ICSEL13[R/W] B, H, W -------0 ICSEL14 [R/W]B, H, W -------0 ICSEL15[R/W] B, H, W -------0 000410H ICSEL16[R/W] B, H, W -------0 ICSEL17[R/W] B, H, W -------0 ICSEL18 [R/W]B, H, W -------0 ICSEL19[R/W] B, H, W -----000 000414H ICSEL20[R/W] B, H, W -----000 ICSEL21[R/W] B, H, W ------00 ICSEL22 [R/W]B, H, W ------00 ― IRPR0H[R] B, H, W 00-----IRPR2H[R] B, H, W 00------ IRPR0L[R] B, H, W 00-----IRPR2L[R] B, H, W 00------ IRPR1H[R] B, H, W 00-----IRPR3H[R] B, H, W 000000-- IRPR1L[R] B, H, W 00-----IRPR3L[R] B, H, W 000000-- IRPR4H[R] B, H, W 0000---- IRPR4L[R] B, H, W 0000---- IRPR5H[R] B, H, W 0000---- IRPR5L[R] B, H, W 000----- IRPR6H[R] B, H, W --000--IRPR8H[R] B, H, W 000----IRPR10H[R] B, H, W 00-----IRPR12H[R] B, H, W 000000-- IRPR6L[R] B, H, W 00000--IRPR8L[R] B, H, W 000----IRPR10L[R] B, H, W 00-----IRPR12L[R] B, H, W 000000-- IRPR7H[R] B, H, W -0000--IRPR9H[R] B, H, W 00-----IRPR11H[R] B, H, W 00-----IRPR13H[R] B, H, W 000----- IRPR7L[R] B, H, W ------00 IRPR9L[R] B, H, W 00-----IRPR11L[R] B, H, W 00-----IRPR13L[R] B, H, W 00000--- 000400H 000404H 000408H 000418H 00041CH 000420H 000424H 000428H 00042CH 000430H June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL Block MPU [S] (Only product supporting MPU 16 channels) (Only the CPU can access this area) Reserved [S] Generation and clear of DMA transfer request Interrupt request batch read register 71 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 Block 000434H IRPR14H[R] B, H, W 00000000 IRPR14L[R] B, H, W 00000000 IRPR15H[R] B, H, W 000----- ― Interrupt request batch read register 000438H to 00043CH ― ― ― ― Reserved 000440H ICR00 [R/W] B, H, W ---11111 ICR01 [R/W] B, H, W ---11111 ICR02 [R/W] B, H, W ---11111 ICR03 [R/W] B, H, W ---11111 000444H ICR04 [R/W] B, H, W ---11111 ICR05 [R/W] B, H, W ---11111 ICR06 [R/W] B, H, W ---11111 ICR07 [R/W] B, H, W ---11111 000448H ICR08 [R/W] B, H, W ---11111 ICR09 [R/W] B, H, W ---11111 ICR10 [R/W] B, H, W ---11111 ICR11 [R/W] B, H, W ---11111 00044CH ICR12 [R/W] B, H, W ---11111 ICR13 [R/W] B, H, W ---11111 ICR14 [R/W] B, H, W ---11111 ICR15 [R/W] B, H, W ---11111 000450H ICR16 [R/W] B, H, W ---11111 ICR17 [R/W] B, H, W ---11111 ICR18 [R/W] B, H, W ---11111 ICR19 [R/W] B, H, W ---11111 ICR20 [R/W] B, H, W ---11111 ICR24 [R/W] B, H, W ---11111 ICR28 [R/W] B, H, W ---11111 ICR32 [R/W] B, H, W ---11111 ICR36 [R/W] B, H, W ---11111 ICR40 [R/W] B, H, W ---11111 ICR21 [R/W] B, H, W ---11111 ICR25 [R/W] B, H, W ---11111 ICR29 [R/W] B, H, W ---11111 ICR33 [R/W] B, H, W ---11111 ICR37 [R/W] B, H, W ---11111 ICR41 [R/W] B, H, W ---11111 ICR22 [R/W] B, H, W ---11111 ICR26 [R/W] B, H, W ---11111 ICR30 [R/W] B, H, W ---11111 ICR34 [R/W] B, H, W ---11111 ICR38 [R/W] B, H, W ---11111 ICR42 [R/W] B, H, W ---11111 ICR23 [R/W] B, H, W ---11111 ICR27 [R/W] B, H, W ---11111 ICR31 [R/W] B, H, W ---11111 ICR35 [R/W] B, H, W ---11111 ICR39 [R/W] B, H, W ---11111 ICR43 [R/W] B, H, W ---11111 00046CH ICR44 [R/W] B, H, W ---11111 ICR45 [R/W] B, H, W ---11111 ICR46 [R/W] B, H, W ---11111 ICR47 [R/W] B, H, W ---11111 000470H to 00047CH ― ― ― ― 000454H 000458H 00045CH 000460H 000464H 000468H 72 CONFIDENTIAL Interrupt controller [S] Reserved [S] MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 Block Reset control [S] Power consumption control [S] RSTRR [R] B,H,W XXXX--XX RSTCR [R/W] B,H,W 111----0 STBCR [R/W] B,H,W * 000---11 ― DIVR0 [R/W] B,H,W 000----― ― DIVR1 [R/W] B,H,W 0001---― ― DIVR2 [R/W] B,H,W 0011---― ― 000490H IORR0[R/W] B, H, W -0000000 IORR1[R/W] B, H, W -0000000 IORR2[R/W] B, H, W -0000000 IORR3[R/W] B, H, W -0000000 000494H IORR4[R/W] B, H, W -0000000 IORR5[R/W] B, H, W -0000000 IORR6[R/W] B, H, W -0000000 IORR7[R/W] B, H, W -0000000 000498H IORR8[R/W] B, H, W -0000000 IORR9[R/W] B, H, W -0000000 IORR10[R/W] B, H, W -0000000 IORR11[R/W] B, H, W -0000000 00049CH IORR12[R/W] B, H, W -0000000 IORR13[R/W] B, H, W -0000000 IORR14[R/W] B, H, W -0000000 IORR15[R/W] B, H, W -0000000 0004A0H ― ― ― ― Reserved 0004A4H CANPRE [R/W] B,H,W ----0000 ― ― ― CAN prescaler 0004A8H to 0004B4H ― ― ― ― Reserved 0004B8H CUCR0 [R/W] B,H,W -------- ---0--00 000480H 000484H 000488H 00048CH ― ― Clock control [S] ― Reserved [S] DMA transfer request from a peripheral [S] CUTD0 [R/W] B,H,W 10000000 00000000 CUTR0 [R] B,H,W -------- 00000000 00000000 00000000 0004BCH 0004C0H ― 0004C4H CUCR1 [R/W] B,H,W -------- ---0--00 ― ― ― CUTD1[R/W] B,H,W 11000011 01010000 RTC/WDT1 calibration (Calibration) CUTR1 [R] B,H,W -------- 00000000 00000000 00000000 0004C8H 0004CCH CRTR [R/W] B,H,W 01111111 ― ― ― 0004D0H to 0004DCH ― ― ― ― June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL *: Writing to STBCR by DMA is not permitted Reserved [S] Reserved 73 D a t a S h e e t Address 0004E0H 0004E4H +0 SCR8/(IBCR8) [R/W] B,H,W 0--00000 Address offset value / Register name +1 +2 SMR8 [R/W] B,H,W 000-0000 RDR8/(TDR8)[R/W] B,H,W *1 -------0 00000000 SSR8 [R/W] B,H,W 0-000011 +3 ESCR8/(IBSR8) [R/W] B,H,W -0000000 BGR8 [R/W] H,W 00000000 00000000 0004E8H ― ― ― ― 0004ECH FCR18 [R/W] B,H,W ---00100 FCR08 [R/W] B,H,W -0000000 FBYTE28 [R/W] B,H,W 00000000 FBYTE18 [R/W] B,H,W 00000000 0004F0H SCR9/(IBCR9) [R/W] B,H,W 0--00000 SMR9 [R/W] B,H,W 000-0000 SSR9 [R/W] B,H,W 0-000011 ESCR9/(IBSR9) [R/W] B,H,W -0000000 0004F4H RDR9/(TDR9)[R/W] B,H,W *1 -------0 00000000 Block BGR9 [R/W] H,W 00000000 00000000 Multi-UART8 *1: Byte access is permitted only for access to lower 8 bits Multi-UART9 *1: Byte access is permitted only for access to lower 8 bits 0004F8H ― ― ― ― 0004FCH FCR19 [R/W] B,H,W ---00100 FCR09 [R/W] B,H,W -0000000 FBYTE29 [R/W] B,H,W 00000000 FBYTE19 [R/W] B,H,W 00000000 000500H to 00050CH ― ― ― ― Reserved 000510H CSELR [R/W] B,H,W 001---00 CMONR [R] B,H,W 001---00 MTMCR [R/W] B,H,W 00001111 CSTBR [R/W] B,H,W -0000000 CPUAR [R/W] B,H,W 0----XXX STMCR [R/W] B,H,W 0000-111 PTMCR [R/W] B,H,W 00------ Clock control [S] ― Reset [S] Reserved [S] 000514H PLLCR [R/W] B,H,W -------- 11110000 000518H ― ― 00051CH ― ― ― ― 000520H CCPSSELR [R/W] B,H,W -------0 ― ― CCPSDIVR [R/W] B,H,W -000-000 000524H ― CCPLLFBR [R/W] B,H,W -0000000 CCSSFBR0 [R/W] B,H,W --000000 CCSSFBR1 [R/W] B,H,W ---00000 000528H ― CCSSCCR0 [R/W] B,H,W ----0000 00052CH ― CCCGRCR0 [R/W] B,H,W 00----00 74 CONFIDENTIAL Clock control 2 CCSSCCR1[R/W]H,W 000----- -------CCCGRCR1 [R/W] B,H,W 00000000 CCCGRCR2 [R/W] B,H,W 00000000 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 000534H 000538H CCRTSELR [R/W] B,H,W 0------0 ― ― 00053CH ― ― ― ― 000540H to 00054CH ― ― ― ― 000550H EIRR0[R/W] B,H,W XXXXXXXX ENIR0[R/W] B,H,W 00000000 ELVR0[R/W] B,H,W 00000000 00000000 External interrupt (INT0 to INT7) 000554H EIRR1[R/W] B,H,W XXXXXXXX ENIR1[R/W] B,H,W 00000000 ELVR1[R/W] B,H,W 00000000 00000000 External interrupt (INT8 to INT15) 000558H ― ― 00055CH ― ― 000560H ― WTCRH [R/W] B ------00 WTCRM [R/W] B,H 00000000 WTCRL [R/W] B,H ----00-0 000564H ― WTBRH [R/W] B --XXXXXX WTBRM [R/W] B XXXXXXXX WTBRL [R/W] B XXXXXXXX 000568H WTHR [R/W] B,H ---00000 WTSR [R/W] B --000000 ― 00056CH ― ― ― Clock supervisor 000570H to 00057CH ― ― ― ― Reserved 000580H REGSEL [R/W] B,H,W 0110011- ― ― ― Regulator control 000584H LVD5R [R/W] B,H,W -------1 LVD5F [R/W] B,H,W 0-100--1 LVD [R/W] B,H,W 01000--0 ― Low-voltage detection 000588H to 00058CH ― ― ― ― Reserved 000530H June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL ― ― CCPMUCR0 [R/W] B,H,W 0-----00 ― ― CCPMUCR1 [R/W] B,H,W 0--00000 ― ― Block ― WTMR [R/W] B,H --000000 CSVCR[R/W]B -001110-001010-*3 ― ― Clock control 2 Reserved Reserved WTDR[R/W] H 00000000 00000000 Real-time clock 75 D a t a S h e e t Address Address offset value / Register name +1 +2 +0 +3 000590H PMUSTR [R/W] B,H,W 0-----1X PMUCTLR [R/W] B,H,W 0-00---- PWRTMCTL [R/W] B,H,W -----011 ― 000594H PMUINTF0 [R/W] B,H,W 00000000 PMUINTF1 [R/W] B,H,W 00000000 PMUINTF2 [R/W] B,H,W 0000---- ― 000598H ― ― ― ― 00059CH to 0005A4H ― ― ― ― 0005A8H LCDCMR [R/W] B,H,W 0------- LCRS [R/W] B,H,W 00000000 LCR0 [R/W] B,H,W 00010000 LCR1 [R/W] B,H,W -------- 0005ACH VRAM0[R/W] B,H,W 00000000 VRAM1[R/W] B,H,W 00000000 VRAM2[R/W] B,H,W 00000000 VRAM3[R/W] B,H,W 00000000 0005B0H VRAM4[R/W] B,H,W 00000000 VRAM5[R/W] B,H,W 00000000 VRAM6[R/W] B,H,W 00000000 VRAM7[R/W] B,H,W 00000000 0005B4H VRAM8[R/W] B,H,W 00000000 VRAM9[R/W] B,H,W 00000000 VRAM10[R/W] B,H,W 00000000 VRAM11[R/W] B,H,W 00000000 0005B8H VRAM12[R/W] B,H,W 00000000 VRAM13[R/W] B,H,W 00000000 VRAM14[R/W] B,H,W 00000000 VRAM15[R/W] B,H,W 00000000 0005BCH LDR0[R/W] B,H,W -------0 LDR1[R/W] B,H,W 00000000 ― ― 0005C0H to 0005FCH ― ― ― ― 000600H ASR0 [R/W] W 00000000 00000000 -------- 1111-001 000604H ASR1 [R/W] W XXXXXXXX XXXXXXXX -------- XXXX-XX0 000608H ASR2 [R/W] W XXXXXXXX XXXXXXXX -------- XXXX-XX0 00060CH ASR3 [R/W] W XXXXXXXX XXXXXXXX -------- XXXX-XX0 000610H to 00063CH 76 CONFIDENTIAL ― ― ― Block PMU Reserved LCD controller Reserved External bus Interface [S] ― Reserved [S] MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address Address offset value / Register name +1 +2 +0 Block ACR0 [R/W] W -------- -------- -------- 01--00-- 000640H ACR1 [R/W] W -------- -------- -------- XX--XX-ACR2 [R/W] W -------- -------- -------- XX--XX-- 000644H 000648H External bus Interface [S] ACR3 [R/W] W -------- -------- -------- XX--XX-- 00064CH 000650H to 00067CH +3 ― ― ― ― 000680H AWR0 [R/W] W ----1111 00000000 11110000 00000-0- 000684H AWR1 [R/W] W ----XXXX XXXXXXXX XXXXXXXX XXXXX-X- 000688H AWR2 [R/W] W ----XXXX XXXXXXXX XXXXXXXX XXXXX-X- 00068CH AWR3 [R/W] W ----XXXX XXXXXXXX XXXXXXXX XXXXX-X- 000690H to 00070CH ― 000710H BPCCRA[R/W] B 00000000 ― 000714H 000718H 00071CH ― BPCCRB[R/W] BPCCRC[R/W] B B 00000000 00000000 BPCTRA [R/W] W 00000000 00000000 00000000 00000000 BPCTRB [R/W] W 00000000 00000000 00000000 00000000 BPCTRC [R/W] W 00000000 00000000 00000000 00000000 Reserved [S] External bus Interface [S] ― Reserved (to 0006FFH[S]) ― Bus performance counter 000720H to 0007F8H ― ― ― ― Reserved 0007FCH BMODR[R] B, H, W XXXXXXXX ― ― ― Operation mode 000800H to 00083CH ― ― ― ― Reserved [S] ― FSTR[R/W] B -----001 Flash memory register [S] ― ― ― ― ― ― ― ― ― ― Reserved [S] FCTLR[R/W] H -0--1000 0--0---- 000840H 000844H 000848H 00084CH 000850H 000854H ― ― ― ― ― ― ― ― ― ― 000858H ― ― June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL WREN[R/W] H 00000000 00000000 Reserved [S] Wild register [S] 77 D a t a S h e e t Address 00085CH 000860H 000864H 000868H 00086CH 000870H 000874H 000878H 00087CH +0 ― ― ― ― ― ― ― ― ― Address offset value / Register name +1 +2 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― +3 ― ― ― ― ― ― ― ― ― 000880H WRAR00 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-- 000884H WRDR00 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000888H 00088CH 000890H 000894H 000898H 00089CH 0008A0H 0008A4H 0008A8H 0008ACH 0008B0H 0008B4H 0008B8H 0008BCH 0008C0H 0008C4H 78 CONFIDENTIAL WRAR01 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR01 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR02 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR02 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR03 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR03 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR04 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR04 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR05 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR05 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR06 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR06 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR07 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR07 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR08 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR08 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block Reserved [S] Reserved [S] Wild register [S] MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address 0008C8H 0008CCH 0008D0H 0008D4H 0008D8H 0008DCH 0008E0H 0008E4H 0008E8H 0008ECH 0008F0H 0008F4H 0008F8H 0008FCH +0 Address offset value / Register name +1 +2 WRAR09 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR09 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR10 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR10 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR11 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR11 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR12 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR12 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR13 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR13 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR14 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR14 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR15 [R/W] W -------- --XXXXXX XXXXXXXX XXXXXX-WRDR15 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000900H to 000BF8H ― ― 000BFCH ― ― 000C00H 000C04H 000C08H +3 ― ― UER [W] B,H,W -------- -------X DDAR0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C10H DCCR1 [R/W] W 0----000 --00--00 00000000 0-000000 DCSR1 [R/W] H 0------- -----000 Reserved OCDU DSAR1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C1CH DDAR1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX June 19, 2015, MB91F577_DS705-00009-3v0-E DMA controller [S] DTCR1 [R/W] H 00000000 00000000 000C18H CONFIDENTIAL Wild register [S] DCCR0[R/W] W 0----000 --00--00 00000000 0-000000 DCSR0[R/W] H DTCR0[R/W] H 0------- -----000 00000000 00000000 DSAR0[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C0CH 000C14H Block 79 D a t a S h e e t Address 000C20H 000C24H +0 Address offset value / Register name +1 +2 +3 DCCR2 [R/W] W 0----000 --00--00 00000000 0-000000 DCSR2 [R/W] H 0------- -----000 DTCR2 [R/W] H 00000000 00000000 000C28H DSAR2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C2CH DDAR2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C30H DCCR3[R/W] W 0----000 --00--00 00000000 0-000000 000C34H DCSR3 [R/W] H 0------- -----000 DTCR3 [R/W] H 00000000 00000000 000C38H DSAR3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C3CH DDAR3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C40H DCCR4 [R/W] W 0----000 --00--00 00000000 0-000000 000C44H DCSR4 [R/W] H 0------- -----000 DTCR4 [R/W] H 00000000 00000000 000C48H DSAR4[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C4CH DDAR4[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C50H DCCR5 [R/W] W 0----000 --00--00 00000000 0-000000 000C54H 000C58H 000C5CH 000C60H 000C64H DCSR5 [R/W] H 0------- -----000 DSAR5 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR5 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR6 [R/W] W 0----000 --00--00 00000000 0-000000 DCSR6 [R/W] H 0------- -----000 DTCR6 [R/W] H 00000000 00000000 DSAR6 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C6CH DDAR6 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX CONFIDENTIAL DMA controller [S] DTCR5 [R/W] H 00000000 00000000 000C68H 80 Block MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address 000C70H 000C74H +0 Address offset value / Register name +1 +2 +3 DCCR7 [R/W] W 0----000 --00--00 00000000 0-000000 DCSR7 [R/W] H 0------- -----000 DTCR7 [R/W] H 00000000 00000000 000C78H DSAR7 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C7CH DDAR7 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C80H DCCR8 [R/W] W 0----000 --00--00 00000000 0-000000 000C84H DCSR8 [R/W] H 0------- -----000 DTCR8 [R/W] H 00000000 00000000 000C88H DSAR8 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C8CH DDAR8 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C90H DCCR9 [R/W] W 0----000 --00--00 00000000 0-000000 000C94H DCSR9 [R/W] H 0------- -----000 DTCR9 [R/W] H 00000000 00000000 000C98H DSAR9 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000C9CH DDAR9 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000CA0H 000CA4H 000CA8H 000CACH 000CB0H 000CB4H 000CB8H 000CBCH DMA controller [S] DCCR10 [R/W] W 0----000 --00--00 00000000 0-000000 DCSR10[R/W] H DTCR10[R/W] H 0------- -----000 00000000 00000000 DSAR10 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR10 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR11[R/W] W 0----000 --00--00 00000000 0-000000 DCSR11 [R/W] H DTCR11 [R/W] H 0------- -----000 00000000 00000000 DSAR11 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR11 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL Block 81 D a t a S h e e t Address 000CC0H 000CC4H +0 Address offset value / Register name +1 +2 +3 DCCR12 [R/W] W 0----000 --00--00 00000000 0-000000 DCSR12 [R/W] H DTCR12 [R/W] H 0------- -----000 00000000 00000000 000CC8H DSAR12 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000CCCH DDAR12 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000CD0H DCCR13 [R/W] W 0----000 --00--00 00000000 0-000000 000CD4H DCSR13[R/W] H 0------- -----000 000CD8H DSAR13[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000CDCH DDAR13[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000CE0H DCCR14[R/W] W 0----000 --00--00 00000000 0-000000 000CE4H 000CE8H 000CECH DTCR13[R/W] H 00000000 00000000 DCSR14[R/W] H 0------- -----000 DTCR14[R/W] H 00000000 00000000 DCCR15[R/W] W 0----000 --00--00 00000000 0-000000 000CF4H DCSR15[R/W] H 0------- -----000 000CF8H DSAR15[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000CFCH DDAR15[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DTCR15[R/W] H 00000000 00000000 000D00H to 000DF0H ― ― ― ― 000DF4H ― ― DNMIR[R/W] B 0------0 DILVR[R/W] B ---11111 DMACR[R/W] W 0------- -------- 0------- -------- 000DF8H 82 CONFIDENTIAL DMA controller [S] DSAR14[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR14[R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000CF0H 000DFCH Block ― ― ― ― Reserved [S] DMA controller [S] Reserved [S] MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address 000E00H 000E04H 000E08H 000E0CH 000E10H 000E14H to 000E1CH 000E20H 000E24H 000E28H 000E2CH 000E30H 000E34H to 000E3CH 000E40H 000E44H 000E48H 000E4CH 000E50H 000E54H to 000E5CH +0 Address offset value / Register name +1 +2 DDR00[R/W] B,H,W 00000000 DDR04[R/W] B,H,W 00000000 DDR08[R/W] B,H,W 00000000 DDR12[R/W] B,H,W 00000000 DDR16[R/W] B,H,W 00000000*4 DDR01[R/W] B,H,W 00000000 DDR05[R/W] B,H,W -0000000 DDR09[R/W] B,H,W 00000000 DDR13[R/W] B,H,W 00-00000 DDR17[R/W] B,H,W 00000000*4 DDR02[R/W] B,H,W 00000000 DDR06[R/W] B,H,W 00000000 DDR10[R/W] B,H,W 00000000 DDR14[R/W] B,H,W 00000000*4 DDR18[R/W] B,H,W 00000000*4 DDR03[R/W] B,H,W 00000000 DDR07[R/W] B,H,W 00000000 DDR11[R/W] B,H,W 00000000 DDR15[R/W] B,H,W 00000000*4 DDR19[R/W] B,H,W 00000000*4 ― ― ― ― PFR00[R/W] B,H,W 00000000 PFR04[R/W] B,H,W 11111111 PFR08[R/W] B,H,W 00000000 PFR01[R/W] B,H,W 00000000 PFR05[R/W] B,H,W 11111111 PFR09[R/W] B,H,W 0-000000 PFR02[R/W] B,H,W 00000000 PFR06[R/W] B,H,W 00000000 PFR10[R/W] B,H,W 00000000 PFR03[R/W] B,H,W 10000000 PFR07[R/W] B,H,W 00000000 PFR11[R/W] B,H,W 00000000 PFR12[R/W] B,H,W 00000000 PFR16[R/W] B,H,W 00000000*4 PFR13[R/W] B,H,W 00-00000 PFR17[R/W] B,H,W 00000000*4 PFR14[R/W] B,H,W 00000000*4 PFR18[R/W] B,H,W 00000000*4 PFR15[R/W] B,H,W 00000000*4 PFR19[R/W] B,H,W 00000000*4 ― ― ― ― PDDR00[R] B,H,W XXXXXXXX PDDR04[R] B,H,W XXXXXXXX PDDR08[R] B,H,W XXXXXXXX PDDR12[R] B,H,W XXXXXXXX PDDR16[R] B,H,W XXXXXXXX*4 PDDR01[R] B,H,W XXXXXXXX PDDR05[R] B,H,W XXXXXXXX PDDR09[R] B,H,W XXXXXXXX PDDR13[R] B,H,W XX-XXXXX PDDR17[R] B,H,W XXXXXXXX*4 PDDR02[R] B,H,W XXXXXXXX PDDR06[R] B,H,W XXXXXXXX PDDR10[R] B,H,W XXXXXXXX PDDR14[R] B,H,W XXXXXXXX*4 PDDR18[R] B,H,W XXXXXXXX*4 PDDR03[R] B,H,W XXXXXXXX PDDR07[R] B,H,W XXXXXXXX PDDR11[R] B,H,W XXXXXXXX PDDR15[R] B,H,W XXXXXXXX*4 PDDR19[R] B,H,W XXXXXXXX*4 ― ― ― ― June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL +3 Block Data direction Register *4:MB91F578/9 only Reserved Port function register *4:MB91F578/9 only Reserved Input data direct read register *4:MB91F578/9 only Reserved 83 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 Block EPFR00[R/W] B,H,W 00000000 EPFR04[R/W] B,H,W ---00000 EPFR08[R/W] B,H,W ---00000 EPFR12[R/W] B,H,W --000000 EPFR16[R/W] B,H,W 00000000 EPFR20[R/W] B,H,W 11111111 EPFR24[R/W] B,H,W -----000 EPFR28[R/W] B,H,W ----0000 EPFR32[R/W] B,H,W 00000000 EPFR36[R/W] B,H,W ---00000 EPFR40[R/W] B,H,W --000000 EPFR01[R/W] B,H,W 00000000 EPFR05[R/W] B,H,W ---00000 EPFR09[R/W] B,H,W ---00000 EPFR13[R/W] B,H,W --000000 EPFR17[R/W] B,H,W 00000000 EPFR21[R/W] B,H,W 00000000 EPFR25[R/W] B,H,W -----000 EPFR29[R/W] B,H,W 00000000 EPFR33[R/W] B,H,W ---00000 EPFR37[R/W] B,H,W 00000000 EPFR41[R/W] B,H,W -----000 EPFR02[R/W] B,H,W ---00000 EPFR06[R/W] B,H,W ---00000 EPFR10[R/W] B,H,W -0000000 EPFR14[R/W] B,H,W --000000 EPFR18[R/W] B,H,W 10000000 EPFR22[R/W] B,H,W 00000000 EPFR26[R/W] B,H,W ----0000 EPFR30[R/W] B,H,W 00000000 EPFR34[R/W] B,H,W ---00000 EPFR38[R/W] B,H,W ---00000 EPFR42[R/W] B,H,W ------00 EPFR03[R/W] B,H,W ---00000 EPFR07[R/W] B,H,W ---00000 EPFR11[R/W] B,H,W --000000 EPFR15[R/W] B,H,W -0000000 EPFR19[R/W] B,H,W 11111111 EPFR23[R/W] B,H,W 00000000 EPFR27[R/W] B,H,W ---00000 EPFR31[R/W] B,H,W 00000000 EPFR35[R/W] B,H,W ---00000 EPFR39[R/W] B,H,W 00000000 EPFR43[R/W] B,H,W 00000000 000E8CH EPFR44[R/W] B,H,W 00000000 EPFR45[R/W] B,H,W 00000000 EPFR46[R/W] B,H,W --000000 EPFR47[R/W] B,H,W -------0 000E90H ― ― ― ― 000E94H EPFR52[R/W] B,H,W -------0 EPFR53[R/W] B,H,W ---00000 EPFR54[R/W] B,H,W ----0000 ― Extended port function register 000E98H to 000E9CH ― ― ― ― Reserved 000E60H 000E64H 000E68H 000E6CH 000E70H 000E74H 000E78H 000E7CH 000E80H 000E84H 000E88H 84 CONFIDENTIAL Extended port function register MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address 000EA0H 000EA4H 000EA8H 000EACH 000EB0H 000EBCH 000EC0H 000EC4H 000EC8H 000ECCH 000ED0H 000EDCH 000EE0H 000EE4H 000EE8H 000EECH 000EF0H 000EFCH +0 Address offset value / Register name +1 +2 PPCR00[R/W] B,H,W 11111111 PPCR01[R/W] B,H,W 11111111 PPCR02[R/W] B,H,W 11111111 PPCR03[R/W] B,H,W 11111111 PPCR04[R/W] B,H,W 11111111 PPCR08[R/W] B,H,W 11111111 PPCR12[R/W] B,H,W 11111111 PPCR16[R/W] B,H,W 11111111*4 PPCR05[R/W] B,H,W 11111111 PPCR09[R/W] B,H,W 11111111 PPCR13[R/W] B,H,W 11-11111 PPCR17[R/W] B,H,W 11111111*4 PPCR06[R/W] B,H,W 11111111 PPCR10[R/W] B,H,W 11111111 PPCR14[R/W] B,H,W 11111111*4 PPCR18[R/W] B,H,W 11111111*4 PPCR07[R/W] B,H,W 11111111 PPCR11[R/W] B,H,W 11111111 PPCR15[R/W] B,H,W 11-11111*4 PPCR19[R/W] B,H,W 11-11111*4 ― ― ― ― PPER00[R/W] B,H,W 00000000 PPER04[R/W] B,H,W 00000000 PPER08[R/W] B,H,W 00000000 PPER12[R/W] B,H,W 00000000 PPER16[R/W] B,H,W 00000000*4 PPER01[R/W] B,H,W 00000000 PPER05[R/W] B,H,W 00000000 PPER09[R/W] B,H,W 00000000 PPER13[R/W] B,H,W 00-00000 PPER17[R/W] B,H,W 00000000*4 PPER02[R/W] B,H,W 00000000 PPER06[R/W] B,H,W 00000000 PPER10[R/W] B,H,W 00000000 PPER14[R/W] B,H,W 00000000*4 PPER18[R/W] B,H,W 00000000*4 PPER03[R/W] B,H,W 00000000 PPER07[R/W] B,H,W 00000000 PPER11[R/W] B,H,W 00000000 PPER15[R/W] B,H,W 00000000*4 PPER19[R/W] B,H,W 00000000*4 ― ― ― ― PILR00[R/W] B,H,W 11111111 PILR04[R/W] B,H,W 11111111 PILR08[R/W] B,H,W 11111111 PILR12[R/W] B,H,W 11111111 PILR16[R/W] B,H,W 11111111*4 PILR01[R/W] B,H,W 11111111 PILR05[R/W] B,H,W 11111111 PILR09[R/W] B,H,W 11111111 PILR13[R/W] B,H,W 11-11111 PILR17[R/W] B,H,W 11111111*4 PILR02[R/W] B,H,W 11111111 PILR06[R/W] B,H,W 11111111 PILR10[R/W] B,H,W 11111111 PILR14[R/W] B,H,W 11111111*4 PILR18[R/W] B,H,W 11111111*4 PILR03[R/W] B,H,W 11111111 PILR07[R/W] B,H,W 11111111 PILR11[R/W] B,H,W 11111111 PILR15[R/W] B,H,W 11111111*4 PILR19[R/W] B,H,W 11111111*4 ― ― ― ― June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL +3 Block Port pull-up/down control register *4:MB91F578/9 only Reserved Port pull-up/down enable register *4:MB91F578/9 only Reserved Port input level selection register *4:MB91F578/9 only Reserved 85 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 EPILR00[R/W] B,H,W 00000000 EPILR04[R/W] B,H,W 00000000 EPILR08[R/W] B,H,W 00000000 EPILR12[R/W] B,H,W 00000000 EPILR16[R/W] B,H,W 00000000*4 EPILR01[R/W] B,H,W 00000000 EPILR05[R/W] B,H,W 00000000 EPILR09[R/W] B,H,W 00000000 EPILR13[R/W] B,H,W 00-00000 EPILR17[R/W] B,H,W 00000000*4 EPILR02[R/W] B,H,W 00000000 EPILR06[R/W] B,H,W 00000000 EPILR10[R/W] B,H,W 00000000 EPILR14[R/W] B,H,W 00000000*4 EPILR18[R/W] B,H,W 00000000*4 EPILR03[R/W] B,H,W 00000000 EPILR07[R/W] B,H,W 00000000 EPILR11[R/W] B,H,W 00000000 EPILR15[R/W] B,H,W 00000000*4 EPILR19[R/W] B,H,W 00000000*4 000F1CH ― ― ― ― 000F20H PODR00[R/W] B,H,W 00000000 PODR01[R/W] B,H,W 00000000 PODR02[R/W] B,H,W 00000000 PODR03[R/W] B,H,W 00000000 000F24H PODR04[R/W] B,H,W 00000000 PODR05[R/W] B,H,W 00000000 PODR06[R/W] B,H,W 00000000 PODR07[R/W] B,H,W 00000000 PODR08[R/W] B,H,W 00000000 PODR12[R/W] B,H,W 00000000 PODR16[R/W] B,H,W 00000000*4 PODR10[R/W] B,H,W 00000000 PODR14[R/W] B,H,W 00000000*4 PODR18[R/W] B,H,W 00000000*4 EPODR02 [R/W] B,H,W 00000000 EPODR08 [R/W] B,H,W 00000000 PODR11[R/W] B,H,W 00000000 PODR15[R/W] B,H,W 00000000*4 PODR19[R/W] B,H,W 00000000*4 EPODR03 [R/W] B,H,W -0000000 000F00H 000F04H 000F08H 000F0CH 000F10H Block Extended Port input level selection register *4:MB91F578/9 only Reserved Port output drive register 000F34H ― 000F38H EPODR06 [R/W] B,H,W 00000000 PODR09[R/W] B,H,W 00000000 PODR13[R/W] B,H,W 00-00000 PODR17[R/W] B,H,W 00000000*4 EPODR01 [R/W] B,H,W 00000000 EPODR07 [R/W] B,H,W 00000000 000F3CH ― ― ― ― Reserved 000F40H PORTEN [R/W] B,H,W -------0 ― ― ― Port input enable register 000F44H to 000F6CH ― ― ― ― Reserved 000F70H RCRH0[W] H,W XXXXXXXX UDCRH0[R] H,W 00000000 UDCRL0[R] B,H,W 00000000 CSR0[R/W] B 00000000 Up/down counter 0 ― Reserved 000F28H 000F2CH 000F30H 000F74H 000F78H to 000F7CH 86 CONFIDENTIAL RCRL0[W] B,H,W XXXXXXXX CCR0[R/W] B,H 00000000 -0001000 ― ― ― ― ― *4:MB91F578/9 only Extended Port output drive register MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address 000F80H 000F84H 000F88H to 000F8CH +0 Address offset value / Register name +1 +2 RCRL1[W] B,H,W XXXXXXXX RCRH1[W] H,W XXXXXXXX CCR1[R/W] B,H 00000000 -0001000 ― ― +3 UDCRH1 [R] H,W 00000000 UDCRL1[R] B,H,W 00000000 ― CSR1[R/W] B 00000000 ― ― 000F90H OCCP4 [R/W] W 00000000 00000000 00000000 00000000 000F94H OCCP5 [R/W] W 00000000 00000000 00000000 00000000 OCFS45 [R/W] B, H, W ------11 ― OCSH45 [R/W] B, H, W ---0--00 OCSL45[R/W] B, H, W 0000--00 000F9CH ― ― ― ― 000FA4H 000FA8H 000FACH 000FB0H 000FB4H 000FB8H CPCLR2 [R/W] W 11111111 11111111 11111111 11111111 TCDT2 [R/W] W 00000000 00000000 00000000 00000000 TCCSH2 [R/W] TCCSL2 [R/W] B,H,W B,H,W ― 0-----00 -1-00000 CPCLR3 [R/W] W 11111111 11111111 11111111 11111111 TCDT3 [R/W] W 00000000 00000000 00000000 00000000 TCCSH3 [R/W] TCCSL3 [R/W] B,H,W B,H,W ― 0-----00 -1-00000 CPCLR4 [R/W] W 11111111 11111111 11111111 11111111 TCDT4 [R/W] W 00000000 00000000 00000000 00000000 000FBCH 000FC0H TCCSH4 [R/W] B,H,W 0-----00 000FC4H 000FC8H 000FCCH TCCSH5 [R/W]B,H,W 0-----00 TCCSL4 [R/W] B,H,W ― -1-00000 CPCLR5 [R/W] W 11111111 11111111 11111111 11111111 TCDT5 [R/W] W 00000000 00000000 00000000 00000000 TCCSL5 [R/W]B,H,W ― -1-00000 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL Up/down counter 1 Reserved Output compare 4,5 000F98H 000FA0H Block Reserved Free-run timer 2 Free-run timer 3 Free-run timer 4 Free-run timer 5 87 D a t a S h e e t Address 000FD0H 000FD4H 000FD8H 000FDCH 000FE0H 000FE4H 000FE8H 000FECH 000FF0H 000FF4H to 000FFCH +0 Address offset value / Register name +1 +2 +3 IPCP6 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPCP7 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICFS67 [R/W] LSYNS1 [R/W] ICS67 [R/W] B, H, W ― B,H,W B, H, W ------00 ----0000 00000000 IPCP8 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPCP9 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICFS89 [R/W] ICS89 [R/W] B, H, W ― ― B, H, W ------00 00000000 IPCP10 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPCP11 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICFS1011 [R/W] ICS1011 [R/W] B, H, W ― ― B, H, W ------00 00000000 Block Input capture 6,7 Input capture 8,9 Input capture 10,11 ― ― ― ― Reserved SACR [R/W] B,H,W PICD [R/W] B,H,W ― ― Clock control -------0 ----0011 001004H to 00103CH ― ― ― ― Reserved 001040H ― SGDER0 [R/W] B,H,W 00000000 001044H SGAR0[R/W] B,H,W 00000000 00000000 001000H 001048H SGTCR0[R/W] B,H,W 00000000 00104CH 001050H to 00105CH 88 CONFIDENTIAL ― SGCR0[R/W] B,H,W -0000-0- 000--000 SGFR0[R/W] B,H,W 00000000 SGNR0[R/W] B,H,W 00000000 SGIDR0[R/W] SGPCR0[R/W] B,H,W B,H,W 00000000 11111111 00000000 SGDMAR0[W] B,H,W 00000000 00000000 00000000 00000000 ― ― ― Sound generator 0 Reserved MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 SGDER1[R/W] B,H,W 00000000 001060H ― 001064H SGAR1[R/W] B,H,W 00000000 00000000 001068H SGTCR1[R/W] B,H,W 00000000 00106CH ― ― 001080H ― SGDER2[R/W] B,H,W 00000000 001084H SGAR2[R/W] B,H,W 00000000 00000000 SGTCR2[R/W] B,H,W 00000000 SGIDR2[R/W] B,H,W 00000000 001090H to 00109CH ― ― 0010A0H ― SGDER3[R/W] B,H,W 00000000 0010A4H SGAR3[R/W] B,H,W 00000000 00000000 SGTCR3[R/W] B,H,W 00000000 0010ACH 0010B0H to 0010BCH ― SGNR1[R/W] B,H,W 00000000 ― Sound generator 1 Reserved SGCR2[R/W] B,H,W -0000-0- 000--000 SGFR2[R/W] B,H,W 00000000 SGNR2[R/W] B,H,W 00000000 Sound generator 2 SGPCR2[R/W] B,H,W 00000000 11111111 ― ― ― ― Reserved SGCR3[R/W] B,H,W -0000-0- 000--000 SGFR3[R/W] B,H,W 00000000 SGIDR3[R/W] SGPCR3[R/W] B,H,W B,H,W 00000000 SGDMAR3[W] B,H,W 00000000 00000000 00000000 00000000 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL SGFR1[R/W] B,H,W 00000000 SGDMAR2[W] B,H,W 00000000 00000000 00000000 00000000 00108CH 0010A8H Block SGCR1[R/W] B,H,W -0000-0- 000--000 SGIDR1[R/W] SGPCR1[R/W] B,H,W B,H,W 00000000 11111111 00000000 SGDMAR1[W] B,H,W 00000000 00000000 00000000 00000000 001070H to 00107CH 001088H +3 ― SGNR3[R/W] B,H,W 00000000 Sound generator 3 00000000 11111111 ― Reserved 89 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 SGDER4[R/W] B,H,W 00000000 0010C0H ― 0010C4H SGAR4[R/W] B,H,W 00000000 00000000 0010C8H SGTCR4[R/W] B,H,W 00000000 SGIDR4[R/W] B,H,W 00000000 +3 SGCR4[R/W] B,H,W -0000-0- 000--000 SGFR4[R/W] B,H,W 00000000 SGNR4[R/W] B,H,W 00000000 SGPCR4[R/W] B,H,W 00000000 11111111 0010D0H to 00112CH ― ― ― ― 001130H ― ― ― CRCCR[R/W] B,H,W -0000000 CRCINIT[R/W] B,H,W 1111111 1111111 1111111 1111111 001134H 00113CH CONFIDENTIAL Reserved CRC operation CRCIN[R/W] B,H,W 00000000 00000000 00000000 00000000 CRCR[R] B,H,W 1111111 1111111 1111111 1111111 001138H 90 Sound generator 4 SGDMAR4[W] B,H,W 00000000 00000000 00000000 00000000 0010CCH 001140H to 001FFCH Block ― ― ― ― Reserved MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 002000H CTRLR0 [R/W] B,H,W --------000-0001 STATR0[R/W] B,H,W -------- 00000000 002004H ERRCNT0 [R] B,H,W 00000000 00000000 BTR0[R/W] B,H,W -0100011 00000001 002008H 00200CH 002010H 002014H 002018H 00201CH 002020H 002024H INTR0 [R] B,H,W 00000000 00000000 BRPER0 [R/W] B,H,W -------- ----0000 IF1CREQ0 [R/W] B,H,W 0------- 00000001 IF1MSK20 [R/W] B,H,W 11-11111 11111111 IF1ARB20 [R/W] B,H,W 00000000 00000000 IF1MCTR0 [R/W] B,H,W 00000000 0---0000 IF1DTA10 [R/W] B,H,W 00000000 00000000 IF1DTB10 [R/W] B,H,W 00000000 00000000 TESTR0[R/W] B,H,W -------- X00000-― IF1CMSK0 [R/W] B,H,W -------- 00000000 IF1MSK10 [R/W] B,H,W 11111111 11111111 IF1ARB10 [R/W] B,H,W 00000000 00000000 ― IF1DTA20[R/W] B,H,W 00000000 00000000 Reserved 002030H, 002034H Reserved (IF1 data mirror) 002038H, 00203CH Reserved 002040H IF2CREQ0 [R/W] B,H,W 0------- 00000001 IF2CMSK0 [R/W] B,H,W -------- 00000000 002044H IF2MSK20 [R/W] B,H,W 11-11111 11111111 IF2MSK10 [R/W] B,H,W 11111111 11111111 002048H IF2ARB20 [R/W] B,H,W 00000000 00000000 IF2ARB10 [R/W] B,H,W 00000000 00000000 00204CH IF2MCTR0 [R/W] B,H,W 00000000 0---0000 ― CONFIDENTIAL CAN0 (64msb) IF1DTB20 [R/W] B,H,W 00000000 00000000 002028H, 00202CH June 19, 2015, MB91F577_DS705-00009-3v0-E Block 91 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 002050H IF2DTA10 [R/W] B,H,W 00000000 00000000 IF2DTA20 [R/W] B,H,W 00000000 00000000 002054H IF2DTB10 [R/W] B,H,W 00000000 00000000 IF2DTB20 [R/W] B,H,W 00000000 00000000 002058H, 00205CH Reserved 002060H, 002064H Reserved (IF2 data mirror) 002068H to 00207CH Reserved 002080H 002084H 002088H 00208CH 002090H 002094H 002098H 00209CH 0020A0H 0020A4H 0020A8H 0020ACH 0020B0H 0020B4H 0020B8H 0020BCH 0020C0H to 0020FCH 92 CONFIDENTIAL TREQR20 [R] B,H,W 00000000 00000000 TREQR40 [R] B,H,W 00000000 00000000 ― ― NEWDT20 [R] B,H,W 00000000 00000000 NEWDT40 [R] B,H,W 00000000 00000000 ― ― INTPND20 [R] B,H,W 00000000 00000000 INTPND40 [R] B,H,W 00000000 00000000 ― ― MSGVAL20 [R] B,H,W 00000000 00000000 MSGVAL40 [R] B,H,W 00000000 00000000 ― ― TREQR10 [R] B,H,W 00000000 00000000 TREQR30 [R] B,H,W 00000000 00000000 ― ― NEWDT10 [R] B,H,W 00000000 00000000 NEWDT30 [R]B,H,W 00000000 00000000 ― ― INTPND10 [R] B,H,W 00000000 00000000 INTPND30 [R] B,H,W 00000000 00000000 ― ― MSGVAL10 [R] B,H,W 00000000 00000000 MSGVAL30 [R] B,H,W 00000000 00000000 ― ― Block CAN0 (64msb) Reserved MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 002100H CTRLR1 [R/W] B,H,W --------000-0001 STATR1[R/W] B,H,W -------- 00000000 002104H ERRCNT1 [R] B,H,W 00000000 00000000 BTR1[R/W] B,H,W -0100011 00000001 002108H 00210CH 002110H 002114H 002118H 00211CH 002120H 002124H INTR1 [R] B,H,W 00000000 00000000 BRPER1 [R/W] B,H,W -------- ----0000 TESTR1[R/W] B,H,W -------- X00000-― IF1CREQ1 [R/W] B,H,W 0------- 00000001 IF1CMSK1 [R/W] B,H,W -------- 00000000 IF1MSK21 [R/W] B,H,W 11-11111 11111111 IF1ARB21 [R/W] B,H,W 00000000 00000000 IF1MCTR1 [R/W] B,H,W 00000000 0---0000 IF1DTA11 [R/W] B,H,W 00000000 00000000 IF1MSK11 [R/W] B,H,W 11111111 11111111 IF1ARB11 [R/W] B,H,W 00000000 00000000 IF1DTB11 [R/W] B,H,W 00000000 00000000 IF1DTB21 [R/W] B,H,W 00000000 00000000 ― IF1DTA21 [R/W] B,H,W 00000000 00000000 002128H, 00212CH Reserved 002130H, 002134H Reserved (IF1 data mirror) 002138H, 00213CH Reserved 002140H 002144H 002148H 00214CH IF2CREQ1 [R/W] B,H,W 0------- 00000001 IF2MSK21 [R/W] B,H,W 11-11111 11111111 IF2ARB21 [R/W] B,H,W 00000000 00000000 IF2MCTR1 [R/W] B,H,W 00000000 0---0000 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL Block CAN1 (32msb) IF2CMSK1 [R/W] B,H,W -------- 00000000 IF2MSK11 [R/W] B,H,W 11111111 11111111 IF2ARB11 [R/W] B,H,W 00000000 00000000 ― 93 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 002150H IF2DTA11 [R/W] B,H,W 00000000 00000000 IF2DTA21 [R/W] B,H,W 00000000 00000000 002154H IF2DTB11 [R/W] B,H,W 00000000 00000000 IF2DTB21 [R/W] B,H,W 00000000 00000000 002158H, 00215CH Reserved 002160H, 002164H 002168H to 00217CH Reserved (IF2 data mirror) Reserved 002180H TREQR21 [R] B,H,W 00000000 00000000 TREQR11 [R] B,H,W 00000000 00000000 002184H 002188H 00218CH ― ― ― ― ― ― 002190H NEWDT21 [R] B,H,W 00000000 00000000 NEWDT11 [R] B,H,W 00000000 00000000 002194H 002198H 00219CH ― ― ― ― ― ― 0021A0H INTPND21 [R] B,H,W 00000000 00000000 INTPND11 [R] B,H,W 00000000 00000000 0021A4H 0021A8H 0021ACH ― ― ― ― ― ― 0021B0H MSGVAL21 [R] B,H,W 00000000 00000000 MSGVAL11 [R] B,H,W 00000000 00000000 0021B4H 0021B8H 0021BCH ― ― ― ― ― ― 0021C0H to 0021FCH 94 CONFIDENTIAL Block CAN1 (32msb) Reserved MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 Address offset value / Register name +1 +2 +3 002200H CTRLR2 [R/W] B,H,W -------- 000-0001 STATR2[R/W] B,H,W -------- 00000000 002204H ERRCNT2[R] B,H,W 00000000 00000000 BTR2[R/W] B,H,W -0100011 00000001 002208H INTR2[R] B,H,W 00000000 00000000 TESTR2[R/W] B,H,W -------- X00000-- 00220CH BRPER2 [R/W] B,H,W -------- ----0000 ― 002210H IF1CREQ2[R/W] B,H,W 0------- 00000001 IF1CMSK2[R/W] B,H,W -------- 00000000 002214H IF1MSK22 [R/W] B,H,W 11-11111 11111111 IF1MSK12[R/W] B,H,W 11111111 11111111 002218H IF1ARB22 [R/W] B,H,W 00000000 00000000 IF1ARB12[R/W] B,H,W 00000000 00000000 00221CH IF1MCTR2[R/W] B,H,W 00000000 0---0000 ― 002220H IF1DTA12 [R/W] B,H,W 00000000 00000000 IF1DTA22[R/W] B,H,W 00000000 00000000 002224H IF1DTB12 [R/W] B,H,W 00000000 00000000 IF1DTB22[R/W] B,H,W 00000000 00000000 002228H, 00222CH Reserved 002230H, 002234H Reserved (IF1 data mirror) 002238H, 00223CH Reserved 002240H IF2CREQ2[R/W] B,H,W 0------- 00000001 IF2CMSK2[R/W] B,H,W -------- 00000000 002244H IF2MSK22 [R/W] B,H,W 11-11111 11111111 IF2MSK12[R/W] B,H,W 11111111 11111111 002248H IF2ARB22[R/W] B,H,W 00000000 00000000 IF2ARB12[R/W] B,H,W 00000000 00000000 00224CH IF2MCTR2[R/W] B,H,W 00000000 0---0000 ― 002250H IF2DTA12[R/W] B,H,W 00000000 00000000 IF2DTA22[R/W] B,H,W 00000000 00000000 002254H IF2DTB12[R/W] B,H,W 00000000 00000000 IF2DTB22[R/W] B,H,W 00000000 00000000 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL Block CAN2 (32msb) 95 D a t a S h e e t Address Address offset value / Register name +1 +2 +0 002258H, 00225CH 002260H, 002264H 002268H to 00227CH +3 Reserved Reserved (IF2 data mirror) Reserved 002280H TREQR22[R] B,H,W 00000000 00000000 TREQR12[R] B,H,W 00000000 00000000 002284H 002288H 00228CH ― ― ― ― ― ― 002290H NEWDT22[R] B,H,W 00000000 00000000 NEWDT12[R] B,H,W 00000000 00000000 002294H 002298H 00229CH ― ― ― ― ― ― 0022A0H INTPND22[R] B,H,W 00000000 00000000 INTPND12[R] B,H,W 00000000 00000000 0022A4H 0022A8H 0022ACH ― ― ― ― ― ― 0022B0H MSGVAL22[R] B,H,W 00000000 00000000 MSGVAL12[R] B,H,W 00000000 00000000 0022B4H 0022B8H ― ― ― ― 0022BCH ― ― 0022C0H to 0022FCH Block ― ― DFCTLR[R/W] B,H,W -0------ -------- 002300H CAN2 (32msb) ― ― Reserved ― DFSTR[R/W] B,H,W -----001 WorkFlash 002304H ― ― ― ― 002308H FLIFCTLR [R/W] B,H,W ---0--00 ― FLIFFER1 [R/W] B,H,W -------- FLIFFER2 [R/W] B,H,W -------- Flash/ WorkFlash 00230CH to 0023FCH ― ― ― ― Reserved 002400H SEEARX[R] B,H,W --000000 00000000 -0000000 00000000*4 002404H 002408H 96 CONFIDENTIAL EECSRX[R/W] B,H,W ----0000 ― ― DEEARX[R] B,H,W --000000 00000000 -0000000 00000000*4 EFEARX [R/W] B,H,W --000000 00000000 -0000000 00000000*4 EFECRX [R/W] B,H,W -------0 00000000 00000000 XBS RAM ECC control register *4: MB91F578/9 only MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Address +0 00240CH to 002FFCH ― ― ― SEEARA[R] B,H,W -----000 00000000 ----0000 00000000*4 003000H 003004H Address offset value / Register name +1 +2 EECSRA[R/W] B,H,W ----0000 00300CH to 003FFCH ― ― ― 004000H to 007FFCH ― DEEARA[R] B,H,W -----000 00000000 ----0000 00000000*4 EFEARA[R/W] B,H,W -----000 00000000 ----0000 00000000*4 EFECRA [R/W] B,H,W -------0 00000000 00000000 ― 003008H +3 ― ― Block Reserved Backup RAM ECC control register *4: MB91F578/9 only Reserved Backup RAM area Backup-RAM*5 008000H to 00FEFCH ― ― ― ― Reserved (00F000H to[S]) 00FF00H DSUCR [R/W] B,H,W -------- -------0 ― ― OCDU [S] 00FF04H to 00FF0CH ― ― ― Reserved [S] ― 00FF10H PCSR [R/W] B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00FF14H PSSR [R/W] B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCDU [S] 00FF18H to 00FFF4H 00FFF8H 00FFFCH ― ― ― ― Reserved [S] EDIR1 [R] B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCDU [S] EDIR0 [R] B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX [S] : It is a system register. The illegal instruction exception (data access error) is generated when read/write is performed on these registers in the user mode. *3: The initial value is different by part number. For details, refer to the CSVCR register in chapter “Clock Supervisor” *4: MB91F578/9 only *5: See the maximum size of series on the memory map June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 97 D a t a S h e e t INTERRUPT VECTOR TABLE This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers. Interrupt Vector Interrupt factor Interrupt number Interrupt level Offset Default address for TBR RN *1 Deci mal Hexadecimal Reset 0 00 - 3FCH 000FFFFCH - System reserved 1 01 - 3F8H 000FFFF8H - System reserved 2 02 - 3F4H 000FFFF4H - System reserved 3 03 - 3F0H 000FFFF0H - System reserved 4 04 - 3ECH 000FFFECH - FPU exception 5 05 - 3E8H 000FFFE8H - Exception of instruction access protection violation 6 06 - 3E4H 000FFFE4H - Exception of data access protection violation 7 07 - 3E0H 000FFFE0H - Data access error interrupt 8 08 - 3DCH 000FFFDCH - INTE instruction 9 09 - 3D8H 000FFFD8H - Instruction break 10 0A - 3D4H 000FFFD4H - System Reserved 11 0B - 3D0H 000FFFD0H - System Reserved 12 0C - 3CCH 000FFFCCH - System Reserved 13 0D - 3C8H 000FFFC8H - Exception of illegal instruction 14 0E - 3C4H 000FFFC4H - NMI request/ XBS RAM double-bit error detection/ Backup RAM double-bit error detection 15 0F 15 (FH) Fixed 3C0H 000FFFC0H - External interrupt 0-7 16 10 ICR00 3BCH 000FFFBCH 0 External interrupt 8-15 17 11 ICR01 3B8H 000FFFB8H 1 Reload timer 0/1/4/5 18 12 ICR02 3B4H 000FFFB4H 2(*2) Reload timer 2/3/6 19 13 ICR03 3B0H 000FFFB0H 3(*2) Multi-function serial interface ch.0 (reception completed)/ Multi-function serial interface ch.0 (status) 20 14 ICR04 3ACH 000FFFACH 4 (*3) Multi-function serial interface ch.0 (transmission completed) 21 15 ICR05 3A8H 000FFFA8H 5 Multi-function serial interface ch.1 (reception completed)/ Multi-function serial interface ch.1 (status) 22 16 ICR06 3A4H 000FFFA4H 6 (*3) Multi-function serial interface ch.1 (transmission completed) 23 17 ICR07 3A0H 000FFFA0H 7 LIN-UART2 (reception completed) 24 18 ICR08 39C H 000FFF9CH 8 LIN-UART2 (transmission completed) 25 19 ICR09 398H 000FFF98H 9 LIN-UART3 (reception completed) 26 1A ICR10 394H 000FFF94H 10 LIN-UART3 (transmission completed) 27 1B ICR11 390H 000FFF90H 11 LIN-UART4 (reception completed) 28 1C ICR12 38CH 000FFF8CH 12 98 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Interrupt factor Interrupt number Interrupt level Offset Default address for TBR RN *1 Deci mal Hexadecimal LIN-UART4 (transmission completed) 29 1D ICR13 388H 000FFF88H 13 LIN-UART5 (reception completed) 30 1E ICR14 384H 000FFF84H 14 LIN-UART5 (transmission completed) 31 1F ICR15 380H 000FFF80H 15 LIN-UART6 (reception completed) 32 20 ICR16 37CH 000FFF7CH 16 LIN-UART6 (transmission completed) 33 21 ICR17 378H 000FFF78H 17 CAN0 34 22 ICR18 374H 000FFF74H - CAN1 35 23 ICR19 370H 000FFF70H - CAN2/ Up/down counter 0/ Up/down counter 1 36 24 ICR20 36CH 000FFF6CH - Real time clock 37 25 ICR21 368H 000FFF68H - Sound generator 0 / LIN-UART7 (reception completed) 38 26 ICR22 364H 000FFF64H 22 Sound generator 1 / LIN-UART7 (transmission completed) 39 27 ICR23 360H 000FFF60H 23 PPG0/1/10/11/20/21 40 28 ICR24 35CH 000FFF5CH 24 PPG2/3/12/13/22/23 41 29 ICR25 358H 000FFF58H 25 PPG4/5/14/15 42 2A ICR26 354H 000FFF54H 26 PPG6/7/16/17 43 2B ICR27 350H 000FFF50H 27 PPG8/9/18/19 44 2C ICR28 34CH 000FFF4CH 28 Multi-function serial interface ch.8 (reception completed)/ Multi-function serial interface ch.8 (status) / HS_SPI reception interrupt request 45 2D ICR29 348H 000FFF48H 29 (*4) Main timer/Sub timer/PLL timer / Multi-function serial interface ch.8(transmission completed)/ HS_SPI transmission interrupt request 46 2E ICR30 344H 000FFF44H 30 (*4) Clock calibration unit (Sub oscillation) / Sound generator 4/ Multi-function serial interface ch.9 (reception completed) / Multi-function serial interface ch.9 (status) 47 2F ICR31 340H 000FFF40H 31 (*5) A/D converter 48 30 ICR32 33CH 000FFF3CH 32 Clock calibration Unit (CR oscillation) / Multi-function serial interface ch.9 (transmission completed) 49 31 ICR33 338H 000FFF38H 33 (*5) Free-run timer 0/2/4 50 32 ICR34 334H 000FFF34H - Free-run timer 1/3/5 51 33 ICR35 330H 000FFF30H - ICU0/6 (fetching) 52 34 ICR36 32CH 000FFF2CH 36 ICU1/7 (fetching) 53 35 ICR37 328H 000FFF28H 37 ICU2/8 (fetching) 54 36 ICR38 324H 000FFF24H 38 ICU3/9 (fetching) 55 37 ICR39 320H 000FFF20H 39 ICU4/10 (fetching) 56 38 ICR40 31CH 000FFF1CH 40 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 99 D a t a S h e e t Interrupt factor Interrupt number Interrupt level Offset Default address for TBR RN *1 Deci mal Hexadecimal ICU5/11 (fetching) 57 39 ICR41 318H 000FFF18H 41 OCU0/1/6/7/10/11 (match) 58 3A ICR42 314H 000FFF14H 42 OCU2/3/4/5/8/9 (match) 59 3B ICR43 310H 000FFF10H 43 Base timer 0 IRQ0 / Base timer 0 IRQ1 / Sound generator 2 60 3C ICR44 30CH 000FFF0CH 44 Base timer 1 IRQ0 / Base timer 1 IRQ1 / Sound generator 3 / XBS RAM single bit error generation / Backup RAM single bit error generation 61 3D ICR45 308H 000FFF08H 45 (*6) DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3E ICR46 304H 000FFF04H - Delayed interrupt 63 3F ICR47 300H 000FFF00H - System reserved (Used for REALOSTM*7.) 64 40 - 2FCH 000FFEFCH - System reserved (Used for REALOS.) 65 41 - 2F8H 000FFEF8H - Used with the INT instruction. 66 | 255 42 | FF - 2F4H | 000H 000FFEF4H | 000FFC00H - *1: It does not support the DMA transfer request by the interrupt generated from a peripheral to which no RN (Resource Number) is assigned. *2: Reload timer ch.4 to ch.6 does not support the DMA transfer by the interrupt. *3: The status of the multi-function serial interface does not support the DMA transfer by I 2C reception. *4: HS_SPI does not support the DMA transfer by the interrupt. *5: The clock calibration unit does not support the DMA transfer by the interrupt. *6: It does not support the DMA transfer by the interrupt because of the RAM ECC bit error. *7: REALOS is the trademark of Spansion LLC. 100 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Power supply voltage*1,*2 Analog power supply voltage*1,*2 Analog reference voltage* 1 Rating Min Max Unit VCC5 DVCC VCCE VSS-0.3 VSS-0.3 VSS-0.3 VSS+6.0 VSS+6.0 VSS+6.0 V V V AVCC VSS-0.3 VSS+6.0 V Remarks DVCC ≤ VCC5 VCCE ≤ VCC5 AVRH ≤ AVCC ≤ VCC5 AVRH ≤ AVCC AVRH VSS-0.3 VSS+6.0 V VI1 VSS-0.3 VCC5+0.3 V Input voltage*1 VI2 VSS-0.3 VCC5+0.3 V SMC shared pin VIE VSS-0.3 VCC5+0.3 V Analog pin input voltage*1 VIA5 VSS-0.3 VCC5+0.3 V VO1 VSS-0.3 VCC5+0.3 V Output voltage*1 VO2 VSS-0.3 VCC5+0.3 V SMC shared pin VOE VSS-0.3 VCC5+0.3 V Maximum clamp current ICLAMP -4 4 mA *8 Total maximum clamp current Σ|ICLAMP | 20 mA *8 – I 7 mA 2mA is selected*6 – OL1 "L" level maximum output current *3 IOL2 40 mA 30mA is selected *7 – IOLAV1 2 mA 2mA is selected *6 – "L" level average output current *4 IOLAV2 30 mA 30mA is selected *7 – ΣIOL1 50 mA *6 – "L" level total output current*5 ΣIOL2 250 mA *7 – 3 IOH1 * -7 mA 2mA is selected*6 – "H" level maximum output current*3 3 IOH2 * -40 mA 30mA is selected *7 – 4 IOHAV1 * -2 mA 2mA is selected *6 – "H" level average output current*4 IOHAV2 *4 -30 mA 30mA is selected *7 – ΣIOH1 -50 mA *6 – "H" level total output current*5 ΣIOH2 -250 mA *7 – Power consumption PD 710 mW – Operating temperature TA -40 +105 °C Storage temperature Tstg -55 +150 °C *1: This parameter is based on VSS=AVSS=DVSS=0.0V. *2: Caution must be taken that AVCC, DVCC, and VCCE do not exceed VCC5 upon power-on and under other circumstances. *3: Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4: Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio. *5: The total output current is defined as the maximum current value flowing through all of corresponding pins. *6: Outputs other than P60-P87 pins *7: Output of P60-P87 pins June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 101 D a t a S h e e t *8: • Corresponding pins: all general-purpose ports. (Except P010 to P017, P020 to P027, P030 to P037, P040 to P047, P050 to P053, P90/ADTG/PPG0_2) • Use within recommended operating conditions. • Use at DC voltage (current). • The + B signal should always be applied by connecting a limiting resistor between the + B signal and the microcontroller. • The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input. • Note that when the microcontroller drive current is low, such as in the low power consumption modes, the + B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. • Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the pin, the microcontroller may operate incompletely. • Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. • Do not leave + B input pins open. Sample recommended circuit MB91570 series Protective diode Limiting resistor current +Binput (12 to 16V) <WARNING> Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. 102 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t 2. Recommended operating conditions (VSS=DVSS=AVSS=0.0V) Parameter Power supply voltage Smoothing capacitor * Symbol VCC5 DVCC AVCC5 VCCE VCC5 DVCC AVCC5 VCCE Value Min Max 4.5 4.5 4.5 3.0 3.5 3.5 3.5 2.7 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 CS Unit V V V V V V V V 4.7 (tolerance within±50%) μF Remarks Recommended operation guarantee range Operation guarantee range Use a ceramic capacitor or a capacitor that has the similar frequency characteristics. Use a capacitor with a capacitance greater than CS as the smoothing capacitor on the VCC pin. Operating TA -40 +105 °C temperature *: Refer to the following diagram for details on the connection of smoothing capacitor CS. C Pin Connection Diagram C CS VSS DVSS AVSS <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 103 D a t a S h e e t 3. DC characteristics (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=DVSS=AVSS=0.0V) Value Parameter Symbol Pin name VIH1 VIH2 P010 to P017, P020 to P027, P030 to P036 VIH3 VIH4 VIH5 “H” level input voltage VIH6 VIH7 VIH8 P000 to P007, P037, P040 to P047, P050 to P057, P060 to P067, P070 to P077, P080 to P087, P090 to P097, P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to P197*1 Condition Unit Remarks Min Typ Max 0.7×VCCE – VCC5 +0.3 V * 0.7×VCCE – VCC5 +0.3 V * 0.8×VCCE – VCC5 +0.3 V * 2.0 – VCC5 +0.3 V * 0.7×VCC5 – VCC5 +0.3 V 0.7×VCC5 – VCC5 +0.3 V 0.8×VCC5 – VCC5 +0.3 V TTL input level is selected 2.0 – VCC5 +0.3 V VCC5 +0.3 VCC5 +0.3 VCC5 +0.3 CMOS input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS input level is selected CMOS hysteresis input level is selected Automotive input level is selected VIH9 RSTX, NMIX, MD2 – 0.7×VCC5 – VIH10 MD0, MD1 – 0.7×VCC5 – VIH11 DEBUGIF – 2.0 – V V V * : VCCE=5.0V±10%, or VCCE=3.0 to 3.6V *1: MB91F578/9 only supports P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to P197. 104 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (TA: Recommended operating conditions, VCC5=5.0 V±10%, VCCE=5.0 V±10%, VSS=DVSS=AVSS=0.0V) Value Parameter Symbol Pin name VIL1 VIL2 P010 to P017, P020 to P027, P030 to P036 VIL3 VIL4 VIL5 “L” level input voltage VIL6 VIL7 VIL8 P000 to P007, P037, P040 to P047, P050 to P057, P060 to P067, P070 to P077, P080 to P087, P090 to P097, P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to P197*1 Condition CMOS input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected VIL9 RSTX, NMIX, MD2 – VIL10 MD0, MD1 – VIL11 DEBUGIF – Unit Remarks Min Typ Max VSS -0.3 – 0.3×VCCE V * VSS -0.3 – 0.3×VCCE V * VSS -0.3 – 0.5×VCCE V * VSS -0.3 – 0.8 V * VSS -0.3 – 0.3×VCC5 V VSS -0.3 – 0.3×VCC5 V VSS -0.3 – 0.5×VCC5 V VSS -0.3 – 0.8 V VSS -0.3 VSS -0.3 VSS -0.3 – 0.3×VCC5 V – 0.3×VCC5 V – 0.8 V *: VCCE=5.0V±10%, or VCCE=3.0 to 3.6V *1: MB91F578/9 only supports P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to P197. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 105 D a t a S h e e t (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=DVSS=AVSS=0.0V) Value Parameter Symbol Pin name VOH1 VOH2 VOH3 P010 to P017, P020 to P027, P030 to P036 Condition Unit Remarks Min Typ Max VCCE = 3.0V IOH = -0.5mA VCCE -0.5 – VCCE V * VCCE = 3.0V IOH = -1.0mA VCCE = 3.0V IOH = -2.0mA VCCE -0.5 VCCE -0.5 – VCCE V * – VCCE V * P000 to P007, VCC5 = 4.5V VCC5 P037, VOH4 VCC5 V – I = -1.0mA -0.5 OH P040 to P047, P050 to P056, P060 to P067, P070 to P077, “H” level P080 to P087, output P090 to P097, voltage P100 to P107, P110 to P117, VCC5 = 4.5V VCC5 P120 to P127, VOH5 VCC5 V – I = -2.0mA -0.5 OH P130 to P137, P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to P197*1 P060 to P067, DVCC = 4.5V DVCC SMC VOH6 P070 to P077, DVCC V – IOH = -30.0mA -0.5 shared pin P080 to P087 * : VCCE=5.0V±10%, or VCCE=3.0 to 3.6V *1: MB91F578/9 only supports P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to P197. 106 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=DVSS=AVSS=0.0V) Value Parameter Symbol Pin name VOL1 VOL2 P010 to P017, P020 to P027, P030 to P036 VOL3 VOL4 “L” level output voltage VOL5 VOL6 P000 to P007, P037, P040 to P047, P050 to P056, P060 to P067, P070 to P077, P080 to P087, P090 to P097, P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to P197*1 P060 to P067, P070 to P077, P080 to P087 Condition Unit Remarks Min Typ Max 0 – 0.4 V * 0 – 0.4 V * 0 – 0.4 V * 0 – 0.4 V VCC5 = 4.5V IOL = 2.0mA 0 – 0.4 V DVCC = 4.5V IOL = 30.0mA 0 – 0.55 V SMC shared pin I2C shared pin (I2C is selected) VCCE = 3.0V IOL = 0.5mA VCCE = 3.0V IOL = 1.0mA VCCE = 3.0V IOL = 2.0mA VCC5 = 4.5V IOL = 1.0mA VOL7 P127, P130, P132, P133 VCC5 = 4.5V IOL = 3.0mA 0 – 0.4 V VOL8 DEBUGIF VCC5 = 2.7V IOL = 25.0mA 0 – 0.25 V * : VCCE=5.0V±10%, or VCCE=3.0 to 3.6V *1: MB91F578/9 only supports P140 to P147, P150 to P157, P160 to P167, P170 to P177, P180 to P187, P190 to P197. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 107 D a t a S h e e t (TA: Recommended operating conditions, VCC5=5.0V±10%,VCCE=5.0V±10%,VSS=DVSS=AVSS=0.0V) Re Value Parameter Symbol Pin name Condition Unit mar Min Typ Max ks Port input pins VCC5=VCCE= IIL1 other than -5 +5 μA – Input leak DVCC=AVCC= P107,123 current 5.5V P107,P123 VSS<VI<VCC IIL2 -10 +10 μA – (DA shared pin) RUP1 RSTX, NMIX 25 100 kΩ – – Pull-up Pull-up resistance resistance RUP2 All port input pins 25 100 kΩ – is selected RDOWN1 MD2 25 100 kΩ – – Pull-down Pull-down resistance RDOWN2 All port input pins resistance is 25 100 kΩ – selected Other than VCCE, VCC5, VSS, DVCC, DVSS, CIN1 AVCC, AVSS, C, 5 15 pF – – P060 to P067, Input P070 to P077, capacitance P080 to P087 P060 to P067, CIN2 P070 to P077, When using SMC 15 45 pF – P080 to P087 108 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (TA: Recommended operating conditions, VCC5=5.0V±10%,VCCE=5.0V±10%,VSS=DVSS=AVSS=0.0V) Parameter Symbol Value Pin name Condition At normal operation Operating frequency FCP=80MHz, Fcpp=40MHz ICC5 ICCS5 Power supply current VCC5 ICCBS5 – – At FLASH erase Operating frequency FCP=80MHz, Fcpp=40MHz – At sleep mode Operating frequency FCP=80MHz, Fcpp=40MHz – At bus sleep mode Operating frequency FCP=80MHz, Fcpp=40MHz Typ *4 60 mA 125 *5 115 *3, *4 75 mA 140 *3, *5 115 75 *3, *4 mA 140 *3, *5 *4 60 – Remarks Max 100 FLASH write Operating frequency FCP=80MHz, Fcpp=40MHz 20 mA 75 *5 55 *4 15 mA *5 70 – 750 1400 μA When using external clock*1, TA=25˚C – 900 1550 μA When using crystal, TA=25˚C At RTC mode shutdown 4MHz source oscillation – 170 330 μA When using external clock*1, TA=25˚C – 320 480 μA When using crystal, TA=25˚C ICCH5 At stop mode – 400 1200 μA TA=25˚C ICCHS5 At stop mode shutdown – 120 240 μA TA=25˚C ICCT5 ICCTS5 June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL Unit Min At RTC mode 4MHz source oscillation 109 D a t a S h e e t (TA: Recommended operating conditions, VCC5=5.0V±10%,VCCE=5.0V±10%,VSS=DVSS=AVSS=0.0V) Value Parameter Symbol Pin name Condition Unit Min Typ Max Rem arks High current output drive capacity Phase-to-phase deviation1 High current output drive capacity Phase-to-phase deviation2 PWM1Pn, DVCC =4.5V PWM1Mn, IOH=-30.0mA ΔVOH6 PWM2Pn, 90 mV *2 – – Maximum PWM2Mn deviation of VOH6 (n=0 to 5) PWM1Pn, DVCC =4.5V PWM1Mn, IOL=30.0mA ΔVOL6 PWM2Pn, 90 mV *2 – – Maximum PWM2Mn deviation of VOL6 (n=0 to 5) V0 to V1, LCD divider RLCD V1 to V2, 6.25 12.5 25 kΩ – resistor V2 to V3 COM0 to COM3 COMm RVCOM 4.5 kΩ – – – output impedance (m=0 to 3) SEG00 to SEG31 SEGn RVSEG 17 kΩ – – – output impedance (n=00 to 31) V0 to V3, COMm LCDC leak ILCDC (m=0 to 3), TA=+25˚C -0.5 +0.5 μA – current SEGn (n=00 to 31) *1: The power supply current value when the external clock is supplied from the X1 pin. Note that the power supply current value when using the external clock is different from that using the oscillator. *2: If PWM1P0/PWM1M0/PWM2P0/PWM2M0 of ch.0 is turned on simultaneously, the maximum deviation of VOH6 / VOL6 for each pin is defined. Same for other channels. *3: This product contains both program flash and WorkFlash. This parameter is defined when only one of them is in the write/erase state. *4: MB91F575/7 *5: MB91F578/9 110 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t 4. AC Characteristics (1) Main Clock Timing (TA: Recommended operating conditions, VCC5 =5.0V±10%, VSS=DVSS=AVSS=0.0V) Parameter Source oscillation clock frequency Source oscillation clock cycle time Internal operating clock cycle time* Internal operating clock cycle time* Symbol Value Pin Condi Unit name tions Min Typ Max FC X0,X1 – – 4 – MHz tCYL X0,X1 – – 250 – ns FCP FCPP FCPT tCP tCPP tCPT – – – – – – – – – – – – 2 2 2 – – – – – – 80 40 40 MHz MHz MHz ns ns ns 12.5 25 25 500 500 500 Remarks CPU clock Peripheral bus clock External bus clock CPU clock Peripheral bus clock External bus clock FCP=80MHz (4MHz×Multiplied by 20) CAN PLL jitter tPJ -10 +10 ns – – – (when lock) Built-in CR oscillation FCCR 50 100 200 kHz – – frequency *: The maximum / minimum value is defined when using the main clock and PLL clock. X0,X1 clock timing tCYL X0 CAN PLL jitter Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 111 D a t a S h e e t (1-2) Sub clock timing (products without s-suffix) (TA: Recommended operating conditions, VCC=5.0V±10%,VSS=DVSS=AVSS=0.0V) Parameter Symbol Pin name FCL X0A,X1A tLCYL X0A,X1A Source oscillation clock frequency Source oscillation clock cycle time Conditions – Value Min Typ Max Unit – 32.768 – kHz – 30.52 – µs Remarks X0A,X1A clock timing tLCYL X0A 112 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Guaranteed operation range Internal operation clock frequency vs. Power supply voltage Note: The CPU will be reset at the power supply voltage 4V±0.3V or less. Oscillation clock frequency vs. Internal operation clock frequency Internal operation clock frequency PLL clock Main Multipli Multipli Multipli Multipli Multipli Multipli Clock ... ed by ed by ed by 1 ed by 2 ed by 3 ed by 4 19 20 Oscillation clock frequency 4MHz 2MHz 4MHz 8MHz 12MHz 16MHz ... 76MHz 80MHz Example of oscillation circuit X0 X1 0 4MHz C1=10pF R=0 C2=10pF Note: As to the product with its clock supervisor’s initial value is ”ON”, when the oscillator is unable to start within 20ms from the stop state the clock supervisor will detect the oscillation stop. As a result, the CPU moves to the fail safe operation. Design your printed circuit board so that the oscillator can start oscillation within 20ms. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 113 D a t a S h e e t AC characteristics are specified by the following measurement reference voltage values. Input Signal Waveform Output Signal Waveform Hysteresis Input Pin (Automotive) Output Pin 0.8Vcc 2.4V 0.5Vcc 0.8V Hysteresis Input Pin (CMOS Normal) 0.7Vcc 0.3Vcc Hysteresis Input Pin (CMOS Hysteresis) 0.7Vcc 0.3Vcc TTL Input Pin 2.0V 0.8V 114 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (2) Reset Input (TA: Recommended operating conditions, VCC5 =5.0V±10%, VSS=AVSS=0.0V) Con Sym Pin ditio bol name ns Parameter Reset input time tRSTL RSTX – Value Unit Remarks Min Max 10 – µs Under normal operation Oscillation time of oscillator* +100µs 100µs – ms In Stop mode µs In RTC mode – Width for reset 1µs µs – input removal *: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is between several hundred μs and several ms, and for an external clock, the time is 0 ms. t RSTL, RSTX 0.2Vcc5 0.2Vcc5 In Stop mode tRSTL RSTX 0.2 VCC5 0.2 VCC5 90% of amplitude X0 Internal operation clock 100 μs Oscillation time of oscillator Internal reset June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL Oscillation stabilization waiting time Instruction execution 115 D a t a S h e e t (3) Power-on Conditions (TA: Recommended operating conditions, VSS=0.0V) Symbol Pin name Conditions Level detection voltage – VCC5 Level detection hysteresis width Level detection time – VCC5 – – Parameter Value Unit Min Typ Max – 2.1 2.3 2.5 V – – – 125 mV Remarks When turning on power for microcontroller During voltage drop *1 – – – 30 us VCC5 = at level Slope detection – VCC5 detection release – – 4 mV/µs *2 undetected standard level time Power off time tOFF VCC5 – 50 – – ms *3 *1: If the fluctuation of the power supply is faster than the low voltage detection time, there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope detection. This is the standard when the power supply fluctuation is stable. *3: This time is to start the slope detection at next power on after power down and internal charge loss 116 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (4) Multi-function Serial (4-1) UART timing Bit setting: SMR:MD2=0,SMR:MD1=1,SMR:MD0=0,SMR:SCINV=0,SCR:SPI=0 (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Parameter Serial clock cycle time SCK ↓→ SOT delay time Valid SIN→ SCK ↑ setup time SCK ↑→ Valid SIN hold time Serial clock "H" pulse width Con Pin name ditio ns Sym bol Valid SIN→ SCK ↑setup time SCK ↑→ Valid SIN hold time Min Max Unit tSCYC SCK0, SCK1, SCK8, SCK9 4tCPP – ns tSLOVI SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 -30 +30 ns 34 – ns 0 – ns tCPP+10 – ns 2tCPP-10 – ns – 33 ns 10 – ns 20 – ns – tIVSHI SCK0, SCK1, SCK8, SCK9, SIN0, SIN1, tSHIXI SIN8, SIN9 tSHSL SCK0, SCK1, SCK8, SCK9 Serial clock "L" pulse width tSLSH SCK ↓→ SOT delay time Value tSLOVE SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 tIVSHE SCK0, SCK1, SCK8, SCK9, SIN0, SIN1, tSHIXE SIN8, SIN9 – SCK fall time tF SCK0, SCK1, SCK8, SCK9 – 5 ns SCK rise time tR SCK0, SCK1, SCK8, SCK9 – 5 ns Remarks Internal shift clock mode: CL=50pF(When drive capability is 2mA or more.) CL=20pF(When drive capability is 1mA) External shift clock mode: CL=50pF(When drive capability is 2mA or more.) CL=20pF(When drive capability is 1mA) Notes: AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operation clock used and other parameters. Refer to Hardware Manual for details. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 117 D a t a S h e e t • Internal shift clock mode tSCYC 2.4V SCKx 0.8V 0.8V tSLOVI 2.4V SOTx 0.8V tIVSHI SINx tSHIXI VIH VIH VIL VIL • External shift clock mode tSLSH SCKx VIH VIH VIL tF SOTx tSHSL VIL tSLOVE 118 CONFIDENTIAL VIL tR 2.4V 0.8V tIVSHE SINx VIH tSHIXE VIH VIH VIL VIL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Bit setting: SMR:MD2=0,SMR:MD1=1,SMR:MD0=0,SMR:SCINV=1,SCR:SPI=0 (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Parameter Serial clock cycle time SCK ↑ → SOT delay time Valid SIN→ SCK ↓setup time SCK ↓ → Valid SIN hold time Serial clock "H" pulse width Sym bol Pin name tSCYC tSHOVI Con ditio ns Max SCK0, SCK1, SCK8, SCK9 4tCPP – ns SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 -30 +30 ns 34 – ns 0 – ns tCPP+10 – ns 2tCPP-10 – ns – 33 ns 10 – ns 20 – ns – SCK0, SCK1, SCK8, SCK9 Serial clock "L"pulse width tSLSH SCK ↑ → SOT delay time Valid SIN→ SCK ↓setup time SCK ↓ → Valid SIN hold time tSHOVE Unit Min tIVSLI SCK0, SCK1, SCK8, SCK9, SIN0, SIN1, tSLIXI SIN8, SIN9 tSHSL Value SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 tIVSLE SCK0, SCK1, SCK8, SCK9, SIN0, SIN1, tSLIXE SIN8, SIN9 – SCK fall time tF SCK0, SCK1, SCK8, SCK9 – 5 ns SCK rise time tR SCK0, SCK1, SCK8, SCK9 – 5 ns Remarks Internal shift clock mode: CL=50pF(When drive capability is 2mA or more.) CL=20pF(When drive capability is 1mA) External shift clock mode: CL=50pF(When drive capability is 2mA or more.) CL=20pF(When drive capability is 1mA) Notes: AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operation clock used and other parameters. Refer to Hardware Manual for details. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 119 D a t a S h e e t Internal shift clock mode tSCYC 2.4V 2.4V SCKx 0.8V t SHOVI 2.4V SOTx 0.8V t IVSLI SINx t SLIXI V IH VIH V IL V IL External shift clock mode tS LS H tS H S L VIH VIH SCKx VIL VIL tR SOTx tS HO V E 120 CONFIDENTIAL VIL tF 2 .4 V 0 .8 V tIV SLE S IN x VIH tS LIX E VIH VIH VIL VIL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=0, SCR: SPI=1 (TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK0, SCK1, SCK8, SCK9 SCK↑→SOT delay time tSHOVI Valid SIN→SCK↓ setup time tIVSLI SCK↓→ Valid SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH SCK↑→SOT delay time tSHOVE Valid SIN→SCK↓ setup time tIVSLE SCK↓→ Valid SIN hold time tSLIXE Conditions SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 Internal shift clock mode CL=50pF(When drive capability is SCK0, SCK1, 2mA or more.) SCK8, SCK9, CL=20pF(When drive capability is SIN0, SIN1, 1mA) SIN8, SIN9 SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 SCK0, SCK1, SCK8, SCK9 SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, External shift clock mode SOT8, SOT9 CL=50pF(When drive capability is 2mA or more.) SCK0, SCK1, C =20pF(When drive capability is SCK8, SCK9, L 1mA) SIN0, SIN1, SIN8, SIN9 Value Unit Min Min 4tCPP – ns -30 +30 ns 34 – ns 0 – ns 2tCPP-30 – ns tCPP+10 – ns 2tCPP-10 – ns – 33 ns 10 – ns 20 – ns SCK fall time tF SCK0, SCK1, SCK8, SCK9 – 5 ns SCK rise time tR SCK0, SCK1, SCK8, SCK9 – 5 ns Notes: AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by internal operation clock used and other parameters. Refer to Hardware Manual for details. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 121 D a t a S h e e t Internal shift clock mode tSCYC 2.4V SCKx tSHOVI 0.8V 0.8V tSOVLI SOTx 2.4V 2.4V 0.8V 0.8V tIVSLI SINx tSLIXI VIH VIH VIL VIL External shift clock mode tSLSH VIH SCKx VIH VIL VIH VIL tF * SOTx tSHSL VIL tR tSHOVE 2.4V 2.4V 0.8V 0.8V tIVSLE SINx tSLIXE VIH VIH VIL VIL *: Changes when writing to TDR register 122 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=1, SCR: SPI=1 (TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK0, SCK1, SCK8, SCK9 SCK↓→SOT delay time tSLOVI Valid SIN→SCK↑ setup time tIVSHI SCK↑→ Valid SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock "H"pulse width tSHSL Serial clock "L" pulse width tSLSH SCK↓→SOT delay time tSLOVE Valid SIN→SCK↑ setup time tIVSHE SCK↑→ Valid SIN hold time tSHIXE Conditions SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 Internal shift clock mode CL=50pF (When drive capability SCK0, SCK1, is 2mA or more.) SCK8, SCK9, CL=20pF (When drive capability SIN0, SIN1, is 1mA) SIN8, SIN9 SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 SCK0, SCK1, SCK8, SCK9 SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, External shift clock mode SOT8, SOT9 CL=50pF (When drive capability is 2mA or more.) SCK0, SCK1, C =20pF (When drive capability SCK8, SCK9, L is 1mA) SIN0, SIN1, SIN8, SIN9 Value Unit Min Min 4tCPP – ns -30 +30 ns 34 – ns 0 – ns 2tCPP-30 – ns tCPP+10 – ns 2tCPP-10 – ns – 33 ns 10 – ns 20 – ns SCK fall time tF SCK0, SCK1, SCK8, SCK9 – 5 ns SCK rise time tR SCK0, SCK1, SCK8, SCK9 – 5 ns Notes: AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by internal operation clock used and other parameters. Refer to Hardware Manual for details. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 123 D a t a S h e e t Internal shift clock mode tSCYC 2.4V SCKx 2.4V 0.8V tSOVHI SOTx tSLOVI 2.4V 2.4V 0.8V 0.8V tIVSHI SINx tSHIXI VIH VIH VIL VIL External shift clock mode tSHSL tSLSH tR tF VIH SCKx VIH VIL VIL tSLOVE * SOTx VIH VIL 2.4V 2.4V 0.8V 0.8V tIVSHE SINx tSHIXE VIH VIH VIL VIL *: Changes when writing to TDR register 124 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (4-2)External clock (EXT = 1): asynchronous only (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Value Parameter Symbol Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH SCK fall time tF SCK rise time tR Pin name SCK0, SCK1, SCK8, SCK9 tR SCK CL=50pF (When drive capability is 2mA or more.) CL=20pF (When drive capability is 1mA) tSHSL VIL June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL Conditions VIH Unit Min Max tCPP+10 - ns tCPP+10 - ns - 5 ns - 5 ns tF tSLSH VIH VIL VIL VIH 125 D a t a S h e e t 2 (4-3) I C timing (TA: Recommended operating conditions, VCC5=5.0V±10%, VSS=AVSS=0.0V) Parameter SCL clock frequency Repeat "start" condition hold time SDA ↓→ SCL ↓ Sym bol fSCL tHDSTA Width of "L" for SCL clock tLOW Width of "H" for SCL clock tHIGH Pin name Conditions SCK0_0, SCK1_0 SOT0_0, SOT1_0 (SDA) SCK0_0,SC K1_0 (SCL) SCK0_0, SCK1_0 (SCL) SCK0_0, SCK1_0 (SCL) SCK0_0, SCK1_0 (SCL) SOT0_0, SOT1_0 (SDA) SCK0_0, SCK1_0 (SCL) SOT0_0, SOT1_0 (SDA) SCK0_0, SCK1_0 (SCL) SOT0_0, SOT1_0 (SDA) SCK0_0, SCK1_0 (SCL) Repeat "start" condition setup time SCL ↑→ SDA ↓ tSUSTA Data hold time SCL ↓→ SDA ↓↑ tHDDAT Data setup time SDA ↓↑→ SCL ↑ tSUDAT "Stop" condition setup time SCL ↑ →SDA ↑ tSUSTO Bus-free time between "stop" condition and "start" condition tBUF – Noise filter tSP – CL = 50 pF (When drive capability is 2mA or more.) CL=20pF (When drive capability is 1mA) R = (VP/IOL) *1 – Standard mode Min Max High-speed Uni Rema mode t rks Min Max 0 100 0 400 kHz 4.0 – 0.6 – µs 4.7 – 1.3 – µs 4.0 – 0.6 – µs 4.7 – 0.6 – µs 0 3.45*2 0 0.9 µs 250*3 – 100 – ns 4.0 – 0.6 – µs 4.7 – 1.3 – µs 2tCPP*4 – 2tCPP*4 – ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. VP shows the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current. *2: The maximum tHDDAT only has to be met if the device does not extend the "L" width(tLOW) of the SCL signal. *3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCPP is the peripheral clock cycle time. Adjust the peripheral bus clock to 8MHz or more when use I2C. 126 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t SDA tSUDAT tSUSTA tBUF tLOW SCL tHDSTA tHDDAT June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL tHIGH tHDSTA tSP tSUSTO 127 D a t a S h e e t (5)LIN-UART timing Bit setting: ESCR:SCES=0,ECCR:SCDE=0 (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%,VSS=AVSS=0.0V) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN→ SCK ↑ setup time SCK ↑ → Valid SIN hold time Serial clock "L" pulse width Serial clock "H" pulse width SCK ↓→ SOT delay time Sym Pin name bol SCK2,SCK3, tSCYC SCK4,SCK5, SCK6,SCK7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, tSLOVI SOT2,SOT3, SOT4,SOT5, SOT6,SOT7 SCK2,SCK3, tIVSHI SCK4,SCK5, SCK6,SCK7, SIN2,SIN3, tSHIXI SIN4,SIN5, SIN6,SIN7 Con ditio ns tSLOVE Valid SIN→ SCK ↑ setup time tIVSHE SCK ↑ → Valid SIN hold time tSHIXE SCK fall time tF SCK rise time tR SCK2,SCK3, SCK4,SCK5, SCK6,SCK7 Unit Min Max 5tCPP – ns -50 +50 ns tCPP+80 – ns 0 – ns 3tCPP-tR – ns tCPP+10 – ns – 2tCPP+60 ns – tSLSH SCK2,SCK3, SCK4,SCK5, tSHSL SCK6,SCK7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, SOT2,SOT3, SOT4,SOT5, SOT6,SOT7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, SIN2,SIN3, SIN4,SIN5, SIN6,SIN7 Value – 30 – ns tCPP+30 – ns – 10 ns – 40 ns Remarks Internal shift clock mode: CL=80pF+1 TTL External shift clock mode: CL=80pF+1 TTL Notes: CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operation clock used and other parameters. Refer to Hardware Manual for details. 128 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Internal shift clock mode t SCYC 2.4V SCKx 0.8V t SLOVI 2.4V SOTx 0.8V t IVSHI SINx t SHIXI V IH V IH V IL V IL External shift clock mode tSLSH tSHSL VIH SCKx VIH VIL tF VIH VIL tR tSLOVE SOTx 2.4V 0.8V tIVSHE SINx June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL tSHIXE VIH VIH VIL VIL 129 D a t a S h e e t Bit setting: ESCR: SCES=1, ECCR: SCDE=0 (TA: Recommended operating conditions,VCC5=5.0V±10%, VCCE=5.0V±10%,VSS=AVSS=0.0V) Parameter Serial clock cycle time SCK ↑→ SOT delay time Valid SIN→ SCK ↓setup time SCK ↓→ Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK ↑→ SOT delay time Sym bol Pin name SCK2,SCK3, tSCYC SCK4,SCK5, SCK6,SCK7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, tSHOVI SOT2,SOT3, SOT4,SOT5, SOT6,SOT7 SCK2,SCK3, tIVSLI SCK4,SCK5, SCK6,SCK7, SIN2,SIN3, tSLIXI SIN4,SIN5, SIN6,SIN7 Con ditio ns tSHOVE Valid SIN → SCK ↓setup time tIVSLE SCK ↓→ Valid SIN hold time tSLIXE SCK fall time tF SCK rise time tR SCK2,SCK3, SCK4,SCK5, SCK6,SCK7 Unit Min Max 5tCPP – ns -50 +50 ns Remarks Internal shift clock mode: CL=80pF+1 TTL – tSHSL SCK2,SCK3, SCK4,SCK5, tSLSH SCK6,SCK7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, SOT2,SOT3, SOT4,SOT5, SOT6,SOT7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, SIN2,SIN3, SIN4,SIN5, SIN6,SIN7 Value tCPP+80 – ns 0 – ns 3tCPP-tR – ns tCPP+10 – ns – 2tCPP+60 ns – 30 – ns tCPP+30 – ns – 10 ns – 40 ns External shift clock mode: CL=80pF+1 TTL Notes: CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operation clock used and other parameters. Refer to Hardware Manual for details. 130 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Internal shift clock mode t SCYC 2.4V SCKx 0.8V t SHOVI 2.4V SOTx 0.8V t IVSLI t SLIXI VIH SINx VIH V IL VIL External shift clock mode tS LS H tS H S L VIH VIH SCKx VIL tR tS HO V E SOTx S IN x June 19, 2015, MB91F577_DS705-00009-3v0-E VIL tF 2 .4 V 0 .8 V tIV SLE CONFIDENTIAL VIH VIL tS LIX E VIH VIH VIL VIL 131 D a t a S h e e t Bit setting: ESCR:SCES=0, ECCR:SCDE=1 (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Parameter Serial clock cycle time SCK ↑→ SOT delay time Valid SIN → SCK ↓setup time SCK ↓→ Valid SIN hold time SOT → SCK ↓ delay time Sym bol Pin name SCK2,SCK3, tSCYC SCK4,SCK5, SCK6,SCK7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, tSHOVI SOT2,SOT3, SOT4,SOT5, SOT6,SOT7 SCK2,SCK3, tIVSLI SCK4,SCK5, SCK6,SCK7, SIN2,SIN3, tSLIXI SIN4,SIN5, SIN6,SIN7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, tSOVLI SOT2,SOT3, SOT4,SOT5, SOT6,SOT7 Con ditio ns – Value Unit Min Max 5tCPP – ns -50 +50 ns tCPP+80 – ns 0 – ns 3tCPP-70 – ns Remarks Internal shift clock mode: CL=80pF+1 TTL Notes: CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operation clock used and other parameters. Refer to Hardware Manual for details. Internal shift clock mode t SCYC 2.4V SCKx 0.8V t SHOVI 0.8V t SOVLI SOTx 2.4V 2.4V 0.8V 0.8V t IVSLI SINx 132 CONFIDENTIAL VIH VIL t SLIXI V IH VIL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Bit setting: ESCR: SCES=1, ECCR: SCDE=1 (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Parameter Sym bol Serial clock cycle time tSCYC SCK ↓→ SOT delay time tSLOVI Valid SIN→ SCK ↑ setup time tIVSHI SCK ↑→ Valid SIN hold time tSHIXI SOT → SCK ↑ delay time tSOVHI Pin name SCK2,SCK3, SCK4,SCK5, SCK6,SCK7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, SOT2,SOT3, SOT4,SOT5, SOT6,SOT7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, SIN2,SIN3, SIN4,SIN5, SIN6,SIN7 SCK2,SCK3, SCK4,SCK5, SCK6,SCK7, SOT2,SOT3, SOT4,SOT5, SOT6,SOT7 Value Conditi ons – Unit Min Max 5tCPP – ns -50 +50 ns tCPP+80 – ns 0 – ns 3tCPP-70 – ns Remarks Internal shift clock Mode: CL=80pF+1 TTL Notes: CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operation clock used and other parameters. Refer to Hardware Manual for details. Internal shift clock mode t SCYC 2.4V SCKx 2.4V 0.8V t SOVHI SOTx 2.4V 2.4V 0.8V 0.8V t IVSHI SINx June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL t SLOVI t SHIXI VIH VIH VIL V IL 133 D a t a S h e e t (6) Timer input timing (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Parameter Input pulse width Symbol Pin name Conditions tTIWH, tTIWL TIN0, TIN1, TIN2, TIN3, ICU0 to ICU11, FRCK0 to FRCK5, TIOA, TIOB, AIN0, BIN0, ZIN0 , AIN1, BIN1, ZIN1 – Value Min Max 4tCPP – Unit ns Timer input timing TINx ICUx FRCKx TIOA,TIOB AINx,BINx,ZINx t TIWH VIH t TIWL VIH VIL VIL (7) Trigger input timing (TA: Recommended operating conditions, VCC5=5.0V±10%, VCCE=5.0V±10%, VSS=AVSS=0.0V) Parameter Input pulse width Symbol Pin name Conditions INT0 to INT15, ADTG, RX0 to RX2 tTRGH, tTRGL – Value Unit Min Max 5tCPP – ns 1 – µs Remarks In stop mode Trigger input timing t TRGH INTx ADTG RXx 134 CONFIDENTIAL V IH t TRGL VIH VIL VIL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (8) NMI input timing (TA: Recommended operating conditions, VCC5 =5.0V±10%, VSS=AVSS=0.0V) Parameter Input pulse width Symbol Pin name Conditions tNMIL NMIX – Value Min Max 4tCPP – Unit ns NMIX input timing t NMIL NMIX VIH VIH VIL June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL VIL 135 D a t a S h e e t (9) Low voltage detection (External low-voltage detection) (TA: Recommended operating conditions, VSS=AVSS=0.0V) Parameter Power supply voltage range Symbol VCC5 Value Pin Conditions Unit name Min Typ Max VCC5 – – – 5.5 Remarks V Detection voltage VDL VCC5 *1 3.9 4.1 4.3 V Hysteresis width VHYS VCC5 – – – 125 mV When power-supply voltage falls and detection level is set initially When power-supply voltage rises Low voltage detection Td – – – – 30 μs time Power supply voltage – VCC5 – -2 – 2 V/ms *2 fluctuation rate *1: If the power supply voltage fluctuates within the time less than the low-voltage detection time (Td), there is a possibility that the low-voltage detection will occur or stop after the power supply voltage passes the detection range. *2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation of the power supply voltage within the limits of the power supply voltage fluctuation rate. 136 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (10) Low voltage detection (Internal low-voltage detection) (TA:Recommended operating conditions, VSS=AVSS=0.0V) Parameter Symbol Value Pin Conditions Unit name Min Typ Max Power supply voltage range VRDP5 – – – 1.3 V Detection voltage VRDL * 0.8 0.9 1.0 V Hysteresis width VRHYS – – – 50 mV VCC Remarks When power-supply voltage falls When power-supply voltage rises Low voltage detection Td – – – – 30 µs time *: If the fluctuation of the power supply is faster than the low voltage detection time (Td), there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 137 D a t a S h e e t (11) High current output slew rate (TA: Recommended operating conditions, DVCC5=AVCC=5.0V±10%, VSS=AVSS=0.0V) Parameter Symbol Pin name Conditions tR2, tF2 P060 to P067, P070 to P077, P080 to P087 – Output rise /fall time Value Min Typ Max 15 – 100 Unit Remarks ns load capacitance 85pF Slew rate output timing VH VL VL t R2 138 CONFIDENTIAL VH VH=VOL2+0.9 × (VOH2-VOL2) VL=VOL2+0.1 × (VOH2-VOL2) t F2 MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (12) Clock output timing (TA: Recommended operating conditions, VCC5=VCCE=AVCC=5.0V±10%, VSS=AVSS=0.0V) Value Sym Conditi Pin name bol ons Min Max Cycle time tCYC SYSCLK tCPT – ns SYSCLK ↑→ SYSCLK ↓ tCHCL SYSCLK (1/2 tCYC) - 7 (1/2 tCYC) + 7 ns SYSCLK ↓→ SYSCLK ↑ tCLCH SYSCLK (1/2 tCYC) - 7 (1/2 tCYC) + 7 ns Parameter – Unit Remark s tCYC tCHCL VOH=VCC/2 SYSCLK June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL VOL=VCC/2 tCLCH VOH 139 D a t a S h e e t (13) External bus I/F (synchronous mode) timing (TA: Recommended operating conditions, VCC5=VCCE =AVCC=5.0V±10%, VSS=AVSS=0.0V) (External load capacitance 50pF) Parameter Cycle time Symbol Pin name tCYC tCHAV, tCHAX tCHRL, tCHRH SYSCLK SYSCLK, ASX SYSCLK, CS0X to CS3X SYSCLK, A00 to A21 SYSCLK, RDX tRLRH RDX tDSRH RDX, D16 to D31 ASX delay time tCHASL, tCHASH CS0X to CS3X delay time tCHCSL, tCHCSH A00 to A21 delay time RDX delay time RDX minimum pulse Data setup → RDX ↑ time RDX ↑→ data hold WRnX delay time WRnX minimum pulse width SYSCLK ↑→ data output time SYSCLK ↑→ data hold time SYSCLK ↑→ address output time tRHDH tCHWL, tCHWH tWLWH tCHDV tCHDX tCHMAV SYSCLK, WR0X, WR1X WR0X, WR1X SYSCLK, D16 to D31 Value Min Max 25 – Unit Remarks ns 0.5 18 ns 0.5 18 ns 0.5 18 ns 0.5 18 ns tCYC× 2 - 20 18 + tCYC 0 – ns – ns – ns 0.5 18 ns tCYC - 10 – ns 0.5 18 ns – 18 ns 0.5 18 ns RWT=1, set RWT to 1 or more. * RWT=1, set RWT to 1 or more. * WWT=0 * Set WRCS to 1 or more. In multiplex mode, set as follows: Set CSWR and CSRD to 2 or more. ASCY must satisfy the following conditions because SYSCLK, of setting ADCY>ASCY and D16 to D31 SYSCLK ↑→ address tCHMAX 18 ns protocol violation – hold time prevention. ADCY + 1 ≤ ACS + CSRD ADCY + 1 ≤ ACS + CSWR ASCY + 1 ≤ ACS + CSRD ASCY + 1 ≤ ACS + CSWR Refer to Hardware Manual for details. *: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated value. 140 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t External bus I/F (synchronous mode, read operation, and multiplex mode) timing t1 t3 t2 t4 tCYC SYSCLK tCHASL tCHASL ASCY=0 ASX tCHCSH tCHASL CS0X to CS3X ACS=0 RDCS=0 tCHRL tCHRH RWT=1 RDX tRLRH CSRD=2 ADCY=1 tCHMAV tCHMAX Read Data Valid Address D16 to D31 tDSRH tRHDH External bus I/F (synchronous mode, read operation, and split mode) timing t1 t3 t2 t4 tCYC SYSCLK tCHASH tCHASL ASCY=0 ASX tCHCSL CS0X to CS3X tCHCSH RDCS=0 ACS=0 tCHRL tCHRH RWT=1 RDX CSRD=0 tRLRH tCHAV A00 to A21 D16 to D31 tCHAX Valid Address Read Data tDSRH June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL tRHDH 141 D a t a S h e e t External bus I/F (synchronous mode, write operation, and multiplex mode) timing t1 t4 t3 t2 tCYC SYSCLK tCHASL tCHASH ASCY=0 ASX tCHCSL CS0X to CS3X tCHCSH WRCS=1 ACS=0 tCHWL WR0X to WR1X tCHMAV D16 to D31 tCHWH tWLWH CSWR=2 WWT=0 ADCY=1 tCHDX tCHDV Write Data Valid Address External bus I/F (synchronous mode, write operation, and split mode) timing t1 t4 t3 t2 tCYC SYSCLK tCHASH tCHASL ASCY=0 ASX tCHCSL tCHCSH WRCS=1 CS0X to CS3X WR0X to WR1X ACS=0 CSWR=0 WWT=0 tCHWL tWLWH tCHWH tCHAV A00 to A21 Valid Address tCHDV D16 to D31 142 CONFIDENTIAL tCHAX tCHDX Write Data MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (14) External bus I/F (Asynchronous mode) timing (TA: Recommended operating conditions, VCC5=VCCE=AVCC=5.0V±10%, VSS=AVSS=0.0V) (External load capacitance 50pF) Value Parameter Cycle time Symbol Pin name tCYC SYSCLK Address setup → RDX↑time RDX ↑→ Address hold Data setup → RDX↑time tRHAH RDX ↑ → Data hold tRHDH tASRH tDSRH Address setup → WRnX↑time WRnX ↑→ Address hold Data setup → WRnX ↑ time tWHAH WRnX ↑→ Data hold tWHDH Address setup → ASX↑time tASWH tDSWH tMASASH RDX, A00 to A21 RDX, D16 to D31 Min Max 25 – Unit Remarks ns 2 ×tCYC – 2 ×tCYC + 12 12 ns RWT=1, Set RWT to “1” or more. * tCYC – 12 tCYC + 12 ns Set RDCS to “1” or more. RWT=1, Set RWT to “1” or more. 18 + tCYC – ns 0 – ns WR0X to tCYC – 12 tCYC + 12 WR1X, A00 to A21 tCYC – 12 tCYC + 12 ns WWT=0 * ns Set WRCS to “1” or more. WR0X to tCYC – 16 tCYC + 16 WR1X, D16 to D31 tCYC – 16 tCYC + 16 ns WWT=0 * ns Set WRCS to “1” or more. tCYC – 16 tCYC + 16 ns ASCY=0 In multiplex mode, set as follows: Set CSWR and CSRD to 2 or more. ASCY must satisfy the following conditions because ASX, of setting ADCY>ASCY and D16 to D31 ASX ↑→ tMASHAH tCYC – 16 tCYC + 16 ns protocol violation Address hold prevention. ADCY + 1 ≤ ACS + CSRD ADCY + 1 ≤ ACS + CSWR ASCY + 1 ≤ ACS + CSRD ASCY + 1 ≤ ACS + CSWR Refer to Hardware Manual for details. *: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated value. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 143 D a t a S h e e t External bus I/F (asynchronous mode, read operation, and multiplex mode) timing t1 t3 t2 t4 t5 tCYC SYSCLK ASCY=0 ASX CS0X to CS3X RDCS=1 ACS=0 RWT=1 RDX CSRD=2 ADCY=1 Read Data Valid Address D16 to D31 tRHDH tMASASH tMASHAH tDSRH External bus I/F (asynchronous mode, read operation, and split mode) Timing t1 t3 t2 t4 t5 tCYC SYSCLK ASCY=0 ASX CS0X to CS3X RDCS=1 ACS=0 RWT=1 RDX A00 to A21 CSRD=0 Valid Address tASRH D16 to D31 tRHAH Read Data tDSRH 144 CONFIDENTIAL tRHDH MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t External bus I/F (asynchronous mode, write operation, and multiplex mode) timing t1 t3 t2 t4 tCYC SYSCLK ASCY=0 ASX CS0X to CS3X WRCS=1 ACS=0 WR0X, WR1X CSWR=2 WWT=0 ADCY=1 D16 to D31 Write Data Valid Address tMASASH tMASHAH tDSWH tWHDH External bus I/F (Asynchronous mode, write operation, and split mode) timing t1 t3 t2 t4 tCYC SYSCLK ASCY=0 ASX CS0X to CS3X ACS=0 WR0X, WR1X CSWR=0 WWT=0 A00 to A21 WRCS=1 Valid Address tASWH D16 to D31 Write Data tDSWH June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL tWHAH tWHDH 145 D a t a S h e e t (15) External bus I/F (ready) timing (TA: Recommended operating conditions, VCC5= VCCE =AVCC=5.0V±10%, VSS=AVSS=0.0V) (External load capacitance 50pF) Parameter Symbol Pin name tCYC SYSCLK Cycle time RDY setup time→ SYSCLK ↑ SYSCLK ↑→ RDY hold time tRDYS tRDYH SYSCLK, RDY SYSCLK, RDY Value Min Max Unit 50 – ns 28 – ns 0 – ns Remarks If using RDY, set SYSCLK to 20 MHz or less. External bus I/F (ready) timing t1 t2 t3 t4 t5 t6 tCYC SYSCLK ASX ASCY=2 CS0X to CS3X RDCS=2 ACS=2 RDX RWT=2 CSRD=2 RDY Auto wait cycle tRDYS tRDYH Added cycle by RDY 146 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t (16) HS-SPI timing (TA: Recommended operating conditions, VCC5= VCCE =AVCC=5.0V±10%, VSS=AVSS=0.0V) (External load capacitance 20pF) Parameter Serial clock cycle time Valid CS → CLK start time (mode0/mode2) Valid CS → CLK start time (mode1/mode3) CLK end → Invalid CS time (mode0/mode2) CLK end → Invalid CS time (mode1/mode3) Symbol tSCYCM Pin name Min Max Master 62.5 – ns Slave 100 – ns 1.5×tSCYCM – 15 – ns tSCYCM – 15 – ns tOSKSL02 tSCYCM -10 – ns tOSKSL13 1.5×tSCYCM -10 – ns Unit Remark s SPI_CLK tOSLSK02 tOSLSK13 Value Condi tions SPI_CLK, SPI_CS0, SPI_CS1, SPI_CS2, SPI_CS3 – *1 *2 SPI_CLK, Master -10 15 ns SPI_SIO0, SIO data output time tOSDAT SPI_SIO1, SPI_SIO2, Slave 28 ns – SPI_SIO3 SPI_CLK, SIO setup tDSSET 22 ns – SPI_SIO0, SPI_SIO1, – SPI_SIO2, SIO hold tSDHOLD ns 0.5×tSCYCM – SPI_SIO3 *1: VCCE=5.0V±10%, or VCCE=3.0 to 3.6V *2: In the voltage range shown in *1, this parameter is defined when IOH is -2mA and IOL is 2mA. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 147 D a t a S h e e t SPI_CS0, SPI_CS1, SPI_CS2, SPI_CS3 t SCYCM mode0 mode2 SPI_CLK t OSLSK02 t OSKSL02 mode1 mode3 t OSKSL13 t OSLSK13 SPI_SIO0, SPI_SIO1, SPI_SIO2, SPI_SIO3 input t SDHOLD t DSSET UP output t OSDAT 148 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t 5. A/D Converter (1) Electrical Characteristics (TA: Recommended operating conditions, VCC5=5.0V±10%, AVCC=5.0V±10%, VSS=AVSS=0.0V) Parameter Resolution Total error Non linearity error Differential linearity error Sym Pin name bol – – – – Zero transition voltage VOT Full-scale transition voltage VFST Sampling time tSMP Compare time tCMP A/D conversion time tCNV Analog port input current IAIN Analog input voltage VAIN Reference voltage Power supply current Max – – – – – – – – – – – – 10 bit ±3.0 ±2.5 ±1.9 LSB AN0 to AN39 AN0 to AN39 AVSS -1.5LSB AVCC -3.5LSB 1.2 – – – – AVRL AVSS IR IRH Variation between channels Typ AVRH IAH – Unit Min AN0 to AN39 AN0 to AN39 AVRH IA Value AVCC AVRH AN0 to AN39 – AVSS +2.5LSB AVCC +0.5LSB Remarks LSB LSB V V 1LSB= (AVCC-AVSS) /1024 – – – µs *1 µs *1 3.0 – – – µs -5 – +5 µA *1 VAVSS ≤ VAIN ≤ VAVCC AVSS – AVRH V 4.5 – 5.5 V – – – – – 0.0 – V – – 4.0 mA 6.0 µA 600 900 µA – 5 µA – 4 LSB 1.8 – AVCC ≥ AVRH *2 *2 *1: Time for each channel. *2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped. Note: Be sure to use the clock with a frequency between 8MHz and 17MHz for the ADC compare clock in order to ensure its accuracy. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 149 D a t a S h e e t (2) Definition of A/D Converter Terms Resolution : Analog variation that is recognized by an A/D converter. Linearity error : Deviation of the actual conversion characteristics from a straight line that connects the zero transition point ("00 0000 0000"←→"00 0000 0001") to the full-scale transition point ("11 1111 1110"← →"11 1111 1111"). Differential linearity error : Deviation of the input voltage from the ideal value that is required to change the output code by 1LSB. Total error : Difference between the actual value and the theoretical value. The total error includes zero transition error, full-scale transition error, and linearity error. Total error 3FF 3FE 1.5 LSB Actual conversion characteristics Digital output 3FD {1 LSB × (N - 1) + 0.5 LSB} 004 VNT 003 (Actually-measured value) Actual conversion characteristics Ideal characteristics 002 001 0.5 LSB AVSS (AVRL) Analog input AVRH VNT - {1LSB × (N - 1) + 0.5LSB} 1LSB AVRH - AVSS [V] 1024 Total error of digital output N = 1LSB (Ideal value) = [LSB] VOT (Ideal value) = AVSS + 0.5 LSB[V] VFST (Ideal value) = AVRH - 1.5 LSB[V] VNT: Voltage at which the digital output changes from (N - 1) to N. 150 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Linearity error of digital output N = VNT - {1LSB × (N - 1) + VOT} 1LSB Differential linearity error of digital output N = V(N + 1) T - VNT [LSB] - 1 LSB [LSB] 1LSB VFST - VOT 1022 1LSB = [V] VOT: Voltage at which the digital output changes from “000H” to “001 H”. VFST: Voltage at which the digital output changes from “3FE H” to “3FF H”. (3) Notes on Using A/D Converter <About the output impedance of the analog input of external circuit> External impedance values of the external input of 4.2 kΩ or lower (sampling time = 1.2 μs@ machine clock of 16 MHz) are recommended. When the external impedance is too high, the sampling time for analog voltages may not be sufficient. In this case, it is recommended to connect the capacitor (approx. 0.1 μF) to the analog input pin. Analog input circuit model Comparator Analog input R During sampling: ON MB91570series C R 4.0kΩ(Max) C 16.5pF(Max) * *: except DA shared pin Note: Listed values must be considered as reference values. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 151 D a t a S h e e t 6. D/A converter (TA: Recommended operating conditions, VCC5=AVCC=5.0V±10%,VSS=AVSS=0.0V) Parameter Resolution Differential linearity error Value Symbol Pin name Min Typ Max – – – – – – – – 8 bit ±3.0 LSB – – – 0.58 0.69 µs – – – 2.90 3.43 µs IDVR AVCC – 475 580 µA IDVRS AVCC – – 7.5 µA – – – 3.8 4.5 kΩ Unit Conversion time Reference voltage supply current Analog output impedance Remarks Load capacitance: 20 pF Load capacitance: 100 pF Per 1ch * Per 1ch in power down mode *: Reference voltage supply current (VCC = AVCC = 5.0 V) is specified. 152 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t 7. Flash memory (1) Electrical characteristics Parameter Value Typ Min Max Unit – 200 800 ms – 300 1100 ms – 400 2000 ms – 700 3700 ms 8-bit writing time – 9 288 µs 16-bit writing time – 12 384 µs ECC writing time – 9 288 µs Sector erase time Remarks 8 Kbyte sector*1, excluding internal preprogramming time 8 Kbyte sector*1, including internal preprogramming time 64 Kbyte sector*1, excluding internal preprogramming time 64 Kbyte sector*1, including internal preprogramming time Exclusive of overhead time at system level*1 Exclusive of overhead time at system level*1 Exclusive of overhead time at system level*1 1,000 cycles/ 20 years, Erase cycle*2/ 10,000 cycles/ – – – Average TA=+85°C*3 Data retain time 10 years, 100,000 cycles/ 5 years *1: The guaranteed value for erasure up to 100,000 cycles. *2: Number of erase cycles for each sector. *3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85°C). (2) Notes While the Flash memory is written or erased, shutdown of the external power (VCC5) is prohibited. In the application system where VCC5 might be shut down while writing or erased, be sure to turn the power off by using an external low-voltage detection function. To put it concretely, after the external power supply voltage falls below the detection voltage (V DL*1), hold VCC5 at 2.7V or more within the duration calculated by the following expression: Td*1[µs] + (period of PCLK [µs] × 257) + 50 [µs] *1: See "4. AC characteristics (9) Low voltage detection (External low-voltage detection) " June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 153 D a t a S h e e t ORDERING INFORMATION Part number Package* MB91F575BPMC MB91F575BSPMC MB91F575BHPMC MB91F575BHSPMC MB91F575CPMC MB91F575CSPMC MB91F575CHPMC MB91F575CHSPMC MB91F577BPMC MB91F577BSPMC MB91F577BHPMC MB91F577BHSPMC MB91F577CPMC LQFP-144 pin, Plastic (FPT-144P-M08) MB91F577CSPMC MB91F577CHPMC MB91F577CHSPMC MB91F578CPMC MB91F578CSPMC MB91F578CHPMC MB91F578CHSPMC MB91F579CPMC MB91F579CSPMC MB91F579CHPMC MB91F579CHSPMC MB91F575BSPMC1 MB91F575BHSPMC1 MB91F577BSPMC1 MB91F577BHSPMC1 MB91F578CPMC1 MB91F578CSPMC1 MB91F578CHPMC1 LQFP-144 pin, Plastic (FPT-144P-M12) MB91F578CHSPMC1 MB91F579CPMC1 MB91F579CSPMC1 MB91F579CHPMC1 MB91F579CHSPMC1 154 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Part number Package* MB91F578CMPMC MB91F578CSMPMC MB91F578CHMPMC MB91F578CHSMPMC MB91F579CMPMC LQFP-208-pin, Plastic (FPT-208P-M06) MB91F579CSMPMC MB91F579CHMPMC MB91F579CHSMPMC *: For details of the package, see " PACKAGE DIMENSIONS ". June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 155 D a t a S h e e t PACKAGE DIMENSIONS 156 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 157 D a t a S h e e t 158 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t Major Changes Page Revision 2.0 Revision 2.1 Revision 2.2 - Section Change Results - Initial release - Company name and layout design change P104-P108 Revised text position See Supplementary Information as described in Document Definition. June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 159 D a t a S h e e t 160 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015 D a t a S h e e t June 19, 2015, MB91F577_DS705-00009-3v0-E CONFIDENTIAL 161 D a t a S h e e t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2013-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 162 CONFIDENTIAL MB91F577_DS705-00009-3v0-E, June 19, 2015