The following document contains information on Cypress products.
MB91580M/S Series
32-bit Microcontroller
MB91F583AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK,
MB91F584AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK,
MB91F585AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB91F585AMG_DS705-00013
CONFIDENTIAL
Revision 2.0
Issue Date April 18, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
CONFIDENTIAL
MB91580M/S Series
FR Family FR81S
MB91F583AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK,
MB91F584AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK,
MB91F585AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASKC
Data Sheet (Full Production)
DESCRIPTION
This series is a Spansion 32-bit microcontroller for automobile motor control. They use the FR81S CPU
that is compatible with the FR family.
Note: FR is a line of products of Spansion Inc.
FEATURES
FR81S CPU Core
32-bit RISC, load/store architecture, pipeline 5-stage structure
Maximum operating frequency: 128MHz (Source oscillation= 4.0MHz, 32 multiplied ( PLL clock
multiplication system) )
General-purpose register: 32 bits 16 sets
16-bit fixed length instructions (basic instructions), 1 instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instructions
Bit manipulation instructions
Barrel shift instructions
High-level language support instructions
Function entry/exit instructions
Register content multi-load and store instructions
Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
Branch instructions with delay slot
Overhead decrement during branch process
Register interlock function
Easy assembler writing
Built-in multiplier and instruction level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
Spansion provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.spansion.com/Support/microcontrollers/Pages/default.aspx
Publication Number MB91F585AMG_DS705-00013
Revision 2.0
Issue Date April 18, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
Interrupt (PC/PS saving)
6 cycles (16 priority levels)
The Harvard architecture allows simultaneous execution of program and data access.
Instruction compatibility with the FR family
Built-in memory protection function (MPU)
Eight protection areas can be specified commonly for instructions and data.
Control access privilege in both privilege mode and user mode
Built-in FPU (floating-point operation)
IEEE754 compliant
Floating-point register: 32 bits 16 sets
Peripheral Functions
Clock generation (SSCG function is available)
Main oscillation (4 MHz to 20 MHz)
PLL multiplication rate:1 to 32 times
CR oscillation
Oscillation frequency: 100kHz, with frequency accuracy 50% (pre-trimming)
Trimming is enabled
To be used as a count clock of hardware watchdog
Oscillation stop feature during standby is not available
MB91F583AMJ/F584AMJ/F585AMJ/F583AMK/F584AMK/F585AMK
MB91F583ASJ/F584ASJ/F585ASJ/F583ASK/F584ASK/F585ASK
Oscillation stop feature during standby is available
MB91F583AMG/F584AMG/F585AMG/F583AMH/F584AMH/F585AMH
MB91F583ASG/F584ASG/F585ASG/F583ASH/F584ASH/F585ASH
Built-in program flash memory capacity
MB91F583: 256+64 Kbytes
MB91F584: 384+64 Kbytes
MB91F585: 512+64 Kbytes
Built-in data flash (WorkFlash) 64 Kbytes
Built-in RAM capacity
Main RAM
MB91F583: 32 Kbytes
MB91F584: 48 Kbytes
MB91F585: 48 Kbytes
Backup RAM 8 Kbytes
General-purpose ports: MB91F583AM/F584AM/F585AM
76 ports
Including eight I2C pseudo open drain corresponding ports
MB91F583AS/F584AS/F585AS
44ports
Including two I2C pseudo open drain corresponding ports
DMA controller
Up to 8 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and software)
External interrupt input
MB91F583AM/F584AM/F585AM: 8 channels
MB91F583AS/F584AS/F585AS: 7 channels
Level ("H" / "L") or edge detection (rising or falling) enabled
Multi-function serial communication (built-in transmission/reception FIFO memory)
MB91F583AM/F584AM/F585AM: 4 channels
MB91F583AS/F584AS/F585AS: 2 channels
UART (Asynchronous serial interface)
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception
FIFO memory
Parity or no parity is selectable.
Built-in dedicated baud rate generator
An external clock can be used as the transfer clock
Parity, frame, and overrun error detection functions provided
DMA transfer supported
2
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
CSIO (Synchronous serial interface)
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception
FIFO memory
SPI supported; master and slave systems supported; 5 to 16, 20, 24, 32-bit data length can be
set.
Built-in dedicated baud rate generator (Master operation)
An external clock can be entered. (Slave operation)
Overrun error detection function is provided.
Built-in chip selection function
DMA transfer supported
LIN interface (v2.1)
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception
FIFO memory
LIN protocol revision2.1 supported.
Master and slave systems supported
Framing error and overrun error detection
LIN sync break generation and detection; LIN sync delimiter generation
Built-in dedicated baud rate generator
An external clock can be adjusted by the reload counter.
DMA transfer supported
I2C
MB91F583AM/F584AM/F585AM: Supported for 3 channels: ch.0,ch.2,and ch.3
MB91F583AS/F584AS/F585AS: Supported for 1 channel: ch.0
Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception
FIFO memory
Standard mode (Max. 100 kbps) / high-speed mode (Max. 400 kbps) supported
DMA transfer supported (for transmission only)
CAN controller (CAN)
MB91F583AM/F584AM/F585AM:
2 channels
MB91F583AS/F584AS/F585AS:
1 channel
Transfer speed: Up to 1Mbps
64-transmission/reception message buffering
FlexRay controller
MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584AMJ/F585AMJ/
F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F585ASJ: 1 unit (ch.A/ch.B)
FlexRay Specifications Version 2.1 supported
Up to 128 message buffers
8K bytes of message RAM
Variable length of message buffers
Each message buffer can be allocated as a part of reception buffer, transmission buffer or reception
FIFO memory
Host access to the message buffer via input and output buffers
Filtering for slot counter, cycle counter and channels
Maskable interrupts are supported
PPG: 16 bits 6 channels
Reload timer: 16 bits 4 channels
A/D converter (successive approximation type)
12-bit resolution
MB91F583AM/F584AM/F585AM:
3 units (23 channels)
MB91F583AS/F584AS/F585AS:
3 units (17 channels)
Conversion time: 1 s
Free-run timer:
16 bits 6 channels (1 channel can be selected for input capture, and 1 channel for output compare.)
Input capture: 16 bits 4 channels (linked to the free-run timer)
Output compare: 16 bits 7 channels (linked to the free-run timer)
Waveform generator: 2 units (7 channels)
10-bit D/A converter: 1 channel
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
3
D a t a S h e e t
Calibration: The hardware watchdog for CR oscillation drive
The CR oscillation frequency can be trimmed.
Clock Supervisor
Anomaly supervisory feature (by damaged quartz, etc.) of external main oscillation (4MHz)
When anomaly is detected, clock is switched to CR.
Up/ down counter: 2 channels
8/16-bit Up/ down counter
Base timer: 2 channels
16-bit timer
Any of four PWM/PPG/PWC/reload timer functions can be selected and used.
As for the functions of PWC and reload timer, 2 channels of cascade mode can be used as 32-bit
timer.
CRC generation
Watchdog timer
Hardware watchdog
Software watchdog
NMI
Interrupt controller
Interrupt request batch read
Multiple interrupts from peripherals can be read by a series of registers.
I/O relocation (MB91F583AM/F584AM/F585AM)
Change of pin position of peripheral functions
Low-power consumption mode
Sleep/Stop/Watch
Stop (Power shutdown)/Watch (Power shutdown)
Power-on reset
Low-voltage detection reset (external low-voltage detection)
Low-voltage detection reset (internal low-voltage detection)
Package
MB91F583AM/F584AM/F585AM:
LQFP-100
MB91F583AS/F584AS/F585AS:
LQFP-64
CMOS 90 nm technology
Power supplies
Single 5V power supply
The voltage step-down circuit brings the 5.0V down to generate 1.2V internally
I/O 5.0V
4
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
PRODUCT LINEUP
MB91580AM Series Product Lineup Comparison
Memory size
Items
MB91F583AMG
MB91F583AMH
MB91F583AMJ
MB91F583AMK
MB91F584AMG
MB91F584AMH
MB91F584AMJ
MB91F584AMK
MB91F585AMG
MB91F585AMH
MB91F585AMJ
MB91F585AMK
256+64 Kbytes
384+64 Kbytes
64 Kbytes
48 Kbytes
8 Kbytes
512+64 Kbytes
Flash memory capacity (program)
Flash memory capacity (work)
RAM capacity (main)
RAM capacity (backup)
32 Kbytes
48 Kbytes
Function
Items
System clock
CR oscillation
Oscillation stop
feature during
standby
External bus interface
DMA transfer
16-bit base timer
Free-run timer
Input capture
Output compare
Waveform generator
16-bit reload timer
PPG
External interrupt
A/D converter
R/D converter
D/A converter
Up/ down counter
Multi-function serial
interface
CAN
FlexRay
MB91F583AMG
MB91F584AMG
MB91F585AMG
MB91F583AMH MB91F583AMJ MB91F583AMK
MB91F584AMH MB91F584AMJ MB91F584AMK
MB91F585AMH MB91F585AMJ MB91F585AMK
On-chip PLL clock multiplication system
(Up to 32 times of multiplication)
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz 32 times of multiplication)
Provided
Provided
Not provided
Not provided
Not provided
8 channels
2 channels
6 channels
4 channels
7 channels
2 units (7 channels)
4 channels
6 channels
8 channels
3 units (23 channels)
Not provided
Provided
2 channels
4 channels
128msb
1 unit
(ch.A / ch.B)
Software watchdog
Hardware watchdog
CRC generation
Low-voltage detection
reset (internal low-voltage
detection)
Low-voltage detection
reset (external low-voltage
detection)
Device package
Debug interface
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Provided
64msb 2 channels (ch.0/ch.1)
128msb
Not provided
1 unit
(ch.A / ch.B)
Provided
Provided
2 channels
Not provided
Provided
Provided
LQFP-100
Built-in OCD (On Chip Debug Unit)
5
D a t a S h e e t
MB91580AS Series Product Lineup Comparison
Memory size
Items
Flash memory capacity (program)
Flash memory capacity (work)
RAM capacity (main)
RAM capacity (backup)
MB91F583ASG
MB91F583ASH
MB91F583ASJ
MB91F583ASK
MB91F584ASG
MB91F584ASH
MB91F584ASJ
MB91F584ASK
MB91F585ASG
MB91F585ASH
MB91F585ASJ
MB91F585ASK
256+64 Kbytes
384+64 Kbytes
64 Kbytes
48 Kbytes
8 Kbytes
512+64 Kbytes
32 Kbytes
48 Kbytes
Function
Items
System clock
CR oscillation
Oscillation stop
feature during
standby
External bus interface
DMA transfer
16-bit base timer
Free-run timer
Input capture
Output compare
Waveform generator
16-bit reload timer
PPG
External interrupt
A/D converter
R/D converter
D/A converter
Up/ down counter
Multi-function serial
interface
CAN
FlexRay
Software watchdog
Hardware watchdog
CRC generation
Low-voltage detection
reset (internal low-voltage
detection)
Low-voltage detection
reset (external low-voltage
detection)
Device package
Debug interface
6
CONFIDENTIAL
MB91F583ASG
MB91F584ASG
MB91F585ASG
MB91F583ASH
MB91F583ASJ
MB91F583ASK
MB91F584ASH
MB91F584ASJ
MB91F584ASK
MB91F585ASH
MB91F585ASJ
MB91F585ASK
On-chip PLL clock multiplication system
(Up to 32 times of multiplication)
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz32 times of multiplication)
Provided
Provided
Provided
Not provided
Not provided
Not provided
8 channels
2 channels
6 channels
4 channels
7 channels
2 units (7 channels)
4 channels
6 channels
7 channels
3 units (17 channels)
Not provided
Provided
2 channels
2 channels
128msb
1unit
(ch.A / ch.B)
64msb 1 channel (ch.0)
128msb
Not provided
1unit
(ch.A / ch.B)
Provided
Provided
2 channels
Not provided
Provided
Provided
LQFP-64
Built-in OCD (On Chip Debug Unit)
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
MB91580L Series Product Lineup Comparison
Memory size
Items
MB91F585LA
MB91F585LB
MB91F585LC
MB91F585LD
MB91F586LA
MB91F586LB
MB91F586LC
MB91F586LD
MB91F587LA
MB91F587LB
MB91F587LC
MB91F587LD
512+64 Kbytes
768+64 Kbytes
64 Kbytes
64 Kbytes
8 Kbytes
1024+64 Kbytes
Flash memory capacity (program)
Flash memory capacity (work)
RAM capacity (main)
RAM capacity (backup)
48 Kbytes
96 Kbytes
Function
Items
System clock
CR oscillation
Oscillation stop
feature during standby
External bus interface
MB91F585LA
MB91F586LA
MB91F587LA
MB91F585LB
MB91F586LB
MB91F587LB
MB91F585LC
MB91F586LC
MB91F587LC
MB91F585LD
MB91F586LD
MB91F587LD
On-chip PLL clock multiplication system
(Up to 32 times of multiplication)
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz 32 times of multiplication)
Provided
Provided
Not provided
Provided
Not provided
Address: 22 bits
Not provided
Data: 16 bits
8 channels
2 channels
6 channels
8 channels
12 channels
2 units (12 channels)
4 channels
24 channels
8 channels
3 units (24 channels)
Not provided
Provided
Provided
Not provided
2 channels
Not provided
Address: 22 bits
Data: 16 bits
DMA transfer
16-bit base timer
Free-run timer
Input capture
Output compare
Waveform generator
16-bit reload timer
PPG
External interrupt
A/D converter
R/D converter
Provided
Not provided
D/A converter
Not provided
Provided
Up/ down counter
Multi-function serial
5 channels
interface
CAN
64 msb 3 channels (ch.0/ch.1/ch.2)
FlexRay
128 msb 1 unit (ch.A / ch.B)
Software watchdog
Provided
Hardware watchdog
Provided
CRC generation
1 channel
Low-voltage detection reset
(internal low-voltage
Provided
detection)
Low-voltage detection reset
(external low-voltage
Provided
detection)
Device package
LQFP-144
Debug interface
Built-in OCD (On Chip Debug Unit)
Note: For details on the MB91580L series, see the "MB91580L Series HARDWARE MANUAL".
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
7
D a t a S h e e t
PIN ASSIGNMENT
LQFP-100 Pin Assignment
MB91F583AM/F584AM/F585AM
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VCC5
P070/TIN0/INT3
P047/TOT0/INT2/ADTG2
P046/ADTG0/MM
P087
P086
P085/SCS3
C
VSS
P084/SCK3
P083/SOT3
P082/SIN3
RSTX
P045/RX0/INT1
P044/TX0
VSS
X1
X0
MD1
MD0
P081/SCK0_1
P080/SOT0_1
P043/SIN0_1/ADTG1/MONCLK
DEBUGIF
VCC5
(TOP VIEW)
VSS
P000
P071/TIN1/AIN0/INT4
P001
P072/TOT1/BIN0/RTO6
P050/RTO5/ZIN0
P002
P051/RTO4/AIN1/FRCK5
P003
P052/RTO3/BIN1/FRCK4
P004
P053/RTO2/ZIN1/FRCK3
P005
P054/RTO1/FRCK2
P006
P055/RTO0/FRCK1
P007
P056/DTTI0/FRCK0
P010/AN0/IN0
P011/AN1/IN1
P012/AN2/IN2
P013/AN3/IN3
P014/AN4/TRG1
P015/AN5
VCC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LQFP-100
VSS
P042/SIN0_0
P066
P041/SCK0_0
P040/SOT0_0
P065/SCS2
P064/SCK2
P037/AN8
NMIX
P063/SOT2
P062/SIN2
P036/AN9/TIOA0/TIN2
P035/AN10/TIOB0/TOT2
P034/AN11/TIOA1/TIN3
P033/AN12/TIOB1/TOT3
P061/TX1
P060/RX1/INT7
AVCC1
AVRH1
AVSS1/AVRL1
P032/AN13
P031/AN14
P030/DAOUT
P097/AN23
VSS
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCC5
P102
P101
P100
P096/AN22
P095/AN21
P094/AN20/PPG5
P093/AN19/PPG4
P027/PPG3/TXDA
P026/PPG2/RXDA
P025/PPG1/TXENA
P024/PPG0/STOPWT
P023/SCS1/TXDB
P022/SOT1/RXDB
P021/SIN1/TXENB/INT0
P020/SCK1/TRG0
P092/AN18
P091/AN17
P090/AN16
AVSS0/AVRL0
AVRH0
P017/AN7/INT5
AVCC0
P016/AN6/INT6
VSS
(FPT-100P-M20)
8
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
LQFP-64 Pin Assignment
MB91F583AS/F584AS/F585AS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VCC5
P070/TIN0/INT3
P047/TOT0/INT2/ADTG2
P046/ADTG0/MM
C
VSS
RSTX
P045/RX0/INT1
P044/TX0
VSS
X1
X0
MD1
MD0
P043/ADTG1/MONCLK
DEBUGIF
(TOP VIEW)
VSS
P071/TIN1/AIN0/INT4
P072/TOT1/BIN0/RTO6
P050/RTO5/ZIN0
P051/RTO4/AIN1/FRCK5
P052/RTO3/BIN1/FRCK4
P053/RTO2/ZIN1/FRCK3
P054/RTO1/FRCK2
P055/RTO0/FRCK1
P056/DTTI0/FRCK0
P010/AN0/IN0
P011/AN1/IN1
P012/AN2/IN2
P013/AN3/IN3
P014/AN4/TRG1
P015/AN5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP-64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P042/SIN0_0
P041/SCK0_0
P040/SOT0_0
P037/AN8
NMIX
P036/AN9/TIOA0/TIN2
P035/AN10/TIOB0/TOT2
P034/AN11/TIOA1/TIN3
P033/AN12/TIOB1/TOT3
AVCC1
AVRH1
AVSS1/AVRL1
P032/AN13
P031/AN14
P030/DAOUT
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC5
P094/AN20/PPG5
P093/AN19/PPG4
P027/PPG3/TXDA
P026/PPG2/RXDA
P025/PPG1/TXENA
P024/PPG0/STOPWT
P023/SCS1/TXDB
P022/SOT1/RXDB
P021/SIN1/TXENB/INT0
P020/SCK1/TRG0
AVSS0/AVRL0
AVRH0
P017/AN7/INT5
AVCC0
P016/AN6/INT6
(FPT-64P-M24)
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
9
D a t a S h e e t
PIN DESCRIPTION
MB91F583AM/F584AM/F585AM
I/O circuit
Pin No.
Pin name
type*
83
84
67
88
81
82
2
4
7
9
11
13
15
17
19
20
21
22
23
24
27
29
35
36
10
CONFIDENTIAL
X0
X1
NMIX
RSTX
MD0
MD1
P000
P001
P002
P003
P004
P005
P006
P007
P010
IN0
AN0
P011
IN1
AN1
P012
IN2
AN2
P013
IN3
AN3
P014
TRG1
AN4
P015
AN5
P016
AN6
INT6
P017
AN7
INT5
P020
SCK1
TRG0
P021
SIN1
TXENB
INT0
A
B
B
C
C
D
D
D
D
D
D
D
D
F
F
F
F
F
F
G
G
D
L
Function
Main clock oscillation input pin
Main clock oscillation output pin
Interrupt input pin without mask
External reset input pin
Mode pin 0 (with high-voltage control)
Mode pin 1 (with high-voltage control)
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
16-bit input capture ch.0 external pulse input pin
ADC analog 0 input pin
General-purpose I/O port
16-bit input capture ch.1 external pulse input pin
ADC analog 1 input pin
General-purpose I/O port
16-bit input capture ch.2 external pulse input pin
ADC analog 2 input pin
General-purpose I/O port
16-bit input capture ch.3 external pulse input pin
ADC analog 3 input pin
General-purpose I/O port
PPG ch.4, ch.5 external trigger
ADC analog 4 input pin
General-purpose I/O port
ADC analog 5 input pin
General-purpose I/O port
ADC analog 6 input pin
INT6 external interrupt input pin
General-purpose I/O port
ADC analog 7 input pin
INT5 external interrupt input pin
General-purpose I/O port
Multi-function serial ch.1 clock I/O pin
PPG ch.0 to ch.3 external trigger
General-purpose I/O port
Multi-function serial ch.1 serial data input pin
FlexRay ch.B operation enable output pin
INT0 external interrupt input pin
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Pin No.
37
38
39
40
41
42
53
54
55
61
62
63
64
68
71
Pin name
P022
SOT1
RXDB
P023
SCS1
TXDB
P024
PPG0
STOPWT
P025
PPG1
TXENA
P026
PPG2
RXDA
P027
PPG3
TXDA
P030
DAOUT
P031
AN14
P032
AN13
P033
TIOB1
TOT3
AN12
P034
TIOA1
TIN3
AN11
P035
TIOB0
TOT2
AN10
P036
TIOA0
TIN2
AN9
P037
AN8
P040
SOT0_0
I/O circuit
type*
K
K
D
K
K
K
M
F
F
F
F
F
F
F
H
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Function
General-purpose I/O port
Multi-function serial ch.1 serial data output pin
FlexRay ch.B data input pin
General-purpose I/O port
Multi-function serial ch.1 serial chip select I/O pin
FlexRay ch.A operation enable output pin
General-purpose I/O port
PPG ch.0 output pin
FlexRay Stopwatch input pin
General-purpose I/O port
PPG ch.1 output pin
FlexRay ch.A operation enable output pin
General-purpose I/O port
PPG ch.2 output pin
FlexRay ch.A data input pin
General-purpose I/O port
PPG ch.3 output pin
FlexRay ch.A data output pin
General-purpose I/O port
DAC analog output pin
General-purpose I/O port
ADC analog 14 input pin
General-purpose I/O port
ADC analog 13 input pin
General-purpose I/O port
Base timer ch.1 TIOB input pin
Reload timer ch.3 output pin
ADC analog 12 input pin
General-purpose I/O port
Base timer ch.1 TIOA I/O pin
Reload timer ch.3 event input pin
ADC analog 11 input pin
General-purpose I/O port
Base timer ch.0 TIOB input pin
Reload timer ch.2 output pin
ADC analog 10 input pin
General-purpose I/O port
Base timer ch.0 TIOA output pin
Reload timer ch.2 event input pin
ADC analog 9 input pin
General-purpose I/O port
ADC analog 8 input pin
General-purpose I/O port
Multi-function serial ch.0 serial data output pin (0)/
I2C ch.0 serial data I/O pin (SDA)
11
D a t a S h e e t
Pin No.
Pin name
I/O circuit
type*
P041
72
74
78
86
87
97
98
6
8
10
12
14
16
18
12
CONFIDENTIAL
SCK0_0
P042
SIN0_0
P043
SIN0_1
ADTG1
MONCLK
P044
TX0
P045
RX0
INT1
P046
ADTG0
MM
P047
TOT0
INT2
ADTG2
P050
RTO5
ZIN0
P051
RTO4
AIN1
FRCK5
P052
RTO3
BIN1
FRCK4
P053
RTO2
ZIN1
FRCK3
P054
RTO1
FRCK2
P055
RTO0
FRCK1
P056
DTTI0
FRCK0
H
D
D
D
E
D
E
D
D
D
D
D
D
D
Function
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin (0)/
I2C ch.0 clock I/O pin (SCL)
General-purpose I/O port
Multi-function serial ch.0 serial data input pin (0)
General-purpose I/O port
Multi-function serial ch.0 serial data input pin (1)
A/D converter ch.8 to ch.14 external trigger input pin
Clock monitor output pin
General-purpose I/O port
CAN transmission data 0 output pin
General-purpose I/O port
CAN reception data 0 input pin
INT1 external interrupt input pin
General-purpose I/O port
A/D converter ch.0 to ch.7 external trigger input pin
Clock supervisor main clock stop detection output pin
General-purpose I/O port
Reload timer ch.0 output pin
INT2 external interrupt input pin
A/D converter ch.16-ch.23 external trigger input pin
General-purpose I/O port
Waveform generator ch.5 output pin
Up/down counter ch.0 ZIN input pin
General-purpose I/O port
Waveform generator ch.4 output pin
Up/down counter ch.1 AIN input pin
Free-run timer ch.5 external clock input pin
General-purpose I/O port
Waveform generator ch.3 output pin
Up/down counter ch.1 BIN input pin
Free-run timer ch.4 external clock input pin
General-purpose I/O port
Waveform generator ch.2 output pin
Up/down counter ch.1 ZIN input pin
Free-run timer ch.3 external clock input pin
General-purpose I/O port
Waveform generator ch.1 output pin
Free-run timer ch.2 external clock input pin
General-purpose I/O port
Waveform generator ch.0 output pin
Free-run timer ch.1 external clock input pin
General-purpose I/O port
Waveform generator output stop signal input pin 0
Free-run timer ch.0 external clock input pin
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Pin No.
59
60
65
66
Pin name
P060
RX1
INT7
P061
TX1
P062
SIN2
P063
SOT2
I/O circuit
type*
E
D
D
H
P064
69
70
73
99
3
5
79
SCK2
P065
SCS2
P066
P070
TIN0
INT3
P071
TIN1
AIN0
INT4
P072
TOT1
BIN0
RTO6
P080
SOT0_1
H
D
D
E
E
D
H
P081
80
89
90
SCK0_1
P082
SIN3
P083
SOT3
H
D
H
P084
91
94
95
96
32
SCK3
P085
SCS3
P086
P087
P090
AN16
H
D
D
D
F
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Function
General-purpose I/O port
CAN reception data 1 input pin
INT7 external interrupt input pin
General-purpose I/O port
CAN transmission data 1 output pin
General-purpose I/O port
Multi-function serial ch.2 serial data input pin
General-purpose I/O port
Multi-function serial ch.2 serial data output pin/
I2C ch.2 serial data I/O pin (SDA)
General-purpose I/O port
Multi-function serial ch.2 clock I/O pin/
I2C ch.2 clock I/O pin (SCL)
General-purpose I/O port
Multi-function serial ch.2 serial chip select I/O pin
General-purpose I/O port
General-purpose I/O port
Reload timer ch.0 event input pin
INT3 external interrupt input pin
General-purpose I/O port
Reload timer ch.1 event input pin
Up/down counter ch.0 AIN input pin
INT4 external interrupt input pin
General-purpose I/O port
Reload timer ch.1 output pin
Up/down counter ch.0 BIN input pin
Waveform generator ch.6 output pin
General-purpose I/O port
Multi-function serial ch.0 serial data output pin (1)/
I2C ch.0 serial data I/O pin (1) (SDA)
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin (1)/
I2C ch.0 clock I/O pin (1) (SCL)
General-purpose I/O port
Multi-function serial ch.3 serial data input pin
General-purpose I/O port
Multi-function serial ch.3 serial data output pin/
I2C ch.3 serial data I/O pin (SDA)
General-purpose I/O port
Multi-function serial ch.3 clock I/O pin/
I2C ch.3 clock I/O pin (SCL)
General-purpose I/O port
Multi-function serial ch.3 serial chip select I/O pin
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
ADC analog 16 input pin
13
D a t a S h e e t
Pin No.
33
34
43
44
45
46
52
47
48
49
77
28
58
30
57
31
56
Pin name
P091
AN17
P092
AN18
P093
PPG4
AN19
P094
PPG5
AN20
P095
AN21
P096
AN22
P097
AN23
P100
P101
P102
DEBUGIF
AVCC0
AVCC1
AVRH0
AVRH1
AVSS0
AVRL0
AVSS1
AVRL1
C
I/O circuit
type*
F
F
F
F
F
F
F
D
D
D
I
-
Function
General-purpose I/O port
ADC analog 17 input pin
General-purpose I/O port
ADC analog 18 input pin
General-purpose I/O port
PPG ch.4 output pin
ADC analog 19 input pin
General-purpose I/O port
PPG ch.5 output pin
ADC analog 20 input pin
General-purpose I/O port
ADC analog 21 input pin
General-purpose I/O port
ADC analog 22 input pin
General-purpose I/O port
ADC analog 23 input pin
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port
DEBUG I/F pin
A/D converter analog power supply
A/D converter analog power supply
A/D converter upper limit reference voltage
A/D converter upper limit reference voltage
A/D converter GND
A/D converter lower limit reference voltage
A/D converter GND
A/D converter lower limit reference voltage
External capacity connection output pin
93
25, 50, 76,
VCC5
+5.0V power supply
100
1, 26, 51,
VSS
GND
75, 85, 92
* For I/O circuit types, see " I/O CIRCUIT TYPE".
14
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
MB91F583AS/F584AS/F585AS
I/O circuit
Pin No.
Pin name
type*
53
54
44
58
51
52
11
12
13
14
15
16
17
19
22
23
24
25
26
X0
X1
NMIX
RSTX
MD0
MD1
P010
IN0
AN0
P011
IN1
AN1
P012
IN2
AN2
P013
IN3
AN3
P014
TRG1
AN4
P015
AN5
P016
AN6
INT6
P017
AN7
INT5
P020
SCK1
TRG0
P021
SIN1
TXENB
INT0
P022
SOT1
RXDB
P023
SCS1
TXDB
P024
PPG0
STOPWT
A
B
B
C
C
F
F
F
F
F
F
G
G
D
L
K
K
D
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Function
Main clock oscillation input pin
Main clock oscillation output pin
Interrupt input pin without mask
External reset input pin
Mode pin 0 (with high-voltage control)
Mode pin 1 (with high-voltage control)
General-purpose I/O port
16-bit input capture ch.0 external pulse input pin
ADC analog 0 input pin
General-purpose I/O port
16-bit input capture ch.1 external pulse input pin
ADC analog 1 input pin
General-purpose I/O port
16-bit input capture ch.2 external pulse input pin
ADC analog 2 input pin
General-purpose I/O port
16-bit input capture ch.3 external pulse input pin
ADC analog 3 input pin
General-purpose I/O port
PPG ch.4, ch.5 external trigger
ADC analog 4 input pin
General-purpose I/O port
ADC analog 5 input pin
General-purpose I/O port
ADC analog 6 input pin
INT6 external interrupt input pin
General-purpose I/O port
ADC analog 7 input pin
INT5 external interrupt input pin
General-purpose I/O port
Multi-function serial ch.1 clock I/O pin
PPG ch.0 to ch.3 external trigger
General-purpose I/O port
Multi-function serial ch.1 serial data input pin
FlexRay ch.B operation enable output pin
INT0 external interrupt input pin
General-purpose I/O port
Multi-function serial ch.1 serial data output pin
FlexRay ch.B data input pin
General-purpose I/O port
Multi-function serial ch.1 serial chip select I/O pin
FlexRay ch.B data output pin
General-purpose I/O port
PPG ch.0 output pin
FlexRay Stopwatch input pin
15
D a t a S h e e t
Pin No.
27
28
29
34
35
36
40
41
42
43
45
46
Pin name
P025
PPG1
TXENA
P026
PPG2
RXDA
P027
PPG3
TXDA
P030
DAOUT
P031
AN14
P032
AN13
P033
TIOB1
TOT3
AN12
P034
TIOA1
TIN3
AN11
P035
TIOB0
TOT2
AN10
P036
TIOA0
TIN2
AN9
P037
AN8
P040
SOT0_0
I/O circuit
type*
K
K
K
M
F
F
F
F
F
F
F
H
P041
47
48
50
56
16
CONFIDENTIAL
SCK0_0
P042
SIN0_0
P043
ADTG1
MONCLK
P044
TX0
H
D
D
D
Function
General-purpose I/O port
PPG ch.1 output pin
FlexRay ch.A operation enable output pin
General-purpose I/O port
PPG ch.2 output pin
FlexRay ch.A data input pin
General-purpose I/O port
PPG ch.3 output pin
FlexRay ch.A data output pin
General-purpose I/O port
DAC analog output pin
General-purpose I/O port
ADC analog 14 input pin
General-purpose I/O port
ADC analog 13 input pin
General-purpose I/O port
Base timer ch.1 TIOB input pin
Reload timer ch.3 output pin
ADC analog 12 input pin
General-purpose I/O port
Base timer ch.1 TIOA I/O pin
Reload timer ch.3 event input pin
ADC analog 11 input pin
General-purpose I/O port
Base timer ch.0 TIOB input pin
Reload timer ch.2 output pin
ADC analog 10 input pin
General-purpose I/O port
Base timer ch.0 TIOA output pin
Reload timer ch.2 event input pin
ADC analog 9 input pin
General-purpose I/O port
ADC analog 8 input pin
General-purpose I/O port
Multi-function serial ch.0 serial data output pin(0)/
I2C ch.0 serial data I/O pin (0) (SDA)
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin (0)/
I2C ch.0 clock I/O pin (0) (SCL)
General-purpose I/O port
Multi-function serial ch.0 serial data input pin (0)
General-purpose I/O port
A/D converter ch.8 to ch.14 external trigger input pin
Clock monitor output pin
General-purpose I/O port
CAN transmission data 0 output pin
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Pin No.
57
61
62
4
5
6
7
8
9
10
63
2
3
Pin name
P045
RX0
INT1
P046
ADTG0
MM
P047
TOT0
INT2
ADTG2
P050
RTO5
ZIN0
P051
RTO4
AIN1
FRCK5
P052
RTO3
BIN1
FRCK4
P053
RTO2
ZIN1
FRCK3
P054
RTO1
FRCK2
P055
RTO0
FRCK1
P056
DTTI0
FRCK0
P070
TIN0
INT3
P071
TIN1
AIN0
INT4
P072
TOT1
BIN0
RTO6
I/O circuit
type*
E
D
E
D
D
D
D
D
D
D
E
E
D
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Function
General-purpose I/O port
CAN reception data 0 input pin
INT1 external interrupt input pin
General-purpose I/O port
A/D converter ch.0 to ch.7 external trigger input pin
Clock supervisor main clock stop detection output pin
General-purpose I/O port
Reload timer ch.0 output pin
INT2 external interrupt input pin
A/D converter ch.19 to ch.20 external trigger input pin
General-purpose I/O port
Waveform generator ch.5 output pin
Up/down counter ch.0 ZIN input pin
General-purpose I/O port
Waveform generator ch.4 output pin
Up/down counter ch.1 AIN input pin
Free-run timer ch.5 external clock input pin
General-purpose I/O port
Waveform generator ch.3 output pin
Up/down counter ch.1 BIN input pin
Free-run timer ch.4 external clock input pin
General-purpose I/O port
Waveform generator ch.2 output pin
Up/down counter ch.1 ZIN input pin
Free-run timer ch.3 external clock input pin
General-purpose I/O port
Waveform generator ch.1 output pin
Free-run timer ch.2 external clock input pin
General-purpose I/O port
Waveform generator ch.0 output pin
Free-run timer ch.1 external clock input pin
General-purpose I/O port
Waveform generator output stop signal input pin 0
Free-run timer ch.0 external clock input pin
General-purpose I/O port
Reload timer ch.0 event input pin
INT3 external interrupt input pin
General-purpose I/O port
Reload timer ch.1 event input pin
Up/down counter ch.0 AIN input pin
INT4 external interrupt input pin
General-purpose I/O port
Reload timer ch.1 output pin
Up/down counter ch.0 BIN input pin
Waveform generator ch.6 output pin
17
D a t a S h e e t
Pin No.
30
31
49
18
39
20
38
21
37
Pin name
P093
PPG4
AN19
P094
PPG5
AN20
DEBUGIF
AVCC0
AVCC1
AVRH0
AVRH1
AVSS0
AVRL0
AVSS1
AVRL1
C
VCC5
I/O circuit
type*
F
F
I
-
Function
General-purpose I/O port
PPG ch.4 output pin
ADC analog 19 input pin
General-purpose I/O port
PPG ch.5 output pin
ADC analog 20 input pin
DEBUG I/F pin
A/D converter analog power supply
A/D converter analog power supply
A/D converter upper limit reference voltage
A/D converter upper limit reference voltage
A/D converter GND
A/D converter lower limit reference voltage
A/D converter GND
A/D converter lower limit reference voltage
External capacity connection output pin
+5.0V power supply
60
32, 64
1, 33, 55,
VSS
GND
59
* For I/O circuit types, see " I/O CIRCUIT TYPE".
18
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Oscillation feedback resistor: Approx.
1 M
X1
Clock input
X0
Standby control signal
CMOS hysteresis input
With 50 k pull-up resistor
B
Pull-up resistor
CMOS hysteresis input
Schmitt input
With high withstand voltage control
C
N-ch
Mode input
N-ch
High withstand voltage mode
input
N-ch
High withstand voltage control
N-ch
D
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
General-purpose I/O port
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
With 50k pull-up resistor control
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vcc)
19
D a t a S h e e t
Type
Circuit
Remarks
E
General-purpose I/O port
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
With 50 k pull-up resistor control
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
F
With analog input, general-purpose
I/O port
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
With 50 k pull-up resistor control
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vcc)
20
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Type
Circuit
Remarks
G
With analog input, general-purpose
I/O port
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
With 50 k pull-up resistor control
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
H
With I2C, general-purpose I/O port
CMOS level output
IOH=-3mA, IOL=3mA (at I2C output)
IOH=-2/-5mA, IOL=2/5mA (other
than above)
With 50 k pull-up resistor control
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vcc)
I
Open drain I/O
Digital output
TTL schmitt input
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
21
D a t a S h e e t
Type
Circuit
Remarks
K
With analog output,
general-purpose I/O port
CMOS level output
IOH=-2/-4mA, IOL=2/4mA
With 50 k pull-up resistor control
FlexRay input (0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vccc)
L
With analog output,
general-purpose I/O port
CMOS level output
IOH=-2/-4mA, IOL=2/4mA
With 50 k pull-up resistor control
FlexRay input (0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
22
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Type
Circuit
M
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Remarks
With D/A converter output,
general-purpose I/O port
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
With 50 k pull-up resistor control
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vcc)
23
D a t a S h e e t
HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-2Ea
24
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MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
25
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
26
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MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
27
D a t a S h e e t
HANDLING DEVICES
The latch-up prevention and pin processing are explained below.
For latch-up prevention
If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding
the ratings is applied between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs,
the power supply current increases excessively and device elements may be damaged by heat. Take care to
prevent any voltage from exceeding the maximum ratings in device application.
Also, the analog power supplies (AVCC0, AVCC1, AVRH0, AVRH1) and analog input must not exceed the
digital power supply (VCC5) when the power supply to the analog system is turned on or off.
In the correct power-on sequence, turn on the digital power supply voltage (VCC5) and analog power
supply voltages (AVCC0, AVCC1, AVRH0, AVRH1) simultaneously. Alternatively, turn on the digital
power supply voltage (VCC5) first, and then turn on the analog power supplies (AVCC0, AVCC1, AVRH0,
AVRH1).
Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to device
malfunction or latch-up. Connect a 2k or higher resistor to each of unused input pins for pull-up or
pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the
input state and treated in the same way as for the input pins.
28
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MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Power supply pins
The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should
be at the same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these
pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from
malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. As shown in
following figure, all VSS power supply pins must be treated in the similar way. If multiple VCC or VSS
systems are connected, the device cannot operate correctly even within the guaranteed operating range.
Power Supply Input Pins
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
The power supply pins should be connected to VCC and VSS of this device at the low impedance from the
power supply source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin
is recommended to use as a bypass capacitor between VCC and VSS pins.
Crystal oscillation circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be
designed to lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be
grounded to the close position to the device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
Mode pin (MD[1:0])
Connect the MD[1:0] mode pin to the VCC or VSS pin directly.
To prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each
mode pin and VCC or VSS pin on the printed circuit board. Also, use the low-impedance pin connection.
During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to
have 50μs or longer (between 0.2V and 2.7V) during power-on.
Notes during PLL clock operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock
may continue to operate at the free running frequency of the self oscillator circuit built in the PLL. This
operation is not guaranteed.
Treatment of A/D converter power supply pins
Connect the pins to have AVCC0 = AVCC1 = AVRH0 = AVRH1 = VCC,
AVSS0/AVRL0 = AVSS1/AVRL1 = VSS even if the A/D converter is not used.
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
29
D a t a S h e e t
Note on using external clock
The external clock is unsupported.
External direct clock input cannot use.
Power-on sequence of A/D converter power supply analog inputs
Be sure to turn on the digital power supply (VCC5) first, and then turn on the A/D converter power supplies
(AVCC0, AVCC1, AVRH0, AVRH1, AVRL0, AVRL1) and analog inputs (AN0 to AN14, AN16 to AN23).
Also, turn off the A/D converter power supplies (AVCC0, AVCC1, AVRH0, AVRH1, AVRL0, AVRL1) and
analog inputs (AN0 to AN14, AN16 to AN23) first, and then turn off the digital power supply (VCC5).
When the AVRH0 and AVRH1 pin voltages are turned on or off, they must not exceed AVCC0 and AVCC1.
Even if a common analog input pin is used as an input port, its input voltage must not exceed AVCC0 or
AVCC1. (However, the analog power supply voltage and digital power supply voltage can be turned on or
off simultaneously.)
Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to
assure the internal stabilization of the device. For the standard values, see the "Recommended Operating
Conditions" of the latest data sheet.
Function Switching of a Multiplexed Port
To switch between the port function and the multiplexed pin function, use the PFR (port function register).
For details, see "I/O PORTS" in Hardware Manual.
Low-power Consumption Mode
To set Sleep mode / Watch mode / Stop mode, or Watch mode (power-off) / Stop mode (power-off), see the
section "Launching Sleep mode / Watch mode / Stop mode" or "Launching Watch mode (power-off) / Stop
mode (power-off)" of "POWER CONSUMPTION CONTROL" in Hardware Manual, and follow the
procedures.
Do not perform the following when using a monitor debugger.
Do not set a break point for the low-power consumption transition program.
Do not execute an operation step for the low-power consumption transition program.
Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control
function, take care not to clear its status flag erroneously.
The program must be written not to clear the flag to the status bit, and to set the control bits to have the
desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can
access to a single bit only.) The Byte, Half-word, or Word access must be used to write data in the control
bits and status flag simultaneously. During this time, take care not to clear other bits (in this case, the bits of
status flag) erroneously.
Note: These points can be ignored because the bit instructions already take the points into consideration
for registers that support read-modify-write (RMW) operations. These points must be considered
when using the bit instructions for registers that do not support RMW operations.
30
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MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
BLOCK DIAGRAM
MB91F583AM/F584AM/F585AM
Regulator
F R 81s C PU core
M P U
CR oscillator
Ins truc tio n
D e b u g In te rfa ce
D ata
XBS
Power-on reset
X B S C ros sbar S w itch
Wild register
RA M
F la sh
Fro m Ma s te r
On-chip bus Layer 2
To S la ve
Fro m Ma s te r
On-chip bus Layer 1
To S la ve
On-chip bus
Main Flash/WorkFlash
RAMECC/Diagnosis
(XBS-RAM)
DMAC
Flash control register
Bus diagnosis register
Bus
performance
counter
Peripheral bus bridge
CAN (2ch)
FlexRay (1unit)
16
Bus bridge
RXDA-B,TXDA-B,
TXENA-B,STOPWT
RAMECC /
Diagnosis
Operating
mode register
B ac kUp
RA M
M D 0,M D 1,P040
Asynchronous bus bridge
Asynchronous bus bridge
(PCLK1
PCLK2)
FlexRay clock control
CAN prescaler
I/O port setting
(PCLK1
16-bit peripheral bus
32-bit peripheral bus
RX0- 1,
TX0- 1
32
PCLK2)
Multi-function serial interface (4ch)
CRC (2ch)
D/A converter
I / O P ort
TIN0- 3, TOT0- 3
TIOA0- 1, TIOB0- 1
MONCLK
(PCLK2
MTRCLK)
U/D counter (2ch)
Waveform generator (2 units (7ch))
Reload timer (4ch)
Free-run timer (6ch)
Base timer (2ch)
Input capture (4ch)
PPG (6ch)
Output compare (7ch)
Clock Monitor
A/D converter
DTTI0,RTO0-6
FRCK0-5
IN0-3
A DTG0-2,
A N0-14, 16-23
I / O P ort
TRG0- 1, PPG0- 5
DAOUT
Motor control extension function
WDT1 calibration
A IN0- 1, BIN0- 1,
Z IN0- 1
SOT0_0-1, SOT1-3,
SIN0_0-1, SIN1-3,
SCK0_0-1, SCK1-3,
SCS1-3
Bus bridge
(32-bit
16-bit)
External interrupt input (8ch)
Clock Supervisor
Interrupt request batch read
INT0- 7
Input cut-off
inhibiting signal
MM
CR oscillation (trimming)
Generation/clear of DMA transfer request
NMI
Watchdog timer (SW and HW)
RSTX
NMIX
Delay interrupt
Clock control
(clock setting, main timer, PLL timer)
Interrupt controller
Power shutdown control
Clock control register
(frequency dividing setting)
Reset control register
Low-power consumption setting register
Low-voltage detection (external
low-voltage detection)
Regulator control
Low-voltage detection (internal
low-voltage detection)
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
31
D a t a S h e e t
MB91F583AS/F584AS/F585AS
Regulator
F R 81s C P U core
Power-on reset
M P U
Ins truc tio n
D e b u g In te rfa ce
D ata
XBS
CR oscillator
X B S C rossbar S w itch
Wild register
RA M
F la sh
Fro m Ma s te r
On-chip bus Layer 2
To S la ve
Fro m Ma s te r
On-chip bus Layer 1
To S la ve
On-chip bus
Main Flash/WorkFlash
RAMECC/Diagnosis
(XBS-RAM)
DMAC
Flash control register
Bus diagnosis register
Bus
performance
counter
Peripheral bus bridge
CAN (1ch)
FlexRay (1unit)
16
Bus bridge
32
Operating
mode register
RAMECC /
Diagnosis
RXDA-B,TXDA-B,
TXENA-B,STOPWT
B ac kUp
RA M
M D0,M D 1,P040
Asynchronous bus bridge
Asynchronous bus bridge
(PCLK1
(PCLK1
PCLK2)
FlexRay clock control
CAN prescaler
I/O port setting
WDT1 calibration
16-bit peripheral bus
32-bit peripheral bus
RX0,
TX0
PCLK2)
Multi-function serial interface (2ch)
CRC (2ch)
D/A converter
I / O P ort
Waveform generator (2 units (7ch))
Reload timer (4ch)
Free-run timer (6ch)
Base timer (2ch)
Input capture (4ch)
PPG (6ch)
Output compare (7ch)
Clock Monitor
A/D converter
MONCLK
DTTI0,RTO0-6
FRCK0-5
IN0-3
A DTG0- 2,
A N0-14, 19, 20
I / O P ort
TRG0- 1, PPG0- 5
MTRCLK)
U/D counter (2ch)
TIN0- 3, TOT0- 3
TIOA0- 1, TIOB0- 1
DAOUT
Motor control extension function
(PCLK2
A IN0- 1, BIN0- 1 ,
Z IN0- 1
SOT0_0, SOT1,
SIN0_0, SIN1,
SCK0_0, SCK1,
SCS1
Bus bridge
(32-bit
16-bit)
External interrupt input (7ch)
Clock Supervisor
Interrupt request batch read
INT0- 6
Input cut-off
inhibiting signal
MM
CR oscillation (trimming)
Generation/clear of DMA transfer request
NMI
Watchdog timer (SW and HW)
RSTX
NMIX
Delay interrupt
Clock control
(clock setting, main timer, PLL timer)
Interrupt controller
Power shutdown control
Clock control register
(frequency dividing setting)
Reset control register
Low-power consumption setting register
Regulator control
Low-voltage detection (external
low-voltage detection)
Low-voltage detection (internal
low-voltage detection)
32
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
MEMORY MAP
MB91F583AM/F583AS
0000_0000 H
IO area
0000_4000 H
0000_6000 H
BackUp RAM(8KB)
0001_0000 H
RAM(32KB)
IO area
0001_8000 H
MB91F584AM/F584AS
0000_0000 H
0000_4000 H
0000_6000 H
0001_0000 H
000C_0000 H
Flash memory
(256+64)KB
Reserved
000F_FC00 H
Interrupt vector table
Reset vector table
0010_0000 H
RAM(48KB)
0007_0000 H
000E_0000 H
000F_FC00 H
WorkFlash
64KB
Flash memory
(384+64)KB
Reserved
Interrupt vector table
Reset vector table
Reserved
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
0001_0000 H
Reserved
0007_0000 H
000F_FC00 H
Flash memory
(512+64)KB
Interrupt vector table
Reset vector table
WorkFlash
64KB
Reserved
0033_0000 H
WorkFlash
64KB
0034_0000 H
Reserved
FFFF_FFFF H
RAM(48KB)
0010_0000 H
0034_0000 H
FFFF_FFFF H
0000_4000 H BackUp RAM(8KB)
0000_6000 H
IO area
Reserved
0033_0000 H
IO area
0001_C000 H
0010_0000 H
0034_0000 H
CONFIDENTIAL
IO area
0000_0000 H
Reserved
Reserved
0033_0000 H
BackUp RAM(8KB)
0001_C000 H
Reserved
0007_0000 H
IO area
MB91F585AM/F585AS
Reserved
FFFF_FFFF H
33
D a t a S h e e t
I/O MAP
The following I/O map shows the relationship between memory space and registers for peripheral
resources.
Legend of I/O Map
Read/Write attribute (R: Read W: Write)
Address
000090H
000094H
000098H
00009CH
0000A0H
0000A4H
0000A8H
Address offset value/Register name
+3
+2
+1
BT1TMR [R] H
BT1TMCR [R/W] B,H,W
00000000 00000000
00000000 00000000
BT1STC [R/W] B
00000000
BT1PCSR/BT1PRLL [R/W] H
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H
00000000 00000000
00000000 00000000
BTSEL [R/W] B
BTSSSR [W] B, H
----0000
--------------11
ADERH [R/W] B, H, W
ADERL [R/W] B, H, W
00000000 00000000
00000000 00000000
ADCR0 [R] B,H,W
ADCS1 [R/W] B,H,W ADCS0 [R/W] B,H,W ADCR1 [R] B,H,W
00000000
------XX
XXXXXXXX
00000000
ADCT1 [R/W] B,H,W ADCT0 [R/W] B,H,W ADSCH [R/W] B,H,W ADECH [R/W] B,H,W
00010000
00101100
---00000
---00000
+0
Block
Base timer 1
A/D converter
Data access attribute
B: Byte
H: Half-word
W: Word
(Note)
The access by the data access attribute
not described is disabled.
Initial register value after reset
The initial register values after reset are indicated as follows:
"1": Initial value "1"
"0": Initial value "0"
"X": Initial value undefined
"-": Reserved bit/Undefined bit
"*": Initial value "0" or "1" according to the setting
Note:
It is prohibited to access addresses not described here.
34
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MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
MB91F583AM/F584AM/F585AM
Address offset value/Register name
Address
+0
+1
+2
000000H
000004H
000008H
00000CH
000010H
|
000038H
00003CH
000040H
000044H
000064H
000068H
|
00007CH
000080H
000084H
000088H
00008CH
000090H
000094H
000098H
PDR01[R/W]
B,H,W
XXXXXXXX
PDR05[R/W]
B,H,W
-XXXXXXX
PDR09[R/W]
B,H,W
XXXXXXXX
-
PDR02[R/W]
B,H,W
XXXXXXXX
PDR06[R/W]
B,H,W
-XXXXXXX
PDR10[R/W]
B,H,W
-----XXX
-
PDR03[R/W]
B,H,W
XXXXXXXX
PDR07[R/W]
B,H,W
-----XXX
-
-
-
-
Reserved
WDTCR0[R/W]
B,H,W
-0--0000
DICR[R/W] B
-------0
WDTCPR0[W]
B,H,W
00000000
-
WDTCR1[R]
B,H,W
----0010
WDTCPR1[W]
B,H,W
00000000
Watchdog timer
[S]
-
-
Port data register
-
-
Reserved
-
Delay interrupt
-
-
Reserved
TMRLRA0[R/W] H
XXXXXXXX XXXXXXXX
TMRLRB0[R/W] H
XXXXXXXX XXXXXXXX
TMR0[R] H
XXXXXXXX XXXXXXXX
TMCSR0[R/W] B,H,W
00000000 0-000000
Reload timer 0
-
-
BT0TMR[R] H
00000000 00000000
BT0TMCR2[R/W]
BT0STC[R/W] B
B
-0-0-0-0
-------0
BT0PCSR/BT0PRLL[R/W] H
00000000 00000000
-
-
BT1TMR[R] H
00000000 00000000
BT1TMCR2[R/W]
BT1STC[R/W] B
B
-0-0-0-0
-------0
BT1PCSR/BT1PRLL[R/W] H
00000000 00000000
00009CH
BTSEL01[R/W] B
----0000
-
0000A0H
|
0000FCH
-
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Block
PDR00[R/W]
B,H,W
XXXXXXXX
PDR04[R/W]
B,H,W
XXXXXXXX
PDR08[R/W]
B,H,W
XXXXXXXX
-
000048H
|
00005CH
000060H
+3
-
-
Reserved
BT0TMCR[R/W] H
-0000000 00000000
-
Base timer 0
BT0PDUT/BT0PRLH/BT0DTBF
[R/W] H
00000000 00000000
BT1TMCR[R/W] H
-0000000 00000000
-
-
BT1PDUT/BT1PRLH/BT1DTBF[R/W]
H
00000000 00000000
BTSSSR[W] B,H
-------- ------11
-
-
Base timer 1
Base timer 0,1
Reserved
35
D a t a S h e e t
Address
000100H
000104H
000108H
00010CH
000110H
000114H
000118H
|
00011CH
000120H
000124H
000128H
00012CH
000130H
000134H
000138H
00013CH
000140 H
000144 H
000148H
|
0001FCH
000200H
000204H
000208H
00020CH
36
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
TMRLRA1[R/W] H
XXXXXXXX XXXXXXXX
TMRLRB1[R/W] H
XXXXXXXX XXXXXXXX
TMRLRA2[R/W] H
XXXXXXXX XXXXXXXX
TMRLRB2[R/W] H
XXXXXXXX XXXXXXXX
TMRLRA3[R/W] H
XXXXXXXX XXXXXXXX
TMRLRB3[R/W] H
XXXXXXXX XXXXXXXX
-
-
IRPR0H[R] B,H,W IRPR0L[R] B,H,W
00-----00-----IRPR2L[R]
IRPR2H[R] B,H,W
B,H,W *5
-------0000---IRPR4H[R] B,H,W IRPR4L[R] B,H,W
00-----000000-IRPR6H[R] B,H,W IRPR6L[R] B,H,W
0000---00-----IRPR8H[R] B,H,W IRPR8L[R] B,H,W
-------00-----IRPR10H[R]
IRPR10L[R]
B,H,W
B,H,W
00-----00-----IRPR12H[R]
IRPR12L[R]
B,H,W
B,H,W
000000000000000
IRPR14H[R]
IRPR14L[R]
B,H,W
B,H,W
00-----00-----IRPR16H[R]
IRPR16L[R]
B,H,W
B,H,W
00-----00-----IRPR18H[R]
IRPR18L[R]
B,H,W
B,H,W
-------000000--
-
PCN0[R/W] B,H,W
00000000 000000-0
PDUT0[W] H,W
XXXXXXXX XXXXXXXX
PCN1[R/W] B,H,W
00000000 000000-0
PDUT1[W] H,W
XXXXXXXX XXXXXXXX
+3
TMR1[R] H
XXXXXXXX XXXXXXXX
TMCSR1[R/W] B,H,W
00000000 0-000000
TMR2[R] H
XXXXXXXX XXXXXXXX
TMCSR2[R/W] B,H,W
00000000 0-000000
TMR3[R] H
XXXXXXXX XXXXXXXX
TMCSR3[R/W] B,H,W
00000000 0-000000
-
-
Block
Reload timer 1
Reload timer 2
Reload timer 3
Reserved
IRPR1H[R] B,H,W IRPR1L[R] B,H,W
00------------IRPR3H[R] B,H,W IRPR3L[R] B,H,W
00-----00-----IRPR5H[R] B,H,W
00-----IRPR7H[R] B,H,W
00-----IRPR9H[R] B,H,W
00-----IRPR11H[R]
B,H,W
00-----IRPR13H[R]
B,H,W
0000000IRPR15H[R]
B,H,W
00000000
IRPR17H[R]
B,H,W
00------
IRPR5L[R] B,H,W
00-----IRPR7L[R] B,H,W
-------IRPR9L[R] B,H,W
00-----IRPR11L[R]
Interrupt request
B,H,W
batch read
0000000register
IRPR13L[R]
B,H,W
00000000
IRPR15L[R]
B,H,W
0000---IRPR17L[R]B,H,W
--------
-
-
-
-
PCSR0[W] H,W
XXXXXXXX XXXXXXXX
PTMR0[R] H,W
11111111 11111111
PCSR1[W] H,W
XXXXXXXX XXXXXXXX
PTMR1[R] H,W
11111111 11111111
Reserved
PPG0
PPG1
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000210H
000214H
000218H
00021CH
000220H
000224H
000228H
00022CH
+0
0002C4H
0002C8H
0002CCH
0002D0H
0002D4H
0002D8H
0002DCH
0002E0H
0002E4H
0002E8H
0002ECH
0002F0H
0002F4H
0002F8H
0002FCH
000300H
000304H
000308H
00030CH
PCSR2[W] H,W
XXXXXXXX XXXXXXXX
PTMR2[R] H,W
11111111 11111111
PCSR3[W] H,W
XXXXXXXX XXXXXXXX
PTMR3[R] H,W
11111111 11111111
PCSR4[W] H,W
XXXXXXXX XXXXXXXX
PTMR4[R] H,W
11111111 11111111
PCSR5[W] H,W
XXXXXXXX XXXXXXXX
PTMR5[R] H,W
11111111 11111111
-
-
GTRS0[R/W] B,H,W
-0000000 -0000000
GTRS2[R/W] B,H,W
-0000000 -0000000
GTREN0[R/W] H,W
-------- --000000
GATEC0[R/W]
B,H,W
------00
GATEC4[R/W]
B,H,W
------00
RCRH0[W] H,W
00000000
PPG5
PPG Control
-
Reserved
GATEC2[R/W]
B,H,W
------00
-
-
-
UDCRL0[R]
B,H,W
00000000
CSR0[R] B
00000000
UDCRL1[R]
B,H,W
00000000
CSR1[R] B
00000000
-
-
-
-
-
-
-
-
PPG4
-
CCR1[R/W] B,H
00000000 -0001000
-
PPG3
Reserved
-
RCRL1[W] B,H,W UDCRH1[R] H,W
00000000
00000000
-
PPG2
-
CCR0[R/W] B,H
00000000 -0001000
RCRH1[W] H,W
00000000
Block
GTRS1[R/W] B,H,W
-0000000 -0000000
RCRL0[W] B,H,W UDCRH0[R] H,W
00000000
00000000
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
PCN2[R/W] B,H,W
00000000 000000-0
PDUT2[W] H,W
XXXXXXXX XXXXXXXX
PCN3[R/W] B,H,W
00000000 000000-0
PDUT3[W] H,W
XXXXXXXX XXXXXXXX
PCN4[R/W] B,H,W
00000000 000000-0
PDUT4[W] H,W
XXXXXXXX XXXXXXXX
PCN5[R/W] B,H,W
00000000 000000-0
PDUT5[W] H,W
XXXXXXXX XXXXXXXX
000230H
|
0002BCH
0002C0H
Address offset value/Register name
+1
+2
PPG GATE
Control
Reserved
U/D counter 0
U/D counter 1
Reserved
Reserved
Reserved
37
D a t a S h e e t
Address
+0
Address offset value/Register name
+1
+2
000310H
-
-
000314H
000318H
00031CH
-
-
-
-
-
000328H
00032CH
-
000330H
000334H
-
000338H
00033CH
-
000340H
000344H
-
000348H
00034CH
-
000350H
000354H
-
000358H
00035CH
-
000360H
000364H
-
000368H
00036CH
000370H
000374H
000378H
00037CH
000380H
000384H
000388H
00038CH
000390H
38
CONFIDENTIAL
Block
MPUCR[R/W] H
000000-0 ----0100
-
-
-
000320H
000324H
+3
-
DPVAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DPVSR[R/W] H
-------- 00000--0
DEAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DESR[R/W] H
-------- 00000--0
PABR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR0[R/W] H
000000-0 00000--0
PABR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR1[R/W] H
000000-0 00000--0
PABR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR2[R/W] H
000000-0 00000--0
PABR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR3[R/W] H
000000-0 00000--0
PABR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR4[R/W] H
000000-0 00000--0
PABR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR5[R/W] H
000000-0 00000--0
PABR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR6[R/W] H
000000-0 00000--0
PABR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR7[R/W] H
000000-0 00000--0
-
MPU [S]
(Only the CPU
can access this
area)
Reserved [S]
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000394H
000398H
00039CH
0003A0H
0003A4H
0003A8H
0003ACH
0003B0H
|
0003CCH
0003D0H
0003D4H
0003D8H
0003DCH
0003E0H
|
0003FCH
000400H
000404H
000408H
00040CH
000410H
000414H
000418H
00041CH
000420H
000424H
|
00043CH
+0
Address offset value/Register name
+1
+2
-
-
Block
-
-
-
-
-
-
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
Reserved [S]
-
-
-
-
Reserved [S]
ICSEL0[R/W]
B,H,W
-----000
ICSEL4[R/W]
B,H,W
-------0
ICSEL8[R/W]
B,H,W
-------0
ICSEL12[R/W]
B,H,W
-------0
ICSEL16[R/W]
B,H,W
-------0
ICSEL20[R/W]
B,H,W
-------0
ICSEL24[R/W]
B,H,W
-----000
-
ICSEL1[R/W]
B,H,W
-------0
ICSEL5[R/W]
B,H,W
-------0
ICSEL9[R/W]
B,H,W
-------0
ICSEL13[R/W]
B,H,W
-------0
ICSEL17[R/W]
B,H,W
-------0
ICSEL21[R/W]
B,H,W
-----000
ICSEL25[R/W]
B,H,W
-----000
-
ICSEL2[R/W]
B,H,W
-------0
ICSEL6[R/W]
B,H,W
-------0
ICSEL10[R/W]
B,H,W
------00
ICSEL14[R/W]
B,H,W
-------0
ICSEL18[R/W]
B,H,W
-------0
ICSEL22[R/W]
B,H,W
-----000
ICSEL26[R/W]
B,H,W
-------0
-
ICSEL3[R/W]
B,H,W
-------0
ICSEL7[R/W]
B,H,W
-----000
ICSEL11[R/W]
B,H,W
-------0
ICSEL15[R/W]
B,H,W
-------0
ICSEL19[R/W]
B,H,W
-------0
ICSEL23[R/W]
B,H,W
-----000
ICSEL27[R/W]
B,H,W
-------0
-
Generation and
clear of DMA
transfer request
-
-
-
-
Reserved
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
39
D a t a S h e e t
Address
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
000470H
|
00047CH
000480H
000484H
000488H
00048CH
40
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
+3
Block
ICR00[R/W]
B,H,W
---11111
ICR04[R/W]
B,H,W
---11111
ICR08[R/W]
B,H,W
---11111
ICR12[R/W]
B,H,W
---11111
ICR16[R/W]
B,H,W
---11111
ICR20[R/W]
B,H,W
---11111
ICR24[R/W]
B,H,W
---11111
ICR28[R/W]
B,H,W
---11111
ICR32[R/W]
B,H,W
---11111
ICR36[R/W]
B,H,W
---11111
ICR40[R/W]
B,H,W
---11111
ICR44[R/W]
B,H,W
---11111
ICR01[R/W]
B,H,W
---11111
ICR05[R/W]
B,H,W
---11111
ICR09[R/W]
B,H,W
---11111
ICR13[R/W]
B,H,W
---11111
ICR17[R/W]
B,H,W
---11111
ICR21[R/W]
B,H,W
---11111
ICR25[R/W]
B,H,W
---11111
ICR29[R/W]
B,H,W
---11111
ICR33[R/W]
B,H,W
---11111
ICR37[R/W]
B,H,W
---11111
ICR41[R/W]
B,H,W
---11111
ICR45[R/W]
B,H,W
---11111
ICR02[R/W]
B,H,W
---11111
ICR06[R/W]
B,H,W
---11111
ICR10[R/W]
B,H,W
---11111
ICR14[R/W]
B,H,W
---11111
ICR18[R/W]
B,H,W
---11111
ICR22[R/W]
B,H,W
---11111
ICR26[R/W]
B,H,W
---11111
ICR30[R/W]
B,H,W
---11111
ICR34[R/W]
B,H,W
---11111
ICR38[R/W]
B,H,W
---11111
ICR42[R/W]
B,H,W
---11111
ICR46[R/W]
B,H,W
---11111
ICR03[R/W]
B,H,W
---11111
ICR07[R/W]
B,H,W
---11111
ICR11[R/W]
B,H,W
---11111
ICR15[R/W]
B,H,W
---11111
ICR19[R/W]
B,H,W
---11111
ICR23[R/W]
B,H,W
---11111
ICR27[R/W]
B,H,W
---11111
ICR31[R/W]
B,H,W
---11111
ICR35[R/W]
B,H,W
---11111
ICR39[R/W]
B,H,W
---11111
ICR43[R/W]
B,H,W
---11111
ICR47[R/W]
B,H,W
---11111
Interrupt
controller [S]
-
-
-
-
Reserved [S]
RSTRR[R]
B,H,W
XXXX--XX
RSTCR[R/W]
B,H,W
111----0
STBCR[R/W]
B,H,W
000---11*
DIVR0[R/W]
B,H,W
000-----
-
DIVR2[R/W]
B,H,W
0011----
-
-
-
Reset control [S]
Power
consumption
control [S]
* Writing to
STBCR by
DMA is
disabled.
Reserved [S]
-
Clock control
[S]
-
Reserved [S]
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000490H
000494H
000498H
00049CH
0004A0H
0004A4H
0004A8H
|
0004ACH
0004B0H
0004B4H
|
0004C0H
0004C4H
+0
Address offset value/Register name
+1
+2
IORR1[R/W]
B,H,W
-0000000
IORR5[R/W]
B,H,W
-0000000
-
IORR2[R/W]
B,H,W
-0000000
IORR6[R/W]
B,H,W
-0000000
-
IORR3[R/W]
B,H,W
-0000000
IORR7[R/W]
B,H,W
-0000000
-
-
-
-
CAN prescaler
-
-
-
-
Reserved
-
-
-
-
Reserved
-
-
-
-
Reserved
CUCR1[R/W] B,H,W
-------- ---0--00
-
-
0004E0H
-
-
0004ECH
0004F0H
|
0004FCH
000500H
000504H
000508H
|
00050CH
000510H
-
-
-
-
-
-
CSELR[R/W]
B,H,W
-0----00
CMONR[R] B,H,W
-01---00
000518H
-
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
DMA transfer
request from a
peripheral [S]
Reserved
WDT1
calibration
Reserved
CSCFG[R/W]
CMCFG[R/W]
B,H,W
B,H,W
Clock monitor
---0---00000000
PLL2DIVG[R/W] PLL2MULG[R/W]
B,H,W
B,H,W
----0000
00000000
FlexRay
clock control *5
CLKR2[R/W]
B,H,W
000--000
-
PLLCR[R/W] B,H,W
00-00000 11110000
CONFIDENTIAL
-
PLL2DIVM[R/W] PLL2DIVN[R/W]
B,H,W
B,H,W
----0000
-0000000
PLL2CTRL[R/W] PLL2DIVK[R/W]
B,H,W
B,H,W
----0000
-------0
000514H
00051CH
CUTD1[R/W] B,H,W
11000011 01010000
CUTR1[R] B,H,W
-------- 00000000 00000000 00000000
0004CCH
|
0004DCH
0004E8H
Block
IORR0[R/W]
B,H,W
-0000000
IORR4[R/W]
B,H,W
-0000000
CANPRE[R/W]
B,H,W
---00000
0004C8H
0004E4H
+3
Reserved
Reserved
Reserved
MTMCR[R/W]
B,H,W
00001111
CSTBR[R/W]
B,H,W
----0000
CPUAR[R/W]
B,H,W
0---XXXX
-
-
Reserved
PTMCR[R/W]
B,H,W
00------
Clock control
[S]
-
Reset [S]
-
Reserved [S]
41
D a t a S h e e t
Address
+0
000520H
CCPSSELR[R/W]
B,H,W
-------0
000524H
-
000528H
-
00052CH
-
000530H
-
000534H
000538H
00053CH
000540H
|
00054CH
-
Address offset value/Register name
+1
+2
+3
Block
CCPSDIVR[R/W]
B,H,W
-000-000
CCPLLFBR[R/W] CCSSFBR0[R/W] CCSSFBR1[R/W]
B,H,W
B,H,W
B,H,W
-0000000
--000000
---00000
CCSSCCR0[R/W]
CCSSCCR1[R/W]
B,H,W
B,H,W
----0000
000----- -------Clock control 2
CCCGRCR0[R/W] CCCGRCR1[R/W] CCCGRCR2[R/W]
B,H,W
B,H,W
B,H,W
00----00
00000000
00000000
CCPMUCR0[R/W] CCPMUCR1[R/W]
B,H,W
B,H,W
0-----00
0--00000
-
-
-
-
-
000550H
EIRR0[R/W]
B,H,W
XXXXXXXX
ENIR0[R/W]
B,H,W
00000000
000554H
|
000568H
-
-
-
-
Reserved
00056CH
-
CSVCR[R/W] B
-0--1--0
-
-
CSV
000570H
CRTR[R/W]
B,H,W 01111111
-
-
-
WDT1
calibration
(trimming)
000574H
|
00057CH
-
-
-
-
Reserved
-
ELVR0[R/W] B,H,W
00000000 00000000
Reserved
External
interrupt
(INT0 to 7)
REGSEL[R/W]
B,H,W
01--110LVD5R[R/W]
B,H,W
-------1
-
-
-
Regulator
control
LVD5F[R/W]
B,H,W
001100-1
LVD[R/W]
B,H,W
01000--0
-
Low-voltage
detection
000588H
|
00058CH
-
-
-
-
Reserved
000590H
PMUSTR [R/W]
B,H,W
0-----1X
000594H
-
000598H
00059CH
0005A0H
|
0005FCH
-
000580H
000584H
42
CONFIDENTIAL
-
PMUCTLR[R/W] PWRTMCTL[R/W]
B,H,W
B,H,W
0-00--------011
PMUINTF1[R/W] PMUINTF2[R/W]
B,H,W
B,H,W
00000000
-00-----
-
-
-
PMU
-
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000600H
|
00060CH
000610H
|
00063CH
000640H
|
00064CH
000650H
|
00067CH
000680H
|
00068CH
000690H
|
0006BCH
0006C0H
|
0006CCH
0006D0H
|
0006F0H
0006F4H
0006F8H
|
0006FCH
000700H
000704H
|
00070CH
000710H
Address offset value/Register name
+1
+2
+0
+3
Block
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved
-
-
Reserved
-
-
-
-
BPCCRA[R/W] B
00000000
000714H
000718H
00071CH
Reserved
Reserved
-
BPCCRB[R/W] B BPCCRC[R/W] B
00000000
00000000
BPCTRA[R/W] W
00000000 00000000 00000000 00000000
BPCTRB[R/W] W
00000000 00000000 00000000 00000000
BPCTRC[R/W] W
00000000 00000000 00000000 00000000
-
Reserved
Bus performance
counter
000720H
|
0007F8H
-
-
-
-
Reserved
0007FCH
BMODR[R] B,H,W
XXXXXXXX
-
-
-
Operation mode
000800H
|
00083CH
-
-
-
-
Reserved [S]
Flash memory
register [S]
Reserved [S]
Reserved [S]
FCTLR[R/W] H
-0--1000 0--0----
-
-
FSTR[R/W] B
-----001
-
-
-
-
-
000840H
000844H
000848H
|
000854H
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
43
D a t a S h e e t
Address
+0
Address offset value/Register name
+1
+2
+3
000858H
-
-
WREN[R/W] H
00000000 00000000
00085CH
|
00087CH
-
-
-
000880H
000884H
000888H
00088CH
000890H
000894H
000898H
00089CH
0008A0H
0008A4H
0008A8H
0008ACH
0008B0H
0008B4H
0008B8H
0008BCH
0008C0H
0008C4H
0008C8H
0008CCH
0008D0H
0008D4H
0008D8H
0008DCH
0008E0H
44
CONFIDENTIAL
-
WRAR00[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR00[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR01[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR02[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR03[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR04[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR05[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR06[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR07[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR08[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR09[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR10[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Block
Wild register [S]
Reserved [S]
Wild register [S]
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
0008E8H
0008ECH
0008F0H
0008F4H
0008F8H
0008FCH
000BFCH
000C00H
000C04H
000C08H
000C0CH
000C10H
000C14H
000C18H
000C1CH
000C20H
000C24H
000C28H
000C2CH
000C30H
000C34H
000C38H
000C3CH
000C40H
000C44H
-
-
-
Block
Wild register [S]
UER[W] B,H,W
-------- -------X
DCCR0[R/W] W
0----000 --00--00 00000000 0-000000
DCSR0[R/W] H
DTCR0[R/W] H
0------- -----000
00000000 00000000
DSAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR1[R/W] W
0----000 --00--00 00000000 0-000000
DCSR1[R/W] H
DTCR1[R/W] H
0------- -----000
00000000 00000000
DSAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2[R/W] W
0----000 --00--00 00000000 0-000000
DCSR2[R/W] H
DTCR2[R/W] H
0------- -----000
00000000 00000000
DSAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3[R/W] W
0----000 --00--00 00000000 0-000000
DCSR3[R/W] H
DTCR3[R/W] H
0------- -----000
00000000 00000000
DSAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4[R/W] W
0----000 --00--00 00000000 0-000000
DCSR4[R/W] H
DTCR4[R/W] H
0------- -----000
00000000 00000000
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
WRDR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR13[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E4H
000900H
|
000BF8H
Address offset value/Register name
+1
+2
Reserved
OCDU
DMA controller
[S]
45
D a t a S h e e t
Address
000C4CH
000C50H
000C54H
000C58H
000C5CH
000C60H
000C64H
000C68H
000C6CH
000C70H
000C74H
000C78H
000C7CH
000DF4H
000DF8H
000DFCH
000E00H
000E04H
000E08H
000E0CH
000E10H
|
000E1CH
000E20H
000E24H
000E28H
000E2CH
46
CONFIDENTIAL
+3
DSAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5[R/W] W
0----000 --00--00 00000000 0-000000
DCSR5[R/W] H
DTCR5[R/W] H
0------- -----000
00000000 00000000
DSAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR6[R/W] W
0----000 --00--00 00000000 0-000000
DCSR6[R/W] H
DTCR6[R/W] H
0------- -----000
00000000 00000000
DSAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7[R/W] W
0----000 --00--00 00000000 0-000000
DCSR7[R/W] H
DTCR7[R/W] H
0------- -----000
00000000 00000000
DSAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C48H
000C80H
|
000DF0H
Address offset value/Register name
+1
+2
+0
-
-
-
DMA controller
[S]
-
DNMIR[R/W] B
DILVR[R/W] B
0------0
---11111
DMACR[R/W] W
0------- -------- 0------- -------DDR00[R/W] B,H DDR01[R/W] B,H DDR02[R/W] B,H DDR03[R/W] B,H
00000000
00000000
00000000
00000000
DDR04[R/W] B,H DDR05[R/W] B,H DDR06[R/W] B,H DDR07[R/W] B,H
00000000
-0000000
-0000000
-----000
DDR08[R/W] B,H DDR09[R/W] B,H DDR10[R/W] B,H
00000000
00000000
-----000
-
Block
-
-
-
-
-
PFR00[R/W] B,H
00000000
PFR04[R/W] B,H
00000000
PFR08[R/W] B,H
00000000
-
PFR01[R/W] B,H
00000000
PFR05[R/W] B,H
-0000000
PFR09[R/W] B,H
00000000
-
PFR02[R/W] B,H
00000000
PFR06[R/W] B,H
-0000000
PFR10[R/W] B,H
-----000
-
PFR03[R/W] B,H
00000000
PFR07[R/W] B,H
-----000
Reserved [S]
Data direction
register
Reserved
Port function
register
-
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000E30H
|
000E3CH
000E40H
000E44H
000E48H
000E4CH
000E50H
|
000E5CH
000E60H
000E64H
000E68H
000E6CH
000E70H
000E74H
000E78H
000E7CH
000E80H
000E84H
|
000EBCH
000EC0H
000EC4H
000EC8H
000ECCH
000ED0H
|
000EDCH
000EE0H
000EE4H
000EE8H
000EECH
000EF0H
|
000EFCH
000F00H
|
000F1CH
+0
Address offset value/Register name
+1
+2
-
-
-
Block
Reserved
PDDR00[R] B,H,W PDDR01[R] B,H,W PDDR02[R] B,H,W PDDR03[R] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDDR04[R] B,H,W PDDR05[R] B,H,W PDDR06[R] B,H,W PDDR07[R] B,H,W
Input data direct
XXXXXXXX
-XXXXXXX
-XXXXXXX
-----XXX
read register
PDDR08[R] B,H,W PDDR09[R] B,H,W PDDR10[R] B,H,W
XXXXXXXX
XXXXXXXX
-----XXX
-
-
-
-
Reserved
EPFR00[R/W] B,H EPFR01[R/W] B,H EPFR02[R/W] B,H EPFR03[R/W] B,H
------00
---00000
--000000
--000000
EPFR06[R/W] B,H EPFR07[R/W] B,H
------00
----0000
EPFR08[R/W]
EPFR09[R/W] B,H EPFR10[R/W] B,H
B,H *5
-------0
-0000000
----0000
Extended port
EPFR14[R/W] B,H
function register
--0-0-0-
-
-
-
Reserved
PPER00[R/W] B,H PPER01[R/W] B,H PPER02[R/W] B,H PPER03[R/W] B,H
00000000
00000000
00000000
00000000
PPER04[R/W] B,H PPER05[R/W] B,H PPER06[R/W] B,H PPER07[R/W] B,H
Port
00000000
-0000000
-0000000
-----000
pull-up/down
enable register
PPER08[R/W] B,H PPER09[R/W] B,H PPER10[R/W] B,H
00000000
00000000
-----000
-
-
-
-
Reserved
PILR00[R/W] B,H PILR01[R/W] B,H PILR02[R/W] B,H PILR03[R/W] B,H
11111111
11111111
11111111
11111111
PILR04[R/W] B,H PILR05[R/W] B,H PILR06[R/W] B,H PILR07[R/W] B,H
Port input level
11111111
-1111111
-1111111
-----111
selection register
PILR08[R/W] B,H PILR09[R/W] B,H PILR10[R/W] B,H
11111111
11111111
-----111
-
-
-
-
Reserved
-
-
-
-
Reserved
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
+3
47
D a t a S h e e t
Address
000F20H
000F24H
000F28H
000F2CH
000F30H
|
000F3CH
000F40H
000F44H
000F48H
000F4CH
+0
Address offset value/Register name
+1
+2
+3
Block
PODR00[R/W]
B,H
00000000
PODR04[R/W]
B,H
00000000
PODR08[R/W]
B,H
00000000
-
PODR01[R/W]
B,H
00000000
PODR05[R/W]
B,H
-0000000
PODR09[R/W]
B,H
00000000
-
PODR02[R/W]
B,H
00000000
PODR06[R/W]
B,H
-0000000
PODR10[R/W]
B,H
-----000
-
PODR03[R/W]
B,H
00000000
PODR07[R/W]
B,H
-----000
-
-
-
-
Reserved
-
-
Port input enable
register
-
-
Port key code
PORTEN[R/W]
B,H,W
------00
KEYCDR[R/W] H
00000000 00000000
ADERH[R/W] B,H
-------- 11111111
DAER[R/W] B,H
-------0
Port output drive
register
-
ADERL[R/W] B,H
-1111111 11111111
-
-
Analog input
enable register
Analog output
enable register
000F50H
|
000FFCH
-
-
-
-
Reserved
001000H
SACR[R/W]
B,H,W
-------0
PICD[R/W]
B,H,W
----0011
-
-
Synchronous/asy
nchronous
switch control
001004H
|
0010BCH
-
-
-
-
Reserved
0010C0H
-
-
-
CRCCR[R/W]
B,H,W
-0000000
CRCINIT[R/W] B,H,W
11111111 11111111 11111111 11111111
CRCIN[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR[R] B,H,W
11111111 11111111 11111111 11111111
0010C4H
0010C8H
0010CCH
0010D0H
-
-
CRC arithmetic
operation 0
CRCCR1[R/W]
B,H,W
-0000000
-
CRCINIT1[R/W] B,H,W
11111111 11111111 11111111 11111111
CRCIN1[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR1[R] B,H,W
11111111 11111111 11111111 11111111
0010D4H
0010D8H
0010DCH
CRC arithmetic
operation 1
0010E0H
|
0010FCH
-
-
-
-
Reserved
001100H
TCGS[R/W]
B,H,W
------00
-
-
TCGSE[R/W]
B,H,W
--000000
Free-run timer
simultaneous
activation
48
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
001104H
001108H
00110CH
001110H
001114H
001118H
00111CH
001120H
001124H
001128H
00112CH
001130H
001134H
001138H
00113CH
001140H
001144H
001148H
00114CH
001150H
001154H
001158H
00115CH
001160H
001164H
001168H
+0
Address offset value/Register name
+1
+2
CPCLRB0/CPCLR0[R/W] H,W
TCDT0[R/W] H,W
11111111 11111111
00000000 00000000
TCCS0[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB1/CPCLR1[R/W] H,W
TCDT1[R/W] H,W
11111111 11111111
00000000 00000000
TCCS1[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB2/CPCLR2[R/W] H,W
TCDT2[R/W] H,W
11111111 11111111
00000000 00000000
TCCS2[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB3/CPCLR3[R/W] H,W
TCDT3[R/W] H,W
11111111 11111111
00000000 00000000
TCCS3[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB4/CPCLR4[R/W] H,W
TCDT4[R/W] H,W
11111111 11111111
00000000 00000000
TCCS4[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB5/CPCLR5[R/W] H,W
TCDT5[R/W] H,W
11111111 11111111
00000000 00000000
TCCS5[R/W] B,H,W
00000000 01000000 ----0000 -------FRS0[R/W] B,H,W
-------- -000-000 -000-000 -000-000
FRS1[R/W] B,H,W
-------- -------- -000-000 -000-000
FRS2[R/W] B,H,W
-------- -000-000 -000-000 -000-000
FRS4[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
FRS5[R/W] B,H,W
-----000 -000-000 -000-000 -000-000
FRS6[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
OCCPB0/OCCP0[R/W] H,W
OCCPB1/OCCP1[R/W] H,W
00000000 00000000
00000000 00000000
OCMOD01[R/W]
OCS01[R/W] B,H,W
B,H,W
-110--00 00001100
------00
OCCPB2/OCCP2[R/W] H,W
OCCPB3/OCCP3[R/W] H,W
00000000 00000000
00000000 00000000
OCMOD23[R/W]
OCS23[R/W] B,H,W
B,H,W
-110--00 00001100
------00
OCCPB4/OCCP4[R/W] H,W
OCCPB5/OCCP5[R/W] H,W
00000000 00000000
00000000 00000000
OCMOD45[R/W]
OCS45[R/W] B,H,W
B,H,W
-110--00 00001100
------00
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
Block
Free-run timer 0
Free-run timer 1
Free-run timer 2
Free-run timer 3
Free-run timer 4
Free-run timer 5
Free-run timer
selection
Output compare
0/1
Output compare
2/3
Output compare
4/5
49
D a t a S h e e t
Address
+0
Address offset value/Register name
+1
+2
00116CH
OCCPB6/OCCP6[R/W] H,W
00000000 00000000
001170H
OCS67[R/W] B,H,W
-110--00 00001100
001174H
OCCPB8/OCCP8[R/W] H,W
00000000 00000000
001178H
OCS89[R/W] B,H,W
-110--00 00001100
00117CH
OCCPB10/OCCP10[R/W] H,W
00000000 00000000
001180H
OCS1011[R/W] B,H,W
-110--00 00001100
001184H
IPCP0[R] H,W
00000000 00000000
001188H
ICS01[R/W] B,H,W
------00 00000000
00118CH
001190H
001194H
001198H
00119CH
0011A0H
0011A4H
0011A8H
0011ACH
0011B0H
0011B4H
0011B8H
0011BCH
0011C0H
0011C4H
0011C8H
50
CONFIDENTIAL
+3
OCCPB7/OCCP7[R/W] H,W
00000000 00000000
OCMOD67[R/W]
B,H,W
------00
OCCPB9/OCCP9[R/W] H,W
00000000 00000000
OCMOD89[R/W]
B,H,W
------00
OCCPB11/OCCP11[R/W] H,W
00000000 00000000
OCMOD1011
[R/W] B,H,W
------00
IPCP1[R] H,W
00000000 00000000
LSYNS[R/W]
B,H,W
----0000
IPCP3[R] H,W
00000000 00000000
IPCP2[R] H,W
00000000 00000000
ICS23[R/W] B,H,W
------00 00000000
DTSR[R/W]
B,H,W
------10
TMRR0[R/W] H,W
TMRR1[R/W] H,W
00000000 00000001
00000000 00000001
TMRR2[R/W] H,W
00000000 00000001
DTSCR0[R/W]
DTSCR1[R/W]
DTSCR2[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
DTIR0[R/W]
DTMNS0[R/W]
B,H,W
B,H,W
000000-00---000
SIGCR10[R/W]
SIGCR20[R/W]
B,H,W
B,H,W
00000000
000000-1
PICS0[R/W] B,H,W
000000-- -------- -------- -------TMRR3[R/W] H,W
TMRR4[R/W] H,W
00000000 00000001
00000000 00000001
TMRR5[R/W] H,W
00000000 00000001
DTSCR3[R/W]
DTSCR4[R/W]
DTSCR5[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
Block
Output compare
6/7
Output compare
8/9
Output compare
10/11
Input capture 0/1
Input capture 2/3
Reserved
Reserved
DTTI selection
Waveform
generator
0/1/2
Waveform
generator
3/4/5
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
0011CCH
0011D0H
0011D4H
0011D8H
0011DCH
0011E0H
0011E4H
0011E8H
0011ECH
0011F0H
0011F4H
0011F8H
0011FCH
001200H
001204H
001208H
00120CH
001210H
001214H
001218H
00121CH
001220H
001224H
001228H
00122CH
001230H
001234H
001238H
00123CH
+0
-
-
Address offset value/Register name
+1
+2
DTIR1[R/W]
B,H,W
000000-SIGCR11[R/W]
B,H,W
00000000
-
DTMNS1[R/W]
B,H,W
00---000
SIGCR21[R/W]
B,H,W
-------1
Block
Waveform
generator
3/4/5
ADTSS[R/W]
B,H,W
-------0
-
-
-
-
-
-
ADTSE[R/W] B,H,W
-------- 00000000 -0000000 00000000
ADCOMP0/ADCOMPB0[R/W] H,W
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP2/ADCOMPB2[R/W] H,W
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP4/ADCOMPB4[R/W] H,W
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP6/ADCOMPB6[R/W] H,W
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP8/ADCOMPB8[R/W] H,W
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP10/ADCOMPB10[R/W] H,W ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP12/ADCOMPB12[R/W] H,W ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP14/ADCOMPB14[R/W] H,W
00000000 00000000
ADCOMP16/ADCOMPB16[R/W] H,W ADCOMP17/ADCOMPB17[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP18/ADCOMPB18[R/W] H,W ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP20/ADCOMPB20[R/W] H,W ADCOMP21/ADCOMPB21[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP22/ADCOMPB22[R/W] H,W ADCOMP23/ADCOMPB23[R/W] H,W
00000000 00000000
00000000 00000000
ADTCS0[R/W] B,H,W
ADTCS1[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS2[R/W] B,H,W
ADTCS3[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS4[R/W] B,H,W
ADTCS5[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS6[R/W] B,H,W
ADTCS7[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS8[R/W] B,H,W
ADTCS9[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS10[R/W] B,H,W
ADTCS11[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS12[R/W] B,H,W
ADTCS13[R/W] B,H,W
00000000 0010-000
00000000 0010-000
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
+3
12-bit A/D
converter
51
D a t a S h e e t
Address
001240H
001244H
001248H
00124CH
001250H
001254H
001258H
00125CH
001260H
001264H
001268H
00126CH
001270H
001274H
001278H
00127CH
001280H
001284H
001288H
00128CH
001290H
001294H
001298H
00129CH
0012A0H
+0
Address offset value/Register name
+1
+2
ADTCS14[R/W] B,H,W
00000000 0010-000
ADTCS16[R/W] B,H,W
00000000 00100000
ADTCS18[R/W] B,H,W
00000000 00100000
ADTCS20[R/W] B,H,W
00000000 00100000
ADTCS22[R/W] B,H,W
00000000 00100000
ADTCD0[R] B,H,W
10--0000 00000000
ADTCD2[R] B,H,W
10--0000 00000000
ADTCD4[R] B,H,W
10--0000 00000000
ADTCD6[R] B,H,W
10--0000 00000000
ADTCD8[R] B,H,W
10--0000 00000000
ADTCD10[R] B,H,W
10--0000 00000000
ADTCD12[R] B,H,W
10--0000 00000000
ADTCD14[R] B,H,W
10--0000 00000000
ADTCD16[R] B,H,W
10--0000 00000000
ADTCD18[R] B,H,W
10--0000 00000000
ADTCD20[R] B,H,W
10--0000 00000000
ADTCD22[R] B,H,W
10--0000 00000000
-
0012A4H
ADCS0[R/W] B,H,W
0------- --------
0012A8H
ADCS1[R/W] B,H,W
0------- --------
0012ACH
ADCS2[R/W] B,H,W
0------- --------
52
CONFIDENTIAL
+3
Block
ADTCS17[R/W] B,H,W
00000000 00100000
ADTCS19[R/W] B,H,W
00000000 00100000
ADTCS21[R/W] B,H,W
00000000 00100000
ADTCS23[R/W] B,H,W
00000000 00100000
ADTCD1[R] B,H,W
10--0000 00000000
ADTCD3[R] B,H,W
10--0000 00000000
ADTCD5[R] B,H,W
10--0000 00000000
ADTCD7[R] B,H,W
10--0000 00000000
ADTCD9[R] B,H,W
10--0000 00000000
ADTCD11[R] B,H,W
10--0000 00000000
ADTCD13[R] B,H,W
10--0000 00000000
12-bit A/D
converter
ADTCD17[R] B,H,W
10--0000 00000000
ADTCD19[R] B,H,W
10--0000 00000000
ADTCD21[R] B,H,W
10--0000 00000000
ADTCD23[R] B,H,W
10--0000 00000000
ADMD0[R/W]
ADCH0[R] B,H,W
B,H,W
-----000
----0000
ADMD1[R/W]
ADCH1[R] B,H,W
B,H,W
-----000
----0000
ADMD2[R/W]
ADCH2[R] B,H,W
B,H,W
-----000
----0000
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
0012B0H
0012B4H
0012B8H
|
0012FCH
001300H
001304H
001308H
00130CH
001310H
001314H
001318 H
00131CH
001320H
001324H
001328H
|
00132CH
001330H
001334H
|
0013FCH
+0
Address offset value/Register name
+1
+2
MTRCSR[R/W]
B,H,W
-------0
RTOSEL0[R/W]
B,H,W
--000000
-
-
-
RTOSEL1[R/W]
B,H,W
-------0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Motor control
extension
function
Reserved
Reserved
-
-
001400H
DACR[R/W]
B,H,W
-------0
-
001404H
|
0014FCH
-
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
Block
-
-
CONFIDENTIAL
+3
-
-
DADR[R/W] H,W
------XX XXXXXXXX
-
-
Reserved
DAC
Reserved
53
D a t a S h e e t
Address
001500H
001504H
001508H
00150CH
+0
Address offset value/Register name
+1
+2
SCR0/(IBCR0)
SMR0[R/W]
[R/W] B,H,W
B,H,W
0--00000
000000-0
-/(RDR10/(TDR10))[R/W] B,H,W
-------- -------- *3
SACSR0[R/W] B,H,W
0----000 00000000
STMCR0[R/W] B,H,W
00000000 00000000
001510H
-
-
001514H
001518H
-
-
00151CH
BGR0[R/W] H,W
00000000 00000000
001520H
001524H
001528H
00152CH
001530H
FCR10[R/W]
B,H,W
00-00100
FCR00[R/W]
B,H,W
-0000000
SCR1[R/W]
SMR1[R/W]
B,H,W
B,H,W
0--00000
000000-0
-/(RDR11/(TDR11))[R/W] B,H,W
-------- -------- *3
SACSR1[R/W] B,H,W
0----000 00000000
STMCR1[R/W] B,H,W
00000000 00000000
001534H
-/(SCSTR31)
[R/W] B,H,W
-------- *3
-/(SCSTR21)
[R/W] B,H,W
-------- *3
001538H
-
-
00153CH
-
-
001540H
001544H
54
CONFIDENTIAL
BGR1[R/W] H,W
00000000 00000000
FCR11[R/W]
FCR01[R/W]
B,H,W
B,H,W
00-00100
-0000000
+3
Block
SSR0[R/W]
ESCR0/(IBSR0) Multi Function
B,H,W
[R/W] B,H,W
Serial I/F 0
0--00011
00000000
*1: Byte access
is possible only
RDR00/(TDR00)[R/W] B,H,W
for access to
-------0 00000000 *1
lower 8 bits.
STMR0[R] B,H,W
*2:
Reserved
00000000 00000000
because
I2C
-/(SFUR0) [R/W] B,H,W
*4
mode is not set
-------- -------immediately
-/(SFLR10) [R/W] -/(SFLR00) [R/W]
after reset
B,H,W
B,H,W
*4
*4
*3:
Reserved
--------------because
CSIO
mode
is
not
set
immediately
-/(ISMK0)[R/W]
-/(ISBA0)[R/W]
after reset
B,H,W
B,H,W
*2
*2
*4:
Reserved
--------------because LIN2.1
FBYTE20[R/W]
FBYTE10[R/W] mode is not set
B,H,W
B,H,W
immediately
00000000
00000000
after reset
SSR1[R/W]
ESCR1[R/W]
B,H,W
B,H,W
0--00011
00000000
RDR01/(TDR01)[R/W] B,H,W
Multi Function
-------0 00000000 *1
Serial I/F 1
STMR1[R] B,H,W
*1: Byte access
00000000 00000000
is possible only
-/(SCSCR1/SFUR1) [R/W] B,H,W
for access to
-------- -------- *3 *4
lower 8 bits.
-/(SCSTR11/
-/(SCSTR01/
*3: Reserved
SFLR11) [R/W]
SFLR01) [R/W]
because CSIO
B,H,W
B,H,W
mode is not set
-------- *3 *4
-------- *3 *4
immediately
after reset
*4: Reserved
TBYTE01[R/W]
because LIN2.1
B,H,W
mode is not set
00000000
immediately
after reset
FBYTE21[R/W]
FBYTE11[R/W]
B,H,W
B,H,W
00000000
00000000
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
001548H
00154CH
001550H
001554H
+0
Address offset value/Register name
+1
+2
SCR2/(IBCR2)
SMR2[R/W]
[R/W] B,H,W
B,H,W
0--00000
000000-0
-/(RDR12/(TDR12))[R/W] B,H,W
-------- -------- *3
SACSR2[R/W] B,H,W
0----000 00000000
STMCR2[R/W] B,H,W
00000000 00000000
001558H
-/(SCSTR32)
[R/W] B,H,W
-------- *3
-/(SCSTR22)
[R/W] B,H,W
-------- *3
00155CH
-
-
001560H
-
-
001564H
BGR2[R/W] H,W
00000000 00000000
001568H
00156CH
001570H
001574H
001578H
FCR12[R/W]
FCR02[R/W]
B,H,W
B,H,W
00-00100
-0000000
SCR3/(IBCR3)
SMR3[R/W]
[R/W] B,H,W
B,H,W
0--00000
000000-0
-/(RDR13/(TDR13))[R/W] B,H,W
-------- -------- *3
SACSR3[R/W] B,H,W
0----000 00000000
STMCR3[R/W] B,H,W
00000000 00000000
00157CH
-/(SCSTR33)
[R/W] B,H,W
-------- *3
-/(SCSTR23)
[R/W] B,H,W
-------- *3
001580H
-
-
001584H
-
-
001588H
BGR3[R/W] H,W
00000000 00000000
00158CH
FCR13[R/W]
B,H,W
00-00100
FCR03[R/W]
B,H,W
-0000000
001590H
|
001FFCH
-
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
SSR2[R/W]
ESCR2/(IBSR2)
B,H,W
[R/W] B,H,W
0--00011
00000000
RDR02/(TDR02)[R/W] B,H,W
-------0 00000000 *1
STMR2[R] B,H,W
00000000 00000000
-/(SCSCR2/SFUR2) [R/W] B,H,W
-------- -------- *3 *4
-/(SCSTR12/
-/(SCSTR02/
SFLR12) [R/W]
SFLR02) [R/W]
B,H,W
B,H,W
-------- *3 *4
-------- *3 *4
TBYTE02[R/W]
B,H,W
00000000
-/(ISMK2)[R/W]
-/(ISBA2)[R/W]
B,H,W
B,H,W
-------- *2
-------- *2
FBYTE22[R/W]
FBYTE12[R/W]
B,H,W
B,H,W
00000000
00000000
SSR3[R/W]
ESCR3/(IBSR3)
B,H,W
[R/W] B,H,W
0--00011
00000000
RDR03/(TDR03)[R/W] B,H,W
-------0 00000000 *1
STMR3[R] B,H,W
00000000 00000000
-/(SCSCR3/SFUR3) [R/W] B,H,W
-------- -------- *3 *4
-/(SCSTR13/
-/(SCSTR03/
SFLR13) [R/W]
SFLR03) [R/W]
B,H,W
B,H,W
-------- *3 *4
-------- *3 *4
TBYTE03[R/W]
B,H,W
00000000
-/(ISMK3)[R/W]
-/(ISBA3)[R/W]
B,H,W
B,H,W
-------- *2
-------- *2
FBYTE23[R/W]
FBYTE13[R/W]
B,H,W
B,H,W
00000000
00000000
-
-
Block
Multi Function
Serial I/F 2
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
Multi Function
Serial I/F 3
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
Reserved
55
D a t a S h e e t
Address
002000H
002004H
002008H
00200CH
002010H
002014H
002018H
00201CH
002020H
002024H
002028H,
00202CH
002030H,
002034H
002038H,
00203CH
002040H
002044H
002048H
00204CH
002050H
002054H
002058H,
00205CH
002060H,
002064H
002068H
|
00207CH
002080H
002084H
002088H
00208CH
002090H
002094H
56
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
CTRLR0[R/W] B,H,W
-------- 000-0001
ERRCNT0 [R] B,H,W
00000000 00000000
INTR0[R] B,H,W
00000000 00000000
BRPER0[R/W] B,H,W
-------- ----0000
IF1CREQ0[R/W] B,H,W
0------- 00000001
IF1MSK20[R/W] B,H,W
11-11111 11111111
IF1ARB20[R/W] B,H,W
00000000 00000000
IF1MCTR0[R/W] B,H,W
00000000 0---0000
IF1DTA10[R/W] B,H,W
00000000 00000000
IF1DTB10[R/W] B,H,W
00000000 00000000
+3
Block
STATR0[R/W] B,H,W
-------- 00000000
BTR0[R/W] B,H,W
-0100011 00000001
TESTR0[R/W] B,H,W
-------- X00000-IF1CMSK0[R/W] B,H,W
-------- 00000000
IF1MSK10[R/W] B,H,W
11111111 11111111
IF1ARB10[R/W] B,H,W
00000000 00000000
IF1DTA20[R/W] B,H,W
00000000 00000000
IF1DTB20[R/W] B,H,W
00000000 00000000
-
Reserved (IF1 data mirror)
-
-
IF2CREQ0[R/W] B,H,W
0------- 00000001
IF2MSK20[R/W] B,H,W
11-11111 11111111
IF2ARB20[R/W] B,H,W
00000000 00000000
IF2MCTR0[R/W] B,H,W
00000000 0---0000
IF2DTA10[R/W] B,H,W
00000000 00000000
IF2DTB10[R/W] B,H,W
00000000 00000000
IF2CMSK0[R/W] B,H,W
-------- 00000000
IF2MSK10[R/W] B,H,W
11111111 11111111
IF2ARB10[R/W] B,H,W
00000000 00000000
-
-
CAN 0
64msb
IF2DTA20[R/W] B,H,W
00000000 00000000
IF2DTB20[R/W] B,H,W
00000000 00000000
Reserved (IF2 data mirror)
-
-
TREQR20[R] B,H,W
00000000 00000000
TREQR40[R] B,H,W
00000000 00000000
NEWDT20[R] B,H,W
00000000 00000000
NEWDT40[R] B,H,W
00000000 00000000
TREQR10[R] B,H,W
00000000 00000000
TREQR30[R] B,H,W
00000000 00000000
NEWDT10[R] B,H,W
00000000 00000000
NEWDT30[R] B,H,W
00000000 00000000
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
002098H
00209CH
0020A0H
0020A4H
0020A8H
0020ACH
0020B0H
0020B4H
0020B8H
0020BCH
0020C0H
|
0020FCH
002100H
002104H
002108H
00210CH
002110H
002114H
002118H
00211CH
002120H
002124H
002128H,
00212CH
002130H,
002134H
002138H,
00213CH
002140H
002144H
002148H
00214CH
002150H
002154H
+0
Address offset value/Register name
+1
+2
INTPND20[R] B,H,W
00000000 00000000
INTPND40[R] B,H,W
00000000 00000000
MSGVAL20[R] B,H,W
00000000 00000000
MSGVAL40[R] B,H,W
00000000 00000000
-
INTPND10[R] B,H,W
00000000 00000000
INTPND30[R] B,H,W
00000000 00000000
MSGVAL10[R] B,H,W
00000000 00000000
MSGVAL30[R] B,H,W
00000000 00000000
-
-
-
CTRLR1[R/W] B,H,W
-------- 000-0001
ERRCNT1 [R] B,H,W
00000000 00000000
INTR1[R] B,H,W
00000000 00000000
BRPER1[R/W] B,H,W
-------- ----0000
IF1CREQ1[R/W] B,H,W
0------- 00000001
IF1MSK21[R/W] B,H,W
11-11111 11111111
IF1ARB21[R/W] B,H,W
00000000 00000000
IF1MCTR1[R/W] B,H,W
00000000 0---0000
IF1DTA11[R/W] B,H,W
00000000 00000000
IF1DTB11[R/W] B,H,W
00000000 00000000
STATR1[R/W] B,H,W
-------- 00000000
BTR1[R/W] B,H,W
-0100011 00000001
TESTR1[R/W] B,H,W
-------- X00000--
Block
CAN 0
64msb
IF1CMSK1[R/W] B,H,W
-------- 00000000
IF1MSK11[R/W] B,H,W
11111111 11111111
IF1ARB11[R/W] B,H,W
00000000 00000000
IF1DTA21[R/W] B,H,W
00000000 00000000
IF1DTB21[R/W] B,H,W
00000000 00000000
-
CAN 1
64msb
Reserved (IF1 data mirror)
-
-
IF2CREQ1[R/W] B,H,W
0------- 00000001
IF2MSK21[R/W] B,H,W
11-11111 11111111
IF2ARB21[R/W] B,H,W
00000000 00000000
IF2MCTR1[R/W] B,H,W
00000000 0---0000
IF2DTA11[R/W] B,H,W
00000000 00000000
IF2DTB11[R/W] B,H,W
00000000 00000000
IF2CMSK1[R/W] B,H,W
-------- 00000000
IF2MSK11[R/W] B,H,W
11111111 11111111
IF2ARB11[R/W] B,H,W
00000000 00000000
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
IF2DTA21[R/W] B,H,W
00000000 00000000
IF2DTB21[R/W] B,H,W
00000000 00000000
57
D a t a S h e e t
Address
+0
002158H,
00215CH
002160H,
002164H
002168H
|
00217CH
002180H
002184H
002188H
00218CH
002190H
002194H
002198H
00219CH
0021A0H
0021A4H
0021A8H
0021ACH
0021B0H
0021B4H
0021B8H
0021BCH
0021C0H
|
0021FCH
002200H
|
0022FCH
002300H
002304H
002308H
00230CH
|
002FFCH
003000H
003004H
003008H
58
CONFIDENTIAL
Address offset value/Register name
+1
+2
-
+3
Block
Reserved (IF2 data mirror)
-
-
TREQR21[R] B,H,W
00000000 00000000
TREQR41[R] B,H,W
00000000 00000000
NEWDT21[R] B,H,W
00000000 00000000
NEWDT41[R] B,H,W
00000000 00000000
INTPND21[R] B,H,W
00000000 00000000
INTPND41[R] B,H,W
00000000 00000000
MSGVAL21[R] B,H,W
00000000 00000000
MSGVAL41[R] B,H,W
00000000 00000000
-
TREQR11[R] B,H,W
00000000 00000000
TREQR31[R] B,H,W
00000000 00000000
NEWDT11[R] B,H,W
00000000 00000000
NEWDT31[R] B,H,W
00000000 00000000
INTPND11[R] B,H,W
00000000 00000000
INTPND31[R] B,H,W
00000000 00000000
MSGVAL11[R] B,H,W
00000000 00000000
MSGVAL31[R] B,H,W
00000000 00000000
-
-
-
-
-
DFCTLR[R/W] B,H,W
-0------ -------FLIFCTLR[R/W]
B,H,W
---0--00
-
-
-
-
SEEARX[R] B,H,W
--000000 00000000
EECSRX[R/W]
B,H,W
----00-0
-
CAN 1
64msb
Reserved
FLIFFER1[R/W]
B,H,W
--------
DFSTR[R/W]
B,H,W
-----001
FLIFFER2[R/W]
B,H,W
--------
WorkFlash
-
-
Reserved
-
DEEARX[R] B,H,W
--000000 00000000
EFEARX[R/W] B,H,W
--000000 00000000
XBS RAM
ECC control
register
EFECRX[R/W] B,H,W
-------0 00000000 00000000
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
00300CH
003010H
003014H
003018H
00301CH
003020H
003024H
003028H
00302CH
003030H
003034H
003038H
00303CH
003040H
003044H
003048H
|
0030FCH
003100H
003104H
003108H
00310CH
003110H
003114H
003118H
00311CH
003120H
+0
Address offset value/Register name
+1
+2
TEAR0X[R] B,H,W
000----- -------- --000000 00000000
TEAR1X[R] B,H,W
000----- -------- --000000 00000000
TEAR2X[R] B,H,W
000----- -------- --000000 00000000
TAEARX[R/W] B,H,W
TASARX[R/W] B,H,W
--101111 11111111
--000000 00000000
TFECRX[R/W]
TICRX[R/W]
TTCRX[R/W] B,H,W
B,H,W
B,H,W
------00 00001100
----0000
----0000
TSRCRX[R/W]
TKCCRX[R/W]
B,H,W
B,H,W
0------00----00
SEEARA[R] B,H,W
DEEARA[R] B,H,W
--000000 00000000
--000000 00000000
EECSRA[R/W]
EFEARA[R/W] B,H,W
B,H,W
--000000 00000000
----00-0
EFECRA[R/W] B,H,W
-------0 00000000 00000000
TEAR0A[R] B,H,W
000----- -------- -----000 00000000
TEAR1A[R] B,H,W
000----- -------- -----000 00000000
TEAR2A[R] B,H,W
000----- -------- -----000 00000000
TAEARA[R/W] B,H,W
TASARA[R/W] B,H,W
-----111 11111111
-----000 00000000
TFECRA[R/W]
TICRA[R/W]
TTCRA[R/W] B,H,W
B,H,W
B,H,W
------00 00001100
----0000
----0000
TSRCRA[R/W]
TKCCRA[R/W]
B,H,W
B,H,W
0------00----00
-
-
-
-
BUSDIGSR0[R/W] H,W
BUSDIGSR1[R/W] H,W
00000000 0-----00
00000000 0-----00
BUSDIGSR2[R/W] H,W
BUSTSTR0[R/W] H,W
00000000 0-----00
00--0000 00000000
BUSADR0[R] W
00000000 00000000 00000000 00000000
BUSADR1[R] W
00000000 00000000 00000000 00000000
BUSADR2[R] W
00000000 00000000 00000000 00000000
BUSDIGSR3[R/W] H,W
00000000 0-----00
BUSDIGSR4[R/W] H,W
BUSTSTR1[R/W] H,W
00000000 0-----00
00--0000 00000000
BUSADR3[R] W
00000000 00000000 00000000 00000000
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
Block
XBS RAM
diagnosis
register
Backup RAM
ECC control
register
Backup RAM
diagnosis
register
Reserved
Bus diagnosis
59
D a t a S h e e t
Address
+0
-
-
-
-
-
-
-
-
00D024H
00D028H
00D02CH
00D030H
00D034H
00D038H
00D03CH
00D040H
00D044H
00D048H
00D04CH
00D050H
-
-
Reserved
Backup RAM
area
-
Reserved
FlexRay
CIF *5
-
-
Reserved
-
-
FlexRay
GIF *5
LCK[R/W] W
-------- -------- -------- 00000000
EIR[R/W] W
-----000 -----000 ----0000 00000000
SIR[R/W] W
------00 ------00 00000000 00000000
EILS[R/W] W
-----000 -----000 ----0000 00000000
SILS[R/W] W
------11 ------11 11111111 11111111
EIES[R/W] W
-----000 -----000 ----0000 00000000
EIER[R/W] W
-----000 -----000 ----0000 00000000
SIES[R/W] W
------00 ------00 00000000 00000000
SIER[R/W] W
------00 ------00 00000000 00000000
ILE[R/W] W
-------- -------- -------- ------00
T0C[R/W] W
--000000 00000000 -0000000 ------00
T1C[R/W] W
--000000 00000010 -------- ------00
STPW1[R/W] W
--000000 00000000 --000000 -0000000
STPW2[R] W
-----000 00000000 -----000 00000000
00D020H
CONFIDENTIAL
-
-
00D01CH
60
-
CIF0[R] W
00000100 11111111 01011011 11111111
CIF1[R/W] W
00000000 -------0 -0000000 --------
00D004H
00D054H
|
00D07CH
-
Block
Bus diagnosis
Backup RAM
00D000H
00D008H
|
00D00CH
00D010H
00D014H
00D018H
+3
BUSADR4[R] W
00000000 00000000 00000000 00000000
003124H
003128H
|
003FFCH
004000H
|
005FFCH
006000H
|
00CFFCH
Address offset value/Register name
+1
+2
-
FlexRay
INT *5
-
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
00D080H
00D084H
00D088H
00D08CH
00D090H
00D094H
00D098H
00D09CH
00D0A0H
00D0A4H
00D0A8H
00D0ACH
00D0B0H
00D0B4H
00D0B8H
00D0BCH
00D0C0H
00D0C4H
00D0C8H
+0
Address offset value/Register name
+1
+2
SUCC1[R/W] W
----1100 01000000 00010-00 1---0000
SUCC2[R/W] W
----0001 ---00000 00000101 00000100
SUCC3[R/W] W
-------- -------- -------- 00010001
NEMC[R/W] W
-------- -------- -------- ----0000
PRTC1[R/W] W
000010-0 01001100 0000-110 00110011
PRTC2[R/W] W
--001111 00101101 --001010 --001110
MHDC[R/W] W
---00000 00000000 -------- -0000000
GTUC1[R/W] W
-------- ----0000 00000010 10000000
GTUC2[R/W] W
-------- ----0010 --000000 00001010
GTUC3[R/W] W
-0000010 -0000010 00000000 00000000
GTUC4[R/W] W
--000000 00001000 --000000 00000111
GTUC5[R/W] W
00001110 ---00000 00000000 00000000
GTUC6[R/W] W
-----000 00000010 -----000 00000000
GTUC7[R/W] W
------00 00000010 ------00 00000100
GTUC8[R/W] W
---00000 00000000 -------- --000010
GTUC9[R/W] W
-------- ------00 ---00001 --000001
GTUC10[R/W] W
-----000 00000010 --000000 00000101
GTUC11[R/W] W
-----000 -----000 ------00 ------00
00D0CCH
|
00D0FCH
00D100H
00D104H
00D114H
00D118H
00D11CH
FlexRay
SUC *5
FlexRay
NEM *5
FlexRay
PRT *5
FlexRay
MHD *5
Reserved
FlexRay
GTU *5
Reserved
CCSV[R] W
--000000 00010000 -100--00 00000000
CCEV[R] W
-------- -------- ---00000 00--0000
FlexRay
SUC *5
-
Reserved
SCV[R] W
-----000 00000000 -----000 00000000
MTCCV[R] W
-------- --000000 --000000 00000000
RCV[R] W
-------- -------- ----0000 00000000
OCV[R] W
-------- -----000 00000000 00000000
FlexRay
GTU *5
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Block
-
00D108H
00D10CH
00D110H
+3
61
D a t a S h e e t
Address
00D120H
00D124H
00D128H
00D12CH
00D130H
00D134H
00D138H
00D13CH
00D140H
00D144H
00D148H
00D14CH
00D150H
00D154H
00D158H
00D15CH
00D160H
00D164H
00D168H
00D16CH
00D170H
00D174H
00D178H
00D17CH
00D180H
00D184H
00D188H
00D18CH
62
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
SFS[R] W
-------- ----0000 00000000 00000000
SWNIT[R] W
-------- -------- ----0000 00000000
ACS[R/W] W
-------- -------- ---00000 ---00000
ESID1[R] W
-------- -------- 00----00 00000000
ESID2[R] W
-------- -------- 00----00 00000000
ESID3[R] W
-------- -------- 00----00 00000000
ESID4[R] W
-------- -------- 00----00 00000000
ESID5[R] W
-------- -------- 00----00 00000000
ESID6[R] W
-------- -------- 00----00 00000000
ESID7[R] W
-------- -------- 00----00 00000000
ESID8[R] W
-------- -------- 00----00 00000000
ESID9[R] W
-------- -------- 00----00 00000000
ESID10[R] W
-------- -------- 00----00 00000000
ESID11[R] W
-------- -------- 00----00 00000000
ESID12[R] W
-------- -------- 00----00 00000000
ESID13[R] W
-------- -------- 00----00 00000000
ESID14[R] W
-------- -------- 00----00 00000000
ESID15[R] W
-------- -------- 00----00 00000000
OSID1[R] W
-------- -------- 00----00 00000000
OSID2[R] W
-------- -------- 00----00 00000000
OSID3[R] W
-------- -------- 00----00 00000000
OSID4[R] W
-------- -------- 00----00 00000000
OSID5[R] W
-------- -------- 00----00 00000000
OSID6[R] W
-------- -------- 00----00 00000000
OSID7[R] W
-------- -------- 00----00 00000000
OSID8[R] W
-------- -------- 00----00 00000000
+3
Block
FlexRay
GTU *5
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
00D190H
00D194H
00D198H
00D19CH
00D1A0H
00D1A4H
00D1A8H
00D1ACH
00D1B0H
00D1B4H
00D1B8H
+0
Address offset value/Register name
+1
+2
OSID9[R] W
-------- -------- 00----00 00000000
OSID10[R] W
-------- -------- 00----00 00000000
OSID11[R] W
-------- -------- 00----00 00000000
OSID12[R] W
-------- -------- 00----00 00000000
OSID13[R] W
-------- -------- 00----00 00000000
OSID14[R] W
-------- -------- 00----00 00000000
OSID15[R] W
-------- -------- 00----00 00000000
NMV1[R] W
00000000 00000000 00000000 00000000
NMV2[R] W
00000000 00000000 00000000 00000000
NMV3[R] W
00000000 00000000 00000000 00000000
00D1BCH
|
00D2FCH
00D300H
00D304H
00D308H
00D30CH
00D310H
00D314H
00D318H
00D31CH
00D320H
00D324H
00D328H
00D32CH
00D330H
00D334H
00D338H
Block
FlexRay
GTU *5
Reserved
FlexRay
NEM *5
-
Reserved
MRC[R/W] W
-----001 10000000 00000000 00000000
FRF[R/W] W
-------1 10000000 ---00000 00000000
FRFM[R/W] W
-------- -------- ---00000 000000-FCL[R/W] W
-------- -------- -------- 10000000
MHDS[R/W] W
-0000000 -0000000 -0000000 00000000
LDTS[R] W
-----000 00000000 -----000 00000000
FSR[R] W
-------- -------- 00000000 -----000
MHDF[R/W] W
-------- -------- -------0 00000000
TXRQ1[R] W
00000000 00000000 00000000 00000000
TXRQ2[R] W
00000000 00000000 00000000 00000000
TXRQ3[R] W
00000000 00000000 00000000 00000000
TXRQ4[R] W
00000000 00000000 00000000 00000000
NDAT1[R] W
00000000 00000000 00000000 00000000
NDAT2[R] W
00000000 00000000 00000000 00000000
NDAT3[R] W
00000000 00000000 00000000 00000000
FlexRay
MHD *5
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
63
D a t a S h e e t
Address
00D33CH
00D340H
00D344H
00D348H
00D34CH
00D350H
|
00D3ECH
00D3F0H
00D3F4H
00D3F8H
|
00D3FCH
00D400H
|
00D4FCH
00D500H
00D504H
00D508H
00D50CH
00D510H
00D514H
00D518H
|
00D5FCH
00D600H
|
00D6FCH
00D700H
00D704H
00D708H
00D70CH
00D710H
00D714H
00D718H
|
00D7FCH
64
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
+3
Block
NDAT4[R] W
00000000 00000000 00000000 00000000
MBSC1[R] W
00000000 00000000 00000000 00000000
MBSC2[R] W
00000000 00000000 00000000 00000000
MBSC3[R] W
00000000 00000000 00000000 00000000
MBSC4[R] W
00000000 00000000 00000000 00000000
FlexRay
MHD *5
-
Reserved
CREL[R] W
00010000 00111001 00000010 00000110
ENDN[R] W
10000111 01100101 01000011 00100001
FlexRay
GIF *5
-
Reserved
WRDSn[1-64][R/W] W
00000000 00000000 00000000 00000000
WRHS1[R/W] W
--000000 -0000000 -----000 00000000
WRHS2[R/W] W
-------- -0000000 -----000 00000000
WRHS3[R/W] W
-------- -------- -----000 00000000
IBCM[R/W] W
-------- ------00 -------- -----000
IBCR[R/W] W
0------- -0000000 0------- -0000000
-
FlexRay
IBF *5
Reserved
RDDSn[1-64][R] W
00000000 00000000 00000000 00000000
RDHS1[R] W
--000000 -0000000 -----000 00000000
RDHS2[R] W
-0000000 -0000000 -----000 00000000
RDHS3[R] W
--000000 --000000 -----000 00000000
MBS[R] W
--000000 --000000 00-00000 00000000
OBCM[R/W] W
-------- ------00 -------- ------00
OBCR[R/W] W
-------- -0000000 0-----00 -0000000
-
FlexRay
OBF *5
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
Address offset value/Register name
+1
+2
00D800H
|
00EFFCH
00F000H
|
00FEFCH
+3
Block
-
Reserved
-
Reserved [S]
00FF00H
DSUCR[R/W] B,H,W
-------- -------0
-
-
OCDU [S]
00FF04H
|
00FF0CH
-
-
-
Reserved [S]
PCSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PSSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF10H
00FF14H
00FF18H
|
00FFF4H
-
-
-
-
OCDU [S]
-
Reserved [S]
EDIR1[R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
EDIR0[R] B,H,W
00FFFCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]: It is a system register. The illegal instruction exception (data access error) is generated when reading and
writing to these registers in the user mode.
*5: For FlexRay, the MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584AMJ/F585AMJ has
corresponding functions.
The following registers are reserved registers for models without the FlexRay function.
000125H IRPR2L[5:4], 000E68H, 0004E8H-0004EFH, 00D000H-00D717H
00FFF8H
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
65
D a t a S h e e t
I/O Map (MB91F583AS/F584AS/F585AS)
Address offset value/Register name
Address
+0
+1
+2
PDR02[R/W]
B,H,W
XXXXXXXX
-
PDR01[R/W]
B,H,W
XXXXXXXX
PDR05[R/W]
B,H,W
-XXXXXXX
PDR09[R/W]
B,H,W
---XX---
WDTCR0[R/W]
B,H,W
-0--0000
DICR[R/W] B
-------0
000000H
-
000004H
PDR04[R/W]
B,H,W
XXXXXXXX
000008H
-
00000CH
000010H
|
000038H
00003CH
000040H
000044H
000048H
|
00005CH
000060H
000064H
000068H
|
00007CH
000080H
000084H
000088H
00008CH
000090H
000094H
000098H
00009CH
0000A0H
|
0000FCH
66
CONFIDENTIAL
+3
PDR03[R/W]
B,H,W
XXXXXXXX
PDR07[R/W]
B,H,W
-----XXX
-
Block
Port data register
-
-
-
-
-
-
-
Reserved
WDTCPR0[W]
B,H,W
00000000
-
WDTCR1[R]
B,H,W
----0010
WDTCPR1[W]
B,H,W
00000000
Watchdog timer
[S]
-
-
-
Reserved
-
Delay interrupt
-
-
Reserved
TMRLRA0[R/W] H
XXXXXXXX XXXXXXXX
TMRLRB0[R/W] H
XXXXXXXX XXXXXXXX
TMR0[R] H
XXXXXXXX XXXXXXXX
TMCSR0[R/W] B,H,W
00000000 0-000000
Reload timer 0
-
-
BT0TMR[R] H
00000000 00000000
BT0TMCR2
BT0STC
[R/W] B
[R/W] B
-------0
-0-0-0-0
BT0PCSR/BT0PRLL
[R/W] H
00000000 00000000
BT1TMR[R] H
00000000 00000000
BT1TMCR2
BT1STC
[R/W] B
[R/W] B
-------0
-0-0-0-0
BT1PCSR/BT1PRLL
[R/W] H
00000000 00000000
BTSEL01[R/W] B
----0000
-
-
-
-
Reserved
BT0TMCR[R/W] H
-0000000 00000000
-
Base timer 0
BT0PDUT/BT0PRLH/BT0DTBF
[R/W] H
00000000 00000000
BT1TMCR[R/W] H
-0000000 00000000
-
-
BT1PDUT/BT1PRLH/BT1DTBF
[R/W] H
00000000 00000000
BTSSSR[W] B,H
-------- ------11
-
-
Base timer 1
Base timer 0, 1
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000100H
000104H
000108H
00010CH
000110H
000114H
000118H
|
00011CH
000120H
000124H
000128H
00012CH
000130H
000134H
000138H
00013CH
000140 H
000144 H
000148H
|
0001FCH
000200H
000204H
000208H
00020CH
000210H
000214H
+0
Address offset value/Register name
+1
+2
TMRLRA1[R/W] H
XXXXXXXX XXXXXXXX
TMRLRB1[R/W] H
XXXXXXXX XXXXXXXX
TMRLRA2[R/W] H
XXXXXXXX XXXXXXXX
TMRLRB2[R/W] H
XXXXXXXX XXXXXXXX
TMRLRA3[R/W] H
XXXXXXXX XXXXXXXX
TMRLRB3[R/W] H
XXXXXXXX XXXXXXXX
-
IRPR0H[R] B,H,W IRPR0L[R] B,H,W
00-----00-----IRPR2L[R]
IRPR2H[R] B,H,W
B,H,W *5
-------0000---IRPR4H[R] B,H,W IRPR4L[R] B,H,W
00-----000000-IRPR6H[R] B,H,W IRPR6L[R] B,H,W
0000---00-----IRPR8H[R] B,H,W IRPR8L[R] B,H,W
-------00-----IRPR10H[R]
IRPR10L[R]
B,H,W
B,H,W
00-----00-----IRPR12H[R]
IRPR12L[R]
B,H,W
B,H,W
000000000000000
IRPR14H[R]
IRPR14L[R]
B,H,W
B,H,W
00-----00-----IRPR16H[R]
IRPR16L[R]
B,H,W
B,H,W
00------------IRPR18H[R]B,H,W IRPR18L[R]B,H,W
-------000000--
-
PCN0[R/W] B,H,W
00000000 000000-0
PDUT0[W] H,W
XXXXXXXX XXXXXXXX
PCN1[R/W] B,H,W
00000000 000000-0
PDUT1[W] H,W
XXXXXXXX XXXXXXXX
PCN2[R/W] B,H,W
00000000 000000-0
PDUT2[W] H,W
XXXXXXXX XXXXXXXX
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
+3
TMR1[R] H
XXXXXXXX XXXXXXXX
TMCSR1[R/W] B,H,W
00000000 0-000000
TMR2[R] H
XXXXXXXX XXXXXXXX
TMCSR2[R/W] B,H,W
00000000 0-000000
TMR3[R] H
XXXXXXXX XXXXXXXX
TMCSR3[R/W] B,H,W
00000000 0-000000
-
-
Block
Reload timer 1
Reload timer 2
Reload timer 3
Reserved
IRPR1H[R] B,H,W IRPR1L[R] B,H,W
00------------IRPR3H[R] B,H,W IRPR3L[R] B,H,W
00-----00-----IRPR5H[R] B,H,W IRPR5L[R] B,H,W
00-----00-----IRPR7H[R] B,H,W IRPR7L[R] B,H,W
00------------IRPR9H[R] B,H,W IRPR9L[R] B,H,W
00-----00-----Interrupt request
IRPR11H[R]
IRPR11L[R]
batch read
B,H,W
B,H,W
register
00-----0000000IRPR13H[R]
IRPR13L[R]
B,H,W
B,H,W
0000000---00--IRPR15H[R]
IRPR15L[R]
B,H,W
B,H,W
00000000
0000---IRPR17H[R]
IRPR17L[R]
B,H,W
B,H,W
---------------
-
-
-
PCSR0[W] H,W
XXXXXXXX XXXXXXXX
PTMR0[R] H,W
11111111 11111111
PCSR1[W] H,W
XXXXXXXX XXXXXXXX
PTMR1[R] H,W
11111111 11111111
PCSR2[W] H,W
XXXXXXXX XXXXXXXX
PTMR2[R] H,W
11111111 11111111
Reserved
PPG0
PPG1
PPG2
67
D a t a S h e e t
Address
000218H
00021CH
000220H
000224H
000228H
00022CH
+0
0002C4H
0002C8H
0002CCH
0002D0H
0002D4H
0002D8H
0002DCH
0002E0H
0002E4H
0002E8H
0002ECH
0002F0H
0002F4H
0002F8H
0002FCH
000300H
000304H
000308H
00030CH
68
CONFIDENTIAL
+3
PCN3[R/W] B,H,W
00000000 000000-0
PDUT3[W] H,W
XXXXXXXX XXXXXXXX
PCN4[R/W] B,H,W
00000000 000000-0
PDUT4[W] H,W
XXXXXXXX XXXXXXXX
PCN5[R/W] B,H,W
00000000 000000-0
PDUT5[W] H,W
XXXXXXXX XXXXXXXX
PCSR3[W] H,W
XXXXXXXX XXXXXXXX
PTMR3[R] H,W
11111111 11111111
PCSR4[W] H,W
XXXXXXXX XXXXXXXX
PTMR4[R] H,W
11111111 11111111
PCSR5[W] H,W
XXXXXXXX XXXXXXXX
PTMR5[R] H,W
11111111 11111111
-
-
000230H
|
0002BCH
0002C0H
Address offset value/Register name
+1
+2
GTRS0[R/W] B,H,W
-0000000 -0000000
GTRS2[R/W] B,H,W
-0000000 -0000000
GTREN0[R/W] H,W
-------- --000000
GATEC0[R/W]
B,H,W
------00
GATEC4[R/W]
B,H,W
------00
RCRH0[W]
RCRL0[W]
H,W
B,H,W
00000000
00000000
CCR0[R/W] B,H
00000000 -0001000
RCRH1[W]
RCRL1[W]
H,W
B,H,W
00000000
00000000
CCR1[R/W] B,H
00000000 -0001000
PPG5
-
PPG Control
-
Reserved
GATEC2[R/W]
B,H,W
------00
-
-
UDCRH0[R]
H,W
00000000
UDCRL0[R]
B,H,W
00000000
CSR0[R] B
00000000
UDCRL1[R]
B,H,W
00000000
CSR1[R] B
00000000
UDCRH1[R]
H,W
00000000
-
-
PPG4
GTRS1[R/W] B,H,W
-0000000 -0000000
-
-
-
-
-
PPG3
Reserved
-
Block
PPG GATE
Control
Reserved
U/D counter 0
U/D counter 1
Reserved
Reserved
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
Address offset value/Register name
+1
+2
000310H
-
-
000314H
000318H
00031CH
-
-
-
-
-
000328H
00032CH
-
000330H
000334H
-
000338H
00033CH
-
000340H
000344H
-
000348H
00034CH
-
000350H
000354H
-
000358H
00035CH
-
000360H
000364H
-
000368H
00036CH
000370H
000374H
000378H
00037CH
000380H
000384H
000388H
00038CH
000390H
MPUCR[R/W] H
000000-0 ----0100
-
-
DPVAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DPVSR[R/W] H
-------- 00000--0
DEAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DESR[R/W] H
-------- 00000--0
PABR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR0[R/W] H
000000-0 00000--0
PABR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR1[R/W] H
000000-0 00000--0
PABR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR2[R/W] H
000000-0 00000--0
PABR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR3[R/W] H
000000-0 00000--0
PABR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR4[R/W] H
000000-0 00000--0
PABR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR5[R/W] H
000000-0 00000--0
PABR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR6[R/W] H
000000-0 00000--0
PABR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR7[R/W] H
000000-0 00000--0
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Block
-
-
000320H
000324H
+3
MPU [S]
(Only the CPU
can access this
area)
Reserved [S]
69
D a t a S h e e t
Address
000394H
000398H
00039CH
0003A0H
0003A4H
0003A8H
0003ACH
0003B0H
|
0003CCH
0003D0H
0003D4H
0003D8H
0003DCH
0003E0H
|
0003FCH
000400H
000404H
000408H
00040CH
000410H
000414H
000418H
00041CH
000420H
000424H
|
00043CH
70
CONFIDENTIAL
+0
-
Address offset value/Register name
+1
+2
-
+3
Block
-
-
-
-
-
-
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
Reserved [S]
-
-
-
-
Reserved [S]
ICSEL0[R/W]
B,H,W
-----000
ICSEL4[R/W]
B,H,W
-------0
ICSEL8[R/W]
B,H,W
-------0
ICSEL12[R/W]
B,H,W
-------0
ICSEL16[R/W]
B,H,W
-------0
ICSEL20[R/W]
B,H,W
-------0
ICSEL24[R/W]
B,H,W
-----000
-
ICSEL1[R/W]
B,H,W
-------0
ICSEL5[R/W]
B,H,W
-------0
ICSEL9[R/W]
B,H,W
-------0
ICSEL13[R/W]
B,H,W
-------0
ICSEL17[R/W]
B,H,W
-------0
ICSEL21[R/W]
B,H,W
-----000
ICSEL25[R/W]
B,H,W
-----000
-
ICSEL2[R/W]
B,H,W
-------0
ICSEL6[R/W]
B,H,W
-------0
ICSEL10[R/W]
B,H,W
------00
ICSEL14[R/W]
B,H,W
-------0
ICSEL18[R/W]
B,H,W
-------0
ICSEL22[R/W]
B,H,W
-----000
ICSEL26[R/W]
B,H,W
-------0
-
ICSEL3[R/W]
B,H,W
-------0
ICSEL7[R/W]
B,H,W
-----000
ICSEL11[R/W]
B,H,W
-------0
ICSEL15[R/W]
B,H,W
-------0
ICSEL19[R/W]
B,H,W
-------0
ICSEL23[R/W]
B,H,W
-----000
ICSEL27[R/W]
B,H,W
-------0
-
Generation and
clear of DMA
transfer request
-
-
-
-
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
000470H
|
00047CH
000480H
000484H
000488H
00048CH
+0
Address offset value/Register name
+1
+2
Block
ICR00[R/W]
B,H,W
---11111
ICR04[R/W]
B,H,W
---11111
ICR08[R/W]
B,H,W
---11111
ICR12[R/W]
B,H,W
---11111
ICR16[R/W]
B,H,W
---11111
ICR20[R/W]
B,H,W
---11111
ICR24[R/W]
B,H,W
---11111
ICR28[R/W]
B,H,W
---11111
ICR32[R/W]
B,H,W
---11111
ICR36[R/W]
B,H,W
---11111
ICR40[R/W]
B,H,W
---11111
ICR44[R/W]
B,H,W
---11111
ICR01[R/W]
B,H,W
---11111
ICR05[R/W]
B,H,W
---11111
ICR09[R/W]
B,H,W
---11111
ICR13[R/W]
B,H,W
---11111
ICR17[R/W]
B,H,W
---11111
ICR21[R/W]
B,H,W
---11111
ICR25[R/W]
B,H,W
---11111
ICR29[R/W]
B,H,W
---11111
ICR33[R/W]
B,H,W
---11111
ICR37[R/W]
B,H,W
---11111
ICR41[R/W]
B,H,W
---11111
ICR45[R/W]
B,H,W
---11111
ICR02[R/W]
B,H,W
---11111
ICR06[R/W]
B,H,W
---11111
ICR10[R/W]
B,H,W
---11111
ICR14[R/W]
B,H,W
---11111
ICR18[R/W]
B,H,W
---11111
ICR22[R/W]
B,H,W
---11111
ICR26[R/W]
B,H,W
---11111
ICR30[R/W]
B,H,W
---11111
ICR34[R/W]
B,H,W
---11111
ICR38[R/W]
B,H,W
---11111
ICR42[R/W]
B,H,W
---11111
ICR46[R/W]
B,H,W
---11111
ICR03[R/W]
B,H,W
---11111
ICR07[R/W]
B,H,W
---11111
ICR11[R/W]
B,H,W
---11111
ICR15[R/W]
B,H,W
---11111
ICR19[R/W]
B,H,W
---11111
ICR23[R/W]
B,H,W
---11111
ICR27[R/W]
B,H,W
---11111
ICR31[R/W]
B,H,W
---11111
ICR35[R/W]
B,H,W
---11111
ICR39[R/W]
B,H,W
---11111
ICR43[R/W]
B,H,W
---11111
ICR47[R/W]
B,H,W
---11111
Interrupt
controller [S]
-
-
-
-
Reserved [S]
RSTRR[R]
B,H,W
XXXX--XX
RSTCR[R/W]
B,H,W
111----0
STBCR[R/W]
B,H,W
000---11 *
DIVR0[R/W]
B,H,W
000-----
-
DIVR2[R/W]
B,H,W
0011----
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
-
-
-
Reset control [S]
Power
consumption
control [S]
* Writing to
STBCR by
DMA is
disabled.
Reserved [S]
-
Clock control
[S]
-
Reserved [S]
71
D a t a S h e e t
Address
000490H
000494H
000498H
00049CH
0004A0H
0004A4H
0004A8H
|
0004ACH
0004B0H
0004B4H
|
0004C0H
0004C4H
+0
Address offset value/Register name
+1
+2
IORR1[R/W]
B,H,W
-0000000
IORR5[R/W]
B,H,W
-0000000
-
IORR2[R/W]
B,H,W
-0000000
IORR6[R/W]
B,H,W
-0000000
-
IORR3[R/W]
B,H,W
-0000000
IORR7[R/W]
B,H,W
-0000000
-
-
-
-
CAN prescaler
-
-
-
-
Reserved
-
-
-
-
Reserved
-
-
-
-
Reserved
CUCR1[R/W] B,H,W
-------- ---0--00
-
-
0004E0H
-
-
0004ECH
0004F0H
|
0004FCH
000500H
000504H
000508H
|
00050CH
000510H
-
-
-
-
-
CSELR[R/W]
B,H,W
-0----00
CMONR[R] B,H,W
-01---00
000518H
-
CONFIDENTIAL
-
-
DMA transfer
request from a
peripheral [S]
Reserved
WDT1
calibration
Reserved
CSCFG[R/W]
CMCFG[R/W]
B,H,W
B,H,W
Clock monitor
---0---00000000
PLL2DIVG[R/W] PLL2MULG[R/W]
B,H,W
B,H,W
----0000
00000000
FlexRay
clock control *5
CLKR2[R/W]
B,H,W
000--000
-
PLLCR[R/W] B,H,W
00-00000 11110000
72
-
PLL2DIVM[R/W] PLL2DIVN[R/W]
B,H,W
B,H,W
----0000
-0000000
PLL2CTRL[R/W] PLL2DIVK[R/W]
B,H,W
B,H,W
----0000
-------0
000514H
00051CH
CUTD1[R/W] B,H,W
11000011 01010000
CUTR1[R] B,H,W
-------- 00000000 00000000 00000000
0004CCH
|
0004DCH
0004E8H
Block
IORR0[R/W]
B,H,W
-0000000
IORR4[R/W]
B,H,W
-0000000
CANPRE[R/W]
B,H,W
---00000
0004C8H
0004E4H
+3
Reserved
Reserved
Reserved
-
-
MTMCR[R/W]
B,H,W
00001111
CSTBR[R/W]
B,H,W
----0000
CPUAR[R/W]
B,H,W
0---XXXX
-
Reserved
PTMCR[R/W]
B,H,W
00------
Clock control
[S]
-
Reset [S]
-
Reserved [S]
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
000520H
CCPSSELR[R/W]
B,H,W
-------0
000524H
-
000528H
-
00052CH
-
000530H
-
000534H
000538H
00053CH
000540H
|
00054CH
-
Address offset value/Register name
+1
+2
+3
Block
CCPSDIVR[R/W]
B,H,W
-000-000
CCPLLFBR[R/W] CCSSFBR0[R/W] CCSSFBR1[R/W]
B,H,W
B,H,W
B,H,W
-0000000
--000000
---00000
CCSSCCR0[R/W]
CCSSCCR1[R/W] B,H,W
B,H,W
000----- -----------0000
Clock control 2
CCCGRCR0[R/W] CCCGRCR1[R/W] CCCGRCR2[R/W]
B,H,W
B,H,W
B,H,W
00----00
00000000
00000000
CCPMUCR0[R/W] CCPMUCR1[R/W]
B,H,W
B,H,W
0-----00
0--00000
-
-
-
-
-
000550H
EIRR0[R/W]
B,H,W
-XXXXXXX
ENIR0[R/W]
B,H,W
-0000000
000554H
|
000568H
-
-
-
-
Reserved
00056CH
-
CSVCR[R/W] B
-0--1--0
-
-
CSV
000570H
CRTR[R/W]
B,H,W 01111111
-
-
-
WDT1
calibration
(trimming)
000574H
|
00057CH
-
-
-
-
Reserved
-
ELVR0[R/W] B,H,W
--000000 00000000
Reserved
External
interrupt
(INT0 to 6)
REGSEL[R/W]
B,H,W
01--110LVD5R[R/W]
B,H,W
-------1
-
-
-
Regulator
control
LVD5F[R/W]
B,H,W
001100-1
LVD[R/W]
B,H,W
01000--0
-
Low-voltage
detection
000588H
|
00058CH
-
-
-
-
Reserved
000590H
PMUSTR [R/W]
B,H,W
0-----1X
000594H
-
000598H
00059CH
0005A0H
|
0005FCH
-
000580H
000584H
PMUCTLR[R/W] PWRTMCTL[R/W]
B,H,W
B,H,W
0-00--------011
PMUINTF1[R/W] PMUINTF2[R/W]
B,H,W
B,H,W
00000000
-00-----
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
-
-
-
PMU
-
Reserved
73
D a t a S h e e t
Address
000600H
|
00060CH
000610H
|
00063CH
000640H
|
00064CH
000650H
|
00067CH
000680H
|
00068CH
000690H
|
0006BCH
0006C0H
|
0006CCH
0006D0H
|
0006F0H
0006F4H
0006F8H
|
0006FCH
000700H
000704H
|
00070CH
000710H
Address offset value/Register name
+1
+2
+0
+3
-
-
-
Reserved [S]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BPCCRA[R/W] B
00000000
000714H
000718H
00071CH
Reserved
Reserved
-
-
-
Reserved [S]
Reserved [S]
-
Reserved [S]
Reserved [S]
-
-
Reserved [S]
Reserved [S]
-
-
Block
Reserved
Reserved
-
-
BPCCRB[R/W] B BPCCRC[R/W] B
00000000
00000000
BPCTRA[R/W] W
00000000 00000000 00000000 00000000
BPCTRB[R/W] W
00000000 00000000 00000000 00000000
BPCTRC[R/W] W
00000000 00000000 00000000 00000000
Reserved
Bus performance
counter
000720H
|
0007F8H
-
-
-
-
Reserved
0007FCH
BMODR[R] B,H,W
XXXXXXXX
-
-
-
Operation mode
000800H
|
00083CH
-
-
-
-
Reserved [S]
Flash memory
register [S]
Reserved [S]
Reserved [S]
FCTLR[R/W] H
-0--1000 0--0----
-
-
FSTR[R/W] B
-----001
-
-
-
-
-
000840H
000844H
000848H
|
000854H
74
CONFIDENTIAL
-
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
Address offset value/Register name
+1
+2
+3
000858H
-
-
WREN[R/W] H
00000000 00000000
00085CH
|
00087CH
-
-
-
000880H
000884H
000888H
00088CH
000890H
000894H
000898H
00089CH
0008A0H
0008A4H
0008A8H
0008ACH
0008B0H
0008B4H
0008B8H
0008BCH
0008C0H
0008C4H
0008C8H
0008CCH
0008D0H
0008D4H
0008D8H
0008DCH
0008E0H
WRAR00[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR00[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR01[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR02[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR03[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR04[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR05[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR06[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR07[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR08[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR09[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR10[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
Block
Wild register [S]
Reserved [S]
Wild register [S]
75
D a t a S h e e t
Address
+0
0008E8H
0008ECH
0008F0H
0008F4H
0008F8H
0008FCH
000BFCH
000C00H
000C04H
000C08H
000C0CH
000C10H
000C14H
000C18H
000C1CH
000C20H
000C24H
000C28H
000C2CH
000C30H
000C34H
000C38H
000C3CH
000C40H
000C44H
76
CONFIDENTIAL
+3
WRDR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR13[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E4H
000900H
|
000BF8H
Address offset value/Register name
+1
+2
-
-
-
Block
Wild register [S]
UER[W] B,H,W
-------- -------X
DCCR0[R/W] W
0----000 --00--00 00000000 0-000000
DCSR0[R/W] H
DTCR0[R/W] H
0------- -----000
00000000 00000000
DSAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR1[R/W] W
0----000 --00--00 00000000 0-000000
DCSR1[R/W] H
DTCR1[R/W] H
0------- -----000
00000000 00000000
DSAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2[R/W] W
0----000 --00--00 00000000 0-000000
DCSR2[R/W] H
DTCR2[R/W] H
0------- -----000
00000000 00000000
DSAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3[R/W] W
0----000 --00--00 00000000 0-000000
DCSR3[R/W] H
DTCR3[R/W] H
0------- -----000
00000000 00000000
DSAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4[R/W] W
0----000 --00--00 00000000 0-000000
DCSR4[R/W] H
DTCR4[R/W] H
0------- -----000
00000000 00000000
Reserved
OCDU
DMA controller
[S]
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000C4CH
000C50H
000C54H
000C58H
000C5CH
000C60H
000C64H
000C68H
000C6CH
000C70H
000C74H
000C78H
000C7CH
000DF4H
000DF8H
000DFCH
000E00H
000E04H
000E08H
000E0CH
000E10H
|
000E1CH
-
-
-
000E24H
PFR04[R/W] B,H
00000000
000E28H
-
000E2CH
-
DMA controller
[S]
-
-
Block
-
DNMIR[R/W] B
DILVR[R/W] B
0------0
---11111
DMACR[R/W] W
0------- -------- 0------- -------DDR01[R/W] B,H DDR02[R/W] B,H DDR03[R/W] B,H
00000000
00000000
00000000
DDR04[R/W] B,H DDR05[R/W] B,H
DDR07[R/W] B,H
00000000
-0000000
-----000
DDR09[R/W] B,H
---00---
000E20H
-
-
-
PFR01[R/W] B,H
00000000
PFR05[R/W] B,H
-0000000
PFR09[R/W] B,H
---00---
PFR02[R/W] B,H
00000000
PFR03[R/W] B,H
00000000
PFR07[R/W] B,H
-----000
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
DSAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5[R/W] W
0----000 --00--00 00000000 0-000000
DCSR5[R/W] H
DTCR5[R/W] H
0------- -----000
00000000 00000000
DSAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR6[R/W] W
0----000 --00--00 00000000 0-000000
DCSR6[R/W] H
DTCR6[R/W] H
0------- -----000
00000000 00000000
DSAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7[R/W] W
0----000 --00--00 00000000 0-000000
DCSR7[R/W] H
DTCR7[R/W] H
0------- -----000
00000000 00000000
DSAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C48H
000C80H
|
000DF0H
Address offset value/Register name
+1
+2
+0
-
-
-
-
Reserved [S]
Data direction
register
Reserved
Port function
register
77
D a t a S h e e t
Address
000E30H
|
000E3CH
000E40H
000E44H
000E48H
000E4CH
000E50H
|
000E5CH
000E60H
000E64H
000E68H
000E6CH
000E70H
000E74H
000E78H
000E7CH
000E80H
000E84H
|
000EBCH
000EC0H
000EC4H
000EC8H
000ECCH
000ED0H
|
000EDCH
000EE0H
000EE4H
000EE8H
000EECH
000EF0H
|
000EFCH
000F00H
|
000F1CH
78
CONFIDENTIAL
+0
-
Address offset value/Register name
+1
+2
-
-
+3
-
Block
Reserved
PDDR01[R] B,H,W PDDR02[R] B,H,W PDDR03[R] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDDR04[R] B,H,W PDDR05[R] B,H,W
PDDR07[R] B,H,W
Input data direct
XXXXXXXX
-XXXXXXX
-----XXX
read register
PDDR09[R] B,H,W
---XX---
-
-
-
-
Reserved
EPFR00[R/W] B,H EPFR01[R/W] B,H EPFR02[R/W] B,H EPFR03[R/W] B,H
-------0
------00
-----000
--000000
EPFR06[R/W] B,H EPFR07[R/W] B,H
------00
----0000
EPFR08[R/W]
EPFR09[R/W] B,H EPFR10[R/W] B,H
B,H *5
-------0
-0000000
Extended port
----0000
function register
-
-
-
-
Reserved
PPER01[R/W] B,H PPER02[R/W] B,H PPER03[R/W] B,H
00000000
00000000
00000000
PPER04[R/W] B,H PPER05[R/W] B,H
PPER07[R/W] B,H
Port
00000000
-0000000
-----000
pull-up/down
enable register
PPER09[R/W] B,H
---00---
-
-
-
-
Reserved
PILR01[R/W] B,H PILR02[R/W] B,H PILR03[R/W] B,H
11111111
11111111
11111111
PILR04[R/W] B,H PILR05[R/W] B,H
PILR07[R/W] B,H
Port input level
11111111
-1111111
-----111
selection register
PILR09[R/W] B,H
---11---
-
-
-
-
Reserved
-
-
-
-
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
000F20H
000F24H
000F28H
000F2CH
000F30H
|
000F3CH
000F40H
000F44H
000F48H
000F4CH
+0
-
Address offset value/Register name
+1
+2
PODR01[R/W] B,H
00000000
PODR04[R/W] B,H PODR05[R/W] B,H
00000000
-0000000
PODR09[R/W] B,H
---00---
-
PORTEN[R/W]
B,H,W
------00
KEYCDR[R/W] H
00000000 00000000
ADERH[R/W] B,H
-------- ---11--DAER[R/W] B,H
-------0
PODR02[R/W]
B,H
00000000
+3
Block
PODR03[R/W] B,H
00000000
PODR07[R/W] B,H Port output drive
-----000
register
-
-
-
-
-
-
Reserved
-
-
Port input enable
register
-
-
Port key code
ADERL[R/W] B,H
-1111111 11111111
-
-
Analog input
enable register
Analog output
enable register
000F50H
|
000FFCH
-
-
-
-
Reserved
001000H
SACR[R/W]
B,H,W
-------0
PICD[R/W]
B,H,W
----0011
-
-
Synchronous/asy
nchronous
switch control
001004H
|
0010BCH
-
-
-
-
Reserved
0010C0H
-
-
-
CRCCR[R/W]
B,H,W
-0000000
CRCINIT[R/W] B,H,W
11111111 11111111 11111111 11111111
CRCIN[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR[R] B,H,W
11111111 11111111 11111111 11111111
0010C4H
0010C8H
0010CCH
0010D0H
-
-
-
CRC arithmetic
operation 0
CRCCR1[R/W]
B,H,W
-0000000
CRCINIT1[R/W] B,H,W
11111111 11111111 11111111 11111111
CRCIN1[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR1[R] B,H,W
11111111 11111111 11111111 11111111
0010D4H
0010D8H
0010DCH
CRC arithmetic
operation 1
0010E0H
|
0010FCH
-
-
-
-
Reserved
001100H
TCGS[R/W]
B,H,W
------00
-
-
TCGSE[R/W]
B,H,W
--000000
Free-run timer
simultaneous
activation
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
79
D a t a S h e e t
Address
001104H
001108H
00110CH
001110H
001114H
001118H
00111CH
001120H
001124H
001128H
00112CH
001130H
001134H
001138H
00113CH
001140H
001144H
001148H
00114CH
001150H
001154H
001158H
00115CH
001160H
001164H
001168H
80
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
+3
CPCLRB0/CPCLR0[R/W] H,W
TCDT0[R/W] H,W
11111111 11111111
00000000 00000000
TCCS0[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB1/CPCLR1[R/W] H,W
TCDT1[R/W] H,W
11111111 11111111
00000000 00000000
TCCS1[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB2/CPCLR2[R/W] H,W
TCDT2[R/W] H,W
11111111 11111111
00000000 00000000
TCCS2[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB3/CPCLR3[R/W] H,W
TCDT3[R/W] H,W
11111111 11111111
00000000 00000000
TCCS3[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB4/CPCLR4[R/W] H,W
TCDT4[R/W] H,W
11111111 11111111
00000000 00000000
TCCS4[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB5/CPCLR5[R/W] H,W
TCDT5[R/W] H,W
11111111 11111111
00000000 00000000
TCCS5[R/W] B,H,W
00000000 01000000 ----0000 -------FRS0[R/W] B,H,W
-------- -000-000 -000-000 -000-000
FRS1[R/W] B,H,W
-------- -------- -000-000 -000-000
FRS2[R/W] B,H,W
-------- -000-000 -000-000 -000-000
FRS4[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
FRS5[R/W] B,H,W
-----000 -000-000 -000-000 -000-000
FRS6[R/W] B,H,W
-------- -----000 -000---- -------OCCPB0/OCCP0[R/W] H,W
OCCPB1/OCCP1[R/W] H,W
00000000 00000000
00000000 00000000
OCMOD01[R/W]
OCS01[R/W] B,H,W
B,H,W
-110--00 00001100
------00
OCCPB2/OCCP2[R/W] H,W
OCCPB3/OCCP3[R/W] H,W
00000000 00000000
00000000 00000000
OCMOD23[R/W]
OCS23[R/W] B,H,W
B,H,W
-110--00 00001100
------00
OCCPB4/OCCP4[R/W] H,W
OCCPB5/OCCP5[R/W] H,W
00000000 00000000
00000000 00000000
OCMOD45[R/W]
OCS45[R/W] B,H,W
B,H,W
-110--00 00001100
------00
Block
Free-run timer 0
Free-run timer 1
Free-run timer 2
Free-run timer 3
Free-run timer 4
Free-run timer 5
Free-run timer
selection
Output compare
0/1
Output compare
2/3
Output compare
4/5
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
Address offset value/Register name
+1
+2
00116CH
OCCPB6/OCCP6[R/W] H,W
00000000 00000000
001170H
OCS67[R/W] B,H,W
-110--00 00001100
001174H
OCCPB8/OCCP8[R/W] H,W
00000000 00000000
001178H
OCS89[R/W] B,H,W
-110--00 00001100
00117CH
001180H
001184H
001188H
00118CH
001190H
001194H
001198H
00119CH
0011A0H
0011A4H
0011A8H
0011ACH
0011B0H
0011B4H
0011B8H
0011BCH
OCCPB7/OCCP7[R/W] H,W
00000000 00000000
OCMOD67[R/W]
B,H,W
------00
OCCPB9/OCCP9[R/W] H,W
00000000 00000000
OCMOD89[R/W]
B,H,W
------00
OCCPB11/OCCP11[R/W] H,W
00000000 00000000
OCMOD1011
[R/W] B,H,W
------00
IPCP1[R] H,W
00000000 00000000
LSYNS[R/W]
B,H,W
------00
IPCP3[R] H,W
00000000 00000000
OCCPB10/OCCP10[R/W] H,W
00000000 00000000
OCS1011[R/W]
B,H,W
-110--00 00001100
IPCP0[R] H,W
00000000 00000000
ICS01[R/W]
B,H,W
------00 00000000
IPCP2[R] H,W
00000000 00000000
ICS23[R/W] B,H,W
------00 00000000
DTSR[R/W]
B,H,W
------10
TMRR0[R/W] H,W
TMRR1[R/W] H,W
00000000 00000001
00000000 00000001
TMRR2[R/W] H,W
00000000 00000001
DTSCR0[R/W]
DTSCR1[R/W]
DTSCR2[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
DTIR0[R/W]
DTMNS0[R/W]
B,H,W
B,H,W
000000-00---000
SIGCR10[R/W]
SIGCR20[R/W]
B,H,W
B,H,W
00000000
000000-1
PICS0[R/W] B,H,W
000000-- -------- -------- --------
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
Block
Output compare
6/7
Output compare
8/9
Output compare
10/11
Input capture 0/1
Input capture 2/3
Reserved
Reserved
DTTI selection
Waveform
generator
0/1/2
81
D a t a S h e e t
Address
0011C0H
0011C4H
0011C8H
0011CCH
0011D0H
0011D4H
0011D8H
0011DCH
0011E0H
0011E4H
0011E8H
0011ECH
0011F0H
0011F4H
0011F8H
0011FCH
001200H
001204H
001208H
00120CH
001210H
001214H
001218H
00121CH
001220H
001224H
001228H
00122CH
001230H
82
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
TMRR3[R/W] H,W
00000000 00000001
TMRR5[R/W] H,W
00000000 00000001
DTSCR3[R/W]
DTSCR4[R/W]
B,H,W
B,H,W
00000000
00000000
DTIR1[R/W]
B,H,W
000000-SIGCR11[R/W]
B,H,W
00000000
+3
Block
TMRR4[R/W] H,W
00000000 00000001
-
-
DTSCR5[R/W]
B,H,W
00000000
-
-
-
DTMNS1[R/W]
B,H,W
00---000
SIGCR21[R/W]
B,H,W
-------1
Waveform
generator
3/4/5
ADTSS[R/W]
B,H,W
-------0
-
-
-
-
-
-
ADTSE[R/W] B,H,W
-------- ---00--- -0000000 00000000
ADCOMP0/ADCOMPB0[R/W] H,W
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP2/ADCOMPB2[R/W] H,W
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP4/ADCOMPB4[R/W] H,W
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP6/ADCOMPB6[R/W] H,W
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP8/ADCOMPB8[R/W] H,W
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP10/ADCOMPB10[R/W] H,W ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP12/ADCOMPB12[R/W] H,W ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP14/ADCOMPB14[R/W] H,W
00000000 00000000
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
ADCOMP20/ADCOMPB20[R/W] H,W
00000000 00000000
ADTCS0[R/W] B,H,W
ADTCS1[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS2[R/W] B,H,W
ADTCS3[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS4[R/W] B,H,W
ADTCS5[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS6[R/W] B,H,W
ADTCS7[R/W] B,H,W
00000000 0010-000
00000000 0010-000
12-bit A/D
converter
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
Address offset value/Register name
+1
+2
001244H
ADTCS8[R/W] B,H,W
00000000 0010-000
ADTCS10[R/W] B,H,W
00000000 0010-000
ADTCS12[R/W] B,H,W
00000000 0010-000
ADTCS14[R/W] B,H,W
00000000 0010-000
-
001248H
-
001234H
001238H
00123CH
001240H
001284H
ADTCS20[R/W] B,H,W
00000000 00100000
ADTCD0[R] B,H,W
10--0000 00000000
ADTCD2[R] B,H,W
10--0000 00000000
ADTCD4[R] B,H,W
10--0000 00000000
ADTCD6[R] B,H,W
10--0000 00000000
ADTCD8[R] B,H,W
10--0000 00000000
ADTCD10[R] B,H,W
10--0000 00000000
ADTCD12[R] B,H,W
10--0000 00000000
ADTCD14[R] B,H,W
10--0000 00000000
-
001288H
-
00124CH
001250H
001254H
001258H
00125CH
001260H
001264H
001268H
00126CH
001270H
001274H
001278H
00127CH
001280H
00128CH
001290H
001294H
001298H
00129CH
0012A0H
0012A4H
0012A8H
0012ACH
ADTCD20[R] B,H,W
10--0000 00000000
ADCS0[R/W]
B,H,W
0------- -------ADCS1[R/W]
B,H,W
0------- -------ADCS2[R/W]
B,H,W
0------- --------
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
Block
ADTCS9[R/W] B,H,W
00000000 0010-000
ADTCS11[R/W] B,H,W
00000000 0010-000
ADTCS13[R/W] B,H,W
00000000 0010-000
ADTCS19[R/W] B,H,W
00000000 00100000
ADTCD1[R] B,H,W
10--0000 00000000
ADTCD3[R] B,H,W
10--0000 00000000
ADTCD5[R] B,H,W
10--0000 00000000
ADTCD7[R] B,H,W
10--0000 00000000
ADTCD9[R] B,H,W
10--0000 00000000
ADTCD11[R] B,H,W
10--0000 00000000
ADTCD13[R] B,H,W
10--0000 00000000
12-bit A/D
converter
ADTCD19[R] B,H,W
10--0000 00000000
ADCH0[R]
B,H,W
-----000
ADCH1[R]
B,H,W
-----000
ADCH2[R]
B,H,W
-----000
ADMD0[R/W]
B,H,W
----0000
ADMD1[R/W]
B,H,W
----0000
ADMD2[R/W]
B,H,W
----0000
83
D a t a S h e e t
Address
0012B0H
0012B4H
0012B8H
|
0012FCH
001300H
001304H
001308H
00130CH
001310H
001314H
001318 H
00131CH
001320H
001324H
001328H
|
00132CH
001330H
001334H
|
0013FCH
+0
Address offset value/Register name
+1
+2
MTRCSR[R/W]
B,H,W
-------0
RTOSEL0[R/W]
B,H,W
--000000
-
-
-
RTOSEL1[R/W]
B,H,W
-------0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Motor control
extension
function
Reserved
Reserved
-
-
001400H
DACR[R/W]
B,H,W
-------0
-
001404H
|
0014FCH
-
-
CONFIDENTIAL
Block
-
-
84
+3
-
-
DADR[R/W]
H,W
------XX XXXXXXXX
-
-
Reserved
DAC
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
001500H
001504H
001508H
00150CH
+0
Address offset value/Register name
+1
+2
SCR0/(IBCR0)
SMR0
[R/W] B,H,W
[R/W] B,H,W
0--00000
000000-0
-/(RDR10/(TDR10))[R/W] B,H,W
-------- -------- *3
SACSR0[R/W] B,H,W
0----000 00000000
STMCR0[R/W] B,H,W
00000000 00000000
001510H
-
-
001514H
001518H
-
-
00151CH
BGR0[R/W] H,W
00000000 00000000
001520H
FCR10[R/W]
B,H,W
00-00100
001524H
SCR1[R/W] B,H,W
0--00000
001528H
00152CH
001530H
FCR00[R/W]
B,H,W
-0000000
SMR1[R/W]
B,H,W
000000-0
-/(RDR11/(TDR11))[R/W] B,H,W
-------- -------- *3
SACSR1[R/W] B,H,W
0----000 00000000
STMCR1[R/W] B,H,W
00000000 00000000
001534H
-/(SCSTR31)
[R/W] B,H,W
-------- *3
-/(SCSTR21)
[R/W] B,H,W
-------- *3
001538H
-
-
00153CH
-
-
001540H
001544H
001548H
|
001FFCH
BGR1[R/W] H,W
00000000 00000000
FCR11[R/W]
FCR01[R/W]
B,H,W
B,H,W
00-00100
-0000000
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
+3
Block
SSR0
ESCR0/(IBSR0) Multi Function
[R/W] B,H,W
[R/W] B,H,W
Serial I/F 0
0--00011
00000000
*1: Byte access
is possible only
RDR00/(TDR00)[R/W] B,H,W
for access to
-------0 00000000 *1
lower 8 bits.
STMR0[R] B,H,W
*2:
Reserved
00000000 00000000
because
I2C
-/(SFUR0) [R/W] B,H,W
*4
mode is not set
-------- -------immediately
-/(SFLR10) [R/W] -/(SFLR00) [R/W]
after reset
B,H,W
B,H,W
*4
*4
*3:
Reserved
--------------because
CSIO
mode
is
not
set
immediately
-/(ISMK0)[R/W]
-/(ISBA0)[R/W]
after reset
B,H,W
B,H,W
*2
*2
*4:
Reserved
--------------because LIN2.1
FBYTE20[R/W]
FBYTE10[R/W] mode is not set
B,H,W
B,H,W
immediately
00000000
00000000
after reset
ESCR1[R/W]
SSR1[R/W] B,H,W
B,H,W
0--00011
00000000
RDR01/(TDR01)[R/W] B,H,W
Multi Function
-------0 00000000 *1
Serial I/F 1
STMR1[R] B,H,W
*1: Byte access
00000000 00000000
is possible only
-/(SCSCR1/SFUR1) [R/W] B,H,W
for access to
-------- -------- *3 *4
lower 8 bits.
-/(SCSTR11/
-/(SCSTR01/
*3: Reserved
SFLR11) [R/W]
SFLR01) [R/W]
because CSIO
B,H,W
B,H,W
mode is not set
-------- *3 *4
-------- *3 *4
immediately
after reset
*4: Reserved
TBYTE01[R/W]
because LIN2.1
B,H,W
mode is not set
00000000
immediately
after reset
FBYTE21[R/W]
FBYTE11[R/W]
B,H,W
B,H,W
00000000
00000000
-
-
Reserved
85
D a t a S h e e t
Address
002000H
002004H
002008H
00200CH
002010H
002014H
002018H
00201CH
002020H
002024H
002028H,
00202CH
002030H,
002034H
002038H,
00203CH
002040H
002044H
002048H
00204CH
002050H
002054H
002058H,
00205CH
002060H,
002064H
002068H
|
00207CH
002080H
002084H
002088H
00208CH
002090H
002094H
86
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
CTRLR0[R/W] B,H,W
-------- 000-0001
ERRCNT0 [R] B,H,W
00000000 00000000
INTR0[R] B,H,W
00000000 00000000
BRPER0[R/W] B,H,W
-------- ----0000
IF1CREQ0[R/W] B,H,W
0------- 00000001
IF1MSK20[R/W] B,H,W
11-11111 11111111
IF1ARB20[R/W] B,H,W
00000000 00000000
IF1MCTR0[R/W] B,H,W
00000000 0---0000
IF1DTA10[R/W] B,H,W
00000000 00000000
IF1DTB10[R/W] B,H,W
00000000 00000000
+3
Block
STATR0[R/W] B,H,W
-------- 00000000
BTR0[R/W] B,H,W
-0100011 00000001
TESTR0[R/W] B,H,W
-------- X00000-IF1CMSK0[R/W] B,H,W
-------- 00000000
IF1MSK10[R/W] B,H,W
11111111 11111111
IF1ARB10[R/W] B,H,W
00000000 00000000
IF1DTA20[R/W] B,H,W
00000000 00000000
IF1DTB20[R/W] B,H,W
00000000 00000000
-
Reserved (IF1 data mirror)
-
-
IF2CREQ0[R/W] B,H,W
0------- 00000001
IF2MSK20[R/W] B,H,W
11-11111 11111111
IF2ARB20[R/W] B,H,W
00000000 00000000
IF2MCTR0[R/W] B,H,W
00000000 0---0000
IF2DTA10[R/W] B,H,W
00000000 00000000
IF2DTB10[R/W] B,H,W
00000000 00000000
IF2CMSK0[R/W] B,H,W
-------- 00000000
IF2MSK10[R/W] B,H,W
11111111 11111111
IF2ARB10[R/W] B,H,W
00000000 00000000
-
-
CAN 0
64msb
IF2DTA20[R/W] B,H,W
00000000 00000000
IF2DTB20[R/W] B,H,W
00000000 00000000
Reserved (IF2 data mirror)
-
-
TREQR20[R] B,H,W
00000000 00000000
TREQR40[R] B,H,W
00000000 00000000
NEWDT20[R] B,H,W
00000000 00000000
NEWDT40[R] B,H,W
00000000 00000000
TREQR10[R] B,H,W
00000000 00000000
TREQR30[R] B,H,W
00000000 00000000
NEWDT10[R] B,H,W
00000000 00000000
NEWDT30[R] B,H,W
00000000 00000000
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
002098H
00209CH
0020A0H
0020A4H
0020A8H
0020ACH
0020B0H
0020B4H
0020B8H
0020BCH
0020C0H
|
0020FCH
002100H
|
0022FCH
002300H
002304H
002308H
00230CH
|
002FFCH
003000H
003004H
003008H
00300CH
003010H
003014H
003018H
00301CH
003020H
+0
Address offset value/Register name
+1
+2
INTPND20[R] B,H,W
00000000 00000000
INTPND40[R] B,H,W
00000000 00000000
MSGVAL20[R] B,H,W
00000000 00000000
MSGVAL40[R] B,H,W
00000000 00000000
-
INTPND10[R] B,H,W
00000000 00000000
INTPND30[R] B,H,W
00000000 00000000
MSGVAL10[R] B,H,W
00000000 00000000
MSGVAL30[R] B,H,W
00000000 00000000
-
-
-
-
-
DFCTLR[R/W] B,H,W
-0------ -------FLIFCTLR[R/W]
B,H,W
---0--00
-
-
-
-
SEEARX[R] B,H,W
--000000 00000000
EECSRX[R/W]
B,H,W
----00-0
Block
CAN 0
64msb
Reserved
FLIFFER1[R/W]
B,H,W
--------
DFSTR[R/W]
B,H,W
-----001
FLIFFER2[R/W]
B,H,W
--------
WorkFlash
-
-
Reserved
-
DEEARX[R] B,H,W
--000000 00000000
EFEARX[R/W] B,H,W
--000000 00000000
EFECRX[R/W] B,H,W
-------0 00000000 00000000
TEAR0X[R] B,H,W
000----- -------- --000000 00000000
TEAR1X[R] B,H,W
000----- -------- --000000 00000000
TEAR2X[R] B,H,W
000----- -------- --000000 00000000
TAEARX[R/W] B,H,W
TASARX[R/W] B,H,W
--101111 11111111
--000000 00000000
TFECRX[R/W]
TICRX[R/W]
TTCRX[R/W]
B,H,W
B,H,W
B,H,W
----0000
----0000
------00 00001100
TSRCRX[R/W]
TKCCRX[R/W]
B,H,W
B,H,W
0------00----00
XBS RAM
ECC control
register
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
XBS RAM
diagnosis
register
87
D a t a S h e e t
Address
003024H
003028H
00302CH
003030H
003034H
003038H
00303CH
003040H
003044H
003048H
|
0030FCH
003100H
003104H
003108H
00310CH
003110H
003114H
003118H
00311CH
003120H
003124H
003128H
|
003FFCH
004000H
|
005FFCH
006000H
|
00CFFCH
88
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
+3
SEEARA[R] B,H,W
--000000 00000000
EECSRA[R/W]
B,H,W
----00-0
DEEARA[R] B,H,W
--000000 00000000
EFEARA[R/W]
B,H,W
--000000 00000000
EFECRA[R/W] B,H,W
-------0 00000000 00000000
TEAR0A[R] B,H,W
000----- -------- -----000 00000000
TEAR1A[R] B,H,W
000----- -------- -----000 00000000
TEAR2A[R] B,H,W
000----- -------- -----000 00000000
TAEARA[R/W] B,H,W
TASARA[R/W] B,H,W
-----111 11111111
-----000 00000000
TFECRA[R/W]
TICRA[R/W]
TTCRA[R/W]
B,H,W
B,H,W
B,H,W
----0000
----0000
------00 00001100
TSRCRA[R/W]
TKCCRA[R/W]
B,H,W
B,H,W
0------00----00
-
-
-
-
BUSDIGSR0[R/W] H,W
BUSDIGSR1[R/W] H,W
00000000 0-----00
00000000 0-----00
BUSDIGSR2[R/W] H,W
BUSTSTR0[R/W] H,W
00000000 0-----00
00--0000 00000000
BUSADR0[R] W
00000000 00000000 00000000 00000000
BUSADR1[R] W
00000000 00000000 00000000 00000000
BUSADR2[R] W
00000000 00000000 00000000 00000000
BUSDIGSR3[R/W] H,W
00000000 0-----00
BUSDIGSR4[R/W] H,W
BUSTSTR1[R/W] H,W
00000000 0-----00
00--0000 00000000
BUSADR3[R] W
00000000 00000000 00000000 00000000
BUSADR4[R] W
00000000 00000000 00000000 00000000
-
-
-
-
-
Backup RAM
ECC control
register
Backup RAM
diagnosis
register
Reserved
Bus diagnosis
Reserved
Backup RAM
area
Backup RAM
-
Block
-
-
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
00D004H
-
-
00D024H
00D028H
00D02CH
00D030H
00D034H
00D038H
00D03CH
00D040H
00D044H
00D048H
00D04CH
00D050H
00D084H
00D088H
00D08CH
00D090H
00D094H
00D098H
-
-
-
-
Reserved
-
-
FlexRay
GIF *5
-
SUCC1[R/W] W
----1100 01000000 00010-00 1---0000
SUCC2[R/W] W
----0001 ---00000 00000101 00000100
SUCC3[R/W] W
-------- -------- -------- 00010001
NEMC[R/W] W
-------- -------- -------- ----0000
PRTC1[R/W] W
000010-0 01001100 0000-110 00110011
PRTC2[R/W] W
--001111 00101101 --001010 --001110
MHDC[R/W] W
---00000 00000000 -------- -0000000
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
LCK[R/W] W
-------- -------- -------- 00000000
EIR[R/W] W
-----000 -----000 ----0000 00000000
SIR[R/W] W
------00 ------00 00000000 00000000
EILS[R/W] W
-----000 -----000 ----0000 00000000
SILS[R/W] W
------11 ------11 11111111 11111111
EIES[R/W] W
-----000 -----000 ----0000 00000000
EIER[R/W] W
-----000 -----000 ----0000 00000000
SIES[R/W] W
------00 ------00 00000000 00000000
SIER[R/W] W
------00 ------00 00000000 00000000
ILE[R/W] W
-------- -------- -------- ------00
T0C[R/W] W
--000000 00000000 -0000000 ------00
T1C[R/W] W
--000000 00000010 -------- ------00
STPW1[R/W] W
--000000 00000000 --000000 -0000000
STPW2[R] W
-----000 00000000 -----000 00000000
00D020H
00D080H
-
Block
FlexRay
CIF *5
-
00D01CH
00D054H
|
00D07CH
+3
CIF0[R] W
00000100 11111111 01011011 11111111
CIF1[R/W] W
00000000 -------0 -0000000 --------
00D000H
00D008H
|
00D00CH
00D010H
00D014H
00D018H
Address offset value/Register name
+1
+2
FlexRay
INT *5
-
Reserved
FlexRay
SUC *5
FlexRay
NEM *5
FlexRay
PRT *5
FlexRay
MHD *5
89
D a t a S h e e t
Address
00D09CH
00D0A0H
00D0A4H
00D0A8H
00D0ACH
00D0B0H
00D0B4H
00D0B8H
00D0BCH
00D0C0H
00D0C4H
00D0C8H
00D0CCH
|
00D0FCH
00D100H
00D104H
00D108H
00D10CH
00D110H
00D114H
00D118H
00D11CH
00D120H
00D124H
00D128H
00D12CH
00D130H
00D134H
00D138H
00D13CH
90
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
+3
Block
GTUC1[R/W] W
-------- ----0000 00000010 10000000
GTUC2[R/W] W
-------- ----0010 --000000 00001010
GTUC3[R/W] W
-0000010 -0000010 00000000 00000000
GTUC4[R/W] W
--000000 00001000 --000000 00000111
GTUC5[R/W] W
00001110 ---00000 00000000 00000000
GTUC6[R/W] W
-----000 00000010 -----000 00000000
GTUC7[R/W] W
------00 00000010 ------00 00000100
GTUC8[R/W] W
---00000 00000000 -------- --000010
GTUC9[R/W] W
-------- ------00 ---00001 --000001
GTUC10[R/W] W
-----000 00000010 --000000 00000101
GTUC11[R/W] W
-----000 -----000 ------00 ------00
Reserved
-
Reserved
CCSV[R] W
--000000 00010000 -100--00 00000000
CCEV[R] W
-------- -------- ---00000 00--0000
FlexRay
SUC *5
-
Reserved
SCV[R] W
-----000 00000000 -----000 00000000
MTCCV[R] W
-------- --000000 --000000 00000000
RCV[R] W
-------- -------- ----0000 00000000
OCV[R] W
-------- -----000 00000000 00000000
SFS[R] W
-------- ----0000 00000000 00000000
SWNIT[R] W
-------- -------- ----0000 00000000
ACS[R/W] W
-------- -------- ---00000 ---00000
ESID1[R] W
-------- -------- 00----00 00000000
ESID2[R] W
-------- -------- 00----00 00000000
ESID3[R] W
-------- -------- 00----00 00000000
ESID4[R] W
-------- -------- 00----00 00000000
FlexRay
GTU *5
FlexRay
GTU *5
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
00D140H
00D144H
00D148H
00D14CH
00D150H
00D154H
00D158H
00D15CH
00D160H
00D164H
00D168H
00D16CH
00D170H
00D174H
00D178H
00D17CH
00D180H
00D184H
00D188H
00D18CH
00D190H
00D194H
00D198H
00D19CH
00D1A0H
00D1A4H
00D1A8H
00D1ACH
+0
Address offset value/Register name
+1
+2
ESID5[R] W
-------- -------- 00----00 00000000
ESID6[R] W
-------- -------- 00----00 00000000
ESID7[R] W
-------- -------- 00----00 00000000
ESID8[R] W
-------- -------- 00----00 00000000
ESID9[R] W
-------- -------- 00----00 00000000
ESID10[R] W
-------- -------- 00----00 00000000
ESID11[R] W
-------- -------- 00----00 00000000
ESID12[R] W
-------- -------- 00----00 00000000
ESID13[R] W
-------- -------- 00----00 00000000
ESID14[R] W
-------- -------- 00----00 00000000
ESID15[R] W
-------- -------- 00----00 00000000
OSID1[R] W
-------- -------- 00----00 00000000
OSID2[R] W
-------- -------- 00----00 00000000
OSID3[R] W
-------- -------- 00----00 00000000
OSID4[R] W
-------- -------- 00----00 00000000
OSID5[R] W
-------- -------- 00----00 00000000
OSID6[R] W
-------- -------- 00----00 00000000
OSID7[R] W
-------- -------- 00----00 00000000
OSID8[R] W
-------- -------- 00----00 00000000
OSID9[R] W
-------- -------- 00----00 00000000
OSID10[R] W
-------- -------- 00----00 00000000
OSID11[R] W
-------- -------- 00----00 00000000
OSID12[R] W
-------- -------- 00----00 00000000
OSID13[R] W
-------- -------- 00----00 00000000
OSID14[R] W
-------- -------- 00----00 00000000
OSID15[R] W
-------- -------- 00----00 00000000
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
+3
Block
FlexRay
GTU *5
Reserved
91
D a t a S h e e t
Address
00D1B0H
00D1B4H
00D1B8H
00D1BCH
|
00D2FCH
00D300H
00D304H
00D308H
00D30CH
00D310H
00D314H
00D318H
00D31CH
00D320H
00D324H
00D328H
00D32CH
00D330H
00D334H
00D338H
00D33CH
00D340H
00D344H
00D348H
00D34CH
00D350H
|
00D3ECH
92
CONFIDENTIAL
+0
Address offset value/Register name
+1
+2
+3
Block
NMV1[R] W
00000000 00000000 00000000 00000000
NMV2[R] W
00000000 00000000 00000000 00000000
NMV3[R] W
00000000 00000000 00000000 00000000
FlexRay
NEM *5
-
Reserved
MRC[R/W] W
-----001 10000000 00000000 00000000
FRF[R/W] W
-------1 10000000 ---00000 00000000
FRFM[R/W] W
-------- -------- ---00000 000000-FCL[R/W] W
-------- -------- -------- 10000000
MHDS[R/W] W
-0000000 -0000000 -0000000 00000000
LDTS[R] W
-----000 00000000 -----000 00000000
FSR[R] W
-------- -------- 00000000 -----000
MHDF[R/W] W
-------- -------- -------0 00000000
TXRQ1[R] W
00000000 00000000 00000000 00000000
TXRQ2[R] W
00000000 00000000 00000000 00000000
TXRQ3[R] W
00000000 00000000 00000000 00000000
TXRQ4[R] W
00000000 00000000 00000000 00000000
NDAT1[R] W
00000000 00000000 00000000 00000000
NDAT2[R] W
00000000 00000000 00000000 00000000
NDAT3[R] W
00000000 00000000 00000000 00000000
NDAT4[R] W
00000000 00000000 00000000 00000000
MBSC1[R] W
00000000 00000000 00000000 00000000
MBSC2[R] W
00000000 00000000 00000000 00000000
MBSC3[R] W
00000000 00000000 00000000 00000000
MBSC4[R] W
00000000 00000000 00000000 00000000
FlexRay
MHD *5
-
Reserved
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Address
+0
00D3F0H
00D3F4H
00D3F8H
|
00D3FCH
00D400H
|
00D4FCH
Address offset value/Register name
+1
+2
+3
Block
CREL[R] W
00010000 00111001 00000010 00000110
ENDN[R] W
10000111 01100101 01000011 00100001
FlexRay
GIF *5
-
Reserved
WRDSn[1-64][R/W] W
00000000 00000000 00000000 00000000
WRHS1[R/W] W
--000000 -0000000 -----000 00000000
WRHS2[R/W] W
-------- -0000000 -----000 00000000
WRHS3[R/W] W
-------- -------- -----000 00000000
IBCM[R/W] W
-------- ------00 -------- -----000
IBCR[R/W] W
0------- -0000000 0------- -0000000
00D500H
00D504H
00D508H
00D50CH
00D510H
00D514H
00D518H
|
00D5FCH
00D600H
|
00D6FCH
FlexRay
IBF *5
-
Reserved
RDDSn[1-64][R] W
00000000 00000000 00000000 00000000
RDHS1[R] W
--000000 -0000000 -----000 00000000
RDHS2[R] W
-0000000 -0000000 -----000 00000000
RDHS3[R] W
--000000 --000000 -----000 00000000
MBS[R] W
--000000 --000000 00-00000 00000000
OBCM[R/W] W
-------- ------00 -------- ------00
OBCR[R/W] W
-------- -0000000 0-----00 -0000000
00D700H
00D704H
00D708H
00D70CH
00D710H
00D714H
00D718H
|
00D7FCH
00D800H
|
00EFFCH
00F000H
|
00FEFCH
FlexRay
OBF *5
-
Reserved
-
Reserved
-
Reserved [S]
00FF00H
DSUCR[R/W] B,H,W
-------- -------0
-
-
OCDU [S]
00FF04H
|
00FF0CH
-
-
-
Reserved [S]
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
-
93
D a t a S h e e t
Address
+0
+3
PCSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PSSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF10H
00FF14H
00FF18H
|
00FFF4H
Address offset value/Register name
+1
+2
-
-
-
Block
OCDU [S]
-
Reserved [S]
EDIR1[R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
EDIR0[R] B,H,W
00FFFCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]: It is a system register. The illegal instruction exception (data access error) is generated when reading and
writing to these registers in the user mode.
*5: For FlexRay, the MB91F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F585ASJ has corresponding
functions.
The following registers are reserved registers for models without the FlexRay function.
000125H IRPR2L[5:4], 000E68H, 0004E8H-0004EFH, 00D000H-00D717H
00FFF8H
94
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
INTERRUPT VECTOR TABLE
MB91F583AM/F584AM/F585AM
Interrupt
number
Interrupt
Interrupt factor
Offset
Hexa
level
Deci
deci
mal
mal
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Instruction access protection violation
exception
Data access protection violation
exception
Data access error interrupts
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of invalid instruction
NMI request
Error generation at internal bus
diagnosis
RAM double-bit error
Backup RAM double-bit error
External interrupt 0-7
Reload timer 0 / 1
Reload timer 2 / 3
Multifunction serial interface ch.0
(reception completed)/
Multifunction serial interface ch.0
(status)
Multifunction serial interface ch.0
(transmission completed)
Multifunction serial interface ch.1
(reception completed)/
Multifunction serial interface ch.1
(status)
Multifunction serial interface ch.1
(transmission completed)
Multifunction serial interface ch.2
(reception completed)/
Multifunction serial interface ch.2
(status)
Multifunction serial interface ch.2
(transmission completed)
Multifunction serial interface ch.3
(reception completed)/
Multifunction serial interface ch.3
(status)
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
TBR
default
address
RN*1
Interrupt
request
batch
read
target
0
1
2
3
4
5
00
01
02
03
04
05
-
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
-
-
6
06
-
3E4H
000FFFE4H
-
-
7
07
-
3E0H
000FFFE0H
-
-
8
9
10
11
12
13
14
08
09
0A
0B
0C
0D
0E
-
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
-
15
0F
15(FH)
Fixed
3C0H
000FFFC0H
-
16
17
18
10
11
12
ICR00
ICR01
ICR02
3BCH
3B8H
3B4H
000FFFBCH
000FFFB8H
000FFFB4H
0
1
2
19
13
ICR03
3B0H
000FFFB0H
3*2
20
14
ICR04
3ACH
000FFFACH
4
21
15
ICR05
3A8H
000FFFA8H
5*2
22
16
ICR06
3A4H
000FFFA4H
6
23
17
ICR07
3A0H
000FFFA0H
7*2
24
18
ICR08
39CH
000FFF9CH
8
25
19
ICR09
398H
000FFF98H
9*2
-
-
-
95
D a t a S h e e t
Interrupt factor
Multifunction serial interface ch.3
(transmission completed)
*5
*5
CAN 0
CAN 1
FlexRay 0 *6
FlexRay 1 *6
FlexRay timer 0 *6
FlexRay timer 1 *6
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
Backup RAM diagnosis completed
Backup RAM initialization
completed
Error generation at Backup RAM
diagnosis
Main timer/PLL timer/
PLL gear for FlexRay*6/
PLL alarm for FlexRay*6
Clock calibration unit
(CR oscillation)
U/D counter 0 / 1
Free-run timer 0 (0 detection) /
(compare clear)
Free-run timer 1 (0 detection) /
(compare clear)
Free-run timer 2 (0 detection) /
(compare clear)
PPG 0 / 1 / 2 / 3
Free-run timer 3 (0 detection) /
(compare clear)
Free-run timer 4 (0 detection) /
(compare clear)
Free-run timer 5 (0 detection) /
(compare clear)
PPG 4 / 5
ICU 0 (fetching) / ICU 1 (fetching)
ICU 2 (fetching) / ICU 3 (fetching)
*5
*5
OCU 0 (match) / OCU 1 (match)
OCU 2 (match) / OCU 3 (match)
OCU 4 (match) / OCU 5 (match)
OCU 6 (match) / OCU 7 (match)
OCU 8 (match) / OCU 9 (match)
OCU 10 (match) / OCU 11 (match)
WG dead timer underflow 0 / 1 / 2
WG dead timer reload 0 / 1 / 2
WG DTTI 0
96
CONFIDENTIAL
Interrupt
number
Interrupt
Offset
Hexa
level
Deci
deci
mal
mal
TBR
default
address
RN*1
Interrupt
request
batch
read
target
26
1A
ICR10
394H
000FFF94H
10
-
27
28
29
30
31
32
33
34
1B
1C
1D
1E
1F
20
21
22
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
390H
38CH
388H
384H
380H
37CH
378H
374H
000FFF90H
000FFF8CH
000FFF88H
000FFF84H
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
-
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
20*3
37
25
ICR21
368H
000FFF68H
-
38
26
ICR22
364H
000FFF64H
22
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
24
41
29
ICR25
358H
000FFF58H
25
42
2A
ICR26
354H
000FFF54H
26
43
2B
ICR27
350H
000FFF50H
27
44
2C
ICR28
34CH
000FFF4CH
28
45
46
47
48
49
50
51
52
53
54
2D
2E
2F
30
31
32
33
34
35
36
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
000FFF48H
000FFF44H
000FFF40H
000FFF3CH
000FFF38H
000FFF34H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
29
30
33
34
35
36
37
38
55
37
ICR39
320H
000FFF20H
39
-
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Interrupt factor
Interrupt
number
Interrupt
Offset
Hexa
level
Deci
deci
mal
mal
WG dead timer underflow 3 / 4 / 5
WG dead timer reload 3 / 4 / 5
WG DTTI 1
AD converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
AD converter 8 / 9 / 10 / 11 / 12 / 13 /
14
AD converter 16 / 17 / 18 / 19 / 20 /
21 / 22 / 23
Base timer 0 IRQ 0/
base timer 0 IRQ 1
Base timer 1 IRQ 0/
base timer 1 IRQ 1
DMAC 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
Delay interrupt
System reserved
(Used for REALOS*4)
System reserved
(Used for REALOS*4)
TBR
default
address
RN*1
Interrupt
request
batch
read
target
56
38
ICR40
31CH
000FFF1CH
40
57
39
ICR41
318H
000FFF18H
41
58
3A
ICR42
314H
000FFF14H
42
59
3B
ICR43
310H
000FFF10H
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45
62
63
3E
3F
ICR46
ICR47
304H
300H
000FFF04H
000FFF00H
-
-
64
40
-
2FCH
000FFEFCH
-
-
65
41
-
2F8H
000FFEF8H
-
-
66
42
2F4H
000FFEF4H
|
|
|
|
255
FF
000H
000FFC00H
Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (resource number) is assigned.
The multi-function serial interface status does not support DMA transfer caused by I 2C reception.
"PLL gear for FlexRay" and "PLL alarm for FlexRay" do not support DMA transfer.
REALOS is a trademark of Spansion LLC.
For MB91F583AM/F584AM/F585AM, the interrupt vectors are unused.
For FlexRay, the MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584AMJ/F585AMJ have
corresponding functions.
Used with the INT instruction.
*1 :
*2 :
*3 :
*4 :
*5 :
*6 :
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
97
D a t a S h e e t
MB91F583AS/F584AS/F585AS
Interrupt
Interrupt
number
request
Interrupt
TBR default
Interrupt factor
Offset
RN*1
batch
Hexa
level
address
Deci
read
deci
mal
target
mal
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Instruction access protection violation
exception
Data access protection violation
exception
Data access error interrupts
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of invalid instruction
NMI request
Error generation at internal bus
diagnosis
RAM double-bit error
Backup RAM double-bit error
External interrupt 0-6
Reload timer 0 / 1
Reload timer 2 / 3
Multifunction serial interface ch.0
(reception completed)/
Multifunction serial interface ch.0
(status)
Multifunction serial interface ch.0
(transmission completed)
Multifunction serial interface ch.1
(reception completed)/
Multifunction serial interface ch.1
(status)
Multifunction serial interface ch.1
(transmission completed)
*5
*5
*5
*5
*5
*5
CAN 0
*5
FlexRay 0 *6
FlexRay 1 *6
FlexRay timer 0 *6
FlexRay timer 1 *6
98
CONFIDENTIAL
0
1
2
3
4
5
00
01
02
03
04
05
-
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
-
-
6
06
-
3E4H
000FFFE4H
-
-
7
07
-
3E0H
000FFFE0H
-
-
8
9
10
11
12
13
14
08
09
0A
0B
0C
0D
0E
-
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
-
15
0F
15(FH)
Fixed
3C0H
000FFFC0H
-
16
17
18
10
11
12
ICR00
ICR01
ICR02
3BCH
3B8H
3B4H
000FFFBCH
000FFFB8H
000FFFB4H
0
1
2
19
13
ICR03
3B0H
000FFFB0H
3*2
20
14
ICR04
3ACH
000FFFACH
4
21
15
ICR05
3A8H
000FFFA8H
5*2
22
16
ICR06
3A4H
000FFFA4H
6
-
23
24
25
26
27
28
29
30
31
32
33
34
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
378H
374H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
000FFF84H
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
-
-
-
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Interrupt factor
Interrupt
Interrupt
number
request
Interrupt
TBR default
Offset
RN*1
batch
Hexa
level
address
Deci
read
deci
mal
target
mal
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
Backup RAM diagnosis completed
Backup RAM initialization
completed
Error generation at Backup RAM
diagnosis
Main timer/PLL timer/
PLL gear for FlexRay*6/
PLL alarm for FlexRay*6
Clock calibration unit
(CR oscillation)
U/D counter 0 / 1
Free-run timer 0 (0 detection) /
(compare clear)
Free-run timer 1 (0 detection) /
(compare clear)
Free-run timer 2 (0 detection) /
(compare clear)
PPG 0 / 1 / 2 / 3
Free-run timer 3 (0 detection) /
(compare clear)
Free-run timer 4 (0 detection) /
(compare clear)
Free-run timer 5 (0 detection) /
(compare clear)
PPG 4 / 5
ICU 0 (fetching) / ICU 1 (fetching)
ICU 2 (fetching) / ICU 3 (fetching)
*5
*5
OCU 0 (match) / OCU 1 (match)
OCU 2 (match) / OCU 3 (match)
OCU 4 (match) / OCU 5 (match)
OCU 6 (match) / OCU 7 (match)
OCU 8 (match) / OCU 9 (match)
OCU 10 (match) / OCU 11 (match)
WG dead timer underflow 0 / 1 / 2
WG dead timer reload 0 / 1 / 2
WG DTTI 0
WG dead timer underflow 3 / 4 / 5
WG dead timer reload 3 / 4 / 5
WG DTTI 1
AD converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
AD converter 8 / 9 / 10 / 11 / 12 / 13 /
14
AD converter 19 / 20
Base timer 0 IRQ 0/
base timer 0 IRQ 1
Base timer 1 IRQ 0/
base timer 1 IRQ 1
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
20*3
37
25
ICR21
368H
000FFF68H
-
38
26
ICR22
364H
000FFF64H
22
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
24
41
29
ICR25
358H
000FFF58H
25
42
2A
ICR26
354H
000FFF54H
26
43
2B
ICR27
350H
000FFF50H
27
44
2C
ICR28
34CH
000FFF4CH
28
45
46
47
48
49
50
51
52
53
54
2D
2E
2F
30
31
32
33
34
35
36
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
000FFF48H
000FFF44H
000FFF40H
000FFF3CH
000FFF38H
000FFF34H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
29
30
33
34
35
36
37
38
55
37
ICR39
320H
000FFF20H
39
56
38
ICR40
31CH
000FFF1CH
40
57
39
ICR41
318H
000FFF18H
41
58
3A
ICR42
314H
000FFF14H
42
59
3B
ICR43
310H
000FFF10H
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45
-
99
D a t a S h e e t
Interrupt factor
DMAC 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
Delay interrupt
System reserved
(Used for REALOS*4)
System reserved
(Used for REALOS*4)
Interrupt
Interrupt
number
request
Interrupt
TBR default
Offset
RN*1
batch
Hexa
level
address
Deci
read
deci
mal
target
mal
62
63
3E
3F
ICR46
ICR47
304H
300H
000FFF04H
000FFF00H
-
-
64
40
-
2FCH
000FFEFCH
-
-
65
41
-
2F8H
000FFEF8H
-
-
66
42
2F4H
000FFEF4H
|
|
|
|
255
FF
000H
000FFC00H
Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (resource number) is assigned.
The multi-function serial interface status does not support DMA transfer caused by I 2C reception.
"PLL gear for FlexRay" and "PLL alarm for FlexRay" do not support DMA transfer.
REALOS is a trademark of Spansion LLC.
For MB91F583AS/F584AS/F585AS, the interrupt vectors are unused.
For FlexRay, the MB91F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F585ASJ have corresponding
functions.
Used with the INT instruction.
*1 :
*2 :
*3 :
*4 :
*5 :
*6 :
100
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
ELECTRICAL CHARACTERISTICS
1.
Absolute Maximum Ratings
Rating
Min
Max
Parameter
Symbol
Unit
Power supply voltage *1, *2
Analog power supply
voltage*1 ,*2
Analog reference voltage*1
Input voltage*1
Analog pin input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp current
VCC
VSS-0.3
VSS+6.0
V
AVCC
VSS-0.3
VSS+6.0
V
Remarks
Avcc Vcc
AVRH
VSS-0.3
VSS+6.0
V
AVRH AVCC
VI
VSS-0.3
VCC+0.3
V
VIA
VSS-0.3
VCC+0.3
V
VO
VSS-0.3
VCC+0.3
V
ICLAMP
4
mA
*9
Σ|ICLAMP |
20
mA
*9
IOL1
7
mA
When setting to 2mA*6
"L" level maximum output
IOL2
14
mA
When setting to 4mA *7
current*3
IOL3
17.5
mA
When setting to 5mA *8
IOLAV1
2
mA
When setting to 2mA *6
"L" level average output
IOLAV2
4
mA
When setting to 4mA *7
current*4
IOLAV3
5
mA
When setting to 5mA *8
"L" level total output current*5
ΣIOL
50
mA
*6
IOH1
-7
mA
When setting to 2mA *6
"H" level maximum output
IOH2
-14
mA
When setting to 4mA *7
current*3
IOH3
-17.5
mA
When setting to 5mA *8
IOHAV1
-2
mA
When setting to 2mA *6
"H" level average output
IOHAV2
-4
mA
When setting to 4mA *7
current*4
IOHAV3
-5
mA
When setting to 5mA *8
"H" level total output current*5
ΣIOH
-50
mA
*6
Power consumption
PD
690
mW
Operating temperature
TA
-40
+125
°C
*10, *11
Storage temperature
Tstg
-55
+150
°C
*1: These parameters are based on the condition that V SS=AVSS =0.0V.
*2: Caution must be taken that AVCC does not exceed VCC.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: Corresponding pins: General-purpose ports
*7: Corresponding pins: General-purpose ports of P021 to P023, P025 to P027
*8: Corresponding pins: General-purpose ports other than those of P021 to P023, P025 to P027
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
101
D a t a S h e e t
*9: Corresponding pins: General-purpose ports
Use the devices within recommended operating conditions.
Use the devices with direct voltage (current).
The + B signal should always be applied by connecting a limiting resistor between the + B signal and the
microcontroller.
The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input.
Note that when the microcontroller drive current is low, such as in the low-power consumption modes, the
+ B input potential can increase the potential at the Vcc pin via a protective diode, possibly affecting other
devices.
Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is
supplied through the pin, the microcontroller may operate incompletely.
Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on
reset may not function in the power supply voltage.
Do not leave + B input pins open.
Sample recommended circuit
MB91580M/S series
Protective diode
Limiting resistor
current
+B input (12 to 16V)
*10: To use this product at TA=125°C, equip this on a multilayer board with four or more layers.
To equip this on a single-layer board, change the operating conditions (operating frequency, power supply
voltage, etc) to use this at the power consumption P D=415mW or lower, or use this at T A=105°C or lower.
*11: When it is used exceeding TA=125°C, contact your sales representative.
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
102
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
2.
Recommended Operating Conditions
(VSS= AVSS=0.0V)
Parameter
Power supply
voltage
Smoothing
capacitor*1
Value
Symbol
Min
Max
4.5
4.5
3.7
3.7
5.5
5.5
5.5
5.5
VCC
AVCC
VCC
AVCC
CS
Unit
V
V
V
V
4.7
(tolerance within ±50%)
µF
Remarks
Recommended operation guarantee range
Operation guarantee range
Use a ceramic capacitor or a capacitor that
has the similar frequency characteristics.
Use a capacitor with a capacitance greater
than CS as the smoothing capacitor on the
VCC pin.
Operating
TA
-40
+125
°C
*2
temperature
*1: For connection of smoothing capacitor C S, see the figure below.
*2: When it is used exceeding TA=125°C, contact your sales representative.
C Pin Connection Diagram
C
CS
VS S
AVS S
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under
any conditions other than these conditions may adversely affect reliability of device and could result in
device failure. No warranty is made with respect to any use, operating conditions or combinations not
represented on this data sheet. If you are considering application under any conditions other than listed
herein, please contact sales representatives beforehand.
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
103
D a t a S h e e t
3.
DC Characteristics
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Parameter Symbol
VIH1
"H" level
input voltage
VIH2
Pin name
P000 to P007*,
P010 to P017,
P020, P024,
P030 to P037,
P040 to P047,
P050 to P056,
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
P000 to P007*,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P056,
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
Conditions
Min
104
CONFIDENTIAL
Max
Unit Remarks
When CMOS
schmitt input
level is
selected
0.7 × VCC
-
VCC+0.3
V
When
Automotive
input level is
selected
0.8 × VCC
-
VCC+0.3
V
-
VCC+0.3
V
-
VCC+0.3
VCC+0.3
VCC+0.3
V
V
V
When
FlexRay input
VIH3
0.7 × VCC
level is
selected
VIH4
RSTX, NMIX
0.7 × VCC
VIH5
MD0, MD1
0.7 × VCC
VIH6
DEBUGIF
2.0
*: Only available with MB91F583AM/F584AM/F585AM
P021 to P023,
P025 to P027
Value
Typ
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Parameter Symbol
VIL1
"L" level
input voltage
VIL2
Pin name
P000 to P007*,
P010 to P017,
P020, P024,
P030 to P037,
P040 to P047,
P050 to P056,
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
P000 to P007*,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P056,
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
Conditions
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Max
Unit
When CMOS
schmitt input
level is
selected
Vss-0.3
-
0.3 × VCC
V
When
Automotive
input level is
selected
Vss-0.3
-
0.5 × VCC
V
Vss-0.3
-
0.3 × VCC
V
Vss-0.3
Vss-0.3
Vss-0.3
-
0.3 × VCC
0.3 × VCC
0.8
V
V
V
When
FlexRay input
VIL3
level is
selected
VIL4
RSTX, NMIX
VIL5
MD0, MD1
VIL6
DEBUGIF
*: Only available with MB91F583AM/F584AM/F585AM
P021 to P023,
P025 to P027
Min
Value
Typ
Remarks
105
D a t a S h e e t
(TA: Recommended operating conditions, Vcc=5.0V±10%,VSS= AVSS=0.0V)
Parameter Symbol
"H" level
output
voltage
Conditions
VOH1
P000 to P007*,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P056,
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
Vcc=4.5V
IOH=-2.0mA
Vcc-0.5
-
Vcc
V
VOH2
P021 to P023,
P025 to P027
Vcc=4.5V
IOH=-4.0mA
Vcc-0.5
-
Vcc
V
Vcc-0.5
-
Vcc
V
P000 to P007*,
P010 to P017,
P020, P024,
P030 to P037,
P040 to P047,
P050 to P056,
Vcc=4.5V
VOH3 P060 to P066*,
IOH=-5.0mA
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
*: Only available with MB91F583AM/F584AM/F585AM
106
CONFIDENTIAL
Value
Typ
Pin name
Min
Max
Unit Remarks
When
FlexRay is
selected
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Parameter Symbol
VOL1
VOL2
"L" level
output
voltage
VOL3
VOL4
Pin name
P000 to P007*,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P056,
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
P021 to P023,
P025 to P027
P000 to P007*,
P010 to P017,
P020, P024,
P030 to P037,
P040 to P047,
P050 to P056,
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
P040, P041,
P063*, P064*,
P080*, P081*,
P083*,P084*
Min
Value
Typ
Max
Vcc=4.5V
IOL=2.0mA
0
-
0.4
V
Vcc=4.5V
IOL=4.0mA
0
-
0.4
V
Vcc=4.5V
IOL=5.0mA
0
-
0.4
V
Conditions
Vcc=4.5V
IOL=3.0mA
Vcc=2.7V
IOL=25.0mA
*: Only available with MB91F583AM/F584AM/F585AM
VOL5
DEBUGIF
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
Unit
0
-
0.4
V
0
-
0.25
V
Remarks
When FlexRay
is selected
I2C shared pin
(when I2C is
selected)
107
D a t a S h e e t
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Parameter
Input Leak
Current
Symbol
IIL
RUP1
Pin name
All input pins
Conditions
Vcc= AVCC=5.5V
VSS < VI < VCC
-
RSTX, NMIX
P000 to P007*,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
Pull-up
P050 to P056,
When pull-up
resistance
RUP2
P060 to P066*,
resistance is
P070 to P072,
selected
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
Other thanVCC,
Input
VSS, AVCC,
CIN
Capacitor
AVSS,
C
*: Only available with MB91F583AM/F584AM/F585AM
108
CONFIDENTIAL
Value
Min Typ Max
Unit
-5
-
+5
µA
25
-
100
kΩ
25
-
100
kΩ
-
5
15
pF
Remarks
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Parameter Symbol
Pin
name
Conditions
Normal
operations
FCP=128MHz,
FCPM=128MHz,
FCPP=32MHz
Normal
operations
FCP=128MHz,
FCPM=32MHz,
FCPP=32MHz
Power supply
current
ICC
VCC5
Normal
operations
FCP=80MHz,
FCPM=80MHz,
FCPP=40MHz
Normal
operations
FCP=80MHz,
FCPM=40MHz,
FCPP=40MHz
Value
Min Typ Max
Unit
Remarks
-
80
110
mA
FlexRay =ON
-
73
103
mA
FlexRay =OFF
-
77
107
mA
FlexRay =ON
-
70
100
mA
FlexRay =OFF
-
62
89
mA
FlexRay =ON
-
57
85
mA
FlexRay =OFF
-
61
88
mA
FlexRay =ON
-
56
84
mA
FlexRay =OFF
Flash write
FCP=128MHz,
95
125
mA *
FCPM=128MHz,
FCPP=32MHz
Flash erase
FCP=128MHz,
95
125
mA *
FCPM=128MHz,
FCPP=32MHz
*: This series has 2 types of flash; main flash and WorkFlash; however, this is the specification when only one of
those is written/erased.
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
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109
D a t a S h e e t
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Parameter Symbol
Pin
name
CPU sleep
FCP=128MHz,
FCPm=128MHz,
FCPP=32MHz
Bus sleep
FCP=128MHz,
FCPm=128MHz,
FCPP=32MHz
ICCS
ICCBS
Clock mode
4MHz source
oscillation
ICCT
Power supply
current
Conditions
VCC5
ICCTS
ICCH
ICCHS
Clock mode
shutdown
4MHz source
oscillation
STOP mode
STOP mode
shutdown
Value
Unit
Min Typ Max
Remarks
-
41
66
mA *1, *2 ,*3, *4
-
19
45
mA *1, *2 ,*3 ,*4
-
1.2
1.8
mA
-
2.7
3.3
mA
-
0.3
0.4
mA
-
1.8
1.9
mA
-
0.7
0.8
mA
-
2.2
2.3
mA
-
0.6
1.1
mA TA=25°C, *1 ,*2
-
1.0
1.6
mA TA=25°C, *3 ,*4
-
0.1
0.2
mA TA=25°C, *1, *2
When using external clock*5
TA=25°C, *1, *2 ,*3 ,*4
When using crystal
TA=25°C, *1, *2, *3, *4
When using external clock*5
TA=25°C, *1, *2
When using crystal
TA=25°C, *1, *2
When using external clock*5
TA=25°C, *3, *4
When using crystal
TA=25°C, *3 ,*4
0.5
0.6 mA TA=25°C, *3, *4
*1: MB91F583AMG/F584AMG/F585AMG/F583AMH/F584AMH/F585AMH
*2: MB91F583ASG/F584ASG/F585ASG/F583ASH/F584ASH/F585ASH
*3: MB91F583AMJ/F584AMJ/F585AMJ/F583AMK/F584AMK/F585AMK
*4: MB91F583ASJ/F584ASJ/F585ASJ/F583ASK/F584ASK/F585ASK
*5: The power supply current is the current value when the external clock is supplied from the X1 pin. Note that
the power supply current value when using the external clock is different from that using the oscillator.
110
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Source oscillation
clock frequency
Source oscillation
clock cycle time
Internal operating
clock frequency*
Internal operating
clock cycle time*
Value
Pin
Conditions
Unit
name
Min Typ Max
FC
X0, X1
-
4
-
20
MHz
tCYL
X0, X1
-
50
-
250
ns
FCP
FCPP
FCPM
tCP
tCPP
tCPM
-
-
7.82
25
7.82
-
128
40
128
-
MHz
MHz
MHz
ns
ns
ns
Remarks
CPU clock
Peripheral bus clock
Motor clock
CPU clock
Peripheral bus clock
Motor clock
CAN PLL jitter
tPJ
-10
+10
ns
(during lock)
Built-in CR
FCCR
50 100 150 kHz
oscillation frequency
*: The maximum/minimum value is defined when using the main clock and PLL clock.
X0,X1 clock timing
tCYL
X0
CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
t1
t2
t3
tn-1
tn
Ideal clock
Slow
t1
PLL output
t2
t3
tn-1
tn
Fast
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
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111
D a t a S h e e t
Guaranteed operation range
Power supply voltage VCC (V)
Internal operation clock frequency vs. Power supply voltage
MB91F58x recommended
guaranteed operation range
MB91F58x guaranteed
operation range
5.5
4.5
3.7
PLL guaranteed
operation range
2
4
128
Internal operation clock frequency FCP (MHz)
Note: The CPU will be reset at the power supply voltage of the low-voltage detection setting
voltage or less.
Oscillation clock frequency vs. Internal operation clock frequency
Internal operation clock frequency
PLL clock
Main
Multipli Multipli Multipli Multipli
Multiplied
Multiplied
clock
...
...
ed by 1 ed by 2 ed by 3 ed by 4
by 20
by 32
Oscillation clock
4MHz 2MHz 4MHz
frequency
8MHz
12MHz
16MHz ...
80MHz
...
128MHz
Example of oscillation circuit
X0
X1
R=330Ω
4MHz
C1=12pF
C2=12pF
Note: If it is impossible to start the oscillation within or equal to 20ms when starting from the
oscillation stop state, the clock supervisor performs a detection of oscillation stop and moves
to the fail safe operation.
Design your print circuit board so that the oscillator can start oscillation within 20ms.
In addition, when configuring the oscillator circuit, it is recommended to ask matching
evaluation of the circuit to oscillator manufacturers for the design.
112
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
AC characteristics are specified by the following measurement reference voltage values.
Input Signal Waveform
Hysteresis Input Pin (Automotive)
Output Signal Waveform
Output Pin
0.8Vcc
2.4V
0.5Vcc
0.8V
Hysteresis Input Pin (CMOS schmitt)
0.7Vcc
0.3Vcc
Hysteresis Input Pin (FlexRay)
0.65Vcc
0.35Vcc
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
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113
D a t a S h e e t
(2) Reset input
(TA: Recommended operating conditions, Vcc =5.0V±10%, Vss=AVss=0.0V)
Parameter
Symbol
Value
Min
Pin
Conditions
name
10
Reset input time
tRSTL
RSTX
-
Unit
Remarks
-
µs
During normal
operation
-
ms
At Stop mode
-
µs
At Clock mode
Max
Oscillation time of
oscillator*
+0.1
100
Reset input
1
µs
removal width
*: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred µs and several ms, and for an external clock, the time is 0 ms.
tRSTL
RSTX
0.2Vcc
0.2Vcc
In Stop mode
tRSTL
RSTX
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 s
Oscillation time
of oscillator
Internal reset
114
CONFIDENTIAL
Oscillation stabilization
waiting time
Instruction
execution
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
(3) Power-on Conditions
(TA: Recommended operating conditions, VSS=0.0V)
Parameter
Symbol
Pin
name
Conditions
Value
Min Typ Max
Unit
Remarks
Level detection
When turning
VCC5
2.024 2.200 2.376
V
voltage
on power
Level detection
During voltage
VCC5
100
mV
hysteresis width
drop
Level detection
30
μs
*1
time
Slope detection
VCC=level detection
undetected
VCC5
4
mV/μs *2
release level
standard
Power off time
tOFF
VCC5
50
ms
*3
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope
detection. This is the standard when the power supply fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss.
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
115
D a t a S h e e t
(4) Multi-function Serial
(4-1) CSIO timing (SMR:MD2-0="010"b)
(4-1-1) Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect level "H"
(SMR:SCINV=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Serial clock cycle
time
tSCYC
SCK SOT
delay time
tSLOVI
Valid SIN SCK
setup time
tIVSHI
SCK Valid SIN
hold time
tSHIXI
Serial clock "H"pulse
width
Serial clock "L"pulse
width
tSHSL
tSLSH
Pin name
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*, SOT0_0,
Master mode
SOT0_1*, SOT1,
CL=50pF
*
*
SOT2 , SOT3
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*, SIN0_0,
SIN0_1*, SIN1, SIN2*,
SIN3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK SOT
tSLOVE SCK3*, SOT0_0,
delay time
SOT0_1*, SOT1,
SOT2*, SOT3*
SCK0_0, SCK0_1*,
Valid SIN SCK
tIVSHE
SCK1, SCK2*,
setup time
SCK3*, SIN0_0,
SCK Valid SIN
SIN0_1*, SIN1, SIN2*,
tSHIXE
hold time
SIN3*
SCK0_0, SCK0_1*,
SCK fall time
tF
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK rise time
tR
SCK1, SCK2*,
SCK3*
*: Only available with MB91F583AM/F584AM/F585AM
Notes:
116
CONFIDENTIAL
Conditions
Slave mode
CL=50pF
Value
Unit Remarks
Min Max
4tCPP
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
SIN
Master Mode
tSLSH
SCK
VIH
VIH
VIL
VIL
tF
SOT
tSHSL
VIH
tR
tSLOVE
VOH
VOL
tIVSHE
SIN
VIH
VIL
tSHIXE
VIH
VIL
Slave Mode
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
117
D a t a S h e e t
(4-1-2) Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect level "L"
(SMR:SCINV=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Serial clock cycle
time
tSCYC
SCK SOT
delay time
tSHOVI
Valid SIN SCK
setup time
tIVSLI
SCK Valid SIN
hold time
tSLIXI
Serial clock "H"pulse
width
Serial clock "L"pulse
width
tSHSL
tSLSH
Pin name
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*, SOT0_0,
SOT0_1*, SOT1,
SOT2*, SOT3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*, SIN0_0,
SIN0_1*, SIN1,
SIN2*, SIN3*
Conditions
Master mode
CL=50pF
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK SOT
tSHOVE SCK3*, SOT0_0,
delay time
SOT0_1*, SOT1,
SOT2*, SOT3*
Slave mode
SCK0_0, SCK0_1*,
Valid SIN SCK
tIVSLE
CL=50pF
SCK1, SCK2*,
setup time
SCK3*, SIN0_0,
SCK Valid SIN
SIN0_1*, SIN1,
tSLIXE
hold time
SIN2*, SIN3*
SCK0_0, SCK0_1*,
SCK fall time
tF
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK rise time
tR
SCK1, SCK2*,
SCK3*
*: Only available with MB91F583AM/F584AM/F585AM
Notes:
118
CONFIDENTIAL
Value
Unit Remarks
Min
Max
4tCPP
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
tSLIXI
VIH
SIN
VIH
VIL
VIL
Master Mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
VIL
VIL
tSHOVE
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave Mode
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
119
D a t a S h e e t
(4-1-3) SPI compatible (SCR:SPI=1) and serial clock output signal detect level "H" (SMR:SCINV=0)
(TA: Recommended operating conditions, VCC =5.0V±10% , VSS=AVSS=0.0V)
Parameter
Symbol
Serial clock cycle
time
tSCYC
SCK SOT
delay time
tSHOVI
Valid SIN SCK
setup time
tIVSLI
SCK Valid SIN
hold time
tSLIXI
SOT SCK
delay time
tSOVLI
Serial clock
"H"pulse width
Serial clock "L"pulse
width
tSHSL
tSLSH
Pin name
Conditions
SCK0_0,
SCK0_1*, SCK1,
SCK2*, SCK3*
SCK0_0,
SCK0_1*, SCK1,
SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*,
SOT3*
SCK0_0,
Master mode
SCK0_1*, SCK1,
CL=50pF
SCK2*, SCK3*,
SIN0_0, SIN0_1*,
SIN1, SIN2*,
SIN3*
SCK0_0,
SCK0_1*, SCK1,
SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*,
SOT3*
SCK0_0,
SCK0_1*, SCK1,
SCK2*, SCK3*
SCK0_0,
SCK0_1*, SCK1,
SCK2*, SCK3*,
SCK SOT
tSHOVE
SOT0_0, SOT0_1*,
delay time
SOT1, SOT2*,
SOT3*
Slave mode
SCK0_0,
Valid SIN SCK
tIVSLE
CL=50pF
SCK0_1*, SCK1,
setup time
SCK2*, SCK3*,
SIN0_0, SIN0_1*,
SCK Valid SIN
tSLIXE SIN1, SIN2*,
hold time
SIN3*
SCK0_0,
SCK fall time
tF
SCK0_1*, SCK1,
SCK2*, SCK3*
SCK0_0,
SCK rise time
tR
SCK0_1*, SCK1,
SCK2*, SCK3*
*: Only available with MB91F583AM/F584AM/F585AM
Notes:
120
CONFIDENTIAL
Value
Min
Max
Unit Remarks
4tCPP
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCPP-30
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
Master Mode
tSLSH
tSHSL
VIH
VIH
VIH
SCK
VIL
tF
VIL
tR
VIL
tSHOVE
*
SOT
VOH
VOL
VOH
VOL
tSLIXE
tIVSLE
SIN
VIH
VIH
VIL
VIL
*: Changes when writing to TDR register
Slave Mode
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
121
D a t a S h e e t
(4-1-4) SPI compatible (SCR:SPI=1) and serial clock output signal detect level "L" (SMR:SCINV=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Serial clock cycle
time
tSCYC
SCK SOT
delay time
tSLOVI
Valid SIN SCK
setup time
tIVSHI
SCK Valid SIN
hold time
tSHIXI
SOT SCK
delay time
tSOVHI
Serial clock
"H" pulse width
Serial clock
"L" pulse width
tSHSL
tSLSH
Pin name
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*, SOT0_0,
SOT0_1*, SOT1,
SOT2*, SOT3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*, SIN0_0,
SIN0_1*, SIN1,
SIN2*, SIN3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*, SOT0_0,
SOT0_1*, SOT1,
SOT2*, SOT3*
Conditions
Master mode
CL=50pF
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK SOT
tSLOVE SCK3*, SOT0_0,
delay time
SOT0_1*, SOT1,
SOT2*, SOT3*
Slave mode
SCK0_0, SCK0_1*,
Valid SIN SCK
tIVSHE
CL=50pF
SCK1, SCK2*,
setup time
SCK3*, SIN0_0,
SCK Valid SIN
*
tSHIXE SIN0_1 , SIN1,
hold time
*
SIN2 , SIN3*
SCK0_0, SCK0_1*,
SCK fall time
tF
SCK1, SCK2*,
SCK3*
SCK0_0, SCK0_1*,
SCK rise time
tR
SCK1, SCK2*,
SCK3*
*: Only available with MB91F583AM/F584AM/F585AM
Notes:
122
CONFIDENTIAL
Value
Unit
Min Max
4tCPP
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCPP-30
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
Remarks
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master Mode
tSHSL
VIH
SCK
VIL
tR
tSLSH
VIH
tF
*
SOT
VOH
VOL
tSLOVE
VOH
VOL
tIVSHE
SIN
VIH
VIL
VIL
tSHIXE
VIH
VIL
VIH
VIL
*: Changes when writing to TDR register
Slave Mode
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
123
D a t a S h e e t
(4-1-5) When the serial chip select is used (SCSCR:CSEN=1)
Serial clock output signal detect level "H" (SMR:SCINV=0)
Serial chip select inactive level "H" (SCSCR:CSLVL=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
SCS SCK
SCK1, SCK2*4,
tCSSI
tCSSU*1+0
setup time
SCK3*4,
SCS1, SCS2*4,
Master mode
SCK SCS
tCSHI
tCSHD*2-50
SCS3*4
CL=50pF
hold time
SCS deselect
SCS1, SCS2*4,
-50+5tCPP
tCSDI
time
SCS3*4
+tCSDS*3
SCS SCK
SCK1, SCK2*4,
tCSSE
3tCPP+30
setup time
SCK3*4,
SCS1, SCS2*4,
SCK SCS
tCSHE SCS3*4
0
hold time
SCS deselect
SCS1, SCS2*4,
Slave mode
tCSDE
3tCPP+30
time
SCS3*4
CL=50pF
SCS SOT
SCS1, SCS2*4,
tDSE
delay time
SCS3*4,
SOT1, SOT2*4,
SCS SOT
tDEE
0
SOT3*4
delay time
*1: tCSSU =SCSTR:CSSU7-0 Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 Serial chip select timing operation clock
*4: Only available with MB91F583AM/F584AM/F585AM
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
124
CONFIDENTIAL
Max
Unit Remarks
tCSSU*1+50
ns
tCSHD*2+0
ns
+50+5tCPP
+tCSDS*3
ns
-
ns
-
ns
-
ns
40
ns
-
ns
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master Mode
SCS input
tCSHE
tCSSE
SCK input
SOT
(Normal Sync
transfer)
tCSDE
tDEE
tDSE
SOT
(SPI compatible)
Slave Mode
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
125
D a t a S h e e t
(4-1-6) When the serial chip select is used (SCSCR:CSEN=1)
Serial clock output signal detect level "L" (SMR:SCINV=1)
Serial chip select inactive level "H" (SCSCR:CSLVL=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
SCS SCK
SCK1, SCK2*4,
tCSSI
tCSSU*1+0
setup time
SCK3*4,
SCS1, SCS2*4,
Master mode
SCK SCS
tCSHI
tCSHD*2-50
SCS3*4
CL=50pF
hold time
SCS deselect
SCS1, SCS2*4,
-50+5tCPP
tCSDI
time
SCS3*4
+tCSDS*3
SCS SCK
SCK1, SCK2*4,
tCSSE
3tCPP+30
setup time
SCK3*4,
SCS1, SCS2*4,
SCK SCS
tCSHE SCS3*4
0
hold time
SCS deselect
SCS1, SCS2*4,
Slave mode
tCSDE
3tCPP+30
time
SCS3*4
CL=50pF
SCS SOT
SCS1, SCS2*4,
tDSE
delay time
SCS3*4,
SOT1, SOT2*4,
SCS SOT
tDEE
0
SOT3*4
delay time
*1: tCSSU =SCSTR:CSSU7-0 Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 Serial chip select timing operation clock
*4: Only available with MB91F583AM/F584AM/F585AM
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
126
CONFIDENTIAL
Max
Unit Remarks
tCSSU*1+50
ns
tCSHD*2+0
ns
+50+5tCPP
+tCSDS*3
ns
-
ns
-
ns
-
ns
40
ns
-
ns
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
SCS output
tCSHI
tCSSI
tCSDI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master Mode
SCS input
tCSHE
tCSSE
SCK input
SOT
(Normal Sync
transfer)
tCSDE
tDEE
tDSE
SOT
(SPI compatible)
Slave Mode
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
127
D a t a S h e e t
(4-1-7) When the serial chip select is used (SCSCR:CSEN=1)
Serial clock output signal detect level "H" (SMR:SCINV=0)
Serial chip select inactive level "L" (SCSCR:CSLVL=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
SCS SCK
SCK1, SCK2*4,
tCSSI
tCSSU*1+0
setup time
SCK3*4,
SCS1, SCS2*4,
Master mode
SCK SCS
tCSHI
tCSHD*2-50
SCS3*4
CL=50pF
hold time
SCS deselect
SCS1, SCS2*4,
-50+5tCPP
tCSDI
time
SCS3*4
+tCSDS*3
SCS SCK
SCK1, SCK2*4,
tCSSE
3tCPP+30
setup time
SCK3*4,
SCS1, SCS2*4,
SCK SCS
tCSHE SCS3*4
0
hold time
SCS deselect
SCS1, SCS2*4,
Slave mode
tCSDE
3tCPP+30
time
SCS3*4
CL=50pF
SCS SOT
SCS1, SCS2*4,
tDSE
delay time
SCS3*4,
SOT1, SOT2*4,
SCS SOT
tDEE
0
SOT3*4
delay time
*1: tCSSU =SCSTR:CSSU7-0 Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 Serial chip select timing operation clock
*4: Only available with MB91F583AM/F584AM/F585AM
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
128
CONFIDENTIAL
Max
Unit Remarks
tCSSU*1+50
ns
tCSHD*2+0
ns
+50+5tCPP
+tCSDS*3
ns
-
ns
-
ns
-
ns
40
ns
-
ns
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master Mode
tCSDE
SCS input
tCSHE
tCSSE
SCK input
SOT
(Normal Sync
transfer)
tDEE
tDSE
SOT
(SPI compatible)
Slave Mode
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
129
D a t a S h e e t
(4-1-8) When the serial chip select is used (SCSCR:CSEN=1)
Serial clock output signal detect level "L" (SMR:SCINV=1)
Serial chip select inactive level "L" (SCSCR:CSLVL=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
SCS SCK
SCK1, SCK2*4,
tCSSI
tCSSU*1+0
setup time
SCK3*4,
SCS1, SCS2*4,
Master mode
SCK SCS
tCSHI
tCSHD*2-50
SCS3*4
CL=50pF
hold time
SCS deselect
SCS1, SCS2*4,
-50+5tCPP
tCSDI
time
SCS3*4
+tCSDS*3
SCS SCK
SCK1, SCK2*4,
tCSSE
3tCPP+30
setup time
SCK3*4,
SCS1, SCS2*4,
SCK SCS
tCSHE SCS3*4
0
hold time
SCS deselect
SCS1, SCS2*4,
Slave mode
tCSDE
3tCPP+30
time
SCS3*4
CL=50pF
SCS SOT
SCS1, SCS2*4,
tDSE
delay time
SCS3*4,
SOT1, SOT2*4,
SCS SOT
tDEE
0
SOT3*4
delay time
*1: tCSSU =SCSTR:CSSU7-0 Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 Serial chip select timing operation clock
*4: Only available with MB91F583AM/F584AM/F585AM
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
130
CONFIDENTIAL
Max
Unit Remarks
tCSSU*1+50
ns
tCSHD*2+0
ns
+50+5tCPP
+tCSDS*3
ns
-
ns
-
ns
-
ns
40
ns
-
ns
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master Mode
tCSDE
SCS input
tCSHE
tCSSE
SCK input
SOT
(Normal Sync
transfer)
tDEE
tDSE
SOT
(SPI compatible)
Slave Mode
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
131
D a t a S h e e t
(4-2) UART (Async Serial Interface) timing (SMR:MD2-0="000"b, "001"b)
(4-2-1) When the external clock is selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Value
Min
Max
Conditions
Serial clock
tSLSH
"L" pulse width
SCK0_0,
Serial clock
tSHSL SCK0_1*, SCK1,
CL=50pF
"H" pulse width
SCK2*, SCK3*
SCK fall time
tF
SCK rise time
tR
*: Only available with MB91F583AM/F584AM/F585AM
tR
SCK
tCPP+10
-
ns
tCPP+10
-
ns
-
5
5
ns
ns
tF
tSHSL
Unit
tSLSH
VIH
VIH
VIL
Remarks
VIH
VIL
VIL
When the external clock is selected
(4-3) LIN interface (v2.1)( LIN Communication Control Interface (v2.1)) timing (SMR:MD2-0="011"b)
(4-3-1) When the external clock is selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Value
Min
Max
Conditions
Serial clock
tSLSH
"L" pulse width
SCK0_0,
Serial clock
tSHSL
SCK0_1*, SCK1,
CL=50pF
"H" pulse width
SCK2*, SCK3*
SCK fall time
tF
SCK rise time
tR
*: Only available with MB91F583AM/F584AM/F585AM
tR
SCK
VIH
VIL
tCPP+10
-
ns
tCPP+10
-
ns
-
5
5
ns
ns
tF
tSHSL
Unit
Remarks
tSLSH
VIH
VIH
VIL
VIL
When the external clock is selected
132
CONFIDENTIAL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
2
(4-4) I C timing (SMR:MD2-0="100"b)
(TA: Recommended operating conditions, VCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
SCL clock
frequency
"Repeat START
condition" hold
time
SDA SCL
"L" width for SCL
clock
"H" width for SCL
clock
"Repeat START
condition" setup
time
SCL SDA
Data hold time
SCL SDA
Data setup time
SDA SCL
"STOP condition"
setup time
SCL SDA
Bus free time
between "STOP
condition" and
"START condition"
Noise filter
Symbol
fSCL
tHDSTA
tLOW
tHIGH
Pin name
Conditions
SCK0_0,
SCK0_1*5,
SCK2*5, SCK3*5
(SCL)
SCK0_0,
SCK0_1*5,
SCK2*5, SCK3*5
(SCL)
SOT0_0,
SOT0_1*5,
SOT2*5, SOT3*5
(SDA)
SCK0_0,
SCK0_1*5,
SCK2*5, SCK3*5
(SCL)
Standard High-spee
mode
d mode*3 Unit Remarks
Min Max Min Max
0
100
0
400
kHz
4.0
-
0.6
-
µs
4.7
-
1.3
-
µs
4.0
-
0.6
-
µs
4.7
-
0.6
-
µs
CL=50pF
R=(VP/IOL) *1
tSUSTA
tHDDAT
tSUDAT
SCK0_0,
SCK0_1*5,
SCK2*5, SCK3*5
(SCL)
SOT0_0,
SOT0_1*5,
SOT2*5, SOT3*5
(SDA)
tSUSTO
tBUF
-
tSP
-
0
3.45
*2
0
250
-
4.0
4.7
2tCPP
*4
0.90
*3
µs
100
-
ns
-
0.6
-
µs
-
1.3
-
µs
-
ns
-
2tCPP
*4
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively.
VP shows that the power supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (t LOW) of the SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCPP is the peripheral clock cycle time. Adjust the clock of the peripheral bus to 8MHz or more when using
I2C.
*5: Only available with MB91F583AM/F584AM/F585AM
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
133
D a t a S h e e t
SDA
t SUDAT
t SUSTA
t BUF
t LOW
SCL
t HDSTA
134
CONFIDENTIAL
t HDDAT
t HIGH
t HDSTA
t SP
t SUSTO
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
(5) Timer Input Timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Input pulse
width
Symbol
Pin name
tTIWH,
tTIWL
TIN0 to TIN3,
IN0 to IN3,
FRCK0 to FRCK5,
TIOA1, TIOB0,
TIOB1
AIN0,AIN1,
BIN0,BIN1,
ZIN0,ZIN1
Conditions
Value
Min Max
Unit
-
4tCPP
-
ns
-
2tCPP
-
ns
Remarks
Timer input timing
TINx
INx
FRCKx
TIOAx,TIOBx
AINx,BINx,ZINx
tTIWH
VIH
t TIWL
VIH
VIL
VIL
(6) Trigger Input Timing
(TA: Recommended operating conditions, VCC =5.0V±10% VSS=AVSS=0.0V)
Parameter
Input pulse
width
Symbol
Pin name
tTRGH,
tTRGL
INT0 to INT6, INT7*,
ADTG0 to ADTG2,
RX0, RX1*,
TRG0, TRG1,
DTTI0
Conditions
Value
Min Max
Unit
5tCPP
-
ns
1
-
s
Remarks
At Stop mode
*: Only available with MB91F583AM/F584AM/F585AM
Trigger input timing
INTx
ADTGx
RXx
TRGx
DTTIx
tTRGH
VIH
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
t TRGL
VIH
VIL
VIL
135
D a t a S h e e t
(7) NMI Input Timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Conditions
tNMIL
NMIX
-
Input pulse width
Value
Min
Max
4tCPP
-
Unit
Remarks
ns
NMIX input timing
t NMIL
NMIX
VIH
VIH
VIL
136
CONFIDENTIAL
VIL
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
(8) Low-voltage Detection (External Low-voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0V)
Parameter
Power supply
voltage range
Symbol
Pin
name
Conditions
VDP5
VCC5
-
Min
Value
Typ
Max
3.7
-
5.5
Unit
Remarks
V
Detection voltage
VDL
VCC5
*1
-8%
3.9
+8%
V
Hysteresis width
VHYS
VCC5
-
-
0.1
-
V
When power
supply voltage falls
and detection level
is set initially
When power
supply voltage rises
Low-voltage
Td
30
μs
detection time
Power supply
voltage
VCC5
-2
2
V/ms *2
fluctuation rate
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the
low-voltage detection time (Td), there is the possibility to generate or release after the power supply voltage
has exceeded the detection voltage range.
*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation
of the power supply within the limits of the power supply voltage fluctuation rate.
(9) Low-voltage Detection (Internal Low-voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0V)
Min
Value
Typ
Max
-
1.1
-
1.3
V
-
*
0.8
0.9
1.0
V
-
-
-
0.1
-
V
Symbol
Pin
name
Conditions
Power supply
voltage range
VRDP5
-
Detection voltage
VRDL
Hysteresis width
VRHYS
Parameter
Unit
Remarks
When power
supply voltage falls
When power
supply voltage
rises
Low-voltage
30
μs
detection time
*: If the fluctuation of the power supply is faster than the low-voltage detection time, there is a possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
CONFIDENTIAL
137
D a t a S h e e t
5.
A/D Converter
(1) Electrical Characteristics
(TA: Recommended operating conditions, VCC =5.0V±10%, AVCC=5.0V±10%, VSS=AVSS=0.0V)
Min
Value
Typ
Max
-
-4.0
-
12
+4.0
bit
LSB
-
-1.9
-
+1.9
LSB
Parameter
Symbol
Pin name
Resolution
Non linearity error
Differential
linearity error
-
Zero transition
voltage
VOT
Full-scale
transition voltage
VFST
Sampling time
Compare time
A/D conversion
time
tSMP
tCMP
tCNV
Analog port input
current
IAIN
Analog input
voltage
VAIN
AVRH
Reference voltage
AVRL
IA
Power supply
current
IAH
IR
IRH
Variation between
channels
-
AN0 to AN14, AN16 to
AVRL+
AN18*3, AN19, AN20,
0.5LSB-20
AN21 to AN23*3
AN0 to AN14, AN16 to
AVRHAN18*3, AN19, AN20,
1.5LSB-20
*3
AN21 to AN23
0.3
0.7
AN0 to AN14, AN16 to
AN18*3, AN19, AN20,
AN21 to AN23*3
AN0 to AN14, AN16 to
AN18*3, AN19, AN20,
AN21 to AN23*3
AVRH0,
AVRH1
AVRL0,
AVRL1,
AVCC0,
AVCC1
AVRH0,
AVRH1
AN0 to AN14, AN16 to
AN18*3, AN19, AN20,
AN21 to AN23*3
-
-
Unit
Remarks
AVRL+
mV
0.5LSB+20
1LSB=
(VFST-VOT)/
4094
AVRHmV
1.5LSB+20
-
12
28
µs
µs
*1
*1
1.0
-
40
µs
*1
-1.0
-
1.0
µA
VAVSS VAIN
VAVCC
AVSS
-
AVRH
V
4.5
-
5.5
V
-
0.0
-
V
-
1.5
2.1
mA
-
-
25
-
3
6
-
-
4.8
-
-
4
Avcc AVRH
3 units
operating
3 units
µA
operating*2
3 units
mA
operating
3 units
µA
operating*2
LSB Every 1 unit*4
*1: Time for each channel.
*2: The Power supply current (Vcc=AVcc=5.0V) is specified if the A/D converter is not operating and CPU is
stopped.
*3: Only available with MB91F583AM/F584AM/F585AM
*4: Unit0 AN0 to AN7
Unit1 AN8 to AN14
Unit2 AN16 to AN23
138
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(2) Definition of Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Linearity error : Deviation of the actual conversion characteristics from a straight line that connects the
zero transition point ("0000 0000 0000""0000 0000 0001") to the full-scale
transition point ("1111 1111 1110""1111 1111 1111").
Differential linearity error: Deviation of the input voltage from the ideal value that is required to
change the output code by 1LSB.
Linearity error
Differential linearity error
FFF
Ideal characteristics
Actual conversion
characteristics
{1 LSB (N - 1) + VOT}
N+1
Digital output
FFD
VFST
(Actuallymeasured
value)
004
VNT
(Actually-measured value)
Actual conversion
characteristics
003
Digital output
FFE
Actual conversion
characteristics
N
N-1
V(N+1)T
VNT
002
(Actually-measured
value)
(Actually-measured value)
Ideal characteristics
Actual conversion
characteristics
N-2
001
VOT (Actually-measured value)
AVSS
(AVRL)
AVRH
Analog input
AVSS
(AVRL)
Analog input
AVRH
VNT - {1LSB×(N-1) + V OT}
[LSB]
1LSB
V(N + 1)T - VNT
Differential linearity error of digital output N =
-1 LSB [LSB]
1LSB
VFST - VOT
1LSB =
[V]
4094
Linearity error of digital output N =
VOT: Voltage at which the digital output changes from "000 H" to "001 H".
VFST: Voltage at which the digital output changes from "FFE H" to "FFF H".
(3) Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling time for analog voltages may not be sufficient.
In this case, it is recommended to connect the capacitor (approx. 0.1 µF) to the analog input pin.
Analog input circuit model
Comparator
Analog input
R
C
Sampling ON
12bit A/D
R
1.9kΩ (max)
C
8.3pF (max) (4.5V
Avcc
5.5V)
Note: Listed values must be considered as reference values.
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6.
D/A Converter
(TA: Recommended operating conditions, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Resolution
Differential linearity
error
140
CONFIDENTIAL
Min
Value
Typ
Max
-
-
-
10
bit
-
-4.0
-
+4.0
LSB
Symbol
Pin name
-
Unit
Remarks
When the analog output
voltage is 0.5V to 4.5V
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
7.
Flash Memory
(1) Electrical Characteristics
Parameter
Value
Min
Typ
Max
Unit
-
200
800
ms
-
300
1100
ms
-
400
2000
ms
-
700
3700
ms
8-bit writing time
-
9
288
µs
16-bit writing time
-
12
384
µs
ECC writing time
-
9
288
µs
Sector erase time
Remarks
8 Kbyte sector*1
excluding internal preprogramming
time
8 Kbyte sector*1
including internal preprogramming
time
64 Kbyte sector*1
excluding internal preprogramming
time
64 Kbyte sector*1
including internal preprogramming
time
Excluding overhead time at system
level*1
Excluding overhead time at system
level*1
Excluding overhead time at system
level*1
1,000 cycles/20 years,
Average temperature TA=+85°C *3
10,000 cycles/10 years,
100,000 cycles/5 years
*1: The guaranteed value for erase up to 100,000 cycles
*2: Number of erase cycles for each sector
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).
Erase cycle*2/
Data retention time
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(2) Notes
While the Flash memory is written or erased, shutdown of the external power (Vcc) is prohibited.
In the application system where Vcc might disappear while writing or erasing, be sure to turn the power off
by using an external low-voltage detection function.
To put it concretely, after the external power supply voltage falls below the detection voltage (V DL*), hold
Vcc at 2.7V or more within the duration calculated by the following expression:
Td*[µs] + (PCLK cycle[µs] × 257) + 50[µs]
*: See "4. AC characteristics (8) Low-voltage detection (External low-voltage detection)."
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EXAMPLE CHARACTERISTICS
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
normal operation
(VCC = 5.5V)
100.00
ICC5 [mA]
(1)
(2)
(3)
(4)
(1)Fcp=128MHz, Fcpp=32MHz, Fcpm=128MHz, FlexRay=ON
(2)Fcp=128MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=ON
(3)Fcp=80MHz, Fcpp=40MHz, Fcpm=80MHz, FlexRay=ON
(4)Fcp=80MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=ON
10.00
-50
0
50
100
150
TA [ºC]
normal operation
(VCC = 5.5V)
100.00
ICC5 [mA]
(1)
(2)
(3)
(4)
(1)Fcp=128MHz, Fcpp=32MHz, Fcpm=128MHz, FlexRay=OFF
(2)Fcp=128MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=OFF
(3)Fcp=80MHz, Fcpp=40MHz, Fcpm=80MHz, FlexRay=OFF
(4)Fcp=80MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=OFF
10.00
-50
0
50
100
150
TA [ºC]
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sleep mode
ICCS5/ICCBS5 [mA]
100.000
(VCC = 5.5V)
CPU Sleep(128MHz)
BUS Sleep (128MHz)
10.000
-50
0
50
100
150
TA [ºC]
144
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D a t a S h e e t
Watch mode
(VCC = 5.5V)
10.000
Main osc (4MHz)
ICCT5 [mA]
1.000
External clock (4MHz)
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
Stop mode
(VCC = 5.5V)
10.000
ICCH5 [mA]
1.000
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
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D a t a S h e e t
Watch mode(power off)
1000.00
(VCC = 5.5V)
Main osc (4MHz)
ICCT52 [µA]
100.00
External clock (4MHz)
10.00
1.00
0.10
0.01
-50
0
50
100
150
TA [ºC]
Stop mode(power off)
(VCC = 5.5V)
1000.00
ICCH52 [µA]
100.00
10.00
1.00
0.10
0.01
-50
0
50
100
150
TA [ºC]
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ORDERING INFORMATION
Part number
Package*
MB91F583AMGPMC-GTE1
MB91F584AMGPMC-GTE1
MB91F585AMGPMC-GTE1
MB91F583AMHPMC-GTE1
MB91F584AMHPMC-GTE1
MB91F585AMHPMC-GTE1
MB91F583AMJPMC-GTE1
MB91F584AMJPMC-GTE1
MB91F585AMJPMC-GTE1
MB91F583AMKPMC-GTE1
MB91F584AMKPMC-GTE1
MB91F585AMKPMC-GTE1
100-pin plastic LQFP
(FPT-100P-M20)
MB91F583ASGPMC1-GTE1
MB91F584ASGPMC1-GTE1
MB91F585ASGPMC1-GTE1
MB91F583ASHPMC1-GTE1
MB91F584ASHPMC1-GTE1
MB91F585ASHPMC1-GTE1
64-pin plastic LQFP
MB91F583ASJPMC1-GTE1
(FPT-64P-M24)
MB91F584ASJPMC1-GTE1
MB91F585ASJPMC1-GTE1
MB91F583ASKPMC1-GTE1
MB91F584ASKPMC1-GTE1
MB91F585ASKPMC1-GTE1
*: For details of the package, see " PACKAGE DIMENSIONS ".
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
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D a t a S h e e t
PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
"A"
1
25
0.50(.020)
C
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.20 ±0.05
(.008 ±.002)
0.08(.003) M
0.145±0.055
(.006 ±.002)
2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5
0°~8°
0.50 ±0.20
(.020 ±.008 )
0.60 ±0.15
(.024 ±.006)
0.10 ±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
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64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
32
49
Details of "A" part
0.08(.003)
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
INDEX
64
0°~8°
17
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
16
0.50(.020)
0.20±0.05
(.008±.002)
C
0.08(.003)
M
2005-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-c-1-3
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
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D a t a S h e e t
Major Changes
Page
Section
Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
-
-
2
■FEATURES
The product series name should be corrected.
MB91F585MG
MB91F585AMG
MB91F585MH
MB91F585AMH
MB91F585MJ
MB91F585AMJ
MB91F585MK
MB91F585AMK
MB91F584MG
MB91F584AMG
MB91F584MH
MB91F584AMH
MB91F584MJ
MB91F584AMJ
MB91F584MK
MB91F584AMK
MB91F583MG
MB91F583AMG
MB91F583MH
MB91F583AMH
MB91F583MJ
MB91F583AMJ
MB91F583MK
→
MB91F583AMK
MB91F585SG
MB91F585ASG
MB91F585SH
MB91F585ASH
MB91F585SJ
MB91F585ASJ
MB91F585SK
MB91F585ASK
MB91F584SG
MB91F584ASG
MB91F584SH
MB91F584ASH
MB91F584SJ
MB91F584ASJ
MB91F584SK
MB91F584ASK
MB91F583SG
MB91F583ASG
MB91F583SH
MB91F583ASH
MB91F583SJ
MB91F583ASJ
MB91F583SK
MB91F583ASK
The features of CR oscillation should be corrected.
Oscillation frequency: 100kHz, with frequency accuracy ± 10%
↓
Oscillation frequency: 100kHz, with frequency accuracy ± 50%
(pre-trimming)
The specification of "H" level input voltage and "L" level input voltage
of FlexRay should be corrected.
22
■I/O CIRCUIT TYPE
FlexRay input (0.65Vcc/0.35Vcc)
↓
FlexRay input (0.7Vcc/0.3Vcc)
33
■MEMORY MAP
54,85
■I/O MAP
Address:00150CH
54,55,85
■I/O MAP
Address: 00150 EH, 001510H, 001511H, 001512H,
001513H
The memory map should be corrected.
The address of "Reset vector table" and "Interrupt vector table" should be
added
The register name should be corrected.
STMCR00 → STMCR0
The registers should be deleted.
SCS CR0,SCSTR30,SCSTR20,SCSTR10,SCSTR00
The initial values of MHDS should be corrected.
63,92
■I/O MAP
Address:00D310H
-0000000 -0000000 -0000000 10000000
↓
-0000000 -0000000 -0000000 00000000
The specification of "H" level input voltage of P021-P023,P025-P027
should be corrected.
104
150
CONFIDENTIAL
■ELECTRICAL CHARACTERISTICS
3. DC Caharacteristics
Min:0.65 ×Vcc
↓
Min: 0.7 × Vcc
MB91F585AMG_DS705-00013-2v0-E, April 18, 2014
D a t a S h e e t
Page
Section
Change Results
The specification of "L" level input voltage of P021-P023,P025-P027
should be corrected.
105
■ELECTRICAL CHARACTERISTICS
3. DC Caharacteristics
111
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1)Main Clock Timing
Max: 0.35 × Vcc
↓
Max: 0.3 × Vcc
The remarks of "CAN PLL jitter" should be deleted.
The specifications of "The Built-in CR oscillation frequency" should be
corrected.
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1)Main Clock Timing
111
-
-
April 18, 2014, MB91F585AMG_DS705-00013-2v0-E
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Min: 90kHz,
Max: 110kHz
↓
Min:50kHz
Max:150kHz,
Company name and layout design change
151
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D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2013-2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit®
EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the
United States and other countries. Other names used are for informational purposes only and may be trademarks of their
respective owners.
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