1.9 MB

The following document contains information on Cypress products.
MB91550 Series
32-bit Microcontroller
FR Family FR81S
MB91F552
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB91F552_DS705-00015
CONFIDENTIAL
Revision 1.0
Issue Date April 25, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to
advise readers of product information or intended specifications throughout the product life
cycle, including development, qualification, initial production, and full production. In all cases,
however, readers are encouraged to verify that they have the latest information before
finalizing their design. The following descriptions of Spansion data sheet designations are
presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more
specific products, but has not committed any design to production. Information presented in
a document with this designation is likely to change, and in some cases, development on the
product may discontinue. Spansion Inc. therefore places the following conditions upon
Advance Information content:
“This document contains information on one or more products under development
at Spansion Inc. The information is intended to help you evaluate this product. Do
not design in this product without contacting the factory. Spansion Inc. reserves the
right to change or discontinue work on this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such
that a commitment to production has taken place. This designation covers several aspects of
the product life cycle, including product qualification, initial production, and the subsequent
phases in the manufacturing process that occur before full production is achieved. Changes
to the technical specifications presented in a Preliminary document should be expected
while keeping these aspects of production under consideration. Spansion places the
following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion
product(s) described herein. The Preliminary status of this document indicates that
product qualification has been completed, and that initial production has begun.
Due to the phases of the manufacturing process that require maintaining efficiency
and quality, this document may be revised by subsequent versions or modifications
due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance
Information, Preliminary, or Full Production). This type of document distinguishes these
products and their designations wherever necessary, typically on the first page, the ordering
information page, and pages with the DC Characteristics table and the AC Erase and
Program table (in the table notes). The disclaimer on the first page refers the reader to the
notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only
nominal changes are expected, the Preliminary designation is removed from the data sheet.
Nominal changes may include those affecting the number of ordering part numbers available,
such as the addition or deletion of a speed option, temperature range, package type, or VIO
range. Changes may also include those needed to clarify a description or to correct a
typographical error or incorrect specification. Spansion Inc. applies the following conditions
to documents in this category:
“This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in
sufficient production volume such that subsequent versions of this document are
not expected to change. However, typographical or specification corrections, or
modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
MB91F552_DS705-00015-1v0-E, April 25, 2014
CONFIDENTIAL
MB91550 Series
32-bit Microcontroller
FR Family FR81S
MB91F552
Data Sheet (Full Production)
 DESCRIPTION
The MB91550 series is a Spansion 32-bit microcontroller designed for automotive devices. This series
contains the FR81S CPU which is compatible with the FR family.
Note: FR is a line of products of Spansion Inc.
Spansion provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.spansion.com/Support/microcontrollers/Pages/default.aspx
Publication Number MB91F552_DS705-00015
Revision 1.0
Issue Date April 25, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
 FEATURES
 FR81S CPU Core
· 32-bit RISC, load/store architecture, 5-stage pipeline
· Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied (PLL clock
multiplication system))
· General-purpose register : 32 bits × 16 sets
· 16-bit fixed length instructions (basic instruction), 1 instruction per cycle
· Instructions appropriate to embedded applications
· Memory-to-memory transfer instruction
· Bit processing instruction
· Barrel shift order etc.
· High-level language support instructions
· Function entry/exit instructions
· Register content multi-load and store instructions
· Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
· Branch instructions with delay slot
Decrease overhead during branch process
· Register interlock function
Easy assembler writing
· Built-in multiplier and instruction level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
· Interrupt (PC/PS saving)
6 cycles (16 priority levels)
· The Harvard architecture allows simultaneous execution of program and data access.
· Instruction compatibility with the FR Family
· Built-in memory protection function (MPU)
· Eight protection areas can be specified commonly for instructions and the data.
· Control access privilege in both privilege mode and user mode.
· Built-in FPU (floating point arithmetic)
· IEEE754 compliant
· Floating-point register 32-bit × 16 sets
 Peripheral functions
· CPU function for clock generation (with SSCG function)
· Main oscillation (4MHz to 16MHz)
· PLL multiplication rate (1 to 20 times)
· PWM function for clock generation
· Main oscillation (4 MHz to 16 MHz)
· PLL multiplication rate (1 to 50 times)
· Built-in program flash memory capacity
MB91F552:128+64KB
· Built-in data flash (WorkFlash) 64KB
· Built-in RAM capacity
· Main RAM
MB91F552:24KB
· General-purpose ports:
MB91F552: 30sets
DMA Controller
· Up to 8 channels can be started simultaneously.
· 2 transfer factors (Internal peripheral request and software)
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· A/D converter 1 (successive approximation type)
· 12-bit resolution : 8 channels × 1 unit
· Conversion time : 1μs
· A/D converter 2 (successive approximation type simultaneous sampling of 4-channel input)
· 12-bit resolution: Max. 4 channels × 1 unit
· Conversion time :
For 1-channel conversion: Min. 0.7 μs
For 4-channel conversion: Min. 1.75 μs
· External interrupt input: 4 channels
· Level ("H"/"L"), or edge detection (rising or falling) supported
· Multi-function serial communication (built-in transmission/reception FIFO memory) :3 channels
· 5V tolerant input: 3 channels (ch.0, ch.1, ch.2) CMOS hysteresis input
< UART (Asynchronous serial interface) >
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· Parity or no parity is selectable.
· Built-in dedicated baud rate generator
· The external clock can be used as the transfer clock.
· Parity, frame, and overrun error detection functions are provided
· DMA transfer support
<CSIO (Synchronous serial interface) >
·
·
·
·
·
·
·
Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
SPI supported; master and slave systems supported; 5-bit to 16-bit, 20-bit, 24-bit, 32-bit data length
can be set.
Built-in dedicated baud rate generator (Master operation)
The external clock can be entered (Slave operation).
Overrun error detection function is provided
DMA transfer support
Serial chip select SPI function
<LIN (Asynchronous Serial Interface for LIN) >
·
·
·
·
·
·
·
·
· Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO
memory
· LIN protocol revision 2.1 supported
· Master and slave systems supported
· Framing error and overrun error detection
· LIN synch break generation and detection; LIN synch delimiter generation
· Built-in dedicated baud rate generator
· The external clock can be adjusted by the reload counter
· DMA transfer support
· Hard assist function
CAN Controller (CAN) : 1 channel
· Transfer speed : Up to 1Mbps
· 64-transmission/reception message buffering: 1 channel
Reload timer: 16-bit × 5 channels
Free-run timer: 16-bit × 1 channel
Input capture: 16-bit × 1 channel (linked with the free-run timer)
PWC: 2 channels
· Max. 80 MHz operation
PWM: 6 channels (2 channels × 3 pairs)
· Max. 200 MHz operation
Clock supervisor
· Monitoring abnormality (by damaged quartz, etc.) of external main oscillation (4 MHz)
· When abnormality is detected, it switches to the CR clock.
Base timer : Max.4 channels
· 16-bit timer
· The timer mode is selected from PWM/PPG/PWC/reload.
· A 32-bit timer can be used in 2 channels of cascade mode for the reload timer/PWC function.
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CONFIDENTIAL
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D a t a S h e e t
· CRC generation
· Watchdog timer
· Hardware watchdog
· Software watchdog (An effective range of a clear counter can be set.)
· Slope compensation (constant current unit): 1 channel
· Comparator: 3 channels
· NMI (non-maskable interrupt)
· Interrupt controller
· Interrupt request batch read
· Multiple interrupts from peripherals can be read by a series of registers.
· Low-power consumption mode
· Sleep / Stop / Watch mode
· Power-on reset
· Low-voltage detection reset (external power supply and internal power supply are independently
observed.)
· Device Package : LQFP-64
· CMOS 90nm Technology
· Power supply
· 5V Power supply
· The internal 1.2V is generated from 5V with the voltage step-down circuit.
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CONFIDENTIAL
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D a t a S h e e t
 PRODUCT LINEUP
MB91F552
System Clock
Minimum instruction execution
time
Flash Capacity (Program)
Flash Capacity (Data)
RAM Capacity
DMA Transfer
16-bit Base Timer
Free-run Timer
Input capture
16-bit Reload Timer
Clock Supervisor
External Interrupt
A/D converter
Multi-Function Serial Interface
CAN
Hardware Watchdog Timer
CRC Formation
Low-voltage detection reset
Flash Security
ECC Flash/WorkFlash
ECC RAM
Memory Protection Function
(MPU)
Floating point arithmetic (FPU)
General-purpose port (#GPIOs)
SSCG
CR oscillator
OCD (On Chip Debug)
TPU (Timing Protection Unit)
Key code register
Comparator
Slope compensation
(constant current unit)
PWC
PWM
NMI request function
Operation guaranteed
temperature (TA)
Power supply
Package
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
On chip PLL Clock multiple method
12.5ns(80MHz)
128+64KB
64KB
24KB
8 channels
4 channels
16bit×1 channel
16bit×1 channel
5 channels
Yes
4 channels
12 bit×8 channels (1unit)
Simultaneous sampling of 12 bit×4 channels input (1 unit)
3 channels
64 msg×1 channel
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
30 ports
Yes
Yes
Yes
Yes
Yes
3 channels
1 channel
2 channels
2 channels×3pairs
Yes
-40°C to +125°C
4.5V to 5.5V
LQFP-64
5
D a t a S h e e t
VSS
P000/PWM0H
P001/PWM0L
P002/PWM1H
P003/PWM1L
P004/PWM2H
P005/PWM2L
VCC
VSS
P046/SYNCIN/SYNCOUT/SCS00
P047/MONCLK/TIN4/ADTG1/SCS01
NMIX
CMP0
CMP1
CMP2
AVCC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49 DEBUGIF
50 P040/MM/ICU/SCS20
51 MD0
52 MD1
54 X1
55 VSS
56 P041/TX
57 P042/RX/INT0
58 RSTX
59 VSS
60 C
61 P043/SOT2/TOT4
53 X0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TOP VIEW
MB91F552
LQFP-64
P037/SIN0/TIOB3/INT1
P036/SCK0/TIOA3
P035/SOT0/TIOB2
P034/PWC0/TIOA2/SCS11
P033/SIN1/TIOB1/INT2
P032/SCK1/PWC1/TIOA1
P031/SOT1/TIOB0
P030/TIOA0/ADTG0/SCS10
P027/AN7/TIN3/SCS21
P026/AN6/TOT3
P025/AN5/TIN2
P024/AN4/TOT2
P023/AN3/TIN1
P022/AN2/TOT1
P021/AN1/TIN0
VSS
32 VCC
31 P020/AN0/TOT0/FRCK
30 AVRH0
29 AVRL0
28 AVSS0
27 AVCC0
26 AVRH1
25 AVRL1
24 VR1
23 AVSS1
22 AVCC1
21 AN8
20 AN9
19 AN10
18 AN11
CONFIDENTIAL
62 P044/SCK2
●
17 AVSS2
6
63 P045/SIN2/INT3
64 VCC
 PIN ASSIGNMENT
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
 PIN DESCRIPTION
Pin
no.
Pin Name
Pola
rity
I/O
circuit
types
Function
2
P000
PWM0H
-
A
General-purpose I/O port
PWM ch.0-H
3
P001
PWM0L
-
A
General-purpose I/O port
PWM ch.0-L
P002
PWM1H
P003
PWM1L
P004
PWM2H
P005
PWM2L
P046
SYNCIN
SYNCOUT
SCS00
P047
MONCLK
TIN4
ADTG1
SCS01
-
12
NMIX
N
L
Interrupt input pin without mask
13
CMP0
-
C
Comparator ch.0 input pin
14
CMP1
-
C
Comparator ch.1 input pin
15
CMP2
-
C
Comparator ch.2 input pin
18
AN11
-
C
A/D converter ch.11 analog input pin
(Simultaneous sampling possible with ch.8, ch.9, ch.10, and ch.11)
19
AN10
-
C
A/D converter ch.10 analog input pin
(Simultaneous sampling possible with ch.8, ch.9, ch.10, and ch.11)
20
AN9
-
C
21
AN8
-
C
P020
AN0
TOT0
FRCK
P021
AN1
TIN0
P022
AN2
TOT1
P023
AN3
TIN1
-
4
5
6
7
10
11
31
34
35
36
A
A
A
A
B
B
D
D
D
D
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CONFIDENTIAL
General-purpose I/O port
PWM ch.1-H
General-purpose I/O port
PWM ch.1-L
General-purpose I/O port
PWM ch.2-H
General-purpose I/O port
PWM ch.2-L
General-purpose I/O port
Master/Slave input pin for PWM parallel operation drive
Master/Slave output pin for PWM parallel operation drive
Multi-function serial ch.0 serial chip select 00 I/O pin
General-purpose I/O port
Clock monitor output pin
Reload timer ch.4 event input pin
A/D converter ch.8-ch.11 external trigger input pin
Multi-function serial ch.0 serial chip select 01 output pin
A/D converter ch.9 analog input pin
(Simultaneous sampling possible with ch.8, ch.9, ch.10, and ch.11)
A/D converter ch.8 analog input pin
(Simultaneous sampling possible with ch.8, ch.9, ch.10, and ch.11)
General-purpose I/O port
A/D converter ch.0 analog input pin
Reload timer ch.0 output pin
Free-run timer clock input pin
General-purpose I/O port
A/D converter ch.1 analog input pin
Reload timer ch.0 event input pin
General-purpose I/O port
A/D converter ch.2 analog input pin
Reload timer ch.1 output pin
General-purpose I/O port
A/D converter ch.3 analog input pin
Reload timer ch.1 event input pin
7
D a t a S h e e t
Pin
no.
Pin Name
Pola
rity
P024
AN4
TOT2
P025
AN5
TIN2
P026
AN6
TOT3
P027
AN7
TIN3
SCS21
P030
TIOA0
ADTG0
SCS10
P031
SOT1
TIOB0
P032
SCK1
PWC1
TIOA1
P033
SIN1
TIOB1
INT2
P034
PWC0
TIOA2
SCS11
P035
SOT0
TIOB2
P036
SCK0
TIOA3
P037
SIN0
TIOB3
INT1
-
49
DEBUGIF
-
50
P040
MM
ICU
SCS20
51
37
38
39
40
41
42
43
44
45
46
47
48
I/O
circuit
types
D
D
D
D
B
B
E
E
B
B
E
E
Function
General-purpose I/O port
A/D converter ch.4 analog input pin
Reload timer ch.2 output pin
General-purpose I/O port
A/D converter ch.5 analog input pin
Reload timer ch.2 event input pin
General-purpose I/O port
A/D converter ch.6 analog input pin
Reload timer ch.3 output pin
General-purpose I/O port
A/D converter ch.7 analog input pin
Reload timer ch.3 event input pin
Multi-function serial ch.2 serial chip select 21 output pin
General-purpose I/O port
Base timer ch.0 TIOA output pin
A/D converter ch.0-ch.7 external trigger input pin
Multi-function serial ch.1 serial chip select 10 I/O pin
General-purpose I/O port
Multi-function serial ch.1 serial data output pin
Base timer ch.0 TIOB input pin
General-purpose I/O port
Multi-function serial ch.1 clock I/O pin
PWC ch.1 input pin
Base timer ch.1 TIOA I/O pin
General-purpose I/O port
Multi-function serial ch.1 serial data input pin
Base timer ch.1 TIOB input pin
INT2 external interrupt input pin
General-purpose I/O port
PWC ch.0 input pin
Base timer ch.2 TIOA output pin
Multi-function serial ch.1 serial chip select 11 output pin
General-purpose I/O port
Multi-function serial ch.0 serial data output pin
Base timer ch.2 TIOB input pin
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin
Base timer ch.3 TIOA I/O pin
General-purpose I/O port
Multi-function serial ch.0 serial data input pin
Base timer ch.3 TIOB input pin
INT1 external interrupt input pin
F
MDI I/O pin for debug (OCD)
-
B
General-purpose I/O port
Clock supervisor main clock stop detection output pin
Input capture input pin
Multi-function serial ch.2 serial chip select 20 I/O pin
MD0
-
G
Mode pin 0
52
MD1
-
G
Mode pin 1
53
X0
-
H
Main clock oscillation input pin
54
X1
-
H
Main clock oscillation output pin
8
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D a t a S h e e t
Pin
no.
Pin Name
Pola
rity
I/O
circuit
types
Function
P041
TX
P042
RX
INT0
-
RSTX
N
P043
SOT2
TOT4
P044
SCK2
P045
SIN2
INT3
-
16
AVCC2
-
-
Analog power supply pin for comparator and slope compensation circuit
22
AVCC1
-
-
Analog power supply pin for A/D converter, with 4ch. simultaneous sampling/hold
function
27
AVCC0
-
-
A/D converter analog power supply pin
26
AVRH1
-
-
Upper limit reference voltage pin for A/D converter, with 4ch. simultaneous
sampling/hold function
30
AVRH0
-
-
A/D converter upper limit reference voltage pin
17
AVSS2
-
-
GND pin for comparator and slope compensation circuit
23
AVSS1
-
-
GND pin for A/D converter, with 4ch. simultaneous sampling/hold function
25
AVRL1
-
-
24
VR1
-
-
28
AVSS0
-
-
A/D converter GND pin
29
AVRL0
-
-
A/D converter lower limit reference voltage pin
60
C
-
-
External capacity connection output pin
VCC
-
-
+5.0 V power supply pin
VSS
-
-
GND
56
57
58
61
62
63
8
32
64
1
9
33
55
59
B
E
L
B
E
E
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
General-purpose I/O port
CAN transmission data output pin
General-purpose I/O port
CAN reception data input pin
INT0 external interrupt input pin
External reset input pin
General-purpose I/O port
Multi-function serial ch.2 serial data output pin
Reload timer ch.4 output pin
General-purpose I/O port
Multi-function serial ch.2 clock I/O pin
General-purpose I/O port
Multi-function serial ch.2 serial data input pin
INT3 external interrupt input pin
Lower limit reference voltage pin for A/D converter, with 4ch. simultaneous
sampling/hold function
Intermediate reference voltage pin for A/D converter, with 4ch. simultaneous
sampling/hold function
9
D a t a S h e e t
 I/O CIRCUIT TYPE
Type
A
Circuit
Digital output
Digital output
Remarks
• General-purpose I/O port
• Output 8mA
• Pull-down resistor control 50kΩ
• Automotive input
Pull-down control
Automotive input
Standby control
B
Pull-up control
• General-purpose I/O port
• Output 4mA
• Pull-up resistor control 50kΩ
• Automotive input
Digital output
Digital output
Automotive input
Standby control
• Analog input
C
Analog input
D
Pull-up control
• Analog input, General-purpose I/O port
• Output 4mA
• Pull-up resistor control 50kΩ
• Automotive input
Digital output
Digital output
Automotive input
Standby control
Analog input
10
CONFIDENTIAL
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D a t a S h e e t
Type
E
Circuit
Remarks
• General-purpose I/O port
• Output 4mA
• Pull-up resistor control 50kΩ
• CMOS hysteresis input
Pull-up control
Digital output
Digital output
CMOS-hys input
Standby control
• Open-drain I/O
• Output 25mA (Nch open drain)
• TTL input
F
Digital output
TTL input
• Mode I/O
• CMOS hysteresis input
G
Mode input
Control
• Main oscillation I/O
H
Input
Standby control
• CMOS hysteresis input
• Pull-up resistor 50kΩ
L
CMOS-hys input
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
11
D a t a S h e e t
 HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-2Ea
12
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D a t a S h e e t
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
 Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
13
D a t a S h e e t
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
14
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
15
D a t a S h e e t
 HANDLING DEVICES
This section explains the latch-up prevention and pin processing.
 For latch-up prevention
If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding
the ratings is applied between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs,
the power supply current increases excessively and device elements may be damaged by heat. Take care to
prevent any voltage from exceeding the maximum ratings in device application.
Also, the analog power supply (AVCC, AVRH) and analog input must not be exceed the digital power
supply (VCC) when the power supply to the analog system is turned on or off.
In the correct power-on sequence of the microcontroller, turn on the digital power supply (VCC) and analog
power supplies (AVCC, AVRH) simultaneously. Or, turn on the digital power supply (VCC), and then turn
on analog power supplies (AVCC, AVRH).
 Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or
latch-up. Connect at least a 2kΩ resistor to each of the unused pins for pull-up or pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the
input state and treated in the same way as for the input pins.
 Power supply pins
The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should
be at the same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these
pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from
malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. As shown in
figure 1, all Vss power supply pins must be treated in the similar way. If multiple Vcc or Vss systems are
connected, the device cannot operate correctly even within the guaranteed operating range.
Figure 1 Power Supply Input Pins
Vcc
Vss
Vss
Vcc
Vss
Vcc
Vcc
Vss
Vss
Vcc
The power supply pins should be connected to VCC and VSS pins of this device at the low impedance from
the power supply source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin
is recommended to use as a bypass capacitor between VCC and VSS pins.
16
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
 Crystal oscillation circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be
designed to lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be
grounded to the close position to the device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
 Mode pins (MD1, MD0)
Connect the MD1 and MD0 mode pins to the VCC or VSS pin directly. To prevent an erroneous selection
of test mode caused by the noise, reduce the pattern length between each mode pin and VCC or VSS pin on
the printed circuit board. Also, use the low-impedance pin connection.
 During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to
have 50μs or longer (between 0.2V and 2.7V) during power-on.
 Notes during PLL clock operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock
may continue to operate at the free running frequency of the self-oscillator circuit built in the PLL clock.
This operation is not guaranteed.
 Treatment of A/D converter power supply pins
Connect the pins to have AVCC=AVRH=VCC and AVSS/AVRL=VSS even if the A/D converter is not
used.
 External clock is not supported
None of the external direct clock input can be used.
 Power-on sequence of A/D converter power supplies and analog inputs
Be sure to turn on the digital power supply (Vcc) first, and then turn on the A/D converter power supplies
(AVcc, AVRH, AVRL) and analog inputs (AN0 to AN7, AN8 to AN11). Also, turn off the A/D converter
power supplies and analog inputs first, and then turn off the digital power supply (Vcc). When the AVRH
pin voltage is turned on or off, it must not exceed AVCC. Even if a common analog input pin is used as an
input port, its input voltage must not exceed AVcc. (However, the analog power supply and digital power
supply can be turned on or off simultaneously.)
 Power-on sequence of comparator and slope compensation power supply
and analog inputs
Be sure to turn on the digital power supply (Vcc) first, and then turn on the comparator and slope
compensation power supply (AVcc) and analog inputs (CMP0 to CMP2). Also, turn off the comparator and
slope compensation power supply and analog inputs first, and then turn off the digital power supply (Vcc).
(However, the analog power supply and digital power supply can be turned on or off simultaneously.)
 Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to
assure the internal stabilization of the device. For the standard values, see the "Recommended Operating
Conditions" of the latest data sheet.
Note: Please see the latest data sheet for a detailed specification of the operation voltage.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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17
D a t a S h e e t
 Function switching of a multiplexed port
To switch between the port function and the multiplexed pin function, use the PFR (port function register).
However, if a pin is also used for an external bus, its function is switched by the external bus setting. For
details, see "I/O PORTS" in the hardware manual.
 Low-power consumption mode
To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off),
follow the procedure explained in "Activating the sleep mode, watch mode, or stop mode" or "Activating
the watch mode (power-off) or stop mode(power-off)" of " POWER CONSUMPTION CONTROL" in the
hardware manual.
Take the following notes when using a monitor debugger.
· Do not set a break point for the low-power consumption transition program.
· Do not execute an operation step for the low-power consumption transition program.
 Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control
function, taking care not to clear its status flag erroneously must be followed.
The program must be written not to clear the flag to the status bit, and then to set the control bits to have the
desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can
access to a single bit only.) By the Byte, Half-word, or Word access, data is written to the control bits and
status flag simultaneously. During this time, take care not to clear other bits (in this case, the bits of status
flag) erroneously.
Note: These points can be ignored because the bit instructions are already taken the points into consideration.
18
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
 BLOCK DIAGRAM
Regulator
FR81s CPU core
M P U
CR oscillator
Instruction
Debug Interface
Data
XBS
Power-on reset
XBS Crossbar Switch
Wild register
Timing Protection
Unit
・Main Flash 128KB+64KB
・WorkFlash
64KB
From Master
To Slave
On chip bus layer 2
From Master
To Slave
On chip bus layer 1
DMAC
(8 ch)
RAM ECC／Diagnosis
(XBS RAM)
Flash control register
AN8-11
PWM0H, PWM0L,
PWM1H, PWM1L,
PWM2H, PWM2L
A/D converter (4ch x 1 unit)
with simultaneous sampling
of 4ch input
On chip bus(AHB)
RAM
24KB
Flash
Peripheral Bus
Bridge
16
32
Bus diagnosis register
Bus
performance
counter
Operation mode
register
PWM(6ch)
PWC0, PWC1
PWC(2ch)
MD0,MD1,P044
RX,TX
CAN (1ch)
Asynchronous bus bridge (PCLK1 ⇔ PCLK2)
Asynchronous bus bridge (PCLK1 ⇔ PCLK2)
CRC (1ch)
16bit free-run timer(1ch)
PWM clock control
CAN prescaler
MONCLK
Base timer(4ch)
ICU
SOT0-2,SCS00-21
SIN0-2,SCK0-2
CMP1, CMP2
CMP0
Multi-function serial interface(3ch)
High-speed comparator (3ch)
Slope compensation (constant current unit) (1ch)
12bit AD converter (8ch×1unit)
AN0-7
Clock Monitor
I / O Port
TIOA0-3,TIOB0-3
Reload timer (5ch)
32bit Peripheral Bus (APB)
TIN0-4,TOT0-4
16bit Peripheral Bus
I / O Port
WDT1 calibration
I/O port setting
FRCK
16bit Input capture(1ch)
Watchdog timer (SW and HW)
DMA request generation and clear
Interrupt Request Batch Reading Register
Delayed Interrupt
Interrupt Controller
RSTX
Clock Control Register
（Division setting, reset control register）
bus bridge (32bit <-> 16bit)
External interrupt input(4ch)
Clock Supervisor
NMI
Input cut-off INT0-3
inhibiting signal
NMIX
MM
Clock control(Clock setting, main timer, PLL timer)
Regulator control
Low-voltage detection
(External low-voltage detection)
Low-voltage detection
(Internal low-voltage detection)
April 25, 2014, MB91F552_DS705-00015-1v0-E
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19
D a t a S h e e t
 MEMORY MAP
0000_0000 H
0000_4000 H
0000_6000 H
0001_0000 H
I/O area
Reserved
I/O area
RAM (24KB)
0001_6000 H
Reserved
0007_0000 H
Reserved
000D_0000 H
000F_FC00 H
Flash memory
(128+64)KB
Interrupt vector table
Reset vector table
0010_0000 H
Reserved
0033_0000 H
WorkFlash
(64KB)
0034_0000 H
Reserved
FFFF_FFFF H
20
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
 I/O MAP
The following I/O map shows the relationship between memory space and registers for peripheral
resources.
Legend of I/O Map
Read/Write attribute (R: Read W: Write)
Address
000090H
000094 H
000098 H
00009C H
0000A0 H
0000A4 H
0000A8 H
Address offset value/ register name
+1
+2
+0
+3
BT1TMR[R] H
BT1TMCR[R/W] B,H,W
0000000000000000
00000000 00000000
BT1STC[R/W] B
-
-
00000000
-
Base timer 1
BT1PCSR/BT1PRLL[R /W] H
BT1PDU T/BT1PRLH/BT1DTBF[R/W] H
0000000000000000
0000000000000000
BTSEL[R/W] B
BTSSSR[W] B,H
-
----000 0
Block
-------- ------11
ADERH [R/W] B,H,W
ADERL [R/W] B,H,W
00000000 00000000
00000000 00000000
ADCS1 [R/W] B,H,W
ADCS0 [R/W] B,H,W
ADCR1 [R] B,H,W
ADCR0 [R] B,H,W
00000000
00000000
------XX
XXXXX XXX
ADCT1 [R/W] B,H,W
ADCT0 [R/W] B,H,W
ADSCH [R/W] B,H,W
ADECH [R/W] B,H,W
00010000
00101100
---00000
---00000
A/D converter
Data access attribute
B: Byte
H: Half-word
W: Word
(Note)The access by the data
access attribute not described
is disabled.
Initial register value after reset
The initial register value after reset indicates as follows:
· "1": Initial value "1"
· "0": Initial value "0"
· "X": Initial value undefined
· "-": Reserved bit/Undefined bit
· "*": Initial value "0" or "1" according to the setting
Note: The access to addresses not described is disabled.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
000000H
PDR00 [R/W] B,H,W
--XXXXXX
―
PDR02 [R/W] B,H,W
XXXXXXXX
PDR03 [R/W] B,H,W
XXXXXXXX
000004H
PDR04 [R/W] B,H,W
XXXXXXXX
―
―
―
000008H
to
000034H
―
―
―
―
000038H
WDTECR0 [R/W]
B,H,W
---00000
―
―
―
00003CH
WDTCR0 [R/W]
B,H,W
-0--0000
WDTCPR0 [W]
B,H,W
00000000
WDTCR1 [R]
B,H,W
----0110
WDTCPR1 [W]
B,H,W
00000000
000040H
―
―
―
―
Reserved
000044H
DICR [R/W] B
-------0
―
―
―
Delayed Interrupt
000048H
to
00005CH
―
―
―
―
Reserved
000060H
TMRLRA0 [R/W] H
XXXXXXXX XXXXXXXX
TMR0 [R] H
XXXXXXXX XXXXXXXX
000064H
TMRLRB0 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR0 [R/W] B,H,W
00000000 0-000000
000068H
to
00007CH
―
Port Data Register
Reserved
Watchdog Timer
[S]
Reload Timer 0
000088H
00008CH
BT0TMCR2 [R/W] B
-------0
000098H
BT0STC [R/W] B
-0-0-0-0
―
―
BT1STC [R/W] B
-0-0-0-0
BT1PCSR/BT1PRLL [R/W] H
XXXXXXXX XXXXXXXX
BTSEL01 [R/W] B
----0000
―
0000A0H
to
0000FCH
―
―
CONFIDENTIAL
Reserved
―
Base Timer 0
BT0PDUT/BT0PRLH/BT0DTBF [R/W] H
XXXXXXXX XXXXXXXX
―
―
Reserved
―
Base Timer 1
BT1TMCR [R/W] H
-000--00 -000-000
00009CH
22
―
BT1TMR [R] H
00000000 00000000
BT1TMCR2 [R/W] B
-------0
―
BT0TMCR [R/W] H
-000--00 -000-000
BT0PCSR/BT0PRLL [R/W] H
XXXXXXXX XXXXXXXX
000090H
000094H
―
BT0TMR [R] H
00000000 00000000
000080H
000084H
―
―
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H
XXXXXXXX XXXXXXXX
BTSSSR [W] B,H
-------- ------11
―
Base Timer 0,1
―
Reserved
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
000100H
TMRLRA1 [R/W] H
XXXXXXXX XXXXXXXX
TMR1 [R] H
XXXXXXXX XXXXXXXX
000104H
TMRLRB1 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR1 [R/W] B, H,W
00000000 0-000000
000108H
TMRLRA2 [R/W] H
XXXXXXXX XXXXXXXX
TMR2 [R] H
XXXXXXXX XXXXXXXX
00010CH
TMRLRB2 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR2 [R/W] B,H,W
00000000 0-000000
000110H
TMRLRA3 [R/W] H
XXXXXXXX XXXXXXXX
TMR3 [R] H
XXXXXXXX XXXXXXXX
000114H
TMRLRB3 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR3 [R/W] B,H,W
00000000 0-000000
000118H
BT2TMR [R] H
00000000 00000000
BT2TMCR [R/W] H
-000--00 -000-000
Reload Timer 1
Reload Timer 2
00011CH
BT2TMCR2 [R/W] B
-------0
BT2STC [R/W] B
-0-0-0-0
―
―
000120H
BT2PCSR/BT2PRLL [R/W] H
XXXXXXXX XXXXXXXX
BT2PDUT/BT2PRLH/BT2DTBF [R/W] H
XXXXXXXX XXXXXXXX
000124H
BT3TMR [R] H
00000000 00000000
BT3TMCR [R/W] H
-000--00 -000-000
000128H
00012CH
BT3TMCR2 [R/W] B
-------0
BT3STC [R/W] B
-0-0-0-0
BT3PCSR/BT3PRLL [R/W] H
XXXXXXXX XXXXXXXX
―
―
Reload Timer 3
Base Timer 2
Base Timer 3
BT3PDUT/BT3PRLH/BT3DTBF [R/W] H
XXXXXXXX XXXXXXXX
000130H
BTSEL23 [R/W] B
----0000
―
000134H
to
0001B4H
―
―
―
―
Reserved
0001B8H
―
EPFR65 [R/W] B,H,W
--000000
―
―
Extended port
function register
0001BCH
to
0001C8H
―
―
―
―
Reserved
0001CCH
―
―
EPFR86 [R/W]
B,H,W
-----0--
―
0001D0H
EPFR88 [R/W]
B,H,W
-------0
―
―
―
0001D4H
―
―
―
―
0001D8H
0001DCH
0001E0H
to
00030CH
Base Timer 2,3
Extended port
function register
TMRLRA4 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB4 [R/W] H
XXXXXXXX XXXXXXXX
TMR4 [R] H
XXXXXXXX XXXXXXXX
TMCSR4 [R/W] B,H,W
00000000 0-000000
―
―
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
BTSSSRA [W] B,H
-------- ------11
―
―
Reserved
Reload Timer 4
Reserved
23
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
000310H
―
―
000314H
―
―
―
―
―
―
―
―
―
―
―
―
24
CONFIDENTIAL
DESR [R/W] H
-------- 00000--0
―
PACR0 [R/W] H
000000-0 00000--0
―
PACR1 [R/W] H
000000-0 00000--0
―
PACR2 [R/W] H
000000-0 00000--0
MPU [S]
(Only CPU core
can access this
area)
―
PACR3 [R/W] H
000000-0 00000--0
―
PACR4 [R/W] H
000000-0 00000--0
―
PACR5 [R/W] H
000000-0 00000--0
―
PACR6 [R/W] H
000000-0 00000--0
PABR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000368H
00036CH
―
PABR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000360H
000364H
DPVSR [R/W] H
-------- 00000--0
PABR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000358H
00035CH
―
PABR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000350H
000354H
―
PABR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000348H
00034CH
―
PABR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000340H
000344H
―
PABR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000338H
00033CH
―
PABR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000330H
000334H
―
DEAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000328H
00032CH
MPUCR [R/W] H
000000-0 ----0100
DPVAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000320H
000324H
+3
―
000318H
00031CH
+2
―
―
PACR7 [R/W] H
000000-0 00000--0
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
000370H
to
0003FCH
―
―
―
―
000400H
ICSEL0 [R/W] B,H,W
-----000
―
ICSEL2 [R/W] B,H,W
------00
ICSEL3 [R/W] B,H,W
-------0
000404H
―
ICSEL5 [R/W] B,H,W
-----000
―
―
000408H
―
―
―
ICSEL11 [R/W] B,H,W
-----000
00040CH
―
ICSEL13 [R/W] B,H,W ICSEL14 [R/W] B,H,W ICSEL15 [R/W] B,H,W
------00
------00
----0000
000410H
ICSEL16 [R/W] B,H,W ICSEL17 [R/W] B,H,W ICSEL18 [R/W] B,H,W ICSEL19 [R/W] B,H,W
------00
----0000
------00
-------0
000414H
ICSEL20 [R/W] B,H,W ICSEL21 [R/W] B,H,W ICSEL22 [R/W] B,H,W ICSEL23 [R/W] B,H,W
-------0
------00
------00
------00
Reserved [S]
DMA request
generation and
clear
000418H
IRPR0H [R] B,H,W
000-----
IRPR0L [R] B,H,W
00------
IRPR1H [R] B,H,W
00------
IRPR1L [R] B,H,W
00------
00041CH
IRPR2H [R] B,H,W
00------
IRPR2L [R] B,H,W
00------
IRPR3H [R] B,H,W
00------
IRPR3L [R] B,H,W
00------
000420H
IRPR4H [R] B,H,W
0000----
IRPR4L [R] B,H,W
0000----
IRPR5H [R] B,H,W
0000----
IRPR5L [R] B,H,W
00------
000424H
IRPR6H [R] B,H,W
-0------
IRPR6L [R] B,H,W
0-0-----
IRPR7H [R] B,H,W
0000----
IRPR7L [R] B,H,W
00000000
000428H
IRPR8H [R] B,H,W
000-----
IRPR8L [R] B,H,W
0000----
IRPR9H [R] B,H,W
00000000
IRPR9L [R] B,H,W
00000000
00042CH
IRPR10H [R] B,H,W
00000000
IRPR10L [R] B,H,W
00000000
IRPR11H [R] B,H,W
0000----
IRPR11L [R] B,H,W
0000----
000430H
IRPR12H [R] B,H,W
00------
IRPR12L [R] B,H,W
00------
IRPR13H [R] B,H,W
00------
IRPR13L [R] B,H,W
00------
000434H
IRPR14H [R] B,H,W
00000000
―
IRPR15H [R] B,H,W
0000----
IRPR15L [R] B,H,W
-000----
000438H
―
ICSEL25 [R/W] B,H,W
---00000
―
―
DMA request
generation and
clear
00043CH
―
―
―
―
Reserved [S]
000440H
ICR00 [R/W] B,H,W
---11111
ICR01 [R/W] B,H,W
---11111
ICR02 [R/W] B,H,W
---11111
ICR03 [R/W] B,H,W
---11111
000444H
ICR04 [R/W] B,H,W
---11111
ICR05 [R/W] B,H,W
---11111
ICR06 [R/W] B,H,W
---11111
ICR07 [R/W] B,H,W
---11111
000448H
ICR08 [R/W] B,H,W
---11111
ICR09 [R/W] B,H,W
---11111
ICR10 [R/W] B,H,W
---11111
ICR11 [R/W] B,H,W
---11111
00044CH
ICR12 [R/W] B,H,W
---11111
ICR13 [R/W] B,H,W
---11111
ICR14 [R/W] B,H,W
---11111
ICR15 [R/W] B,H,W
---11111
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
Interrupt Request
Batch Reading
Register
Interrupt Controller
[S]
25
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
000450H
ICR16 [R/W] B,H,W
---11111
ICR17 [R/W] B,H,W
---11111
ICR18 [R/W] B,H,W
---11111
ICR19 [R/W] B,H,W
---11111
000454H
ICR20 [R/W] B,H,W
---11111
ICR21 [R/W] B,H,W
---11111
ICR22 [R/W] B,H,W
---11111
ICR23 [R/W] B,H,W
---11111
000458H
ICR24 [R/W] B,H,W
---11111
ICR25 [R/W] B,H,W
---11111
ICR26 [R/W] B,H,W
---11111
ICR27 [R/W] B,H,W
---11111
00045CH
ICR28 [R/W] B,H,W
---11111
ICR29 [R/W] B,H,W
---11111
ICR30 [R/W] B,H,W
---11111
ICR31 [R/W] B,H,W
---11111
000460H
ICR32 [R/W] B,H,W
---11111
ICR33 [R/W] B,H,W
---11111
ICR34 [R/W] B,H,W
---11111
ICR35 [R/W] B,H,W
---11111
000464H
ICR36 [R/W] B,H,W
---11111
ICR37 [R/W] B,H,W
---11111
ICR38 [R/W] B,H,W
---11111
ICR39 [R/W] B,H,W
---11111
000468H
ICR40 [R/W] B,H,W
---11111
ICR41 [R/W] B,H,W
---11111
ICR42 [R/W] B,H,W
---11111
ICR43 [R/W] B,H,W
---11111
00046CH
ICR44 [R/W] B,H,W
---11111
ICR45 [R/W] B,H,W
---11111
ICR46 [R/W] B,H,W
---11111
ICR47 [R/W] B,H,W
---11111
000470H
to
00047CH
―
―
―
―
Reserved[S]
000480H
RSTRR [R]
B,H,W
XXXX--XX
RSTCR [R/W]
B,H,W
111----0
STBCR [R/W]
B,H,W *
000---11
―
Reset Control [S]
Power Control [S]
*: Writing STBCR
by DMA is
forbidden
000484H
―
―
―
―
Reserved [S]
000488H
DIVR0 [R/W] B,H,W
000-----
―
DIVR2 [R/W] B,H,W
0011----
―
Clock Control [S]
00048CH
―
―
―
―
Reserved [S]
000490H
IORR0 [R/W] B,H,W
-0000000
IORR1 [R/W] B,H,W
-0000000
IORR2 [R/W] B,H,W
-0000000
IORR3 [R/W] B,H,W
-0000000
000494H
IORR4 [R/W] B,H,W
-0000000
IORR5 [R/W] B,H,W
-0000000
IORR6 [R/W] B,H,W
-0000000
IORR7 [R/W] B,H,W
-0000000
―
―
―
―
―
―
―
―
0004A0H
―
―
―
―
Reserved
0004A4H
CANPRE [R/W] B,H,W
---00000
―
―
―
CAN prescaler
0004A8H
―
―
CSCFG[R/W]B,H,W
---0----
CMCFG[R/W]B,H,W
00000000
Clock monitor
control register
0004ACH
―
―
0004B0H
to
0004C0H
―
―
000498H
00049CH
26
CONFIDENTIAL
ADERL0[R/W] B,H
-------- 11111111
―
Interrupt Controller
[S]
DMA request by
peripheral[S]
Analog input
control register
―
Reserved
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
CUCR1 [R/W] B,H,W
-------- ---0--00
0004C4H
+3
CUTD1 [R/W] B,H,W
11000011 01010000
WDT1 calibration
CUTR1 [R] B,H,W
-------- 00000000 00000000 00000000
0004C8H
0004CCH
to
0004E4H
―
―
0004E8H
PLL2DIVM [R/W]
B,H,W
----0000
0004ECH
―
0004F0H
―
PLL2DIVN [R/W]
B,H,W
-0000000
PLL2DIVK [R/W]
B,H,W
-------0
PWMCGRCR0 [R/W]
B,H,W
00----00
0004F4H
to
00050CH
―
000510H
CSELR [R/W] B,H,W
-01---00
―
―
―
―
CLKR2 [R/W] B,H,W
000--000
―
PWMCGRCR1 [R/W]
B,H,W
00000000
PWMCGRCR2 [R/W]
B,H,W
00000000
―
―
―
CMONR [R] B,H,W
-01---00
MTMCR [R/W] B,H,W
00001111
―
CSTBR [R/W] B,H,W
----0000
PTMCR [R/W] B,H,W
00------
Reserved
PWM
Clock control
Reserved
Clock Control[S]
PLLCR [R/W] B,H,W
-------- 11110000
000514H
000518H
―
―
CPUAR [R/W] B,H,W
0----XXX
―
Reset clock[S]
00051CH
―
―
―
―
Reserved[S]
000520H
CCPSSELR [R/W]
B,H,W
-------0
―
―
CCPSDIVR [R/W]
B,H,W
-000-000
000524H
―
CCPLLFBR [R/W]
B,H,W
-0000000
CCSSFBR0 [R/W]
B,H,W
--000000
CCSSFBR1 [R/W]
B,H,W
---00000
000528H
―
CCSSCCR0 [R/W]
B,H,W
----0000
00052CH
―
CCCGRCR0 [R/W]
B,H,W
00----00
CCCGRCR1 [R/W]
B,H,W
00000000
CCCGRCR2 [R/W]
B,H,W
00000000
―
―
―
―
―
―
―
―
000550H
EIRR0 [R/W] B,H,W
----XXXX
ENIR0 [R/W] B,H,W
----0000
000554H
to
000568H
―
―
000530H
to
00053CH
000540H
to
00054CH
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
CCSSCCR1 [R/W] H,W
000----- --------
ELVR0 [R/W] B,H,W
-------- 00000000
―
Clock Control 2[S]
Reserved
External Interrupt
(INT0 to 3)
―
Reserved
27
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
00056CH
―
CSVCR [R/W] B
-0-11--0
―
―
Clock Supervisor
000570H
to
00057CH
―
―
―
―
Reserved
000580H
REGSEL [R/W]
B,H,W
01------
―
―
―
000584H
LVD5R [R/W]
B,H,W
-------1
LVD5F [R/W]
B,H,W
00110001
LVD [R/W]
B,H,W
01000--0
―
000588H
to
00059CH
―
―
―
―
0005A0H
SLPCNT [R/W] B,H,W
------00
―
―
―
0005A4H
0005A8H
SLPEDGESEL1 [R/W] B,H,W
---0-000 ---0-000
SLPSWA [R/W] B,H,W SLPSWB [R/W] B,H,W SLPSWC [R/W] B,H,W
-----100
-----100
-----100
―
SLP1A [R/W] H,W
00000000 00000000
SLP1B [R/W] H,W
00000000 00000000
0005B0H
SLP1C [R/W] H,W
00000000 00000000
SLP3 [R/W] H,W
00000000 00000000
0005B4H
SLP2A [R/W] H,W
00000000 00000000
SLP2B [R/W] H,W
00000000 00000000
0005B8H
SLP2C [R/W] H,W
00000000 00000000
SLP4 [R/W] H,W
00000000 00000000
0005C0H
0005C4H
0005C8H
to
0005DCH
0005E0H
0005E4H
0005E8H
0005ECH
28
CONFIDENTIAL
―
SLPCVE [R] H,W
------XX XXXXXXXX
Slope
Compensation
Control
SLPDADR [R/W] H,W
------00 00000000
―
SLPSTMSEL1 [R/W] B,H,W
-000-000 -----000
SLPSTMSEL2 [R/W] B,H,W
-000-000 -------―
―
―
―
―
―
CMPCTL0 [R/W]
B,H,W
--001000
CMPDACR0 [R/W]
B,H,W
-------0
CMPDACR1 [R/W]
B,H,W
-------0
CMPDACR2 [R/W]
B,H,W
-------0
CMPCTL1 [R/W]
B,H,W
--001000
CMPCTL2 [R/W]
B,H,W
--001000
CMPDIV [R/W] B,H,W
------00
―
Reserved
SLPEDGESEL2 [R/W] B,H,W
---0-000 ---0-000
0005ACH
0005BCH
Regulator Control /
Low Voltage
Detection
CMPDADR0 [R/W] H,W
------00 00000000
―
CMPDADR1 [R/W] H,W
------00 00000000
―
CMPDADR2 [R/W] H,W
------00 00000000
Reserved
Comparator
Control
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
0005F0H
CMPINT [R/W] B,H,W
-----000
―
―
―
0005F4H
CMPST [R] B,H,W
-----XXX
―
―
―
Comparator
Control
0005F8H
to
0005FCH
―
―
―
―
Reserved
―
―
―
―
Reserved[S]
―
―
―
―
Reserved
BPCCRA [R/W] B
00000000
BPCCRB [R/W] B
00000000
BPCCRC [R/W] B
00000000
―
000600H
to
0006FCH
000700H
to
00070CH
000710H
000714H
BPCTRA [R/W] W
00000000 00000000 00000000 00000000
000718H
BPCTRB [R/W] W
00000000 00000000 00000000 00000000
00071CH
BPCTRC [R/W] W
00000000 00000000 00000000 00000000
Bus Performance
Counter
000720H
to
0007F8H
―
―
―
―
Reserved
0007FCH
BMODR [R] B, H, W
XXXXXXXX
―
―
―
Operation Mode
000800H
to
00083CH
―
―
―
―
Reserved[S]
―
FSTR [R/W] B
-----001
―
―
FCTLR [R/W] H
-0--1000 0--0----
000840H
000844H
to
000854H
―
―
000858H
―
―
00085CH
to
00087CH
―
―
WREN [R/W] H
00000000 00000000
―
000880H
WRAR00 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
000884H
WRDR00 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000888H
WRAR01 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
00088CH
WRDR01 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Flash Memory
Register [S]
Reserved[S]
Wild Register [S]
―
Reserved[S]
Wild Register [S]
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
29
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
000890H
WRAR02 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
000894H
WRDR02 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000898H
WRAR03 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
00089CH
WRDR03 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008A0H
WRAR04 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008A4H
WRDR04 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008A8H
WRAR05 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008ACH
WRDR05 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008B0H
WRAR06 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008B4H
WRDR06 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008B8H
WRAR07 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008BCH
WRDR07 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008C0H
WRAR08 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008C4H
WRDR08 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008C8H
WRAR09 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008CCH
WRDR09 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Wild Register [S]
0008D0H
0008D4H
WRAR10 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008D8H
WRAR11 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008DCH
WRDR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E0H
WRAR12 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008E4H
WRDR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
30
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
0008E8H
WRAR13 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008ECH
WRDR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008F0H
WRAR14 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008F4H
WRDR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008F8H
WRAR15 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008FCH
WRDR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000900H
TPUUNLOCK [R/W] W
00000000 00000000 00000000 00000000
000904H
TPULST [R] B,H,W
-------0
―
TPUVST [R/W] B,H,W
-----000
+3
Wild Register [S]
―
TPUCFG [R/W] B,H,W
-------0 0-000000 -------- -------0
000908H
00090CH
TPUTIR [R] B,H,W
00000000
―
―
―
000910H
TPUTST [R] B,H,W
00000000
―
―
―
000914H
TPUTIE [R/W] B,H,W
00000000
―
―
―
TPUTMID [R] B,H,W
00000000 00000000 00000000 00000000
000918H
00091CH
to
00092CH
―
000930H
000934H
000938H
00093CH
000940H
―
―
TPUTCN00 [R/W] B,H,W
000000-- 00000000 00000000 00000000
TPUTCN01 [R/W] B,H,W
000000-- 00000000 00000000 00000000
TPUTCN03 [R/W] B,H,W
000000-- 00000000 00000000 00000000
TPUTCN04 [R/W] B,H,W
000000-- 00000000 00000000 00000000
TPUTCN05 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000948H
TPUTCN06 [R/W] B,H,W
000000-- 00000000 00000000 00000000
00094CH
TPUTCN07 [R/W] B,H,W
000000-- 00000000 00000000 00000000
CONFIDENTIAL
Time Protection
Unit[S]
TPUTCN02 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000944H
April 25, 2014, MB91F552_DS705-00015-1v0-E
―
31
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
000950H
000954H
000958H
00095CH
000960H
000964H
000968H
00096CH
TPUTCN10 [R/W]
B,H,W
---00000
TPUTCN11 [R/W]
B,H,W
---00000
TPUTCN12 [R/W]
B,H,W
---00000
TPUTCN13 [R/W]
B,H,W
---00000
TPUTCN14 [R/W]
B,H,W
---00000
TPUTCN15 [R/W]
B,H,W
---00000
TPUTCN16 [R/W]
B,H,W
---00000
TPUTCN17 [R/W]
B,H,W
---00000
+1
+2
+3
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
TPUTCC0 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC1 [R] B,H,W
-------- 00000000 00000000 00000000
000970H
000974H
000978H
TPUTCC2 [R] B,H,W
-------- 00000000 00000000 00000000
00097CH
TPUTCC3 [R] B,H,W
-------- 00000000 00000000 00000000
000980H
TPUTCC4 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC5 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC6 [R] B,H,W
-------- 00000000 00000000 00000000
TPUTCC7 [R] B,H,W
-------- 00000000 00000000 00000000
000984H
000988H
00098CH
000990H
to
0009FCH
000A00H
to
000BECH
―
―
―
―
―
―
―
―
32
CONFIDENTIAL
Reserved
HSCFR [R/W] B,H,W
-------- ------00 00000000 00000000
000BF0H
000BF4H
Time Protection
Unit[S]
―
―
―
―
OCDU
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
000BF8H
―
―
MBR [R/W] B,H,W
00------ XXXXXXXX
000BFCH
―
―
UER [W] B,H,W
-------- -------X
+3
DCSR0 [R/W] H
0------- -----000
DTCR0 [R/W] H
00000000 00000000
000C08H
DSAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C0CH
DDAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C10H
DCCR1 [R/W] W
0----000 --00--00 00000000 0-000000
000C14H
DCSR1 [R/W] H
0------- -----000
DTCR1 [R/W] H
00000000 00000000
000C18H
DSAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C1CH
DDAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C20H
DCCR2 [R/W] W
0----000 --00--00 00000000 0-000000
000C24H
DCSR2 [R/W] H
0------- -----000
DTCR2 [R/W] H
00000000 00000000
000C28H
DSAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C2CH
DDAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C30H
000C34H
DCCR3 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR3 [R/W] H
DTCR3 [R/W] H
0------- -----000
00000000 00000000
000C38H
DSAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C3CH
DDAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C40H
000C44H
000C48H
000C4CH
000C50H
DMA
Controller[S]
DCCR4 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR4 [R/W] H
DTCR4 [R/W] H
0------- -----000
00000000 00000000
DSAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5 [R/W] W
0----000 --00--00 00000000 0-000000
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
OCDU
DCCR0 [R/W] W
0----000 --00--00 00000000 0-000000
000C00H
000C04H
+2
33
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
DCSR5 [R/W] H
0------- -----000
000C54H
+3
DTCR5 [R/W] H
00000000 00000000
000C58H
DSAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C5CH
DDAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C60H
DCCR6 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR6 [R/W] H
0------- -----000
000C64H
DTCR6 [R/W] H
00000000 00000000
000C68H
DSAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C6CH
DDAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C70H
DCCR7 [R/W] W
0----000 --00--00 00000000 0-000000
DCSR7 [R/W] H
0------- -----000
000C74H
DMA
Controller[S]
DTCR7 [R/W] H
00000000 00000000
000C78H
DSAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C7CH
DDAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C80H
to
000DF0H
―
―
―
―
000DF4H
―
―
DNMIR [R/W] B
0------0
DILVR [R/W] B
---11111
DMACR[R/W] W
0------- -------- 0------- --------
000DF8H
000DFCH
―
―
―
―
000E00H
―
―
DDR02 [R/W] B,H,W
00000000
DDR03 [R/W] B,H,W
00000000
000E04H
DDR04 [R/W] B,H,W
00000000
―
―
―
000E08H
to
000E1CH
―
―
―
―
000E20H
PFR00 [R/W] B,H,W
--000000
―
PFR02 [R/W] B,H,W
00000000
PFR03 [R/W] B,H,W
00000000
000E24H
PFR04 [R/W] B,H,W
00000000
―
―
―
000E28H
to
000E3CH
―
―
―
―
34
CONFIDENTIAL
Reserved[S]
DMA
Controller[S]
Reserved[S]
Data Direction
Register
Reserved
Port Function
Register
Reserved
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
000E40H
PDDR00 [R] B,H,W
--XXXXXX
―
PDDR02 [R] B,H,W
XXXXXXXX
PDDR03 [R] B,H,W
XXXXXXXX
000E44H
PDDR04 [R] B,H,W
XXXXXXXX
―
―
―
000E48H
to
000E5CH
―
―
―
―
000E60H
―
―
EPFR02 [R/W]
B,H,W
---00000
―
000E64H
to
000E68H
―
―
―
―
000E70H
EPFR16 [R/W]
B,H,W
-------0
―
―
―
000E74H
―
―
―
―
000E78H
―
―
EPFR26 [R/W]
B,H,W
-0-0-0-0
―
000E7CH
―
―
―
―
000E80H
―
―
―
EPFR35 [R/W]
B,H,W
--000000
000E84H
to
000EBCH
―
―
―
―
000EC0H
PPER00 [R/W] B,H,W
--000000
―
PPER02 [R/W] B,H,W
00000000
PPER03 [R/W] B,H,W
00000000
000EC4H
PPER04 [R/W] B,H,W
00000000
―
―
―
000EC8H
to
000F3CH
―
―
―
―
Reserved
PORTEN [R/W] B,H,W
―
-------0
KEYCDR [R/W] H
00000000 00000000
―
―
Port Enable
Register
―
―
Key Code Register
000F40H
000F44H
Port Direct
Read Register
Reserved
Extended Port
Function Register
Reserved
Port Pull-up/down
Enable Register
000F48H
to
000FFCH
―
―
―
―
Reserved
001000H
SACR [R/W] B,H,W
-------0
PICD [R/W] B,H,W
----0011
―
―
Clock Control
001004H
to
00112CH
―
―
―
―
Reserved
001130H
―
―
―
CRCCR [R/W] B,H,W
-0000000
CRC calculation
unit
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
35
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
001134H
CRCINIT [R/W] B,H,W
11111111 11111111 11111111 11111111
001138H
CRCIN [R/W] B,H,W
00000000 00000000 00000000 00000000
00113CH
CRCR [R] B,H,W
11111111 11111111 11111111 11111111
001140H
to
001200H
001204H
―
―
―
CPCLRB0/CPCLR0 [W] H,W
11111111 11111111
―
TCDT0 [R/W] H,W
00000000 00000000
―
00127CH
001280H
―
―
―
IPCP0 [R] H,W
00000000 00000000
―
―
ICS01 [R/W] B,H,W
-------0 -0-0--00
―
LSYNS [R/W] B,H,W
-----000
001284H
to
001300H
―
―
―
―
001304H
ADTSS0[R/W]B,H,W
-------0
―
―
―
00130CH
―
―
001310H
―
―
001314H
―
―
001318H
―
―
―
―
―
―
00134CH
ADTCS0[R/W] B,H,W
00000000 --------
ADTCS1[R/W] B,H,W
00000000 --------
001350H
ADTCS2[R/W] B,H,W
00000000 --------
ADTCS3[R/W] B,H,W
00000000 --------
001354H
ADTCS4[R/W] B,H,W
00000000 --------
ADTCS5[R/W] B,H,W
00000000 --------
36
CONFIDENTIAL
Reserved
Input Capture 0
(16bit)
Reserved
ADTSE0[R/W] B,H,W
-------- -------- -------- 00000000
001308H
00131CH
to
001348H
Reserved
Free-run Timer 0
(16bit)
TCCS0 [R/W] B,H,W
00000000 01000000 ----0000 --------
001208H
00120CH
to
001278H
CRC calculation
unit
12 bit
A/D converter
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+2
ADTCS6[R/W] B,H,W
00000000 --------
001358H
00135CH
to
001388H
+1
―
+3
ADTCS7[R/W] B,H,W
00000000 --------
―
―
―
00138CH
ADTCD0[R] B,H,W
10--0000 00000000
ADTCD1[R] B,H,W
10--0000 00000000
001390H
ADTCD2[R] B,H,W
10--0000 00000000
ADTCD3[R] B,H,W
10--0000 00000000
001394H
ADTCD4[R] B,H,W
10--0000 00000000
ADTCD5[R] B,H,W
10--0000 00000000
001398H
ADTCD6[R] B,H,W
10--0000 00000000
ADTCD7[R] B,H,W
10--0000 00000000
00139CH
to
0013C8H
―
―
―
―
0013CCH
ADTECS0[R/W] B,H,W
-------0 ---00000
ADTECS1[R/W] B,H,W
-------0 ---00000
0013D0H
ADTECS2[R/W] B,H,W
-------0 ---00000
ADTECS3[R/W] B,H,W
-------0 ---00000
0013D4H
ADTECS4[R/W] B,H,W
-------0 ---00000
ADTECS5[R/W] B,H,W
-------0 ---00000
0013D8H
ADTECS6[R/W] B,H,W
-------0 ---00000
ADTECS7[R/W] B,H,W
-------0 ---00000
0013DCH
to
001454H
―
―
―
001458H
ADPRTF0[R] B,H,W
-------- -------- -------- 00000000
00145CH
―
ADCS0[R] B,H,W
0------- --------
001460H
―
ADCH0[R] B,H,W
---00000
ADMD0[R/W] B,H,W
0---0000
001464H
ADSTPCS0[R/W]
B,H,W
00000000
ADSTPCS1[R/W]
B,H,W
00000000
―
―
001468H
―
―
―
―
EADTCS0 [R/W]
B,H,W
----0000
EADTCS4 [R/W]
B,H,W
----0000
EADTCS1 [R/W]
B,H,W
----0000
EADTCS5 [R/W]
B,H,W
----0000
EADTCS2 [R/W]
B,H,W
----0000
EADTCS6 [R/W]
B,H,W
----0000
EADTCS3 [R/W]
B,H,W
----0000
EADTCS7 [R/W]
B,H,W
----0000
―
―
―
―
00146CH
001470H
001474H
to
00174CH
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
12 bit
A/D converter
Reserved
37
D a t a S h e e t
Address offset value / Register name
Block
Address
001750H
+0
+1
+2
+3
SCR0[R/W] B,H,W
0--00000
SMR0[R/W]
B,H,W
000-00-0
SSR0[R/W]
B,H,W
0-000011
ESCR0[R/W] B,H,W
00000000
001754H
― /(RDR10/(TDR10))[R/W] H,W
-------- --------*2
RDR00/(TDR00)[R/W] B,H,W*4
-------0 00000000*1
001758H
SACSR0[R/W] B,H,W
00-----0 0--00000
STMR0[R] B,H,W
00000000 00000000
00175CH
STMCR0[R/W] B,H,W
00000000 00000000
― /(SCSCR0/SFUR0)[R/W] B,H,W
-------- --------*2 *3
― /(SCSTR00)/
(SFLR00)
[R/W] B,H,W
--------*2
001760H
― /(SCSTR30)/
(LAMSR0)
[R/W] B,H,W
--------*2
― /(SCSTR20)/
(LAMCR0)
[R/W] B,H,W
--------*2
― /(SCSTR10)
/(SFLR10)
[R/W] B,H,W
--------*2
001764H
―
―
―
― /(SCSFR00)
[R/W] B,H,W
--------*2
001768H
―/(LAMESR0)
[R/W] B,H,W
--------*2
―/(LAMERT0)
[R/W] B,H,W
--------*2
―/(TBYTE10)/
(LAMIER0)
[R/W] B,H,W
--------*2
TBYTE00/(LAMRID0)/
(LAMTID0)
[R/W] B,H,W
00000000
―
―
BGR0[R/W] H, W
00000000 00000000
00176CH
001770H
FCR10[R/W]
B,H,W
---00100
FTICR0[R/W] B,H,W
00000000 00000000
001774H
001778H
FCR00[R/W]
B,H,W
-0000000
SCR1[R/W] B,H,W
0--00000
SMR1[R/W] B,H,W
000-00-0
―
―
SSR1[R/W] B,H,W
0-000011
ESCR1[R/W] B,H,W
00000000
― /(RDR11/(TDR11))[R/W] H,W
-------- --------*2
RDR01/(TDR01)[R/W] B,H,W *4
-------0 00000000*1
001780H
SACSR1[R/W] B,H,W
00-----0 0--00000
STMR1[R] B,H,W
00000000 00000000
001784H
STMCR1[R/W] B,H,W
00000000 00000000
― /(SCSCR1/SFUR1)[R/W] B,H,W
-------- --------*2 *3
001788H
― /(SCSTR31)/
(LAMSR1)
[R/W] B,H,W
--------*2
― /(SCSTR21)/
(LAMCR1)
[R/W] B,H,W
--------*2
― /(SCSTR11)/
(SFLR11)
[R/W] B,H,W
--------*2
― /(SCSTR01)/
(SFLR01)
[R/W] B,H,W
--------*2
00178CH
―
―
―
― /(SCSFR01)
[R/W] B,H,W
--------*2
CONFIDENTIAL
*2: Reserved
because CSIO
mode is not set
immediately after
reset.
*3: Reserved
because LIN2.1
mode is not set
immediately after
reset.
* 4: Byte access in
CSIO mode is
prohibited.
FBYTE0[R/W] B,H,W
00000000 00000000
00177CH
38
Multi-UART0
*1: Byte access is
possible only for
access to lower 8
bits.
Multi-UART1
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because CSIO
mode is not set
immediately after
reset.
*3: Reserved
because LIN2.1
mode is not set
immediately after
reset.
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
001790H
+0
+1
+2
―/(LAMESR1)
[R/W] B,H,W
--------*2
―/(LAMERT1)
[R/W] B,H,W
--------*2
―/(TBYTE11)/
(LAMIER1)
[R/W] B,H,W
--------*2
BGR1[R/W] H,W
00000000 00000000
001794H
001798H
FCR11[R/W]
B,H,W
---00100
0017A0H
SCR2[R/W] B,H,W
0--00000
TBYTE01/(LAMRID1)/ * 4: Byte access in
CSIO mode is
(LAMTID1)
prohibited.
[R/W] B,H,W
00000000
―
FCR01[R/W]
B,H,W
-0000000
FTICR1[R/W] B,H,W
00000000 00000000
00179CH
+3
SMR2[R/W] B,H,W
000-00-0
―
FBYTE1[R/W] B,H,W
00000000 00000000
―
―
SSR2[R/W] B,H,W
0-000011
ESCR2[R/W] B,H,W
00000000
0017A4H
― /(RDR12/(TDR12))[R/W] H,W
-------- --------*2
RDR02/(TDR02)[R/W] B,H,W*4
-------0 00000000*1
0017A8H
SACSR2[R/W] B,H,W
00-----0 0--00000
STMR2[R] B,H,W
00000000 00000000
0017ACH
STMCR2[R/W] B,H,W
00000000 00000000
― /(SCSCR2/SFUR2)[R/W] B,H,W
-------- --------*2 *3
0017B0H
― /(SCSTR32)/
(LAMSR2)
[R/W] B,H,W
--------*2
― /(SCSTR22)/
(LAMCR2)
[R/W] B,H,W
--------*2
― /(SCSTR12)/
(SFLR12)
[R/W] B,H,W
--------*2
― /(SCSTR02)/
(SFLR02)
[R/W] B,H,W
--------*2
0017B4H
―
―
―
― /(SCSFR02)
[R/W] B,H,W
--------*2
―/(LAMERT2)
[R/W] B,H,W
--------*2
―/(TBYTE12)/
(LAMIER2)
[R/W] B,H,W
--------*2
0017B8H
―/(LAMESR2)
[R/W] B,H,W
--------*2
BGR2[R/W] H, W
00000000 00000000
0017BCH
0017C0H
FCR12[R/W]
B,H,W
---00100
FTICR2[R/W] B,H,W
00000000 00000000
0017C4H
0017C8H
to
0020FCH
―
―
FBYTE2[R/W] B,H,W
00000000 00000000
―
―
―
―
CTRLR1 [R/W] B,H,W
-------- 000-0001
STATR1 [R/W] B,H,W
-------- 00000000
002104H
ERRCNT1 [R] B,H,W
00000000 00000000
BTR1 [R/W] B,H,W
-0100011 00000001
CONFIDENTIAL
*3: Reserved
because LIN2.1
mode is not set
immediately after
reset.
―
002100H
April 25, 2014, MB91F552_DS705-00015-1v0-E
*2: Reserved
because CSIO
mode is not set
immediately after
reset.
* 4: Byte access in
TBYTE02/(LAMRID2)/ CSIO mode is
(LAMTID2)
prohibited.
[R/W] B,H,W
00000000
―
FCR02[R/W]
B,H,W
-0000000
Multi-UART2
*1: Byte access is
possible only for
access to lower 8
bits.
Reserved
CAN
(64msb)
39
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
002108H
INTR1 [R] H,W
00000000 00000000
TESTR1 [R/W] B,H,W
-------- X00000--
00210CH
BRPER1 [R/W] B,H,W
-------- ----0000
002110H
IF1CREQ1 [R/W] B,H,W
0------- 00000001
IF1CMSK1 [R/W] B,H,W
-------- 00000000
002114H
IF1MSK21 [R/W] B,H,W
11-11111 11111111
IF1MSK11 [R/W] B,H,W
11111111 11111111
002118H
IF1ARB21 [R/W] B,H,W
00000000 00000000
IF1ARB11 [R/W] B,H,W
00000000 00000000
00211CH
IF1MCTR1 [R/W] B,H,W
00000000 0---0000
002120H
IF1DTA11 [R/W] B,H,W
00000000 00000000
IF1DTA21 [R/W] B,H,W
00000000 00000000
002124H
IF1DTB11 [R/W] B,H,W
00000000 00000000
IF1DTB21 [R/W] B,H,W
00000000 00000000
―
―
―
―
002128H
―
―
―
―
00212CH
―
―
―
―
002130H,
002134H
Reserved (IF1 data mirror)
002138H
―
―
―
―
00213CH
―
―
―
―
002140H
IF2CREQ1 [R/W] B,H,W
0------- 00000001
IF2CMSK1 [R/W] B,H,W
-------- 00000000
002144H
IF2MSK21 [R/W] B,H,W
11-11111 11111111
IF2MSK11 [R/W] B,H,W
11111111 11111111
002148H
IF2ARB21 [R/W] B,H,W
00000000 00000000
IF2ARB11 [R/W] B,H,W
00000000 00000000
00214CH
IF2MCTR1 [R/W] B,H,W
00000000 0---0000
002150H
IF2DTA11 [R/W] B,H,W
00000000 00000000
IF2DTA21 [R/W] B,H,W
00000000 00000000
002154H
IF2DTB11 [R/W] B,H,W
00000000 00000000
IF2DTB21 [R/W] B,H,W
00000000 00000000
―
―
002158H
―
―
―
―
00215CH
―
―
―
―
002160H,
002164H
40
CONFIDENTIAL
CAN
(64msb)
Reserved (IF2 data mirror)
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
002168H
to
00217CH
+2
+3
―
002180H
TREQR21 [R] B,H,W
00000000 00000000
TREQR11 [R] B,H,W
00000000 00000000
002184H
TREQR41 [R] B,H,W
00000000 00000000
TREQR31 [R] B,H,W
00000000 00000000
002188H
―
―
―
―
00218CH
―
―
―
―
002190H
NEWDT21 [R] B,H,W
00000000 00000000
NEWDT11 [R] B,H,W
00000000 00000000
002194H
NEWDT41 [R] B,H,W
00000000 00000000
NEWDT31 [R] B,H,W
00000000 00000000
002198H
―
―
―
―
00219CH
―
―
―
―
0021A0H
INTPND21 [R] B,H,W
00000000 00000000
INTPND11 [R] B,H,W
00000000 00000000
0021A4H
INTPND41 [R] B,H,W
00000000 00000000
INTPND31 [R] B,H,W
00000000 00000000
0021A8H
―
―
―
―
0021ACH
―
―
―
―
0021B0H
MSGVAL21 [R] B,H,W
00000000 00000000
MSGVAL11 [R] B,H,W
00000000 00000000
0021B4H
MSGVAL41 [R] B,H,W
00000000 00000000
MSGVAL31 [R] B,H,W
00000000 00000000
0021B8H
―
―
―
―
0021BCH
―
―
―
―
0021C0H
to
0022FCH
002300H
―
DFCTLR [R/W] B,H,W
-0------ --------
Reserved
―
DFSTR [R/W] B,H,W
-----001
002304H
―
―
―
―
002308H
FLIFCTLR [R/W]
B,H,W
---0--00
―
FLIFFER1 [R/W]
B,H,W
--------
FLIFFER2 [R/W]
B,H,W
--------
00230CH
to
0023FCH
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
―
CAN
(64msb)
WorkFlash
Flash / WorkFlash
Reserved
41
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
SEEARX [R] B,H,W
-0000000 00000000
002400H
002404H
EECSRX [R/W]
B,H,W
----00-0
002408H
―
+3
DEEARX [R] B,H,W
-0000000 00000000
EFEARX [R/W] B,H,W
-0000000 00000000
―
EFECRX [R/W] B,H,W
-------0 00000000 00000000
00240CH
to
003008H
―
00300CH
TEAR0X[R] B,H,W
000----- -------- -0000000 00000000
003010H
TEAR1X[R] B,H,W
000----- -------- -0000000 00000000
003014H
TEAR2X[R] B,H,W
000----- -------- -0000000 00000000
003018H
Reserved
TAEARX [R/W] B,H,W
-1111111 11111111
00301CH
TFECRX [R/W]
B,H,W
----0000
TICRX [R/W]
B,H,W
----0000
003020H
TSRCRX [W]
B,H,W
0-------
―
003024H
to
0030FCH
TASARX [R/W] B,H,W
-0000000 00000000
TKCCRX [R/W]
B,H,W
00----00
―
―
Reserved
BUSDIGSR0[R/W] H,W
00000000 0-----00
BUSDIGSR1[R/W] H,W
00000000 0-----00
003104H
BUSDIGSR2[R/W] H,W
00000000 0-----00
BUSTSTR0[R/W] H,W
00--0000 00000000
003108H
BUSADR0 [R] W
00000000 00000000 00000000 00000000
00310CH
BUSADR1 [R] W
00000000 00000000 00000000 00000000
003110H
BUSADR2 [R] W
00000000 00000000 00000000 00000000
003118H
00311CH
―
―
BUSDIGSR3[R/W] H,W
00000000 0-----00
BUSDIGSR4[R/W] H,W
00000000 0-----00
―
―
―
BUSADR3 [R] W
00000000 00000000 00000000 00000000
003124H
BUSADR4 [R] W
00000000 00000000 00000000 00000000
CONFIDENTIAL
Bus diagnosis
BUSTSTR1[R/W] H,W
00--000- 00000000
003120H
42
RAM diagnosis
XBS RAM
TTCRX [R/W] B,H,W
------00 00001100
003100H
003114H
XBS RAM
ECC control
―
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
003128H
to
00313CH
+2
+3
―
PWCC0 [R/W]
B,H,W
---00000
Reserved
003140H
PWCINIT0 [R/W]
B,H,W
-------0
003144H
PWCCPCLRB00/PWCCPCLR00 [W] H,W
11111111 11111111
003148H
PWCTCCS00 [R/W] B,H,W
-0000000 0--0-000
00314CH
PWCCPCLRB10/PWCCPCLR10 [W] H,W
11111111 11111111
003150H
PWCTCCS10 [R/W] B,H,W
-0000000 0--0----
003154H
PWCDBR00 [R] H,W
00000000 00000000
PWCDBR10 [R] H,W
00000000 00000000
003158H
PWCDBR20 [R] H,W
00000000 00000000
PWCDBR30 [R] H,W
00000000 00000000
00315CH
PWCDBS0 [R] B,H,W
-000-000 -000-000
―
―
003160H
PWCBFIRQF0 [R/W] B,H,W
00000000 00000000
―
―
―
PWCTCDT00 [R/W] H,W
00000000 00000000
―
―
PWCTCDT10 [R/W] H,W
00000000 00000000
―
PWCBFIRQC0 [R/W] B,H,W
00000000 00000000 00000000
003164H
―
―
―
003168H
PWCCUC00 [R/W] H,W
00000000 00000000
PWCCLC00 [R/W] H,W
00000000 00000000
00316CH
PWCCUC10 [R/W] H,W
00000000 00000000
PWCCLC10 [R/W] H,W
00000000 00000000
003170H
PWCCUC20 [R/W] H,W
00000000 00000000
PWCCLC20 [R/W] H,W
00000000 00000000
003174H
PWCCUC30 [R/W] H,W
00000000 00000000
PWCCLC30 [R/W] H,W
00000000 00000000
003178H
PWCINIT1 [R/W]
B,H,W
-------0
00317CH
PWCCPCLRB01/PWCCPCLR01 [W] H,W
11111111 11111111
003180H
PWCTCCS01 [R/W] B,H,W
-0000000 0--0-000
003184H
PWCCPCLRB11/PWCCPCLR11 [W] H,W
11111111 11111111
003188H
PWCTCCS11 [R/W] B,H,W
-0000000 0--0----
00318CH
PWCDBR01 [R] H,W
00000000 00000000
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
PWCC1 [R/W]
B,H,W
---00000
PWC 0ch
―
―
PWCTCDT01 [R/W] H,W
00000000 00000000
―
―
PWC 1ch
PWCTCDT11 [R/W] H,W
00000000 00000000
―
―
PWCDBR11 [R] H,W
00000000 00000000
43
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
003190H
PWCDBR21 [R] H,W
00000000 00000000
PWCDBR31 [R] H,W
00000000 00000000
003194H
PWCDBS1 [R] B,H,W
-000-000 -000-000
―
―
003198H
PWCBFIRQF1 [R/W] B,H,W
00000000 00000000
―
―
PWCBFIRQC1 [R/W] B,H,W
00000000 00000000 00000000
00319CH
―
0031A0H
PWCCUC01 [R/W] H,W
00000000 00000000
PWCCLC01 [R/W] H,W
00000000 00000000
0031A4H
PWCCUC11 [R/W] H,W
00000000 00000000
PWCCLC11 [R/W] H,W
00000000 00000000
0031A8H
PWCCUC21 [R/W] H,W
00000000 00000000
PWCCLC21 [R/W] H,W
00000000 00000000
0031ACH
PWCCUC31 [R/W] H,W
00000000 00000000
PWCCLC31 [R/W] H,W
00000000 00000000
0031B0H
to
0031BCH
―
―
0031C0H
0031C4H
PWMTCGS [R/W]
B,H,W
------00
PWMCPCLRB0/PWMCPCLR0 [W] H,W
11111111 11111111
―
PWMCPCLRB1/PWMCPCLR1 [W] H,W
11111111 11111111
Reserved
PWMTCGSE [R/W]
B,H,W
------00
PWMTCDT0 [R/W] H,W
00000000 00000000
PWMTCCS0 [R/W] B,H,W
-0000000 0100-000 ----0000
0031C8H
0031CCH
―
―
PWMTCDT1 [R/W] H,W
00000000 00000000
0031D0H
PWMTCCS1 [R/W] B,H,W
-0000000 0100---- ----0000
―
0031D4H
PWMTRC [R/W] B,H,W
-0000000 -000-000 -----000
―
0031D8H
PWMSYNCP0 [R/W] H,W
00000000 00000000
0031DCH
PWMSEVCON [R/W] B,H,W
---00000 ---00000
0031E0H
PWMSEVST [R/W]
B,H,W
------00
―
PWMSYNCP1 [R/W] H,W
00000000 00000000
―
―
―
―
0031E4H
PWMSEVCP0 [R/W] H,W
00000000 00000000
PWMSEVCP1 [R/W] H,W
00000000 00000000
0031E8H
PWMMCD0B [R/W] H,W
00000000 00000000
PWMMCD1B [R/W] H,W
00000000 00000000
0031ECH
PWMST0 [R/W] B,H,W PWMST1 [R/W] B,H,W
----0000
----0000
44
CONFIDENTIAL
PWC 1ch
PWMST2 [R/W]
B,H,W
----0000
PWM
master clock
generation
PWMFLTST [R] B,H,W
--XXXXXX
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
+3
0031F0H
PWMCMD [R/W] H,W
00000000 00000000
PWMPCGS [R/W]
B,H,W
-----000
―
0031F4H
PWMPCN01 [R/W] B,H,W
00000000 ------00
―
―
0031F8H
PWMCC0B [R/W] H,W
00000000 00000000
PWMCP0B [R/W] H,W
00000000 00000000
0031FCH
PWMCD0B [R/W] H,W
00000000 00000000
PWMPTMR0 [R] H,W
00000000 00000000
003200H
PWMCC1B [R/W] H,W
00000000 00000000
PWMCP1B [R/W] H,W
00000000 00000000
003204H
PWMCD1B [R/W] H,W
00000000 00000000
PWMPTMR1 [R] H,W
00000000 00000000
003208H
PWMPCN23 [R/W] B,H,W
00000000 ------00
00320CH
PWMCC2B [R/W] H,W
00000000 00000000
PWMCP2B [R/W] H,W
00000000 00000000
003210H
PWMCD2B [R/W] H,W
00000000 00000000
PWMPTMR2 [R] H,W
00000000 00000000
003214H
PWMCC3B [R/W] H,W
00000000 00000000
PWMCP3B [R/W] H,W
00000000 00000000
003218H
PWMCD3B [R/W] H,W
00000000 00000000
PWMPTMR3 [R] H,W
00000000 00000000
00321CH
PWMPCN45 [R/W] B,H,W
00000000 ------00
003220H
PWMCC4B [R/W] H,W
00000000 00000000
PWMCP4B [R/W] H,W
00000000 00000000
003224H
PWMCD4B [R/W] H,W
00000000 00000000
PWMPTMR4 [R] H,W
00000000 00000000
003228H
PWMCC5B [R/W] H,W
00000000 00000000
PWMCP5B [R/W] H,W
00000000 00000000
00322CH
PWMCD5B [R/W] H,W
00000000 00000000
PWMPTMR5 [R] H,W
00000000 00000000
003230H
PWMFLTCON00 [R/W] B,H,W
00000000 -0000-00
PWMFLTCON01 [R/W] B,H,W
00000000 -0000-00
003234H
PWMFLTRCON0 [R/W] B,H,W
-000-000 -000-000
PWMFLTCAPCON0 [R/W] B,H,W
--00--00 -0000000
003238H
PWMFLTSR0 [R/W] B,H,W
-------0 -------0
―
00323CH
PWMCAPITH0 [R/W] H,W
00000000 00000000
―
―
―
―
―
003240H
PWMFLTRDCON00 [R/W] H,W
00000000 00000000 00000000 00000000
003244H
PWMFLTRDCON01 [R/W] H,W
00000000 00000000 00000000 00000000
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
PWM
PWM generation
―
―
PWM
fault
45
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+1
+2
003248H
PWMFLTCAPRDCON0 [R/W] H,W
00000000 00000000 00000000 00000000
00324CH
PWMFLTCAPD0 [R] H,W
00000000 00000000 00000000 00000000
+3
003250H
PWMFLTCON10 [R/W] B,H,W
00000000 -0000-00
PWMFLTCON11 [R/W] B,H,W
00000000 -0000-00
003254H
PWMFLTRCON1 [R/W] B,H,W
-000-000 -000-000
PWMFLTCAPCON1 [R/W] B,H,W
--00--00 -0000000
003258H
PWMFLTSR1 [R/W] B,H,W
-------0 -------0
―
―
00325CH
PWMCAPITH1 [R/W] H,W
00000000 00000000
―
―
003260H
PWMFLTRDCON10 [R/W] H,W
00000000 00000000 00000000 00000000
003264H
PWMFLTRDCON11 [R/W] H,W
00000000 00000000 00000000 00000000
003268H
PWMFLTCAPRDCON1 [R/W] H,W
00000000 00000000 00000000 00000000
00326CH
PWMFLTCAPD1 [R] H,W
00000000 00000000 00000000 00000000
PWM
fault
003270H
PWMFLTCON20 [R/W] B,H,W
00000000 -0000-00
PWMFLTCON21 [R/W] B,H,W
00000000 -0000-00
003274H
PWMFLTRCON2 [R/W] B,H,W
-000-000 -000-000
PWMFLTCAPCON2 [R/W] B,H,W
--00--00 -0000000
003278H
PWMFLTSR2 [R/W] B,H,W
-------0 -------0
―
―
00327CH
PWMCAPITH2 [R/W] H,W
00000000 00000000
―
―
003280H
PWMFLTRDCON20 [R/W] H,W
00000000 00000000 00000000 00000000
003284H
PWMFLTRDCON21 [R/W] H,W
00000000 00000000 00000000 00000000
003288H
PWMFLTCAPRDCON2 [R/W] H,W
00000000 00000000 00000000 00000000
00328CH
PWMFLTCAPD2 [R] H,W
00000000 00000000 00000000 00000000
003290H
PWMSOWCON0 [R/W] B,H,W
00000000 -------0 00000000 00000000
003294H
PWMSOWCON1 [R/W] B,H,W
00000000 -------0 00000000 00000000
003298H
PWMSOWCON2 [R/W] B,H,W
00000000 -------0 00000000 00000000
46
CONFIDENTIAL
PWM
soft overwrite
control
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
00329CH
+0
+1
+2
+3
PWMDMOD [R/W]
B,H,W
--000000
―
―
―
0032A0H
PWMHRTMRR0 [R/W] H,W
00000000 00000000
PWMHFTMRR0 [R/W] H,W
00000000 00000000
0032A4H
PWMLRTMRR0 [R/W] H,W
00000000 00000000
PWMLFTMRR0 [R/W] H,W
00000000 00000000
0032A8H
PWMHRTMRR1 [R/W] H,W
00000000 00000000
PWMHFTMRR1 [R/W] H,W
00000000 00000000
0032ACH
PWMLRTMRR1 [R/W] H,W
00000000 00000000
PWMLFTMRR1 [R/W] H,W
00000000 00000000
0032B0H
PWMHRTMRR2 [R/W] H,W
00000000 00000000
PWMHFTMRR2 [R/W] H,W
00000000 00000000
0032B4H
PWMLRTMRR2 [R/W] H,W
00000000 00000000
PWMLFTMRR2 [R/W] H,W
00000000 00000000
0032B8H
PWMLEBCON0 [R/W] B,H,W
-000-000 -000-000 ----0000
―
0032BCH
PWMLEBSDCON00 [R/W] H,W
00000000 00000000
PWMLEBSDCON01 [R/W] H,W
00000000 00000000
0032C0H
PWMLEBSDCON02 [R/W] H,W
00000000 00000000
PWMLEBSDCON03 [R/W] H,W
00000000 00000000
0032C4H
PWMLEBTCON00 [R/W] H,W
00000000 00000000 00000000 00000000
0032C8H
PWMLEBTCON01 [R/W] H,W
00000000 00000000 00000000 00000000
0032CCH
PWMLEBCON1 [R/W] B,H,W
-000-000 -000-000 ----0000
―
0032D0H
PWMLEBSDCON10 [R/W] H,W
00000000 00000000
PWMLEBSDCON11 [R/W] H,W
00000000 00000000
0032D4H
PWMLEBSDCON12 [R/W] H,W
00000000 00000000
PWMLEBSDCON13 [R/W] H,W
00000000 00000000
0032D8H
PWMLEBTCON10 [R/W] H,W
00000000 00000000 00000000 00000000
0032DCH
PWMLEBTCON11 [R/W] H,W
00000000 00000000 00000000 00000000
0032E0H
PWMLEBCON2 [R/W] B,H,W
-000-000 -000-000 ----0000
PWM
Blanking
―
0032E4H
PWMLEBSDCON20 [R/W] H,W
00000000 00000000
PWMLEBSDCON21 [R/W] H,W
00000000 00000000
0032E8H
PWMLEBSDCON22 [R/W] H,W
00000000 00000000
PWMLEBSDCON23 [R/W] H,W
00000000 00000000
0032ECH
PWMLEBTCON20 [R/W] H,W
00000000 00000000 00000000 00000000
0032F0H
PWMLEBTCON21 [R/W] H,W
00000000 00000000 00000000 00000000
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
PWM
dead time
47
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
+2
+3
PWMADTCON [R/W] B,H,W
00000000 00000000 --000000 ----0000
0032F4H
0032F8H
+1
PWMADTST [R/W]
B,H,W
----0000
―
―
―
0032FCH
PWMADTDCON0 [R/W] H,W
00000000 00000000
PWMADTDCON1 [R/W] H,W
00000000 00000000
003300H
PWMADTDCON2 [R/W] H,W
00000000 00000000
PWMADTDCON3 [R/W] H,W
00000000 00000000
003304H
to
00331CH
―
Reserved
003320H
AD4EN [R/W] B,H,W
-------0
―
―
―
003324H
AD4TSS [R/W] B,H,W
-------0
―
―
―
AD4TSE [R/W] B,H,W
-------- -------- -------- 00000000
003328H
00332CH
AD4TCS0 [R/W] B,H,W
---00--- --------
AD4TCS1 [R/W] B,H,W
---00--- --------
003330H
AD4TCS2 [R/W] B,H,W
---00--- --------
AD4TCS3 [R/W] B,H,W
---00--- --------
003334H
AD4TCS4 [R/W] B,H,W
---00--- --------
AD4TCS5 [R/W] B,H,W
---00--- --------
003338H
AD4TCS6 [R/W] B,H,W
---00--- --------
AD4TCS7 [R/W] B,H,W
---00--- --------
003340H
AD4TECS0 [R/W] B,H,W
00--0000 0000----
AD4TECS1 [R/W] B,H,W
00--0000 0000----
003344H
AD4TECS2 [R/W] B,H,W
00--0000 0000----
AD4TECS3 [R/W] B,H,W
00--0000 0000----
003348H
AD4TECS4 [R/W] B,H,W
00--0000 0000----
AD4TECS5 [R/W] B,H,W
00--0000 0000----
00334CH
AD4TECS6 [R/W] B,H,W
00--0000 0000----
AD4TECS7 [R/W] B,H,W
00--0000 0000----
003354H
48
CONFIDENTIAL
12 bit 4ch A/D
converter
AD4TBUSY [R/W] B,H,W
-------- -------- -------- 00000000
00333CH
003350H
PWM
trigger
AD4PTC8 [R/W]
B,H,W
0000----
AD4PTC9 [R/W]
B,H,W
0000----
AD4TCD8 [R] B,H,W
10--0000 00000000
AD4PTC10 [R/W]
B,H,W
0000----
AD4PTC11 [R/W]
B,H,W
0000----
AD4TCD9 [R] B,H,W
10--0000 00000000
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Address offset value / Register name
Block
Address
+0
003358H
+1
+2
AD4TCD10 [R] B,H,W
10--0000 00000000
AD4TCD11 [R] B,H,W
10--0000 00000000
AD4CS [R/W] B,H,W
00------ 00------
00335CH
―
003360H
AD4PRTF [R] B,H,W
-------- -------- -------- ----0000
003364H
to
00EFFCH
―
00F000H
to
00FEFCH
00FF00H
―
+3
―
DSUCR [R/W] B,H,W
-------- -------0
AD4MD [R/W] B,H,W
----0000
12 bit 4ch A/D
converter
Reserved
―
―
―
―
00FF04H
to
00FF0CH
―
00FF10H
PCSR [R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF14H
PSSR [R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18H
to
00FFF4H
―
00FFF8H
EDIR1 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FFFCH
EDIR0 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved[S]
OCDU [S]
[S]: It is a system register. The illegal instruction exception (data access error) is generated in
these registers in the user mode when reading and writing to it.
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
49
D a t a S h e e t
 INTERRUPT VECTOR TABLE
This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers.
 Interrupt vector
Interrupt factor
Interrupt
Default
number
Interru
RN
Offset address for
*
Hexad pt level
TBR
Decimal
ecimal
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of invalid instruction
NMI request
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
TPU violation
External interrupt 0-3
External low-voltage detection interrupt
Reload timer 0/1/4
Reload timer 2/3
Multi-function serial interface ch.0
(reception completed)
Multi-function serial interface ch.0 (status)
Multi-function serial interface ch.0
(transmission completed)
Multi-function serial interface ch.1
(reception completed)
Multi-function serial interface ch.1(status)
Multi-function serial interface ch.1
(transmission completed)
Multi-function serial interface ch.2
(reception completed)
Multi-function serial interface ch.2(status)
Multi-function serial interface ch.2
(transmission completed)
-
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
0A
0B
0C
0D
0E
-
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
15
0F
15(FH)
Fixed
3C0H
000FFFC0H
-
16
17
18
19
10
11
12
13
ICR00
ICR01
ICR02
ICR03
3BCH
3B8H
3B4H
3B0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
0
2
3
20
14
ICR04 3ACH 000FFFACH 4(*1)
21
15
ICR05
3A8H
000FFFA8H 5(*1)
22
16
ICR06
3A4H
000FFFA4H 6(*1)
23
17
ICR07
3A0H
000FFFA0H 7(*1)
24
18
ICR08
39CH
000FFF9CH 8(*1)
25
19
ICR09
398H
000FFF98H 9(*1)
26
27
1A
1B
ICR10
ICR11
394H
390H
000FFF94H
000FFF90H
-
-
28
1C
ICR12
38CH
000FFF8CH
-
50
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
Interrupt factor
Interrupt
Default
number
Interru
RN
Offset address for
*
Hexad pt level
TBR
Decimal
ecimal
CAN
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
4ch A/D converter irregular activation
interrupt/insufficient sampling time interrupt
PWM special event interrupt 0/1
29
30
31
32
33
34
1D
1E
1F
20
21
22
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
388H
384H
380H
37CH
378H
374H
000FFF88H
000FFF84H
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
-
35
23
ICR19
370H
000FFF70H
-
36
24
ICR20
36CH
000FFF6CH
-
37
38
25
26
ICR21
ICR22
368H
364H
000FFF68H
000FFF64H
-
16-bit Free-run timer 0 (0 detection) / (compare clear)
39
27
ICR23
360H
000FFF60H
23
40
28
ICR24
35CH
000FFF5CH
-
41
29
ICR25
358H
000FFF58H
-
42
2A
ICR26
354H
000FFF54H
-
43
2B
ICR27
350H
000FFF50H
-
44
2C
ICR28
34CH
000FFF4CH
-
45
2D
ICR29
348H
000FFF48H
29
46
2E
ICR30
344H
000FFF44H
30
PWM trigger interrupt 0/1/2/3
A/D converter 0/1/2/3/4/5/6/7
47
48
2F
30
ICR31
ICR32
340H
33CH
000FFF40H
000FFF3CH
32
Clock calibration unit (CR oscillation)
49
31
ICR33
338H
000FFF38H
-
PLL alarm interrupt for PWM
reserved
Comparator output detection interrupt 0/1/2
PWC0 0 detection interrupt 00/10,
compare clear interrupt 00/10
PWC0 capture data upper limit interrupt 00/10/20/30,
PWC0 capture data lower limit interrupt 00/10/20/30,
PWC0 data buffer interrupt 00/10/20/30,
PWC0 buffer overrun interrupt 00/10/20/30
PWC1 0 detection interrupt 01/11,
compare clear interrupt 01/11
PWC1 capture data upper limit interrupt 01/11/21/31,
PWC1 capture data lower limit interrupt 01/11/21/31,
PWC1 data buffer interrupt 01/11/21/31,
PWC1 buffer overrun interrupt 01/11/21/31
A/D converter 8/9/10/11
Base Timer 2 IRQ0
Base Timer 2 IRQ1
50
51
52
32
33
34
ICR34
ICR35
ICR36
334H
330H
32CH
000FFF34H
000FFF30H
000FFF2CH
36
53
35
ICR37
328H
000FFF28H -(*2)
54
36
ICR38
324H
000FFF24H -(*2)
55
37
ICR39
320H
000FFF20H -(*2)
56
38
ICR40
31CH
000FFF1CH -(*2)
57
39
ICR41
318H
000FFF18H -(*2)
58
3A
ICR42
314H
000FFF14H
PWM 0 detection interrupt 0, compare clear interrupt
0
PWM 0 detection interrupt 1, compare clear interrupt
1
PWM SOW interrupt 0, fault interrupt 0/1,
capture interrupt 0
PWM SOW interrupt 1, fault interrupt 2/3,
capture interrupt 1
PWM SOW interrupt 2, fault interrupt 4/5,
capture interrupt 2
16bit ICU 0 (fetching)
Main timer
PLL timer
April 25, 2014, MB91F552_DS705-00015-1v0-E
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42
51
D a t a S h e e t
Interrupt factor
Base Timer 3 IRQ0
Base Timer 3 IRQ1
Base Timer 0 IRQ0
Base Timer 0 IRQ1
Base Timer 1 IRQ0
Base Timer 1 IRQ1
Interrupt
Default
number
Interru
RN
Offset address for
*
Hexad pt level
TBR
Decimal
ecimal
59
3B
ICR43
310H
000FFF10H
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45
DMAC0/1/2/3/4/5/6/7
62
3E
ICR46
304H
000FFF04H
-
Delay interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOSTM*3)
64
40
-
2FCH 000FFEFCH
-
System reserved
(Used for REALOS)
65
41
-
2F8H
000FFEF8H
-
Used with the INT instruction
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
*: DMA transfer request by interrupt from peripherals without an assigned RN number is not supported.
*1: DMA transfer by the multi-function serial interface status is not supported.
*2: DMA transfer request by on-chip bus IP interrupt is supported.
*3: REALOS is a trademark of Spansion LLC.
52
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MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
 ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage *1, *2
1,
2
Analog power supply voltage * *
Analog reference voltage *1
Input voltage *1
Analog pin input voltage *1
Output voltage *1
Maximum clamp current
Total maximum clamp current
"L" level maximum output current *3
"L" level average output current *4
Rating
Unit
Min
Max
VCC
VSS-0.3
VSS+6.0
V
AVCC
VSS-0.3
VSS+6.0
V
AVRH
VI
VIA5
VO
ICLAMP
Σ|ICLAMP|
IOL1
IOL2
IOLAV1
VSS-0.3
VSS-0.3
VSS-0.3
VSS-0.3
-
VSS+6.0
VCC+0.3
VCC+0.3
VCC+0.3
4.0
20
15
30
4
V
V
V
V
mA
mA
mA
mA
mA
Remarks
AVRH ≤ AVCC
≤VCC
AVRH ≤ AVCC
*6
*6
*8
IOLAV2
8
mA
*8
ΣI
50
mA
OL1
"L" level total output current *5
ΣIOL2
60
mA
*8
I
-15
mA
OH1
"H" level maximum output current *3
IOH2
-30
mA
*8
IOHAV1
-4
mA
4
"H" level average output current *
IOHAV2
-8
mA
*8
ΣIOH1
-50
mA
5
"H" level total output current *
ΣIOH2
-60
mA
*8
Power consumption
PD
690
mW
Operating temperature
TA
-40
+125
°C
*7
Storage temperature
Tstg
-55
+150
°C
*1: These parameters are based on the condition that V SS=AVSS=0.0V
*2: Caution must be taken that AVCC, AVRH do not exceed VCC upon power-on and under other circumstances.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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D a t a S h e e t
*6: · Corresponding pins: all general-purpose ports.
· Use within recommended operating conditions.
· Use at DC voltage (current).
· The + B signal should always be applied by connecting a limiting resistor between the + B signal and the
microcontroller.
· The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input.
· Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+ B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other
devices.
· Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is
supplied through the pin, the microcontroller may operate incompletely.
· Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on
reset may not function in the power supply voltage.
· Do not leave + B input pins open.
*7：When you use this product at TA = 125°C, it is necessary to built-in multi-layer substrate at least four -layer
or more. If you use a 2-layer substrate, change the operating conditions (such as operating frequency, power
supply voltage) , you will need to either you use the power consumption PD = 400mW or less, or use the
operating temperature TA = 105°C or less.
*8：Corresponding pins:PWM0H, PWM0L, PWM1H, PWM1L, PWM2H, PWM2L
Sample recommended circuit
MB91550 series
Protective diode
Limiting resistor current
+B input(12 to 16V)
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
54
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MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
2. Recommended operating conditions
(VSS=AVSS=0.0V)
Parameter
Symbol
VCC
Power supply voltage
Smoothing capacitor
*2
AVcc0
AVcc1
AVcc2
Value
Unit
Max
4.5
5.5
V
3.4
5.5
V
Recommended operation guarantee
range
Operation guarantee range*1
4.5
5.5
V
Operation guarantee range*1
4.925
5.075
V
Operation guarantee range*1
Use a ceramic capacitor or a
capacitor that has the similar
frequency characteristics. Use a
capacitor with a capacitance greater
than CS as the smoothing capacitor
on the VCC pin.
4.7
(tolerance within ±50%)
CS
Remarks
Min
µF
Operating
TA
-40
+125
°C
temperature
*1: When it is used outside recommended operation guarantee range (range of the operation guarantee), contact
your sales representative. Moreover, minimum value with an effective external low-voltage detection reset
becomes a voltage until generating low-voltage detection reset.
*2: See the following diagram for details on the connection of smoothing capacitor CS.
 C Pin Connection Diagram
C
CS
VSS
VSS
AVSS
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under
any conditions other than these conditions may adversely affect reliability of device and could result in
device failure. No warranty is made with respect to any use, operating conditions or combinations not
represented on this data sheet. If you are considering application under any conditions other than listed
herein, please contact sales representatives beforehand.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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55
D a t a S h e e t
3. DC characteristics
(TA:-40°C to +125°C, Vcc=AVcc=4.5V to 5.5V, VSS=AVSS=0.0V)
Para
meter
Sym
bol
Pin
nam
e
ICC5
Power
supply
current
VCC
ICCS5
ICCBS
5
ICCT5
ICCH5
56
CONFIDENTIAL
Value
Conditions
Operating frequency
FCP=80MHz, Fcpp=40MHz
Fcpwm=200MHz,
at normal operation
Operating frequency
FCP=80MHz, Fcpp=40MHz
Fcpwm=200MHz,
at Flash write
Operating frequency FCP=80MHz,
Fcpp=40MHz
Fcpwm=200MHz,
at Flash erase
Operating frequency
FCP=80MHz, Fcpp=40MHz,
Fcpwm=200MHz
at CPU sleep mode
Operating frequency FCP=80MHz,
Fcpp=40MHz,
Fcpwm=200MHz
at bus sleep mode
When using crystal
Watch
4MHz
mode
TA=+25°C
Stop mode
TA=+25°C
Unit
Min
Typ
Max
-
60
98
mA
-
72
112
mA
-
72
112
mA
-
33
66
mA
-
26
56
mA
-
1320
2600
µA
-
190
1370
µA
Remark
s
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Input leak
current
Input
capacitance 1
Pull-up
resistance
Pull-down
resistance
Symbo
l
Min
Typ
Max
Unit
VCC=AVCC=5.5V
VSS<VI<VCC
-5
-
5
µA
CIN1
Other than
VCC,VSS,
AVCC, AVSS,
C
-
-
5
15
pF
RUP1
RSTX, NMIX
-
25
-
100
kΩ
RUP2
Port pin other
than P000 to
P005
-
25
-
100
kΩ
RDOWN
P000 to P005
-
25
-
100
kΩ
VOH1
Normal output
pin
Vcc=4.5V
IOH=-4.0mA
VCC
-0.5
-
VCC
V
VOH2
P000 to P005
Vcc=4.5V
IOH=-8.0mA
VCC
-0.5
-
VCC
V
VOL1
Normal output
pin
Vcc=4.5V
IOL=4.0mA
0
-
0.4
V
VOL2
P000 to P005
Vcc=4.5V
IOL=8.0mA
0
-
0.4
V
CMOS
hysteresis input
level
0.7×
VCC
-
VCC
V
Automotive input
level
CMOS
hysteresis input
level
0.8×
VCC
-
VCC
V
0.8×
VCC
-
VCC
V
TTL input level
2
-
VCC
V
CMOS
hysteresis input
level
Vss
-
0.3×
VCC
V
Vss
-
0.5×
VCC
V
Vss
-
0.2×
VCC
V
Vss
-
0.8
V
VIH1
VIH3
P032,P033,
P036,P037
P042,
P044,P045
Port other than
VIH1
VIH5
RSTX, NMIX,
MD0, MD1
VIHT
DEBUGIF
VIL1
VIL3
P032, P033,
P036, P037
P042,
P044, P045
Port other than
VIH1
VIL5
RSTX, NMIX,
MD0, MD1
VILT
DEBUGIF
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
Value
All input pins
“L” level
output voltage
“L” level
input voltage
Conditions
IIL
“H” level
output voltage
“H” level
input voltage
Pin name
Automotive
input level
CMOS
hysteresis input
level
TTL input level
Remar
ks
PWM
pin
output
PWM
pin
output
57
D a t a S h e e t
4. AC Characteristics
(1-1) Main Clock Timing
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Source oscillation
clock frequency
Source oscillation
clock cycle time
Internal operating
clock frequency *1
Symb
ol
Pin
name
FC
tCYL
Con
ditio
ns
Typ
Max
X0, X1
4
-
16
MHz
X0, X1
62.5
-
250
ns
FCP
2
80
FCPP
1
40
FCPWM
2
-
FCPWMD
-
tCP
tCPP
CAN PLL jitter
(during lock)
tCPWM
-
-
200
CPU clock
Peripheral bus
clock
PWM clock
PWM division
clock
200
2
50
Comparator clock
12.5
500
25
1000
CPU clock
Peripheral bus
clock
PWM clock
PWM division
clock
Comparator clock
FCP=80MHz
(4MHzMultipli
ed by 20)
5
-
500
5
500
tCCMP
20
500
-
MHz
Remarks
2
tCPWMD
tPJ
Unit
Min
FCCMP
Internal operating
clock cycle time *1
Value
-10
-
10
ns
ns
Built-in CR
FCCR
50
100
150
kHz
oscillation frequency
*1: The maximum / minimum value is defined when using the main clock and PLL clock.
 X0,X1 clock timing
tCYL
X0
58
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
 CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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D a t a S h e e t
・Guaranteed operation range
Internal operation clock frequency vs. Power supply voltage
MB91F552 recommended guaranteed
operation range
MB91F552 guaranteed operation
range
Power supply voltage V CC (V)
5.5
4.5
3.4
PLL
guaranteed operation
range
PLL guaranteed operation
range for PWM
4
2
80
200
Internal operation clock frequency FCP/FCPWM(MHz)
Note: The power supply voltage, which is the low-voltage detection setting voltage or lower, is in the
reset state.
・Example of oscillation circuit
X0
4MHz
C1=12pF
X1
R=330Ω
C2=12pF
Note: As to the product with its clock supervisor’s initial value is “ON”, when the oscillator is unable
to start within 20ms from the stop state the clock supervisor will detect the oscillation stop. As
a result, the CPU moves to the fail safe operation.
Design your print circuit board so that the oscillator can start oscillation within 20ms.
Moreover, it is recommended to be designed after the match evaluation of the circuit is
requested to the departure pendulum maker when the oscillation circuit is composed.
60
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MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(1-2)The using condition of PLL
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS =AVSS=0.0V)
Parameter
PLL Oscillation
stabilization waiting time
(LOCK UP time)
PLL input clock frequency
PLL multiplication rate
PLL Macro oscillation
clock frequency
Sym
bol
Con
ditio
ns
Min
Typ
Max
tLOCK
-
-
-
fPLLI
-
4
-
Unit
Remarks
100
µs
Time until the
oscillation of PLL is
stabilized
-
16
13
-
100
MHz
multiplic
ation
200
-
400
fPLLO
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
Value
MHz
61
D a t a S h e e t
AC characteristics are specified by the following measurement reference voltage values.
・Input
Signal Waveform
Hysteresis Input Pin (Automotive)
・Output
Signal Waveform
Output Pin
0.8Vcc
2.4V
0.5Vcc
0.8V
Hysteresis Input Pin (CMOS schmitt)
0.7Vcc
0.3Vcc
62
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MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(2) Reset Input
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Value
Symb Pin Condi
ol
name tions
Parameter
tRSTL
RSTX
-
Remarks
Max
10
-
µs
When normal
operation
-
µs
At Stop mode
Oscillation time of
oscillator*
+100
100
Reset input time
Unit
Min
µs At Watch mode
Width for reset input
1
µs
removal
*: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred μs and several ms.
tRSTL
RSTX
0.2 vcc
 At Stop mode
0.2 vcc
tRSTL
RSTX
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation clock
100 μs
Oscillation time
of oscillator
Internal reset
April 25, 2014, MB91F552_DS705-00015-1v0-E
CONFIDENTIAL
Oscillation stabilization
waiting time
Instruction
execution
63
D a t a S h e e t
(3) Power-on Conditions
(TA:-40°C to +125°C, VSS=0.0V)
Parameter
Symbol
Pin
name
Conditions
Value
Min
Typ
Max
Unit
Remarks
Level detection
VCC
2.1
2.3
2.5
V
voltage
Level detection
VCC
100
mV
hysteresis width
Level detection
30
µs
*1
time
Slope detection
VCC = at level
undetected
VCC
detection release
4
mV/µs *2
standard
level time
Power off time
tOFF
VCC
50
ms
*3
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope
detection. This is the standard when the power supply fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss.
64
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MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=0, SCR: SPI=0
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ →
SOT delay time
tSLOVI
Valid SIN →
SCK ↑ setup time
tIVSHI
SCK ↑ →
Valid SIN hold time
Con
ditio
ns
Value
Unit
Min
Max
SCK0 to SCK2
4tCPP
-
ns
SCK0 to SCK2
SOT0 to SOT2
-30
30
ns
34
-
ns
tSHIXI
0
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
Serial clock
"L" pulse width
tSLSH
2tCPP-1
0
-
ns
SCK ↓ →
SOT delay time
tSLOVE
-
33
ns
Valid SIN →
SCK ↑ setup time
tIVSHE
10
-
ns
SCK ↑ →
Valid SIN hold time
tSHIXE
20
-
ns
-
Remarks
Internal shift clock
mode output pin :
CL=50pF
SCK0 to SCK2
SIN0 to SIN2
SCK0 to SCK2
SCK0 to SCK2
SOT0 to SOT2
SCK0 to SCK2
SIN0 to SIN2
SCK fall time
tF
SCK0 to SCK2
-
5
ns
SCK rise time
tR
SCK0 to SCK2
-
5
ns
External shift clock
mode output pin:
CL=50pF
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters.
See Hardware Manual for details.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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65
D a t a S h e e t
 Internal shift clock mode
tSCYC
2.4V
SCKx
0.8V
0.8V
tSLOVI
2.4V
SOTx
0.8V
tIVSHI
SINx
tSHIXI
VIH1
VIH1
VIL1
VIL1
 External shift clock mode
tSLSH
SCKx
VIH1
VIH1
VIL1
tF
SOTx
tSHSL
VIL1
tSLOVE
tR
2.4V
0.8V
tIVSHE
SINx
66
CONFIDENTIAL
tSHIXE
VIH1
VIH1
VIL1
VIL1
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4-1-2) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=1, SCR: SPI=0
(TA:-40°C to 125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
Pin name
Serial clock cycle time
tSCYC
SCK ↑ →
SOT delay time
tSHOVI
Valid SIN →
SCK ↓ setup time
tIVSLI
SCK ↓ →
Valid SIN hold time
tSLIXI
Serial clock
"H"pulse width
tSHSL
Con
ditio
ns
Value
Min
Max
Uni
t
SCK0 to SCK2
4tCPP
-
ns
SCK0 to SCK2
SOT0 to SOT2
-30
30
ns
34
-
ns
0
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
33
ns
10
-
ns
20
-
ns
-
Remarks
Internal shift clock
mode output pin :
CL=50pF
SCK0 to SCK2
SIN0 to SIN2
SCK0 to SCK2
Serial clock
"L" pulse width
tSLSH
SCK ↑ →
SOT delay time
tSHOVE
Valid SIN →
SCK ↓ setup time
tIVSLE
SCK ↓ →
Valid SIN hold time
tSLIXE
SCK0 to SCK2
SOT0 to SOT2
SCK0 to SCK2
SIN0 to SIN2
SCK fall time
tF
SCK0 to SCK2
-
5
ns
SCK rise time
tR
SCK0 to SCK2
-
5
ns
External shift clock
mode output pin:
CL=50pF
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters.
See Hardware Manual for details.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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67
D a t a S h e e t
 Internal shift clock mode
tSCYC
2.4V
SCKx
2.4V
0.8V
tSHOVI
2.4V
SOTx
0.8V
tIVSLI
SINx
tSLIXI
VIH1
VIH1
VIL1
VIL1
 External shift clock mode
tSHSL
SCKx
VIH1
VIH1
VIL1
tR
SOTx
tSLSH
VIL1
tSHOVE
tF
2.4V
0.8V
tIVSLE
SINx
68
CONFIDENTIAL
tSLIXE
VIH1
VIH1
VIL1
VIL1
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4-1-3) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=0, SCR: SPI=1
(TA:-40°C +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
Pin name
Serial clock cycle time
tSCYC
SCK ↑ →
SOT delay time
tSHOVI
Valid SIN →
SCK ↓ setup time
tIVSLI
SCK ↓ →
Valid SIN hold time
tSLIXI
SOT→SCK↓
delay time
tSOVLI
Serial clock
"H"pulse width
tSHSL
Con
ditio
ns
Value
Unit
Min
Max
SCK0 to SCK2
4tCPP
-
ns
SCK0 to SCK2
SOT0 to SOT2
-30
30
ns
34
-
ns
0
-
ns
2tCPP-3
0
-
ns
tCPP+10
-
ns
2tCPP-1
0
-
ns
-
33
ns
10
-
ns
20
-
ns
SCK0 to SCK2
SIN0 to SIN2
SCK0 to SCK2
SOT0 to SOT2
Remarks
Internal shift clock
mode output pin :
CL=50pF
SCK0 to SCK2
Serial clock
"L" pulse width
tSLSH
SCK ↑ →
SOT delay time
tSHOVE
Valid SIN →
SCK ↓ setup time
tIVSHE
SCK ↓ →
Valid SIN hold time
tSLIXE
SCK0 to SCK2
SOT0 to SOT2
SCK0 to SCK2
SIN0 to SIN2
-
SCK fall time
tF
SCK0 to SCK2
-
5
ns
SCK rise time
tR
SCK0 to SCK2
-
5
ns
External shift clock
mode output pin:
CL=50pF
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters.
See Hardware Manual for details.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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69
D a t a S h e e t
 Internal shift clock mode
tSCYC
2.4V
SCKx
tSHOVI
0.8V
0.8V
tSOVLI
SOTx
2.4V
2.4V
0.8V
0.8V
tIVSLI
SINx
tSLIXI
VIH
VIH
VIL
VIL
 External shift clock mode
tSLSH
VIH
SCKx
VIH
VIL
VIL
tR
tSHOVE
2.4V
2.4V
0.8V
0.8V
IVSLE
ttIVSHE
SINx
VIH
VIL
tF
*
SOTx
tSHSL
tSLIXE
VIH
VIH
VIL
VIL
*: It writes in the TDR register and, then, it changes.
70
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4-1-4) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=1, SCR: SPI=1
(TA:-40°C + 125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
Pin name
Serial clock cycle time
tSCYC
SCK↓→
SOT delay time
tSLOVI
Valid SIN →
SCK↑setup time
tIVSHI
SCK↑→
Valid SIN hold time
tSHIXI
SOT→SCK↑
delay time
tSOVHI
Serial clock
"H"pulse width
tSHSL
Con
ditio
ns
Value
Unit
Min
Max
SCK0 to SCK2
4tCPP
-
ns
SCK0 to SCK2
SOT0 to SOT2
-30
30
ns
34
-
ns
0
-
ns
2tCPP-3
0
-
ns
tCPP+10
-
ns
2tCPP-1
0
-
ns
-
33
ns
10
-
ns
20
-
ns
SCK0 to SCK2
SIN0 to SIN2
SCK0 to SCK2
SOT0 to SOT2
Remarks
Internal shift clock
mode output pin :
CL=50pF
SCK0 to SCK2
Serial clock
"L" pulse width
tSLSH
SCK↓→
SOT delay time
tSLOVE
Valid SIN →
SCK↑setup time
tIVSHE
SCK↑→
Valid SIN hold time
tSHIXE
SCK0 to SCK2
SOT0 to SOT2
SCK0 to SCK2
SIN0 to SIN2
-
SCK fall time
tF
SCK0 to SCK2
-
5
ns
SCK rise time
tR
SCK0 to SCK2
-
5
ns
External shift clock
mode output pin:
CL=50pF
Notes:
· AC characteristic in CLK synchronized mode.
· CL is the load capacitance applied to pins during testing.
· The maximum bard rate is limited by internal operation clock used and other parameters.
See Hardware Manual for details.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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71
D a t a S h e e t
 Internal shift clock mode
tSCYC
2.4V
SCKx
2.4V
0.8V
tSOVHI
SOTx
tSLOVI
2.4V
2.4V
0.8V
0.8V
tIVSHI
SINx
tSHIXI
VIH
VIH
VIL
VIL
 External shift clock mode
tSHSL
tSLSH
tR
VIH
SCKx
VIH
VIL
VIL
tSLOVE
2.4V
2.4V
0.8V
0.8V
tIVSHE
SINx
VIH
VIL
*
SOTx
tF
tF
tSHIXE
VIH
VIH
VIL
VIL
*: It writes in the TDR register and, then, it changes.
72
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4-1-5) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "H" : SMR, SCSFR:SCINV=0,
Serial chip select Inactive level "H" : SCSCR, SCSFR:CSLVL=1
(TA:-40°C to + 125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
SCS↓→SCK↓
setup time
tCSSI
SCK↑→SCS↑
hold time
tCSHI
SCS
deselect time
tCSDI
SCS↓→SCK↓
setup time
tCSSE
SCK↑→SCS↑
hold time
tCSHE
SCS
deselect time
tCSDE
SCS↓→SOT
delay time
tDSE
SCS↑→SOT
delay time
tDEE
SCK↓→SCS↓
clock switch time
tSCC
Pin name
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
Con
ditio
ns
-
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
Value
Min
Max
tCSSU+0
tCSSU+50
*1
*1
tCSHD-50
*2
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21,
SOT0 to SOT2
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
ns
tCSDS+50
*3
*3
ns
-
ns
-
ns
3tCPP+30
-
*2
-
ns
-
40
ns
+0
-
ns
3tCPP+30
Remarks
ns
tCSDS-50
+0
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
tCSHD+0
Unit
Internal shift
clock mode
output pin :
CL=50pF
External shift
clock mode
output pin:
CL=50pF
Internal shift
clock mode
-
3tCPP+0
3tCPP+50
ns
Round operation
output pin:
CL=50pF
*1: tCSSU =SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1, *2, and *3.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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73
D a t a S h e e t
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
When Serial chip select is used, Serial clock output mark level "H",
Serial chip select Inactive level "H"
Internal shift clock mode
SCS input
tCSDE
tCSHE
tCSSE
SCK input
tDEE
SOT
(Normal
Sync transfer)
tDSE
SOT
(SPI compatible)
When Serial chip select is used, Serial clock output mark level "H",
Serial chip select Inactive level "H"
External shift clock mode
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used, Serial clock output mark level "H",
Serial chip select Inactive level "H"
Internal shift clock mode, Example of switching clock by round operation (x,y=0, 1, 2, 3)
74
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4-1-6) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "L" : SMR, SCSFR:SCINV=1,
Serial chip select Inactive level "H" : SCSCR, SCSFR:CSLVL=1
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
SCS↓→SCK↑
setup time
tCSSI
SCK↓→SCS↑
hold time
tCSHI
SCS
deselect time
tCSDI
SCS↓→SCK↑
setup time
tCSSE
SCK↓→SCS↑
hold time
tCSHE
SCS
deselect time
tCSDE
SCS↓→SOT
delay time
tDSE
SCS↑→SOT
delay time
tDEE
SCK↑→SCS↓
clock switch time
tSCC
Pin name
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
Con
ditio
ns
-
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
Value
Min
Max
tCSSU+0
tCSSU+50
*1
*1
tCSHD-50
*2
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21,
SOT0 to SOT2
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
ns
tCSDS+50
*3
*3
ns
-
ns
-
ns
3tCPP+30
-
*2
-
ns
-
40
ns
+0
-
ns
3tCPP+30
Remarks
ns
tCSDS-50
+0
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
tCSHD+0
Unit
Internal shift
clock mode
output pin :
CL=50pF
External shift
clock mode
output pin:
CL=50pF
Internal shift
clock mode
-
3tCPP+0
3tCPP+50
ns
Round operation
output pin:
CL=50pF
*1: tCSSU =SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1, *2, and *3
April 25, 2014, MB91F552_DS705-00015-1v0-E
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75
D a t a S h e e t
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
When Serial chip select is used, Serial clock output mark level "L",
Serial chip select Inactive level "H"
Internal shift clock mode
SCS input
tCSDE
tCSHE
tCSSE
SCK input
tDEE
SOT
(Normal
Sync transfer)
tDSE
SOT
(SPI compatible)
When Serial chip select is used, Serial clock output mark level "L",
Serial chip select Inactive level "H"
External shift clock mode
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used, Serial clock output mark level "L",
Serial chip select Inactive level "H"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
76
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4-1-7) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "H" : SMR, SCSFR:SCINV=0,
Serial chip select Inactive level "L" : SCSCR, SCSFR:CSLVL=0
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
SCS↑→SCK↓
setup time
tCSSI
SCK↑→SCS↓
hold time
tCSHI
SCS
deselect time
tCSDI
SCS↑→SCK↓
setup time
tCSSE
SCK↑→SCS↓
hold time
tCSHE
SCS
deselect time
tCSDE
SCS↑→SOT
delay time
tDSE
SCS↓→SOT
delay time
tDEE
SCK↓→SCS↑
clock switch time
tSCC
Pin name
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
Con
ditio
ns
-
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
Value
Min
Max
tCSSU+0
tCSSU+50
*1
*1
tCSHD-50
*2
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21,
SOT0 to SOT2
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
ns
tCSDS+50
*3
*3
ns
-
ns
-
ns
3tCPP+30
-
*2
-
ns
-
40
ns
+0
-
ns
3tCPP+30
Remarks
ns
tCSDS-50
+0
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
tCSHD+0
Unit
Internal shift
clock mode
output pin :
CL=50pF
External shift
clock mode
output pin:
CL=50pF
Internal shift
clock mode
-
3tCPP+0
3tCPP+50
ns
Round operation
output pin:
CL=50pF
*1: tCSSU =SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1, *2, and *3.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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77
D a t a S h e e t
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
Internal shift clock mode
tCSDE
SCS input
tCSHE
tCSSE
SCK input
tDEE
SOT
(Normal
Sync transfer)
tDSE
SOT
(SPI compatible)
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
External shift clock mode
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
Internal shift clock mode , Example of switching clock by round operation (x, y=0, 1, 2, 3)
78
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4-1-8) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used: SCSCR: CSEN=1,
Serial clock output mark level "L" : SMR, SCSFR:SCINV=1,
Serial chip select Inactive level "L" : SCSCR, SCSFR:CSLVL=0
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
SCS↑→SCK↑
setup time
tCSSI
SCK↓→SCS↓
hold time
tCSHI
SCS
deselect time
tCSDI
SCS↑→SCK↑
setup time
tCSSE
SCK↓→SCS↓
hold time
tCSHE
SCS
deselect time
tCSDE
SCS↑→SOT
delay time
tDSE
SCS↓→SOT
delay time
tDEE
SCK↑→SCS↑
clock switch time
tSCC
Pin name
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
Con
ditio
ns
-
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
Value
Min
Max
tCSSU+0
tCSSU+50
*1
*1
tCSHD-50
*2
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21,
SOT0 to SOT2
SCK0 to SCK2,
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
ns
tCSDS+50
*3
*3
ns
-
ns
-
ns
3tCPP+30
-
*2
-
ns
-
40
ns
+0
-
ns
3tCPP+30
Remarks
ns
tCSDS-50
+0
SCS00, SCS01,
SCS10, SCS11,
SCS20, SCS21
tCSHD+0
Unit
Internal shift
clock mode
output pin :
CL=50pF
External shift
clock mode
output pin:
CL=50pF
Internal shift
clock mode
-
3tCPP+0
3tCPP+50
ns
Round operation
output pin:
CL=50pF
*1: tCSSU =SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1, *2, and *3.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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D a t a S h e e t
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Master mode
tCSDE
SCS input
tCSHE
tCSSE
SCK input
tDEE
SOT
(Normal
Sync transfer)
tDSE
SOT
(SPI compatible)
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Slave mode
SCSx output
tSCC
SCSy output
SCK output
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Master mode, Example of switching clock by round operation (x, y=0, 1, 2, 3)
80
CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(4-2) UART (Asynchronous serial interface) timing
Bit setting: SMR : MD2=0, SMR:MD1=0, SMR : MD0=0
Bit setting: SMR : MD2=0, SMR:MD1=0, SMR : MD0=1
When external clock is selected (BGR: EXT=1)
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
Pin name
Conditio
ns
Value
Unit
Min
Max
Serial clock
"L" pulse width
tSLSH
tCPP+10
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
-
SCK0 to SCK2
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
tR
output pin:
CL=50pF
tSLSH
VIH
VIH
SCK
tF
tSHSL
Remarks
VIH
VIL
VIL
VIL
When external clock is selected
(4-3) LIN Interface (v2.1) (Asynchronous Serial Interface for LIN (v2.1)) timing
Bit setting: SMR: MD2=0, SMR:MD1=1, SMR : MD0=1
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sym
bol
Pin name
Conditio
ns
Value
Unit
Min
Max
Serial clock
"L" pulse width
tSLSH
tCPP+10
-
ns
Serial clock
"H"pulse width
tSHSL
tCPP+10
-
ns
output pin:
-
SCK0 to SCK2
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
tR
VIH
SCK
VIL
tF
tSHSL
Remarks
CL=50pF
tSLSH
VIH
VIH
VIL
VIL
When external clock is selected
April 25, 2014, MB91F552_DS705-00015-1v0-E
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D a t a S h e e t
(5) Timer input timing
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Symbo
l
Parameter
tTIWH,
tTIWL
Input pulse width
Pin name
Value
Cond
itions
Min
Max
-
4tCPP
-
ns
-
4tCP*
-
ns
TIN0 to TIN4,
ICU,
FRCK,
TIOA0 to TIOA3,
TIOB0 to TIOB3,
PWC0, PWC1
Unit
Remarks
*: In the case of digital LPF of PWC with buffers is setting as through.
 Timer input timing
TINx,
ICU,
FRCK,
TIOAx,TIOBx,
PWCx
t TIWH
VIH
t TIWL
VIH
VIL
VIL
(6) Trigger input timing
(TA:-40°C + 125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbo
l
Input pulse width
Pin name
Conditi
ons
INT0 to INT3
-
Value
Unit
Min
Max
5tCPP
-
ns
1
-
µs
tTRGH,
tTRGL
ADTG0
-
5tCPP
-
ns
ADTG1
-
5tCP
-
ns
Remarks
At stop mode
 Trigger input timing
t TRGH
INTx
ADTGx
82
CONFIDENTIAL
VIH
t TRGL
VIH
VIL
VIL
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
(7) NMI input timing
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Input pulse width
tNMIL
Pin
name
Condition
s
NMIX
-
Value
Min
4tCPP
Max
-
Unit
Remarks
ns
 NMIX input timing
t NMIL
NMIX
VIH5
VIH5
VIL5
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VIL5
83
D a t a S h e e t
(8) PWM
(8-1)SYNCIN input timing
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Input pulse width
Value
Symbol
Pin name
Condi
tions
Min
Max
tSYNH,
tSYNL
SYNCIN
-
16 tCPWMD
-
Unit
ns
Remarks
*
・SYNCIN input timing
t SYNH
VIH
t SYNL
VIH
VIL
SYNCIN
VIL
*:In the case of digital LPF of SYNCIN pin is setting as through.
(8-2)PWM output
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Sy
mb
ol
Pin name
CMPn⇒
PWMnH/PWMnL
Delay time
tCPD
Min pulse width
tpw
Co
ndit
ion
s
Value
Unit
Remarks
Min
Max
CMP0 to CMP2
PWM0H to PWM2H
PWM0L to PWM2L
-
100
ns
n=0, 1, 2
*
PWM0H to PWM2H
PWM0L to PWM2L
40
-
ns
*
*In the case of PWM division clock is 200MHz
84
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MB91F552_DS705-00015-1v0-E, April 25, 2014
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(9) Low voltage detection (External low-voltage detection)
(TA:-40°C to +125°C, VSS=AVSS=0.0V)
Parameter
Power supply
voltage range
Symb
ol
Pin
name
VDP5
Detection voltage
VDL
Hysteresis width
VHYS
VCC
Con
ditio
ns
Min
Typ
Max
-
3.7
-
5.5
*1
Value
Unit
Remarks
V
-8%
3.9
+8%
V
-
0.1
-
V
-
When
power-supply
voltage falls
and detection
level is set
initially
When
power-supply
voltage rises
Low voltage
Td
30
µs
detection time
Power supply
VCC
-2
2
V/ms
*2
voltage regulation
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is a possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: Please suppress the change of the power supply within the range of the power-supply voltage regulation to
do a low-voltage detection by detecting voltage (VDL).
(10) Low voltage detection (Internal low-voltage detection)
(TA:-40°C to +125°C, VSS=AVSS=0.0V)
Parameter
Symb
ol
Pin
name
Con
ditio
ns
Min
Typ
Max
Value
Unit
Power supply
voltage range
VRDP5
-
0.6
-
1.4
V
Detection voltage
VRDL
*
0.8
0.9
1.0
V
Hysteresis width
VRHYS
-
0.1
-
V
-
-
Remarks
When
power-supply
voltage falls
When
power-supply
voltage rises
Low voltage
30
µs
detection time
*: If the fluctuation of the power supply is faster than the low-voltage detection time, there is a possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
April 25, 2014, MB91F552_DS705-00015-1v0-E
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85
D a t a S h e e t
5. A/D Converter
(1) 12-bit A/D Converter Electrical Characteristics
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Sym
bol
Pin name
Resolution
-
Total error
Parameter
Value
Unit
Remarks
Min
Typ
Max
-
-
-
12
bit
-
-
-
-
±6.0
LSB
Linearity error
-
-
-
-
±4.0
LSB
Differential linearity error
-
-
-
VOT
AN0 to AN7
Full-scale transition voltage
VFST
AN0 to AN7
Sampling time
tSMP
-
-
±1.9
AVRL+
0.5LSB
+8mV
AVRH1.5LSB
+8mV
-
LSB
Zero transition voltage
AVRL+
0.5LSB
-8mV
AVRH1.5LSB
-8mV
0.3
µs
*1*3
Compare time
tCMP
-
0.7
-
28
µs
*1
A/D conversion time
tCNV
-
1.0
-
-
µs
Analog port input current
IAIN
AN0 to AN7
-2.0
-
+2.0
µA
*1
VAVSS ≤
VAIN ≤ VAVCC
Analog input voltage
VAIN
AN0 to AN7
AVRL
-
AVRH
V
AVRH
AVRH0
4.5
-
5.5
V
AVRL
AVRL0
-
0.0
-
V
-
0.5
0.69
mA
-
-
6.1
µA
-
1
1.96
mA
-
-
4.0
µA
-
-
4
LSB
Reference voltage
IA
Power supply current
IAH
IR
IRH
Variation between channels
-
AVCC0
AVRH0
AN0 to AN7
-
-
V
V
1LSB=
(VFST-VOT)/
4094
*2
*2
*1: Time for each channel.
*2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped.
*3: external impedance is 500Ω or less.
86
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(2) 12-bit A/D Converter (4-channel simultaneous sampling) Electrical Characteristics
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Sym
bol
Pin name
Resolution
-
Total error
Parameter
Value
Unit
Remarks
Min
Typ
Max
-
-
-
12
bit
-
-
-
-
±6.0
LSB
Linearity error
-
-
-
-
±4.0
LSB
Differential linearity error
-
-
-
VOT
AN8 to
AN11
Full-scale transition voltage
VFST
AN8 to
AN11
Sampling time
tSMP
-
-
±1.9
AVRL+
0.5LSB
+8mV
AVRH1.5LSB
+8mV
-
LSB
Zero transition voltage
AVRL+
0.5LSB
-8mV
AVRH1.5LSB
-8mV
0.35
µs
*3
Compare time
tCMP
-
1.4
-
5.6
µs
*1
A/D conversion time
tCNV
1.75
-
-
µs
Analog port input current
IAIN
-1.0
-
+1.0
µA
*1
VAVSS ≤
VAIN ≤ VAVCC
Analog input voltage
VAIN
AVRL
-
AVRH
V
AVRH
AN8 to
AN11
AN8 to
AN11
AVRH1
4.5
-
5.5
V
AVRL
AVRL1
-
0.0
-
V
-
1.0
1.5
mA
-
0.1
20
µA
-
2
4
mA
-
0.1
10
µA
1
-
-
µF
10.9
-
-
ms
Reference voltage
IA
Power supply current
IAH
IR
IRH
Decoupling capacitance
Resumption Time
CREF
tRS
AVCC1
AVRH1
connected to
VR1
-
-
-
V
V
1LSB=
(VFST-VOT)/
4094
*2
*2
*4 *5
*1: Conversion time of 4-channel.
*2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped.
*3: external impedance is 500Ω or less.
*4: Calculate the minimum value by decoupling capacitance, the others parasitic capacitance value is defined as 0.
*5: Resumption time is defined by the capacitance of the decoupling capacitance which connected to the pin VR1.
Resumption Time=9*CREF*1.2k + 1µ[s]
CREF :VR Decoupling capacitance [µF]
April 25, 2014, MB91F552_DS705-00015-1v0-E
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87
D a t a S h e e t
Decoupling Capacitance
VR1 pin
Connection Example
CREF: Decoupling Capacitance
AVRL1 pin
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D a t a S h e e t
(3) Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Linearity error
: Deviation of the actual conversion characteristics from a straight line that
connects the zero transition point ("0000 0000 0000"← →"0000 0000 0001") to
the full-scale transition point ("1111 1111 1110"← →"1111 1111 1111").
Differential linearity
error
: Deviation of the input voltage from the ideal value that is required to change the
output code by LSB.
Total error
: Difference between the actual value and the theoretical value. The total error
includes zero transition error, full-scale transition error, and linearity error.
Total error
FFFH
FFEH
1.5 LSB
Actual conversion
characteristics
FFDH
Digital output
{1 LSB × (N - 1) + 0.5 LSB}
004H
VNT
003H
(Actual measurement value)
Actual conversion
characteristics
002H
Ideal
characteristics
001H
0.5 LSB
AVRL
Analog input
AVRH
VNT- {1LSB×(N-1)+ VOT LSB}
[LSB]
1LSB
AVRH-AVRL
1LSB (Ideal value)=
[V]
4096
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH – 1.5 LSB [V]
VNT : Digital output is the voltage which transitions from (N - 1) to N.
Total error of digital output N=
(Continue)
April 25, 2014, MB91F552_DS705-00015-1v0-E
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89
D a t a S h e e t
(Continuity)
Linearity error
FFFH
Actual conversion
FFEH
characteristics
Differential linearity error
Ideal characteristics
VFST
characteristics
(Actual
Measurement value)
V
NT
(Actual measurement value)
003H
Digital output
Digital output
{1 LSB (N - 1) + VOT}
FFDH
004H
Actual conversion
N+1
Actual conversion
characteristics
002H
N
V(N+1)T
(Actual measurement
V NT value)
(Actual measurement value)
Actual conversion
characteristics
N-1
Ideal characteristics
N-2
001H
VOT (Actual measurement value)
AVRL
Analog input
Linearity error of digital output N =
Analog input
AVRL
AVRH
VNT - {1LSB × (N - 1) + VOT}
1LSB
V(N + 1) T - VNT
Differential linearity error of digital output N =
AVRH
[LSB]
- 1 LSB
[LSB]
1LSB
1LSB =
VOT
VFST
VFST - VOT
4094
[V]
: Voltage at which the digital output changes from “000H” to “001H”.
: Voltage at which the digital output changes from “FFEH” to “FFFH”.
(4) Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
· When the external impedance is too high, the sampling period for analog voltages may not be
sufficient. In this case, it is recommended to connect the capacitor (approx. 0.1 μF) to the analog
input pin.
・ Analog input circuit model
R
Comparator
Analog input
C
During sampling: ON
R
C
2.0kΩ(Max)
11.65pF(Max)
5.0kΩ(Max)
11.0pF(Max)
Note: Listed values must be considered as reference values.
12bit A/D
12bit A/D(4-channel simultaneous sampling )
90
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(4.5V ≤ AVCC ≤ 5.5V)
(4.5V ≤ AVCC ≤ 5.5V)
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
6. Flash memory
(1) Electrical Characteristics
Parameter
Min
Value
Typ
Max
Unit
-
200
800
ms
-
300
1100
ms
-
400
2000
ms
-
700
3700
ms
8-bit writing time
-
9
288
µs
16-bit writing time
-
12
384
µs
ECC writing time
-
9
288
µs
Sector erase time
Remarks
8 Kbytes sector*1,
excluding internal
preprogramming time
8 Kbytes sector*1,
including internal
preprogramming time
64 Kbytes sector*1,
excluding internal
preprogramming time
64 Kbytes sector*1,
including internal
preprogramming time
Exclusive of overhead time at
system level*1
Exclusive of overhead time at
system level*1
Exclusive of overhead time at
system level*1
1,000
cycles/
20 years,
Temperature at writing/erasing
10,000
2
Erase cycle* /
Tj<+105°C,
cycles/
Data retain time
Average TA=+85°C*3
10 years,
100,000
cycles/
5 years
*1: The guaranteed value for erasure up to 100,000 cycles.
*2: Number of erase cycles for each sector.
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).
(2) Notes
While the Flash memory is written or erased, shutdown of the external power (Vcc) is prohibited.
In the application system where Vcc might be shut down while writing or erasing, be sure to turn the
power off by using an external voltage detection function.
To put it concretely, after the external power supply voltage falls below the detection
voltage (VDL*), hold Vcc at 2.7V or more within the duration calculated by the following expression:
Td*[µs] + (period of PCLK [µs] × 257) + 50 [µs]
*: See “4.AC Characteristics (9) Low-voltage detection (External low-voltage detection).”
April 25, 2014, MB91F552_DS705-00015-1v0-E
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D a t a S h e e t
7. D/A converter
(TA:-40°C to +125°C, VCC=5.0V±10%, AVcc2=5.0V±1.5%, VSS=AVSS=0.0V)
Value
Typ
Max
Symbol
Pin
name
Condition
Resolution
Linearity error
Differential
non-linearity
error
-
-
-
-4
-
10
4
Bit
LSB
-
-
-
-0.9
-
0.9
LSB
conversion time
IA
AVCC2
-
-
475
200
600
ns
µA
IAH
AVCC2
-
-
-
21
µA
Parameter
Power supply
current *2
Min
Unit
Remarks
COUT=5pF*1
Each channel
When powerdown
Each channel
*1: capacitance of internal node
*2: The power supply current described only current value on D/A converter.
The power supply current of AVCC2 = 3 unit × (the power supply current of D/A converter) + 3 unit × (the
power supply current of comparator) + (the power supply current of slope compensation).
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8. Comparator
(TA:-40°C to +125°C, VCC=5.0V±10%, AVcc2=5.0V±1.5%VSS=AVSS=0.0V)
Parameter
Input voltage
Compare time
Power down delay
time
Power supply
current *2
Value
Typ
Max
Symbol
Pin
name
Condition
-
-
-
0
-
-
AVcc2-1
tCCMP
V
ns
-
-
-
-
-
50
ns
IA
AVCC2
-
-
565
785
µA
IAH
AVCC2
-
-
0.2
2.5
µA
Min
Unit
Remarks
*1
Each channel
When
powerdown
Each channel
CMP0
CMP1
-12
12
mV
CMP2
*1: tCCMP is comparator clock cycle time.
*2: The power supply current described only current value on D/A converter.
The power supply current of AVCC2 = 3 unit × (the power supply current of D/A converter) + 3 unit × (the
power supply current of comparator) + the power supply current of slope compensation).
Input offset voltage
-
April 25, 2014, MB91F552_DS705-00015-1v0-E
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D a t a S h e e t
9. Slope compensation
(TA:-40°C to +125°C, VCC=5.0V±10%, AVCC2=5.0V±1.5%, VSS=AVSS2=0.0V)
Parameter
Slope voltage
Symbol
Pin name Condition
V
*2
0.5
-
2.0
V
CTSI base
2
-
10
µs
-
0.05
-
1.0
V/µs
*3
-10
-
+10
%
*4
-14
-
+14
%
(Vslope)*1
-
200
-
-
ns
-
-
-
-
-
10
µs
IA
AVCC2
-
-
500
20
900
µs
µA
IAH
AVCC2
-
-
0.01
33
µA
(Vslope)*1
Slope amount
dVslope/dt
(Vslope)*1
Slope output
resolution
-
(Vslope)*1
toff
Power supply
current *8
Remarks
AVcc2-1
T
OFF time
Switching
stability time of
slope amount
PD return time
Unit
-
(Vslope)*1
Operation cycle
Value
Typ
Max
0
Vslope
-
Min
*5
*6
When
power down
*7
Slope
CMP0
-3
+3
%
transmission error
ESD resistance
CMP0
700
800
900
Ω
SWS on
7
kΩ
resistance
SWE on
20
Ω
resistance
SWI on resistance
600
Ω
*1: (Vslope) is Voltage of internal node.
*2: Please do not let the total of external voltage input from slope voltage and CMP0 exceeds AVcc2-1[V].
Besides, if reference voltage of the comparator is AVcc2-1 [V] or less, we do not erroneously judged even if the
slope voltage is more than AVcc2-1 [V].
*3: 1.0V/µs ≥ dVslope/dt ≥ 0.1V/µs, 2.0V ≥ Vslope ≥ 0.5V, or voltage of internal node CTSI is defined as the
reference.
*4: 0.05V/µs ≤ dVslope/dt<0.1V/µs, 2.0V ≥Vslope ≥ 0.5V, or voltage of internal node CTSI is defined as the
reference.
*5: slope output resolution is the specification when calibration was performed. Calibration condition is
dVslope/dt=0.4V/µs.
*6: When SLPDADR register is switching
*7: Slope transmission error is the specification when calibration was performed. Calibration condition is
correction voltage is 3.0V, voltage lower limits is 1.0V.
*8: The power supply current described only current value on D/A converter.
The power supply current of AVCC2 = 3 unit × (the power supply current of D/A converter) + 3 unit × (the
power supply current of comparator) + (the power supply current of slope compensation).
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Slope compensation voltage addition circuit
AVCC2
(Current mirror)
＋
－
Voltage
current
conversion
circuit
R
(To comparator 0)
Vslope
SWI
C
Slope compensation
output
SWS
(External input)
CTSI
CMP0
SWE
AVSS2
Operation cycle T/Off time toff
SWI
SWS
SWE
CMP0
Vslope
T
toff
April 25, 2014, MB91F552_DS705-00015-1v0-E
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95
D a t a S h e e t
 EXAMPLE CHARACTERISTICS
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
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D a t a S h e e t
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97
D a t a S h e e t
 ORDERING INFORMATION
Part number
Package*
MB91F552PMC1-GTE1
LQFP・64 pin,
Plastic (FPT-64P-M24)
*: For details of the package, see " PACKAGE DIMENSIONS ".
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D a t a S h e e t
 PACKAGE DIMENSIONS
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
32
49
Details of "A" part
0.08(.003)
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
INDEX
64
0°~8°
17
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
16
0.50(.020)
0.20±0.05
(.008±.002)
C
0.08(.003) M
2005-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-c-1-3
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
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D a t a S h e e t
■Major Changes
Page
Revision 1.0
-
100
CONFIDENTIAL
Section
-
Change Results
Initial release
MB91F552_DS705-00015-1v0-E, April 25, 2014
D a t a S h e e t
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D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
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The contents of this document are subject to change without notice. This document may contain information on a
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Copyright © 2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States
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owners.
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CONFIDENTIAL
MB91F552_DS705-00015-1v0-E, April 25, 2014