The following document contains information on Cypress products. S6J3110 Series 32-bit Microcontroller Spansion® TraveoTM Family S6J311EJAA Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. Publication Number S6J311E_DS708-00002 CONFIDENTIAL Revision 0.1 Issue Date June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. 2 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 S6J3110 Series 32-bit Microcontroller Spansion® TraveoTM Family S6J311EJAA Data Sheet (Preliminary) 1. DESCRIPTION This section provides an overview of the S6J3110 series. ® The S6J3110 series is a set of 32-bit microcontrollers designed for in-vehicle use. It uses the ARM Cortex-R5 CPU as a CPU. Publication Number S6J311E_DS708-00002 CONFIDENTIAL Revision 0.1 Issue Date June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) Table of Contents 1. DESCRIPTION ..................................................................................................................................... 3 2. FEATURES .......................................................................................................................................... 5 2.1 Cortex-R5 Core ........................................................................................................................ 5 2.2 Peripheral Functions ................................................................................................................ 6 3. PRODUCT LINEUP ............................................................................................................................. 9 4. PIN ASSIGNMENT ............................................................................................................................ 11 5. PIN DESCRIPTION ............................................................................................................................ 12 6. I/O CIRCUIT TYPES .......................................................................................................................... 27 7. HANDLING PRECAUTIONS ............................................................................................................. 29 7.1 Precautions for Product Design.............................................................................................. 29 7.2 Precautions for Package Mounting ........................................................................................ 31 7.3 Precautions for Use Environment........................................................................................... 33 8. HANDLING DEVICES ........................................................................................................................ 34 9. BLOCK DIAGRAM ............................................................................................................................ 37 10. MEMORY MAP .................................................................................................................................. 38 11. PIN STATUSES IN CPU STATUS ..................................................................................................... 43 12. ELECTRICAL CHARACTERISTICS ................................................................................................. 46 12.1 Absolute Maximum Ratings.................................................................................................... 46 12.2 Recommended operating conditions ...................................................................................... 48 12.3 DC characteristics .................................................................................................................. 49 12.4 AC characteristics .................................................................................................................. 53 12.4.1 Source clock timing .................................................................................................... 53 12.4.2 Internal clock timing ................................................................................................... 54 12.4.3 Reset input ................................................................................................................. 57 12.4.4 Power-on and power-on conditions ............................................................................ 58 12.4.5 Multi-function serial .................................................................................................... 59 12.5 Timer input timing ................................................................................................................... 79 12.6 Trigger input timing ................................................................................................................ 80 12.7 NMI input timing ..................................................................................................................... 81 12.8 Low-voltage detection (external low-voltage detection).......................................................... 82 12.9 Low-voltage detection (internal low-voltage detection)........................................................... 83 12.10 Low-voltage detection (1.2 V power supply low-voltage detection) ........................................ 83 12.11 A/D converter ......................................................................................................................... 84 12.11.1 Electrical characteristics ................................................................................... 84 12.11.2 Notes on A/D converters .................................................................................. 85 12.11.3 Glossary ........................................................................................................... 86 12.12 Flash memory ........................................................................................................................ 88 13. ORDERING INFORMATION .............................................................................................................. 89 14. PART NUMBER OPTION .................................................................................................................. 89 15. PACKAGE DIMENSIONS .................................................................................................................. 90 16. MAJOR CHANGES IN THIS EDITION .............................................................................................. 91 4 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 2. FEATURES This section explains the features of the S6J3110 series. 2.1 Cortex-R5 Core This section explains the Cortex-R5 CPU core. − ARM® Cortex®-R5 − 32-bit ARM architecture − 2-instruction issuance super scalar − 8-stage pipeline − ARMv7/Thumb®-2 instruction set − MPU (memory protection) equipped − 16-area support − ECC support for the TCM ports 1-bit error correction and 2-bit error detection (SEC-DED) − TCM ports 2 TCM ports − ATCM port − BTCM port (B0TCM, B1TCM) − Caches − Instruction cache 16 KB − Data cache 16 KB − VIC port Low latency interrupt − AXI master interface 64-bit AXI interface (instruction/data access) 32-bit AXI interface (I/O access) − AXI slave interface 64-bit AXI interface (TCM port access) − ETM-R5 trace June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 5 D a t a S h e e t ( P r e l i m i n a r y ) 2.2 Peripheral Functions This section explains peripheral functions. − Clock generation − Main clock oscillation (4 MHz) − No sub clock oscillation − CR oscillation (100 kHz) − CR oscillation (4 MHz) − Built-in flash memory size − Program: 4096 K + 64 KB (S6J311EJAA) − Work: 112 KB (S6J311EJAA) − Built-in RAM size − TCRAM 64 KB − System SRAM 256 KB (S6J311EJAA) − Backup RAM 64 KB (S6J311EJAA) − General-purpose ports: 150 channels (S6J311EJAA) − DMA controller − Up to 16 channels can be activated simultaneously. − A/D converter (successive approximation type) − 12-bit resolution, 2 units mounted: Max 64 channels (32 channels + 32 channels) − External interrupt input: 16 channels − Level ("H"/"L") and edge (rising/falling) can be detected. − Multi-function serial (transmission and reception FIFOs mounted) :Max 22 channels <UART (asynchronous serial interface) > − Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO − Parity check can be enabled/disabled. − Built-in dedicated baud rate generator − An external clock can be used as a transfer clock. − Parity, frame, overrun error detection functions are available. − DMA transfer is supported (only for ch.0 to 7). <CSIO (synchronous serial interface) > − Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO − Support for SPI. Both master and slave roles are supported. Data length in bits can be set to a value from 5 to 16 or one of the values of 20, 24, and 32. − Built-in dedicated baud rate generator (master operation) − External clock input is enabled (slave operation). − Overrun error detection function is available. − DMA transfer is supported (only for ch.0 to ch.7). − Serial chip select SPI function <LIN-UART (asynchronous serial interface for LIN) > 6 CONFIDENTIAL − Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO − Support for LIN protocol revision 2.1 − Both master and slave roles are supported. − Framing error and overrun error detection S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) − LIN Synch break generation and detection, LIN Synch Delimiter generation − Built-in dedicated baud rate generator − The external clock can be adjusted by the reload counter. DMA transfer is supported (only for ch.0 to ch.7). − CAN controller: CAN-FD Max 2 channel − CAN transfer speed :1Mbps − CAN Clock :Max 40MHz − 192 message buffers/channel − Base timer: MAX 30 channels − 16bit Timer. − It is selectable by 4 functions of the PWM/PPG/PWC/Reload Timer. − 2-channel cascade connection enables operation as a 32-bit timer.(PWC and Reload Timer) − Free-run timer: Max 6 channels − 32bit Timer. − Main clock oscillation and CR oscillation are available. − Free-run timer output can work in combination with an input capture and an output compare. − Input capture: Max 12 channels − 32bit Timer. − Output compare: Max 12 channels − 32bit Timer. − Real time clock (RTC) (day/hour/minute/second) − Main clock oscillation or CR oscillation (100 kHz) can be selected as an operation clock. − Calibration: Real time clock (RTC) driven by the CR clock − Correction can be done by configuring the prescaler of the real time clock based on the ratio between the main clock and the CR clock. − Clock supervisor − Abnormality (such as damaged crystal) of the main clock oscillation (4 MHz) can be monitored. − The clock can switch to the CR clock when an abnormality is detected. − PLL abnormality can be detected. − CRC generation − Fixed-length CRC − CCITT CRC16 generator polynomial: 0x1021 − IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7 − Watchdog timer − Hardware watchdog − Software watchdog − NMI − I/O relocation − Peripheral function pin locations can be changed. − Low-power consumption control − Standby function − Power-off function − Partial wakeup function − Power-on reset − Low-voltage detection reset June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 7 D a t a S h e e t ( P r e l i m i n a r y ) − Security − Flash security − Interface security (JTAG + test port) − SHE − Unique device ID − Package: LEP176 (S6J311EJAA) − CMOS 55 nm technology − Power supply 8 CONFIDENTIAL − 5 V single power supply − The voltage step-down circuit generates internal 1.2 V from 5 V. − 5 V power supply is used for I/O. S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 3. PRODUCT LINEUP The following table lists the models available in the S6J3110 series. Table 3-1Comparison of models available S6J311EJAA CPU core Coretex-R5 CMOS 55 nm technology 55 nm Package LEP176 Main clock 4 MHz 100 kHz Built-in CR oscillator 4 MHz Maximum CPU operating frequency 144 MHz (target) 4096K bytes Flash Program Small sector (8 KB x 8) Work RAM + 112K bytes TCRAM 64K bytes System SRAM 256K bytes Backup RAM 64K bytes Watchdog timer 1 channel (hardware) 1 channel (software) Clock supervisor Available External power supply, low-voltage detection reset Available Internal power supply, low-voltage detection reset Available NMI request Available External interrupt 16 channels DMA controller 16 channels CAN-FD Multi-function serial 2 channels (192 msg buffers/ch) 22 channels 12-bit (2 units) A/D converter Unit 0 x 32 channels Unit 1 x 32 channels Free-run timer 6 channels Input capture 12 channels Output compare 12 channels Base timer (16-bit) 30 channels Real time clock (RTC) 1 channel CR clock calibration Available CRC generation Low-power consumption mode June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL Available Standby function Power-off function 9 D a t a S h e e t ( P r e l i m i n a r y ) S6J311EJAA Partial wakeup function SHE General-purpose port GPIO Available 150 channels Power supply 5 V + 5% to 10% Operation assurance temperature (Ta) -40 °C to +105 °C On-chip debugger (JTAG) 10 CONFIDENTIAL Available S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 4. PIN ASSIGNMENT The following figures show the pin assignment of the S6J3110 series. 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VCC P421/SIN2_1/SCS120_0/TRACECTL P420/SCK2_1/SCK12_0/TRACECLK P419/SCS23_0/SOT12_0/TIOA27_1 P418/SCS22_0/SIN12_0/INT14_0 P417/SOT7_1/SCS110_0/TIOA23_1/INT15_1 P416/IN5_0/SIN7_1/SCK11_0/TIOA22_1 P415/SOT11_0/TIOA26_1/INT13_0 P414/SCS21_0/SIN11_0 P413/SCS73_1/SCS20_0/INT14_1 P412/SCS72_1/TIOA25_1 P411/SCS71_1/SCK2_0/INT13_1/TRACEDATA7 P410/SCS70_1 P409/SOT2_0/TIOA24_1/TRACEDATA6 P408/SIN2_0/INT12_0/TRACEDATA5 P407/SCK7_1/SCK9_0/TRACEDATA4 P406/SOT9_0/TRACEDATA3 P405/IN4_0/SIN9_0/INT11_0/TRACEDATA2 P404/IN3_0/TRACEDATA1 P403/IN2_0/TRACEDATA0 P402/IN1_0/RX1_0/SCS63_1/SCS90_0/INT2_0 P401/IN0_0/TX1_0/SCS62_1 C VSS VCC RSTX P400/SCS61_1 P331/SCS60_1 VSS X1 X0 MD P330 P329/SIN6_1 P328/SOT6_1/SCS210_0 P327/SCK6_1/SCK21_0 P326/SOT21_0 P325/SIN21_0/INT10_0 TCK TMS TDI/P324 TDO/P323 TRST/P322 VCC Figure 4-1 Pin Assignment for S6J311EJAA VSS P000/SOT2_1 P001/SCS20_1 P002/SCS21_1/TIOA0_1 P003/SCS22_1 P004/SCS23_1/TIOA1_1 P005/IN6_0/SIN3_0 P006/IN7_0/SOT3_0 P007/IN8_0/SCK18_1/SCK3_0 P008/IN9_0/SCS180_1/SCS30_0/TIOA0_0 P009/IN10_0/SIN8_0/TIOA1_0/INT0_1 P010/IN11_0/SOT8_0/TIOA2_0 P011/SIN18_1/TIOA2_1 P012/OUT5_0/SCK8_0/TIOA3_0 P013/OUT6_0/SCS80_0/TIOA4_0 P014/SOT18_1/TIOA3_1 P015/OUT7_0/SCS81_0/TIOA5_0 P016/OUT8_0/SCS82_0/TIOA6_0 P017/OUT9_0/SCS83_0/TIOA7_0 P018/OUT10_0/TIOA8_0 P019/OUT11_0/TIOB0_0/TEXT0_0 P020/SOT0_0/TIOB1_0/TEXT1_0 P021/SCK4_1/SCK0_0/TIOB2_0 P022/SIN0_0/TIOB3_0/INT3_0 P023/SIN4_1/SCS0_0/TIOB4_0 P024/SOT4_1/TIOB5_0 P025/SCS40_1 P026/SCS41_1 P027/SCS42_1/TIOA4_1/TIOB6_0/INT1_1/TEXT0_1 P028/OUT0_1/SIN1_0/TIOB7_0/INT4_0 P029/OUT1_1/SOT1_0/AN0 P030/OUT2_1/SCS43_1 P031/OUT3_1/SCS1_0/AN1 P100/OUT4_1/SCK1_0/AN2 P101/OUT5_1/AN3 P102/AN4 P103/OUT6_1/SIN17_0/AN5 P104/SOT17_0 P105/OUT7_1/SCK17_0/TIOA9_0 P106/OUT8_1/TX1_2/SCS170_0 P107/OUT9_1/RX1_2/SIN19_0/TIOA10_0/INT2_1 P108/OUT10_1/SOT19_0/AN6/TIOA11_0/INT3_1 P109/OUT11_1/SIN19_1/SCK19_0/TIOA12_0 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 ● TOP VIEW LEP176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VSS P321 P320/PWUTRG P319/SIN7_0/AN63/INT12_1 P318/RX1_1/TIOA10_1/INT9_0 P317/TX1_1/AN62/TIOA9_1/INT11_1 P316/TIOA21_1 P315/IN5_1/SCS70_0/AN61/TIOA8_1 P314/IN4_1/SCK7_0/AN60/TIOA7_1 P313/IN3_1/SOT7_0/AN59/INT10_1 P312/IN2_1/SCS71_0/AN58 P311/SOT13_0 P310/SIN13_0/INT15_0 P309/IN1_1/SCS130_0/AN57/TIOA29_1 P308/IN0_1/SCK13_0/AN56/TIOA28_1 P307/RX0_0/SCS72_0/AN55/INT1_0 P306/TX0_0/SCS73_0/AN54 NMIX P305/SCS140_0/AN53/TIOA29_0/TEXT5_0 P304/SCK14_0/AN52/TIOA20_1/TEXT4_0 P303/SOT14_0 P302/SIN14_0/AN51/TIOA19_1 P301/OUT4_0/SCS100_0/AN50/TIOA18_1 P300/OUT3_0/SCS101_0/AN49/TIOA28_0 P231/OUT2_0/SCS102_0/AN48/TIOA27_0 P230/OUT1_0/PWU_AN7/SCS103_0/AN47/TIOA26_0 P229/OUT0_0/PWU_AN6/RX0_1/SIN10_0/AN46/TIOA25_0/INT8_0 P228/PWU_AN5/TX0_1/SOT10_0/AN45/TIOA24_0 P227/PWU_AN4/SCK10_0/AN44/TIOA23_0 AVCC1 AVRH1 AVSS1/AVRL1 P226/IN11_2/PWU_AN3/SCK5_0/AN43/TIOA17_1 P225/IN10_2/PWU_AN2/RX0_2/SOT5_0/AN42/INT0_0 P224/IN9_2/PWU_AN1/TX0_2/SCS50_0/AN41 P223/IN8_2/PWU_AN0/SCS51_0/AN40 P222/IN7_2/SIN5_0/AN39/INT7_0 P221/SCS52_0 P220/IN6_2/SCS53_0/AN38 P219/SCS150_0/AN37/TEXT3_0 P218/SCK15_0/AN36/TEXT2_0 P217/SOT15_0 P216/SIN15_0 VSS 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 VCC P215/IN5_2/SCK5_1/TIOA16_1/INT9_1 P214/IN4_2/SOT5_1/TIOA15_1 P213/IN3_2/SIN5_1/TIOA14_1/INT8_1 P212/IN2_2/SCS50_1/SCS41_0/AN35/TIOA13_1 P211/IN1_2/SCS40_0/AN34/TIOA22_0 P210/IN0_2/SIN4_0/AN33/TIOA21_0/INT6_0 P209/SOT4_0/AN32/TIOA20_0 P208/SCS42_0/AN31/TIOA19_0 P207/SCK4_0/AN30/INT7_1/TEXT5_1 P206/SCS43_0/AN29/TEXT4_1 P205/SCK20_0/AN28/TEXT3_1 P204/IN11_1/SOT20_0/AN27 P203/IN10_1 P202/IN9_1/SCK6_0/INT6_1 P201/SIN20_0/AN26/TIOA18_0 P200/SCS202_0/AN25/TIOA17_0 P131/IN8_1/SOT6_0/AN24 P130/IN7_1/SIN6_0/AN23/INT5_0 P129/IN6_1/SCS201_0/AN22 P128/SCS200_0/AN21/TEXT2_1 P127/SCS203_0/AN20/TEXT1_1 P126/SCK16_0/AN19 P125/SOT16_0/TIOA16_0 P124/SIN16_0/TIOA15_0 P123/SCS63_0/AN18/TIOA12_1 P122/SCS62_0/AN17/TIOA11_1 P121/SCS160_0/AN16/TIOA14_0 P120/SCS61_0/AN15 P119/SCS60_0/AN14 P118/AN13/INT5_1 P117/AN12/INT4_1 P116/AN11 P115 AVSS0/AVRL0 AVRH0 AVCC0 P114/SCS180_0/AN10/TIOA6_1 P113/SOT19_1/SCK18_0/TIOA5_1 P112/SOT18_0/AN9/TIOA13_0 P111/SIN18_0/AN8 P110/SCS190_0/AN7 C VSS June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 11 D a t a S h e e t ( P r e l i m i n a r y ) 5. PIN DESCRIPTION This section provides a list of the pin functions of the S6J3110 series Table 5-1 S6J311EJAA Pin Functions I/O Pin No. Pin Name S6J311EJAA 2 3 Polarity Circuit Type P000 SOT2_1 P001 SCS20_1 - A - A - A P002 4 SCS21_1 P003 SCS22_1 7 8 9 SCS23_1 - A 12 13 CONFIDENTIAL General-purpose I/O port Serial chip select 2-2 output pin (1) - A Serial chip select 2-3 output pin (1) Base timer ch.1 TIOA output pin (1) P005 General-purpose I/O port IN6_0 - A Input capture ch.6 input pin (0) SIN3_0 Multi-function serial ch.3 serial data input pin (0) P006 General-purpose I/O port IN7_0 - A Input capture ch.7 input pin (0) SOT3_0 Multi-function serial ch.3 serial data output pin (0) P007 General-purpose I/O port IN8_0 SCK18_1 - A Input capture ch.8 input pin (0) Multi-function serial ch.18 clock I/O pin (1) Multi-function serial ch.3 clock I/O pin (0) P008 General-purpose I/O port IN9_0 Input capture ch.9 input pin (0) SCS180_1 - A Serial chip select 18-0 I/O pin (1) SCS30_0 Serial chip select 3-0 I/O pin (0) TIOA0_0 Base timer ch.0 TIOA output pin (0) P009 General-purpose I/O port SIN8_0 Input capture ch.10 input pin (0) - A Multi-function serial ch.8 serial data input pin (0) TIOA1_0 Base timer ch.1 TIOA I/O pin (0) INT0_1 INT0 external interrupt input pin (1) P010 General-purpose I/O port IN11_0 SOT8_0 - A Input capture ch.11 input pin (0) Multi-function serial ch.8 serial data output pin (0) TIOA2_0 Base timer ch.2 TIOA output pin (0) P011 General-purpose I/O port SIN18_1 TIOA2_1 12 Serial chip select 2-1 output pin (1) TIOA1_1 IN10_0 11 Serial chip select 2-0 I/O pin (1) General-purpose I/O port SCK3_0 10 General-purpose I/O port Base timer ch.0 TIOA output pin (1) P004 6 General-purpose I/O port Multi-function serial ch.2 serial data output pin (1) General-purpose I/O port TIOA0_1 5 Functions - A Multi-function serial ch.18 serial data input pin (1) Base timer ch.2 TIOA output pin (1) S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P012 14 SCK8_0 TIOA3_0 General-purpose I/O port - A OUT5_0 15 16 18 P013 General-purpose I/O port SCS80_0 Serial chip select 8-0 I/O pin (0) TIOA4_0 - A Output compare ch.6 output pin (0) P014 General-purpose I/O port SOT18_1 - A P015 General-purpose I/O port SCS81_0 Serial chip select 8-1 output pin (0) TIOA5_0 - A Output compare ch.7 output pin (0) P016 General-purpose I/O port SCS82_0 TIOA6_0 - A 23 General-purpose I/O port SCS83_0 Serial chip select 8-3 output pin (0) TIOA7_0 TIOA8_0 - A Base timer ch.7 TIOA I/O pin (0) Output compare ch.9 output pin (0) General-purpose I/O port - A Base timer ch.8 TIOA output pin (0) Output compare ch.10 output pin (0) P019 General-purpose I/O port OUT11_0 Output compare ch.11 output pin (0) TIOB0_0 - A Base timer ch.0 TIOB input pin (0) TEXT0_0 Free-run timer 0 clock input pin (0) P020 General-purpose I/O port SOT0_0 TIOB1_0 - A Multi-function serial ch.0 serial data output pin (0) Base timer ch.1 TIOB input pin (0) TEXT1_0 Free-run timer 1 clock input pin (0) P021 General-purpose I/O port SCK4_1 TIOB2_0 - A Multi-function serial ch.4 clock I/O pin (1) Base timer ch.2 TIOB input pin (0) Multi-function serial ch.0 clock I/O pin (0) P022 General-purpose I/O port SIN0_0 Multi-function serial ch.0 serial data input pin (0) TIOB3_0 INT3_0 June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL Base timer ch.6 TIOA output pin (0) P017 SCK0_0 24 Serial chip select 8-2 output pin (0) Output compare ch.8 output pin (0) OUT10_0 22 Base timer ch.5 TIOA I/O pin (0) OUT7_0 P018 21 Multi-function serial ch.18 serial data output pin (1) Base timer ch.3 TIOA output pin (1) OUT9_0 20 Base timer ch.4 TIOA output pin (0) OUT6_0 OUT8_0 19 Multi-function serial ch.8 clock I/O pin (0) Base timer ch.3 TIOA I/O pin (0) Output compare ch.5 output pin (0) TIOA3_1 17 Functions Type - A Base timer ch.3 TIOB input pin (0) INT3 external interrupt input pin (0) 13 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P023 25 SIN4_1 SCS0_0 General-purpose I/O port - A TIOB4_0 SOT4_1 General-purpose I/O port - A TIOB5_0 27 28 29 30 31 P025 SCS40_1 P026 SCS41_1 - A - A 35 14 CONFIDENTIAL Serial chip select 4-1 output pin (1) General-purpose I/O port Serial chip select 4-2 output pin (1) TIOA4_1 TIOB6_0 - A Base timer ch.4 TIOA output pin (1) Base timer ch.6 TIOB input pin (0) INT1_1 INT1 external interrupt input pin (1) TEXT0_1 Free-run timer 0 clock input pin (1) P028 General-purpose I/O port SIN1_0 Multi-function serial ch.1 serial data input pin (0) TIOB7_0 - A Base timer ch.7 TIOB input pin (0) INT4_0 INT4 external interrupt input pin (0) OUT0_1 Output compare ch.0 output pin (1) P029 General-purpose I/O port SOT1_0 AN0 - A SCS43_1 Multi-function serial ch.1 serial data output pin (0) ADC analog 0 input pin Output compare ch.1 output pin (1) General-purpose I/O port - A Serial chip select 4-3 output pin (1) Output compare ch.2 output pin (1) P031 General-purpose I/O port SCS1_0 Serial chip select 1 I/O pin (0) AN1 - A ADC analog 1 input pin OUT3_1 Output compare ch.3 output pin (1) P100 General-purpose I/O port SCK1_0 AN2 - A Multi-function serial ch.1 clock I/O pin (0) ADC analog 2 input pin OUT4_1 Output compare ch.4 output pin (1) P101 General-purpose I/O port AN3 - A OUT5_1 36 General-purpose I/O port SCS42_1 OUT2_1 34 General-purpose I/O port Serial chip select 4-0 I/O pin (1) P027 P030 33 Multi-function serial ch.4 serial data output pin (1) Base timer ch.5 TIOB input pin (0) OUT1_1 32 Multi-function serial ch.4 serial data input pin (1) Serial chip select 0 I/O pin (0) Base timer ch.4 TIOB input pin (0) P024 26 Functions Type P102 AN4 ADC analog 3 input pin Output compare ch.5 output pin (1) - A General-purpose I/O port ADC analog 4 input pin S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P103 37 SIN17_0 AN5 General-purpose I/O port - A OUT6_1 38 P104 SOT17_0 40 SCK17_0 TIOA9_0 - A 42 43 - A Output compare ch.7 output pin (1) P106 General-purpose I/O port TX1_2 SCS170_0 - A General-purpose I/O port RX1_2 CAN reception data 1 input pin (2) SIN19_0 TIOA10_0 - A Multi-function serial ch.19 serial data input pin (0) Base timer ch.10 TIOA output pin (0) INT2_1 INT2 external interrupt input pin (1) OUT9_1 Output compare ch.9 output pin (1) P108 General-purpose I/O port SOT19_0 Multi-function serial ch.19 serial data output pin (0) AN6 TIOA11_0 - A ADC analog 6 input pin Base timer ch.11 TIOA output pin (0) INT3_1 INT3 external interrupt input pin (1) OUT10_1 Output compare ch.10 output pin (1) P109 General-purpose I/O port SIN19_1 Multi-function serial ch.19 serial data input pin (1) SCK19_0 - A Multi-function serial ch.19 clock I/O pin (0) TIOA12_0 Base timer ch.12 TIOA output pin (0) OUT11_1 Output compare ch.11 output pin (1) SCS190_0 General-purpose I/O port - A SIN18_0 Serial chip select 19-0 I/O pin (0) ADC analog 7 input pin General-purpose I/O port - A AN8 Multi-function serial ch.18 serial data input pin (0) ADC analog 8 input pin P112 General-purpose I/O port SOT18_0 Multi-function serial ch.18 serial data output pin (0) AN9 TIOA13_0 June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL Serial chip select 17-0 I/O pin (0) P107 P111 49 CAN transmission data 1 output pin (2) Output compare ch.8 output pin (1) AN7 48 Multi-function serial ch.17 clock I/O pin (0) Base timer ch.9 TIOA output pin (0) OUT7_1 P110 47 General-purpose I/O port Multi-function serial ch.17 serial data output pin (0) General-purpose I/O port OUT8_1 41 Multi-function serial ch.17 serial data input pin (0) ADC analog 5 input pin Output compare ch.6 output pin (1) P105 39 Functions Type - A ADC analog 9 input pin Base timer ch.13 TIOA output pin (0) 15 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P113 50 SOT19_1 SCK18_0 General-purpose I/O port - A TIOA5_1 51 56 P114 General-purpose I/O port SCS180_0 Serial chip select 18-0 I/O pin (0) AN10 - A P115 P116 AN11 58 59 60 61 62 AN12 - A - A 64 65 66 CONFIDENTIAL General-purpose I/O port ADC analog 11 input pin - A ADC analog 12 input pin INT4_1 INT4 external interrupt input pin (1) P118 General-purpose I/O port AN13 - A ADC analog 13 input pin INT5_1 INT5 external interrupt input pin (1) P119 General-purpose I/O port SCS60_0 - A Serial chip select 6-0 I/O pin (0) AN14 ADC analog 14 input pin P120 General-purpose I/O port SCS61_0 - A Serial chip select 6-1 output pin (0) AN15 ADC analog 15 input pin P121 General-purpose I/O port SCS160_0 AN16 - A Serial chip select 16-0 I/O pin (0) ADC analog 16 input pin TIOA14_0 Base timer ch.14 TIOA output pin (0) P122 General-purpose I/O port SCS62_0 AN17 - A Serial chip select 6-2 output pin (0) ADC analog 17 input pin Base timer ch.11 TIOA output pin (1) P123 General-purpose I/O port SCS63_0 Serial chip select 6-3 output pin (0) AN18 - A ADC analog 18 input pin TIOA12_1 Base timer ch.12 TIOA output pin (1) P124 General-purpose I/O port SIN16_0 - A Multi-function serial ch.16 serial data input pin (0) TIOA15_0 Base timer ch.15 TIOA output pin (0) P125 General-purpose I/O port SOT16_0 - A Multi-function serial ch.16 serial data output pin (0) TIOA16_0 Base timer ch.16 TIOA output pin (0) P126 General-purpose I/O port SCK16_0 AN19 16 General-purpose I/O port General-purpose I/O port TIOA11_1 63 ADC analog 10 input pin Base timer ch.6 TIOA output pin (1) P117 57 Multi-function serial ch.19 serial data output pin (1) Multi-function serial ch.18 clock I/O pin (0) Base timer ch.5 TIOA output pin (1) TIOA6_1 55 Functions Type - A Multi-function serial ch.16 clock I/O pin (0) ADC analog 19 input pin S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P127 67 SCS203_0 AN20 General-purpose I/O port - A TEXT1_1 68 69 71 72 74 General-purpose I/O port SCS200_0 Serial chip select 20-0 I/O pin (0) AN21 - A 76 77 Free-run timer 2 clock input pin (1) P129 General-purpose I/O port IN6_1 SCS201_0 - A Input capture ch.6 input pin (1) Serial chip select 20-1 output pin (0) AN22 ADC analog 22 input pin P130 General-purpose I/O port SIN6_0 Input capture ch.7 input pin (1) - A Multi-function serial ch.6 serial data input pin (0) AN23 ADC analog 23 input pin INT5_0 INT5 external interrupt input pin (0) P131 General-purpose I/O port IN8_1 SOT6_0 - A Input capture ch.8 input pin (1) Multi-function serial ch.6 serial data output pin (0) AN24 ADC analog 24 input pin P200 General-purpose I/O port SCS202_0 AN25 - A Serial chip select 20-2 output pin (0) ADC analog 25 input pin Base timer ch.17 TIOA output pin (0) P201 General-purpose I/O port SIN20_0 Multi-function serial ch.20 serial data input pin (0) AN26 - A ADC analog 26 input pin TIOA18_0 Base timer ch.18 TIOA output pin (0) P202 General-purpose I/O port IN9_1 SCK6_0 P203 IN10_1 - A Input capture ch.9 input pin (1) Multi-function serial ch.6 clock I/O pin (0) INT6 external interrupt input pin (1) - A General-purpose I/O port Input capture ch.10 input pin (1) P204 General-purpose I/O port IN11_1 Input capture ch.11 input pin (1) SOT20_0 - A Multi-function serial ch.20 serial data output pin (0) AN27 ADC analog 27 input pin P205 General-purpose I/O port SCK20_0 AN28 TEXT3_1 June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL ADC analog 21 input pin TEXT2_1 INT6_1 75 ADC analog 20 input pin P128 TIOA17_0 73 Serial chip select 20-3 output pin (0) Free-run timer 1 clock input pin (1) IN7_1 70 Functions Type - A Multi-function serial ch.20 clock I/O pin (0) ADC analog 28 input pin Free-run timer 3 clock input pin (1) 17 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P206 78 SCS43_0 AN29 General-purpose I/O port - A TEXT4_1 79 80 82 83 84 85 86 CONFIDENTIAL ADC analog 29 input pin P207 General-purpose I/O port SCK4_0 Multi-function serial ch.4 clock I/O pin (0) AN30 - A ADC analog 30 input pin INT7_1 INT7 external interrupt input pin (1) TEXT5_1 Free-run timer 5 clock input pin (1) P208 General-purpose I/O port SCS42_0 AN31 - A Serial chip select 4-2 output pin (0) ADC analog 31 input pin Base timer ch.19 TIOA output pin (0) P209 General-purpose I/O port SOT4_0 Multi-function serial ch.4 serial data output pin (0) AN32 - A ADC analog 32 input pin TIOA20_0 Base timer ch.20 TIOA output pin (0) P210 General-purpose I/O port IN0_2 Input capture ch.0 input pin (2) SIN4_0 AN33 - A Multi-function serial ch.4 serial data input pin (0) ADC analog 33 input pin TIOA21_0 Base timer ch.21 TIOA output pin (0) INT6_0 INT6 external interrupt input pin (0) P211 General-purpose I/O port IN1_2 Input capture ch.1 input pin (2) SCS40_0 - A Serial chip select 4-0 I/O pin (0) AN34 ADC analog 34 input pin TIOA22_0 Base timer ch.22 TIOA output pin (0) P212 General-purpose I/O port IN2_2 Input capture ch.2 input pin (2) SCS50_1 SCS41_0 - A Serial chip select 5-0 I/O pin (1) Serial chip select 4-1 output pin (0) AN35 ADC analog 35 input pin TIOA13_1 Base timer ch.13 TIOA output pin (1) P213 General-purpose I/O port IN3_2 Input capture ch.3 input pin (2) SIN5_1 - A Multi-function serial ch.5 serial data input pin (1) TIOA14_1 Base timer ch.14 TIOA output pin (1) INT8_1 INT8 external interrupt input pin (1) P214 General-purpose I/O port IN4_2 SOT5_1 TIOA15_1 18 Serial chip select 4-3 output pin (0) Free-run timer 4 clock input pin (1) TIOA19_0 81 Functions Type - A Input capture ch.4 input pin (2) Multi-function serial ch.5 serial data output pin (1) Base timer ch.15 TIOA output pin (1) S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P215 General-purpose I/O port IN5_2 87 90 91 SCK5_1 Input capture ch.5 input pin (2) - A 93 Base timer ch.16 TIOA output pin (1) INT9_1 INT9 external interrupt input pin (1) P216 SIN15_0 P217 SOT15_0 - A - A SCK15_0 AN36 - A 96 98 Multi-function serial ch.15 clock I/O pin (0) ADC analog 36 input pin P219 General-purpose I/O port SCS150_0 AN37 - A Serial chip select 15-0 I/O pin (0) ADC analog 37 input pin Free-run timer 3 clock input pin (0) P220 General-purpose I/O port IN6_2 Input capture ch.6 input pin (2) SCS53_0 P221 SCS52_0 - A Serial chip select 5-3 output pin (0) ADC analog 38 input pin - A General-purpose I/O port Serial chip select 5-2 output pin (0) P222 General-purpose I/O port IN7_2 Input capture ch.7 input pin (2) SIN5_0 - A Multi-function serial ch.5 serial data input pin (0) AN39 ADC analog 39 input pin INT7_0 INT7 external interrupt input pin (0) P223 General-purpose I/O port PWU_AN0 Input capture ch.8 input pin (2) - A Partial wakeup ADC analog 0 input pin SCS51_0 Serial chip select 5-1 output pin (0) AN40 ADC analog 40 input pin P224 General-purpose I/O port IN9_2 Input capture ch.9 input pin (2) PWU_AN1 TX0_2 - A Partial wakeup ADC analog 1 input pin CAN transmission data 0 output pin (2) SCS50_0 Serial chip select 5-0 I/O pin (0) AN41 ADC analog 41 input pin June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL General-purpose I/O port Multi-function serial ch.15 serial data output pin (0) Free-run timer 2 clock input pin (0) IN8_2 97 Multi-function serial ch.15 serial data input pin (0) TEXT2_0 AN38 95 General-purpose I/O port General-purpose I/O port TEXT3_0 94 Multi-function serial ch.5 clock I/O pin (1) TIOA16_1 P218 92 Functions Type 19 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA 99 100 104 105 106 107 Polarity Circuit P225 General-purpose I/O port IN10_2 Input capture ch.10 input pin (2) PWU_AN2 Partial wakeup ADC analog 2 input pin RX0_2 - A 20 CONFIDENTIAL CAN reception data 0 input pin (2) SOT5_0 Multi-function serial ch.5 serial data output pin (0) AN42 ADC analog 42 input pin INT0_0 INT0 external interrupt input pin (0) P226 General-purpose I/O port IN11_2 Input capture ch.11 input pin (2) PWU_AN3 SCK5_0 - A Partial wakeup ADC analog 3 input pin Multi-function serial ch.5 clock I/O pin (0) AN43 ADC analog 43 input pin TIOA17_1 Base timer ch.17 TIOA output pin (1) P227 General-purpose I/O port PWU_AN4 Partial wakeup ADC analog 4 input pin SCK10_0 - A Multi-function serial ch.10 clock I/O pin (0) AN44 ADC analog 44 input pin TIOA23_0 Base timer ch.23 TIOA output pin (0) P228 General-purpose I/O port PWU_AN5 Partial wakeup ADC analog 5 input pin TX0_1 CAN transmission data 0 output pin (1) SOT10_0 - A Multi-function serial ch.10 serial data output pin (0) AN45 ADC analog 45 input pin TIOA24_0 Base timer ch.24 TIOA output pin (0) P229 General-purpose I/O port PWU_AN6 Partial wakeup ADC analog 6 input pin RX0_1 CAN reception data 0 input pin (1) SIN10_0 AN46 - A Multi-function serial ch.10 serial data input pin (0) ADC analog 46 input pin TIOA25_0 Base timer ch.25 TIOA output pin (0) INT8_0 INT8 external interrupt input pin (0) OUT0_0 Output compare ch.0 output pin (0) P230 General-purpose I/O port PWU_AN7 Partial wakeup ADC analog 7 input pin SCS103_0 Serial chip select 10-3 output pin (0) AN47 - A ADC analog 47 input pin TIOA26_0 Base timer ch.26 TIOA output pin (0) OUT1_0 Output compare ch.1 output pin (0) P231 General-purpose I/O port SCS102_0 108 Functions Type AN48 Serial chip select 10-2 output pin (0) - A ADC analog 48 input pin TIOA27_0 Base timer ch.27 TIOA output pin (0) OUT2_0 Output compare ch.2 output pin (0) S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P300 General-purpose I/O port SCS101_0 109 AN49 Serial chip select 10-1 output pin (0) - A TIOA28_0 110 111 113 OUT3_0 Output compare ch.3 output pin (0) P301 General-purpose I/O port SCS100_0 Serial chip select 10-0 I/O pin (0) AN50 - A 115 116 117 118 Base timer ch.18 TIOA output pin (1) OUT4_0 Output compare ch.4 output pin (0) P302 General-purpose I/O port SIN14_0 Multi-function serial ch.14 serial data input pin (0) AN51 P303 SOT14_0 - A ADC analog 51 input pin Base timer ch.19 TIOA output pin (1) - A General-purpose I/O port Multi-function serial ch.14 serial data output pin (0) P304 General-purpose I/O port SCK14_0 Multi-function serial ch.14 clock I/O pin (2) AN52 - A ADC analog 52 input pin TIOA20_1 Base timer ch.20 TIOA output pin (1) TEXT4_0 Free-run timer 4 clock input pin (0) P305 General-purpose I/O port AN53 Serial chip select 14-0 I/O pin (0) - A ADC analog 53 input pin TIOA29_0 Base timer ch.29 TIOA output pin (0) TEXT5_0 Free-run timer 5 clock input pin (0) NMIX N F Non-maskable interrupt input pin P306 General-purpose I/O port TX0_0 CAN transmission data 0 output pin (0) SCS73_0 - A Serial chip select 7-3 output pin (0) AN54 ADC analog 54 input pin P307 General-purpose I/O port RX0_0 CAN reception data 0 input pin (0) SCS72_0 - A Serial chip select 7-2 output pin (0) AN55 ADC analog 55 input pin INT1_0 INT1 external interrupt input pin (0) P308 General-purpose I/O port IN0_1 Input capture ch.0 input pin (1) SCK13_0 - A Multi-function serial ch.13 clock I/O pin (0) AN56 ADC analog 56 input pin TIOA28_1 Base timer ch.28 TIOA output pin (1) June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL ADC analog 50 input pin TIOA18_1 SCS140_0 114 ADC analog 49 input pin Base timer ch.28 TIOA output pin (0) TIOA19_1 112 Functions Type 21 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P309 General-purpose I/O port IN1_1 119 120 SCS130_0 Input capture ch.1 input pin (1) - A ADC analog 57 input pin TIOA29_1 Base timer ch.29 TIOA output pin (1) P310 General-purpose I/O port SIN13_0 - A P311 SOT13_0 IN2_1 SCS71_0 - A 124 - A 126 129 General-purpose I/O port Input capture ch.3 input pin (1) SOT7_0 - A CONFIDENTIAL Multi-function serial ch.7 serial data output pin (0) AN59 ADC analog 59 input pin INT10_1 INT10 external interrupt input pin (1) P314 General-purpose I/O port IN4_1 Input capture ch.4 input pin (1) SCK7_0 - A Multi-function serial ch.7 clock I/O pin (0) AN60 ADC analog 60 input pin TIOA7_1 Base timer ch.7 TIOA output pin (1) P315 General-purpose I/O port SCS70_0 Input capture ch.5 input pin (1) - A Serial chip select 7-0 I/O pin (0) AN61 ADC analog 61 input pin TIOA8_1 Base timer ch.8 TIOA output pin (1) P316 TIOA21_1 AN62 - A General-purpose I/O port Base timer ch.21 TIOA output pin (1) General-purpose I/O port CAN transmission data 1 output pin (1) - A ADC analog 62 input pin TIOA9_1 Base timer ch.9 TIOA output pin (1) INT11_1 INT11 external interrupt input pin (1) P318 General-purpose I/O port RX1_1 TIOA10_1 - A CAN reception data 1 input pin (1) Base timer ch.10 TIOA output pin (1) INT9_0 INT9 external interrupt input pin (0) P319 General-purpose I/O port SIN7_0 AN63 INT12_1 22 Serial chip select 7-1 output pin (0) IN3_1 TX1_1 128 Input capture ch.2 input pin (1) P313 P317 127 Multi-function serial ch.13 serial data output pin (0) ADC analog 58 input pin IN5_1 125 General-purpose I/O port General-purpose I/O port AN58 123 Multi-function serial ch.13 serial data input pin (0) INT15 external interrupt input pin (0) P312 122 Serial chip select 13-0 I/O pin (0) AN57 INT15_0 121 Functions Type - A Multi-function serial ch.7 serial data input pin (0) ADC analog 63 input pin INT12 external interrupt input pin (1) S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA 130 131 134 135 136 Polarity Circuit Functions Type P320 - A P321 - D TRST N P322 - PWUTRG TDO P323 TDI P324 J - I - D General-purpose I/O port Partial wakeup trigger output pin General-purpose output port JTAG test reset input pin General-purpose output port JTAG test data output pin General-purpose output port JTAG test data input pin General-purpose output port 137 TMS - E JTAG test mode state input pin 138 TCK - E JTAG test clock input pin - A Multi-function serial ch.21 serial data input pin (0) P325 139 SIN21_0 General-purpose I/O port INT10_0 140 P326 SOT21_0 INT10 external interrupt input pin (0) - A P327 141 142 SCK6_1 Multi-function serial ch.21 serial data output pin (0) General-purpose I/O port - A Multi-function serial ch.6 clock I/O pin (1) SCK21_0 Multi-function serial ch.21 clock I/O pin (0) P328 General-purpose I/O port SOT6_1 - A SCS210_0 143 General-purpose I/O port P329 SIN6_1 Multi-function serial ch.6 serial data output pin (1) Serial chip select 21-0 I/O pin (0) - A General-purpose I/O port Multi-function serial ch.6 serial data input pin (1) 144 P330 - A General-purpose I/O port 145 MD - C Mode pin 146 X0 - G Main clock oscillation input pin 147 X1 - G Main clock oscillation output pin - A - A N F 149 150 151 P331 SCS60_1 P400 SCS61_1 RSTX P401 155 IN0_0 TX1_0 SCS62_1 June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL General-purpose I/O port Serial chip select 6-0 I/O pin (1) General-purpose I/O port Serial chip select 6-1 output pin (1) External reset input pin General-purpose I/O port - B Input capture ch.0 input pin (0) CAN transmission data 1 output pin (0) Serial chip select 6-2 output pin (1) 23 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA 156 157 158 Polarity Circuit P402 General-purpose I/O port IN1_0 Input capture ch.1 input pin (0) RX1_0 SCS63_1 - B 160 161 162 Serial chip select 9-0 I/O pin (0) INT2 external interrupt input pin (0) P403 General-purpose I/O port IN2_0 - B Trace data 0 output pin P404 General-purpose I/O port IN3_0 - B Trace data 1 output pin P405 General-purpose I/O port SIN9_0 Input capture ch.4 input pin (0) - B INT11 external interrupt input pin (0) TRACEDATA2 Trace data 2 output pin P406 General-purpose I/O port SOT9_0 - B CONFIDENTIAL Multi-function serial ch.9 serial data output pin (0) TRACEDATA3 Trace data 3 output pin P407 General-purpose I/O port SCK7_1 SCK9_0 - B Multi-function serial ch.7 clock I/O pin (1) Multi-function serial ch.9 clock I/O pin (0) TRACEDATA4 Trace data 4 output pin P408 General-purpose I/O port SIN2_0 INT12_0 - B Multi-function serial ch.2 serial data input pin (0) INT12 external interrupt input pin (0) Trace data 5 output pin P409 General-purpose I/O port SOT2_0 Multi-function serial ch.2 serial data output pin (0) TIOA24_1 P410 SCS70_1 SCK2_0 - B Base timer ch.24 TIOA output pin (1) Trace data 6 output pin - B General-purpose I/O port Serial chip select 7-0 I/O pin (1) General-purpose I/O port Serial chip select 7-1 output pin (1) - B Multi-function serial ch.2 clock I/O pin (0) INT13_1 INT13 external interrupt input pin (1) TRACEDATA7 Trace data 7 output pin P412 General-purpose I/O port SCS72_1 TIOA25_1 24 Multi-function serial ch.9 serial data input pin (0) INT11_0 SCS71_1 166 Input capture ch.3 input pin (0) TRACEDATA1 P411 165 Input capture ch.2 input pin (0) TRACEDATA0 TRACEDATA6 164 Serial chip select 6-3 output pin (1) INT2_0 TRACEDATA5 163 CAN reception data 1 input pin (0) SCS90_0 IN4_0 159 Functions Type - B Serial chip select 7-2 output pin (1) Base timer ch.25 TIOA output pin (1) S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA Polarity Circuit P413 167 SCS73_1 SCS20_0 General-purpose I/O port - B INT14_1 SCS21_0 General-purpose I/O port - B SIN11_0 169 171 172 P415 General-purpose I/O port SOT11_0 Multi-function serial ch.11 serial data output pin (0) TIOA26_1 - B 174 175 Base timer ch.26 TIOA output pin (1) INT13 external interrupt input pin (0) P416 General-purpose I/O port IN5_0 Input capture ch.5 input pin (0) SIN7_1 - B Multi-function serial ch.7 serial data input pin (1) SCK11_0 Multi-function serial ch.11 clock I/O pin (0) TIOA22_1 Base timer ch.22 TIOA output pin (1) P417 General-purpose I/O port SOT7_1 Multi-function serial ch.7 serial data output pin (1) SCS110_0 - B Serial chip select 11-0 I/O pin (0) TIOA23_1 Base timer ch.23 TIOA output pin (1) INT15_1 INT15 external interrupt input pin (1) P418 General-purpose I/O port SCS22_0 SIN12_0 - B INT14_0 173 Serial chip select 2-1 output pin (0) Multi-function serial ch.11 serial data input pin (0) INT13_0 170 Serial chip select 7-3 output pin (1) Serial chip select 2-0 I/O pin (0) INT14 external interrupt input pin (1) P414 168 Functions Type Serial chip select 2-2 output pin (0) Multi-function serial ch.12 serial data input pin (0) INT14 external interrupt input pin (0) P419 General-purpose I/O port SCS23_0 Serial chip select 2-3 output pin (0) SOT12_0 - B Multi-function serial ch.12 serial data output pin (0) TIOA27_1 Base timer ch.27 TIOA output pin (1) P420 General-purpose I/O port SCK2_1 SCK12_0 - B Multi-function serial ch.2 clock I/O pin (1) Multi-function serial ch.12 clock I/O pin (0) TRACECLK Trace clock P421 General-purpose I/O port SIN2_1 SCS120_0 - B TRACECTL Multi-function serial ch.2 serial data input pin (1) Serial chip select 12-0 I/O pin (0) Trace control 52 AVCC0 - - Analog power supply pin for AD converter unit 0 103 AVCC1 - - Analog power supply pin for AD converter unit 1 53 AVRH0 - - Upper-limit reference voltage pin for AD converter unit 0 102 AVRH1 - - Upper-limit reference voltage pin for AD converter unit 1 - - 54 AVSS0 AVRL0 June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL GND pin for AD converter unit 0 Lower-limit reference voltage pin for AD converter unit 0 25 D a t a S h e e t ( P r e l i m i n a r y ) I/O Pin No. Pin Name S6J311EJAA 101 46 154 Polarity Circuit Functions Type AVSS1 GND pin for AD converter unit 1 - - C - - External capacity connection output pin VCC - - Power supply pin VSS - - GND AVRL1 Lower-limit reference voltage pin for AD converter unit 1 44 88 133 152 176 1 45 89 132 148 153 26 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 6. I/O CIRCUIT TYPES This section explains I/O circuit types. Type A Circuit Overview Pull-up control Digital output Digital output − General-purpose I/O port with analog input − Output of 1 mA or 2 mA selectable − 50 kΩ with pull-up resistor control − 50 kΩ with pull-down resistor control − CMOS hysteresis input Pull-down CMOS PSS Analog input B Pull-up control Digital output Digital output Pull-down Automotive/ CMOS input PSS Analog input C − General-purpose I/O port with analog input − Output of 1 mA or 2 mA selectable − 50 kΩ with pull-up resistor control − 50 kΩ with pull-down resistor control − Automotive/CMOS hysteresis input selectable − Mode input − CMOS hysteresis input Mode input Control D − JTAG Pull-up Digital output Digital output − General-purpose output port − Output of 2 mA − 50 kΩ with pull-up resistor control − TTL input TTL input June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 27 D a t a S h e e t ( P r e l i m i n a r y ) Type E Circuit Overview − JTAG Pull-up control − 50 kΩ with pull-up resistor control − TTL input TTL input F − CMOS hysteresis input − 50 kΩ with pull-up resistor CMOS-hys G Input − Main oscillation I/O Standby control I − JTAG Digital output − Output of 2 mA Digital J − JTAG Digital output Digital Pull-down control − General-purpose output port − Output of 2 mA − 50 kΩ with pull-down resistor control − TTL input TTL input 28 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 7. HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 7.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 29 D a t a S h e e t ( P r e l i m i n a r y ) Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 30 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 7.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion’s recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C and 30 ˚C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 31 D a t a S h e e t ( P r e l i m i n a r y ) Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125 ˚C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 32 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 7.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 33 D a t a S h e e t ( P r e l i m i n a r y ) 8. HANDLING DEVICES For latch-up prevention The latch-up phenomenon may occur on a CMOS IC in the following cases: the voltage applied to an input or output pin is higher than VCC or lower than VSS; or the voltage applied between a VCC pin and a VSS pin exceeds the rating. A latch-up causes a rapid increase in the power supply current, possibly resulting in thermal damage to an element. When using the device, take sufficient care not to exceed the maximum rating. Also be careful that analog power supplies (AVCC0, AVCC1, AVRH0, and AVRH1) and analog inputs do not exceed the digital power supply (VCC) at the analog system power-on and power-off times. The power-on sequence is as follows. Simultaneously turn on the digital supply voltage (VCC) and analog supply voltages (AVCC0, AVCC1, AVRH0, and AVRH1), or turn on the digital supply voltage (VCC) and then the analog supply voltages (AVCC0, AVCC1, AVRH0, and AVRH1). About handling unused pins Leaving unused input pins open may cause permanent damage from a malfunction or latch-up. Take measures for unused pins, such as pulling up or pulling down the voltage with resistors of 2 kiloohms or higher. If there are any unused input/output pins, set them to the output state and then open them, or set them to the input state and handle them in the same way as input pins. About power supply pins If the device has multiple VCC and VSS pins, the device is designed in such a way that the pins that should be at the same potential are connected to each other inside the device to prevent malfunctions such as latch-up. However, to reduce unwanted emissions, prevent malfunctions of strobe signals caused by an increase of the ground level, and observe standards on total output current, be sure to connect all the VCC and VSS pins to the power source and ground externally. Also handle all the VSS power supply pins in this way as shown in the following diagram. If there are multiple VCC or VSS systems, the device does not operate normally even within the guaranteed operating range. 34 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) Figure 8-1 Pin Assignment In addition, consider connecting with low impedance from the power supply source to the VCC and VSS of this device. We recommend connecting a ceramic capacitor as a bypass capacitor between VCC and VSS, near this device. About the crystal oscillation circuit Noise entering the X0 or X1 pin may cause a malfunction. Design the printed circuit board in such a way that the X0 and X1 pins, the crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to the device. We recommend that the printed circuit board artwork have the X0 and X1 pins enclosed by ground. About the mode pin (MD) Use mode pin MD by directly connecting it to a VCC or VSS pin. To prevent noise from causing the device to accidentally enter test mode, reduce the pattern length between each mode pin and a VCC or VSS pin on the printed circuit board, and connect them with low impedance. About the power-on time To prevent the internal built-in voltage step-down circuit from malfunctioning, secure a voltage rising time of 50 µs (between 0.2 V and 2.7 V) or longer at the power-on time. Point to note during PLL clock operation While a PLL clock is selected, if the oscillator breaks off or input stops, the PLL clock may continue operating with the free running frequency of the internal self-oscillator circuit. This operation is outside of the guaranteed range. Power supply pin processing of an A/D converter Even when no A/D converter is used, establish a connection such that AVCC=AVRH=VCC and AVSS/AVRL=VSS. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 35 D a t a S h e e t ( P r e l i m i n a r y ) Points to note about using external clocks External clocks are not supported. External direct clock input cannot be used. Power-on sequence of the power supply analog inputs of an A/D converter Be sure to turn on the digital power supply (VCC) before the application of the power supplies (AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN63) of an A/D converter. At the power-off time, turn off the power supplies and analog inputs of the A/D converter, and then turn off the digital power supply (VCC). Perform these power-on and power-off operations without AVRH exceeding AVCC. Even when using a pin shared with an analog input as an input port, do not allow the input voltage to exceed AVCC. (Turning on or off the analog supply voltage and digital supply voltage simultaneously is not a problem.) About C pin processing This device has a built-in voltage step-down circuit. Be sure to connect a capacitor to the C pin (pin 154 in S6J311EJAA specifications) for internal stabilization of the device. For the standard values, see "Recommended operating conditions" in the latest data sheet. Precautions on designing a mounting substrate Measures against heat generation from the package must be taken for the mounting substrate to observe the absolute maximum rating (operating temperature). Design a mounting substrate with 4 or more layers. Connect the back of the package stage and the substrate pad with solder paste. Arrange thermal via holes on the substrate pad. Notes on writing to a register containing a status flag In writing to a register containing a status flag (particularly an interrupt request flag, etc.) to control a function, it is important to take care not to accidentally clear the status flag. Therefore, before the write operation, configure the status bit such that the flag is not cleared, and then set the control bit to the desired value. Especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit instructions have only 1-bit access). In such cases, byte, half-word, or word access is used to write to the control bits and a status flag simultaneously. However, at this time, be careful not to accidentally clear bits other than the intended ones (the status flag bit in this case). Note: Bit instructions take this point into account for registers that support bit-band units, so it does not need to be a concern. You need to take care when using bit instructions for registers that do not support bit-band units. 36 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 9. BLOCK DIAGRAM This section provides block diagrams of the S6J3110 series. Figure 9-1 S6J311EJAA Block Diagram Trace I/F(8Pin) Debug I/F (JTAG/SWD) Power Domain 2 JTAG_SWCLKTCK JTAG Wakeup Debug Group (CoreSightTM) Bus Config Group From/To PPU-SLAVEs - Bus Performance Counters - Misc Register Module DAP CLK_DBG CLK_LLPBM2 Security APB-M PPU Master APB-S AHB-M CLK_HPM Debug APB CLK_HPM Trace Group CLK_CPU CLK_DBG ATB CLK_ATB Core Group (1-Core) Power Domain 3 Security Checker ETB (Trace Buffer) 16KB CLK_TRC From/To CommonPERI#2 From/To CommonPERI#2 AHB2APB (Priviledge Protection) APB-32 CLK_LLPBM2 Debug APB TCFLASH #0 4MB + 64KB + EEFlash #0 112KB WorkFlash TCF AHB-64 AHB-64 (Reg & Data) (Reg) AHB-64 CLK_MEMC AXI-64 AHB-32 CLK_SHE TCF AXI-64 (data) CLK_MEMC CLK_FCLK CLK_SHE CLK_CPU Flash Group SHE Group CLK_SHE From/To Memory Config Grp. ETMTM #0 TCF ATCM #0 Procceser TCRAM #0 (2bank) 64KB (32KB×2) AXI-64 - DMAC 16.ch - ReloadTimer 4ch CLK_DMA MPU #0 AXI-64 CLK_CPU D$ #0 I$ #0 16KB 16KB CLK_HPM LLPP AXI32-M AHB32 AXI-M AXI-S CLK_CPU DMAC Complex #0 CortexTM -R5F ATCM #0 AHB-64 CLK_MEMC From/To Memory Config Grp. CPU #0 B0TCM B1TCM #0 AXI-64 CLK_CPU AXI-32 CLK_CPU From/To CommonPERI#2 DMAC Config AHB-32 CLK_CPU AHB-32 CLK_HPM2 AHB-64 CLK_HPM AHB-32 CLK_HPM2 High Performance Matrix (HPM) AXI-64 CLK_HPM System SRAM 256KB AHB-32 AXI-64 AHB-32 CLK_HPM CLK_SYSC1 EAM CLK_MEMC CLK_HPM AHB-32 CLK_CPU AHB-64 CLK_HPM From/To Flash Group BBU BBU AHB-32 CLK_LLPBM Low Latency Peripheral Bus Matrix (LLPBM) AHB-32 CLK_LLPBM AHB-32 BBU BBU CLK_SYSC0H Power Domain 6_0 System Controller(SYSC) (CLK_CAN) Reset manage CLK_LCP BootROM 16KB SW-Watchdog CSV(for PLL) Timing Protection (TPU) #0 SYSC1 CLK_SYSC1 Power manage Source Clock Timer LVD CSV Fast-CR Slow-CR PLL0 SSCG PLL0 CLK_MEMC State manage CLK_CAN CLK_LCP0A CRC 4ch P M.F.S 22ch Peripheral Bus Bridge CLK_LLPBM2 P Bus Config Group (Config) GPIO DMAC Complex #0 (Config) 32Bit FRT 6ch #0 TCRAM (Config) Peripheral Bus Bridge CLK_HPM Base Timer 30ch Wakeup Request #0 32Bit ICU 12ch PPU Master (Cnofig) 32Bit OCU 12ch Memory & Config Group CLK_MEMC Power Domain 3 C Peripheral Bus Bridge RAM RAM PONR CLK_LCP0A CAN-FD 2ch IRC #0 512 Vectors Clock manage EICU 16ch CAN prescaler Backup RAM 32KB (8+5 bit width RAM x 4) Power Domain 4_1 CLK_RAM1H Power CLK_RAM0H Domain 4_0 Backup RAM 32KB (8+5 bit width RAM x 4) ECC-ed RAM I/F Flash Group I/F Clock divide and distribution CLK_COMH CLK_LLPBM BBU CLK_LLPBM CLK_LLPBM From/To Core-Group AHB-32 State manage (2) Common PERI #0 Group 12Bit A/DC Unit0×32ch Common PERI #1 Group Common PERI #2 Group Wakeup-detect RTC Clock Calibration H/W Watchdog EXT-IRQ 16ch Pertial Wake up 12Bit A/DC Unit1×32ch Common PERI #0 Group Power Domain 1 (Always on) NMI MCU Config Group Power Domain 1 (Always on) June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 37 D a t a S h e e t ( P r e l i m i n a r y ) 10. MEMORY MAP This section explains the memory map. Figure 10-1 Memory Map S6J311EJAA ADRESS START END group 0x0000_0000 part TCRAM 0x0000_FFFF (Main 64KByte) 0x0001_0000 0x007F_FFFF Reserved 0x0080_0000 0x008F_FFFF Reserved 0x009F_0000 TCM_FLASH 0x009F_FFFF (Small Sector 8KByte×8) 0x00A0_0000 TCM_FLASH 0x00AF_FFFF Internal area for CR5 0x00B0_0000 0x00DF_FFFF 0x00E0_0000 0x00FF_FFFF 0x0100_0000 0x018F_FFFF (Code 4MByte) Complex Reserved Reserved 0x019F_0000 AXI_FLASH_MEMORY 0x019F_FFFF (Small Sector 8KByte×8 *Mirror) 0x01A0_0000 AXI_FLASH_MEMORY 0x01AF_FFFF (Code 4MByte *Mirror) 0x01B0_0000 0x01DF_FFFF 0x01E0_0000 0x01FF_FFFF Reserved 0x0200_0000 SYSTEM SRAM 0x0200_3FFF (256KByte) 0x0200_4000 0x0203_FFFF 0x0204_0000 0x027F_FFFF Reserved 0x0280_0000 0x0280_002F Exclusive Access Memory 0x0280_0030 0x03FF_FFFF Reserved 0x0400_0000 0x05FF_FFFF AXI_SLAVE_CORE0 0x0600_0000 Reserved 0x0DFF_FFFF 0x0E00_0000 WORK_FLASH 0x0E00_BFFF 0x0E00_C000 0x0E01_BFFF 0x0E01_C000 0x0E0F_FFFF 0x0E10_0000 0x0E1F_FFFF 0x0E20_0000 (112KByte mirror area 1) Shared Flash and memory area 0x0E21_BFFF 0x0E21_C000 0x0E2F_FFFF (112KByte mirror area 3) Reserved 0x0E30_0000 WORK_FLASH 0x0E30_BFFF 0x0E30_C000 0x0E31_BFFF 0x0E31_C000 0x0E3F_FFFF 0x0E40_0000 0x0E7F_FFFF (112KByte mirror area 4) Reserved Reserved 0x0E80_0000 Backup RAM 0x0E80_1FFF 0x0E80_2000 0x0E80_FFFF 0x0E81_0000 0x0E87_FFFF Reserved WORK_FLASH 0x0E20_BFFF 0x0E20_C000 Reserved 64KByte Reserved 0x0E88_0000 Reserved 0x0FFF_FFFF 0x1000_0000 Reserved Reserved 0xAFFF_FFFF 0xB000_0000 0xB483_FFFF Peri_area 0xB484_0000 0xB484_FFFF APPS#5 0xB485_0000 Peri area Peri_area 0xB7FF_FFFF 0xB800_0000 Reserved Reserved 0xFFFE_DFFF 38 CONFIDENTIAL 0xFFFE_E000 0xFFFE_FFFF 0xFFFF_0000 0xFFFF_3FFF 0xFFFF_4000 0xFFFF_FFFF ERRCFG BootROM ERRCFG BootRom Reserved S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) Only the CPU core can access 0000_0000 ~ 01FF_FFFF. Bus masters other than the CPU core cannot access the region. Internal area of CR5 complex (0000_0000 ~ 01FF_FFFF) is mapped to AXI_SLAVE_CORE0. All bus masters can access to internal area of CR5 complex via AXI_SLAVE_CORE0. In each of the following memory area combinations, the areas are physically the same memory area. 1. TCM FLASH (0x00A0_0000 -) and AXI FLASH MEMORY (0x01A0_0000 -) 2. TCM FLASH Small Sector (0x009F_0000 -) and AXI FLASH MEMORY Small Sector (0x019F_0000 -) 3. WORKFLASH (0x0E00_0000 -), WORKFLASH (0x0E20_0000 -), and WORKFLASH (0x0E30_0000 -) − The differences between the TCM FLASH and AXI FLASH include the following. Function High-speed Access Using Dedicated Bus Write and Erase TCM FLASH AXI FLASH Applicable Not applicable Not applicable Applicable (Read-only) Read Applicable Applicable − The differences between WORKFLASH areas include the following. Area Function WORKFLASH Area 1 Used in write operation (with ECC) WORKFLASH Area 3 Used in write operation (without ECC) WORKFLASH Area 4 Used in read operation − Terms are as follows. Term Description TCM RAM Main RAM TCM FLASH Program FLASH (TCM area) AXI FLASH Program FLASH (AXI area) This is physically the same as the TCM FLASH. SYSTEM RAM System RAM AXI SLAVE CORE AXI CPU control area WORKFLASH FLASH for work BACKUP RAM Backup RAM Peri area Entire area for peripheral functions APPS#5 Part of area for peripheral functions ERRCFG Error configuration area BootROM ROM for reset boot June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 39 D a t a S h e e t ( P r e l i m i n a r y ) S6J311EJAA Peripheral Map START Address B000_0000 B010_8000 B010_8100 B030_0000 B030_8000 B040_0000 B040_8000 B041_0000 B041_1000 B041_2000 B041_2100 B050_0000 B060_0000 B060_0080 B060_0100 B060_0180 B060_0200 B060_0280 B060_0300 B060_0380 B060_0400 B060_0480 B060_0500 B060_0600 B060_0680 B060_0700 B060_0800 B060_C000 B061_0000 B061_8000 B062_0000 B064_0000 B066_0000 B068_0000 B068_8000 B068_8400 B068_8800 B068_8C00 B069_0000 B070_0000 B080_0000 B100_0000 B110_0000 B120_0000 B200_0000 B210_0000 B470_0000 B470_4000 B471_0000 B471_1000 B471_4000 B471_5000 B471_8000 B471_8400 B471_8800 B471_8C00 B471_9000 B473_8000 B474_0000 B474_8000 B475_0000 B475_8000 B478_FC00 B479_0000 40 CONFIDENTIAL END Address B010_7FFF B010_80FF B02F_FFFF B030_7FFF B03F_FFFF B040_7FFF B040_FFFF B041_0FFF B041_1FFF B041_20FF B04F_FFFF B05F_FFFF B060_007F B060_00FF B060_017F B060_01FF B060_027F B060_02FF B060_037F B060_03FF B060_047F B060_04FF B060_05FF B060_067F B060_06FF B060_07FF B060_BFFF B060_FFFF B061_7FFF B061_FFFF B063_FFFF B065_FFFF B067_FFFF B068_7FFF B068_83FF B068_87FF B068_8BFF B068_FFFF B06F_FFFF B07F_FFFF B0FF_FFFF B10F_FFFF B11F_FFFF B1FF_FFFF B20F_FFFF B46F_FFFF B470_3FFF B470_FFFF B471_0FFF B471_3FFF B471_4FFF B471_7FFF B471_83FF B471_87FF B471_8BFF B471_8FFF B473_7FFF B473_FFFF B474_7FFF B474_FFFF B475_7FFF B478_FBFF B478_FFFF B47F_FFFF Group SystemSRAM SYSC1 SYSC1 MEMORY_CONFIG_GROUP MEMORY_CONFIG_GROUP MEMORY_CONFIG_GROUP MEMORY_CONFIG_GROUP MEMORY_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP MCU_CONFIG_GROUP Bit RMW alias Bit RMW alias Bit RMW alias SHE CommonPERI #2 CommonPERI #2 CommonPERI #2 CommonPERI #2 CommonPERI #2 CommonPERI #2 CommonPERI #2 CommonPERI #2 CommonPERI #2 CommonPERI #2 CommonPERI #2 Function Reserved SystemSRAM registers Reserved System Controller #1 SWDT IRC0 TPU0 TCRAM Control Status Register TCFlash Control Status Register WFlash Control Status Register Reserved Reserved Protection register area RUN profile register area PSS profile register area APP profile register area STS profile register area System register area CSV RESET SCT(Fast CR) SCT(Slow CR) SCT(Main clock) Clock System Special register area Debug register area Mode HWDT Reserved RTC EIC Reserved Reserved BURAMIF EICU CR_Calibration IRQ ALL CAN Prescaler Reserved Reserved Bit RMW alias for MCU config Gr (Covers B060_0000 -- B06F_FFFF) Bit RMW alias for SYSC1 (Covers B030_0000 -- B031_FFFF) Bit RMW alias for MEMC (Covers B040_0000 -- B041_FFFF) Reserved SHE configuration registers Reserved DMAC #0 registers Reserved MPU for DMAC#0 Reserved DMA Complex #0 registers (Additional registers, RLTs) Reserved CRC#0 CRC#1 CRC#2 CRC#3 Reserved GPIO PPC RIC PPU Reserved Reserved Reserved PPU No 21 19 16 17 18 34 33 35 32 37 38 42 43 63 64 66 68 70 71 72 73 74 75 76 - S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) START Address B480_0000 B480_0400 B480_0800 B480_0C00 B480_1000 B480_1400 B480_1800 B480_1C00 B480_2000 B480_8000 B480_8400 B480_8800 B480_8C00 B480_9000 B480_9400 B480_9800 B480_9C00 B480_A000 B480_A400 B480_A800 B480_AC00 B480_B000 B482_0000 B482_0400 B482_0800 B482_0C00 B482_1000 B482_1400 B482_1800 B482_8000 B482_8400 B482_8800 B482_8C00 B482_9000 B482_9400 B482_9800 B483_0000 B483_0400 B483_0800 B483_0C00 B483_1000 B483_1400 B483_1800 B483_FC00 B484_0000 B485_0000 B48A_0000 B48B_1000 B48B_FC00 B48C_0000 B490_0000 B491_0000 B492_0000 B4C0_0000 B500_0000 B600_0000 B700_0000 B780_0000 B7C0_0000 B800_0000 FFFE_E000 FFFE_FC00 END Address B480_03FF B480_07FF B480_0BFF B480_0FFF B480_13FF B480_17FF B480_1BFF B480_1FFF B480_7FFF B480_83FF B480_87FF B480_8BFF B480_8FFF B480_93FF B480_97FF B480_9BFF B480_9FFF B480_A3FF B480_A7FF B480_ABFF B480_AFFF B481_FFFF B482_03FF B482_07FF B482_0BFF B482_0FFF B482_13FF B482_17FF B482_7FFF B482_83FF B482_87FF B482_8BFF B482_8FFF B482_93FF B482_97FF B482_FFFF B483_03FF B483_07FF B483_0BFF B483_0FFF B483_13FF B483_17FF B483_FBFF B483_FFFF B484_FFFF B489_FFFF B48B_0FFF B48B_FBFF B48B_FFFF B48F_FFFF B490_FFFF B491_FFFF B4BF_FFFF B4FF_FFFF B5FF_FFFF B6FF_FFFF B77F_FFFF B7BF_FFFF B7FF_FFFF FFFE_DFFF FFFE_FBFC FFFE_FFFF CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 CommonPERI #0 APPS #5 CommonPERI #0 CommonPERI #0 Bit RMW alias Bit RMW alias Bit RMW alias Error Config Error Config June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL Function M.F.Serial ch.0 M.F.Serial ch.1 M.F.Serial ch.2 M.F.Serial ch.3 M.F.Serial ch.4 M.F.Serial ch.5 M.F.Serial ch.6 M.F.Serial ch.7 Reserved BaseTimer ch.0 BaseTimer ch.1 BaseTimer ch.2 BaseTimer ch.3 BaseTimer ch.4 BaseTimer ch.5 BaseTimer ch.6 BaseTimer ch.7 BaseTimer ch.8 BaseTimer ch.9 BaseTimer ch.10 BaseTimer ch.11 Reserved FRT ch.0 FRT ch.1 FRT ch.2 FRT ch.3 FRT ch.4 FRT ch.5 Reserved ICU ch.0 / ch1 ICU ch.2 / ch3 ICU ch.4 / ch5 ICU ch.6 / ch7 ICU ch.8 / ch9 ICU ch.10 / ch11 Reserved OCU ch.0 / ch1 OCU ch.2 / ch3 OCU ch.4 / ch5 OCU ch.6 / ch7 OCU ch.8 / ch9 OCU ch.10 / ch11 Reserved Reserved APPS#5 area Reserved Reserved Reserved Reserved Reserved CAN_FD ch0 CAN_FD ch1 Reserved Bit RMW alias for CPERI#0(Covers B490_0000 -- B497_FFFF) Reserved Reserved Bit RMW alias for CPERI#2 (Covers B470_0000 -- B47F_FFFF) Bit RMW alias for CPERI#0 (Covers B480_0000 -- B487_FFFF) Reserved Reserved IRC BootROM I/F PPU No 176 177 178 179 180 181 182 183 88 89 90 91 92 93 94 95 96 97 98 99 208 209 210 211 212 213 224 225 226 227 228 229 240 241 242 243 244 245 256 257 20 41 D a t a S h e e t ( P r e l i m i n a r y ) - APPS#5 area START Address B484_0000 B484_0400 B484_0800 B484_0C00 B484_1000 B484_1400 B484_1800 B484_1C00 B484_2000 B484_2400 B484_2800 B484_2C00 B484_3000 B484_3400 B484_3800 B484_3C00 B484_4000 B484_4400 B484_4800 B484_4C00 B484_5000 B484_5400 B484_5800 B484_5C00 B484_6000 B484_6400 B484_6800 B484_6C00 B484_7000 B484_7400 B484_7800 B484_7C00 B484_8000 B484_8400 B484_8800 B484_8C00 42 CONFIDENTIAL END Address B484_03FF B484_07FF B484_0BFF B484_0FFF B484_13FF B484_17FF B484_1BFF B484_1FFF B484_23FF B484_27FF B484_2BFF B484_2FFF B484_33FF B484_37FF B484_3BFF B484_3FFF B484_43FF B484_47FF B484_4BFF B484_4FFF B484_53FF B484_57FF B484_5BFF B484_5FFF B484_63FF B484_67FF B484_6BFF B484_6FFF B484_73FF B484_77FF B484_7BFF B484_7FFF B484_83FF B484_87FF B484_8BFF B484_FFFF Group APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 APPS #5 Function M.F.Serial ch.8 M.F.Serial ch.9 M.F.Serial ch.10 M.F.Serial ch.11 M.F.Serial ch.12 M.F.Serial ch.13 M.F.Serial ch.14 M.F.Serial ch.15 M.F.Serial ch.16 M.F.Serial ch.17 M.F.Serial ch.18 M.F.Serial ch.19 M.F.Serial ch.20 M.F.Serial ch.21 BaseTimer ch.12 BaseTimer ch.13 BaseTimer ch.14 BaseTimer ch.15 BaseTimer ch.16 BaseTimer ch.17 BaseTimer ch.18 BaseTimer ch.19 BaseTimer ch.20 BaseTimer ch.21 BaseTimer ch.22 BaseTimer ch.23 BaseTimer ch.24 BaseTimer ch.25 BaseTimer ch.26 BaseTimer ch.27 BaseTimer ch.28 BaseTimer ch.29 A/D unit0 A/D unit1 , Partial Wake Up A/D analog input control Reserved PPU No 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 - S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 11. PIN STATUSES IN CPU STATUS Table 11-1 Pin state table (1/2) 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 10 9 11 P009/IN10_0/SIN8_0/TIOA1_0/INT0_1 13 14 15 16 17 12 13 14 15 16 17 18 19 20 21 18 22 P020/SOT0_0/TIOB1_0/TEXT1_0 19 23 P021/SCK4_1/SCK0_0/TIOB2_0 20 24 P022/SIN0_0/TIOB3_0/INT3_0 21 22 52 53 54 55 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 47 48 49 50 51 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 56 70 P130/IN7_1/SIN6_0/AN23/INT5_0 57 71 P131/IN8_1/SOT6_0/AN24 72 P200/SCS202_0/AN25/TIOA17_0 73 P201/SIN20_0/AN26/TIOA18_0 58 74 P202/IN9_1/SCK6_0/INT6_1 59 60 61 62 75 76 77 78 63 79 P207/SCK4_0/AN30/INT7_1/TEXT5_1 64 65 80 P208/SCS42_0/AN31/TIOA19_0 81 P209/SOT4_0/AN32/TIOA20_0 23 24 25 26 27 28 29 30 31 32 33 34 35 39 40 41 45 46 47 48 49 50 51 P010/IN11_0/SOT8_0/TIOA2_0 P011/SIN18_1/TIOA2_1 P012/OUT5_0/SCK8_0/TIOA3_0 P013/OUT6_0/SCS80_0/TIOA4_0 P014/SOT18_1/TIOA3_1 P015/OUT7_0/SCS81_0/TIOA5_0 P016/OUT8_0/SCS82_0/TIOA6_0 P017/OUT9_0/SCS83_0/TIOA7_0 P018/OUT10_0/TIOA8_0 P019/OUT11_0/TIOB0_0/TEXT0_0 P023/SIN4_1/SCS0_0/TIOB4_0 P024/SOT4_1/TIOB5_0 P025/SCS40_1 P026/SCS41_1 P027/SCS42_1/TIOA4_1/TIOB6_0/INT1_1/TEXT0_1 P028/OUT0_1/SIN1_0/TIOB7_0/INT4_0 P029/OUT1_1/SOT1_0/AN0 P030/OUT2_1/SCS43_1 P031/OUT3_1/SCS1_0/AN1 P100/OUT4_1/SCK1_0/AN2 P101/OUT5_1/AN3 P102/AN4 P103/OUT6_1/SIN17_0/AN5 P104/SOT17_0 P105/OUT7_1/SCK17_0/TIOA9_0 P106/OUT8_1/TX1_2/SCS170_0 P107/OUT9_1/RX1_2/SIN19_0/TIOA10_0/INT2_1 P108/OUT10_1/SOT19_0/AN6/TIOA11_0/INT3_1 P109/OUT11_1/SIN19_1/SCK19_0/TIOA12_0 P110/SCS190_0/AN7 P111/SIN18_0/AN8 P112/SOT18_0/AN9/TIOA13_0 P113/SOT19_1/SCK18_0/TIOA5_1 P114/SCS180_0/AN10/TIOA6_1 P115 P116/AN11 P117/AN12/INT4_1 P118/AN13/INT5_1 P119/SCS60_0/AN14 P120/SCS61_0/AN15 P121/SCS160_0/AN16/TIOA14_0 P122/SCS62_0/AN17/TIOA11_1 P123/SCS63_0/AN18/TIOA12_1 P124/SIN16_0/TIOA15_0 P125/SOT16_0/TIOA16_0 P126/SCK16_0/AN19 P127/SCS203_0/AN20/TEXT1_1 P128/SCS200_0/AN21/TEXT2_1 P129/IN6_1/SCS201_0/AN22 Controlled Hiz/Input turned off P203/IN10_1 P204/IN11_1/SOT20_0/AN27 P205/SCK20_0/AN28/TEXT3_1 P206/SCS43_0/AN29/TEXT4_1 66 82 P210/IN0_2/SIN4_0/AN33/TIOA21_0/INT6_0 67 68 83 P211/IN1_2/SCS40_0/AN34/TIOA22_0 84 P212/IN2_2/SCS50_1/SCS41_0/AN35/TIOA13_1 69 85 P213/IN3_2/SIN5_1/TIOA14_1/INT8_1 70 86 P214/IN4_2/SOT5_1/TIOA15_1 71 87 P215/IN5_2/SCK5_1/TIOA16_1/INT9_1 June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL Hiz/ Previous Hiz/Input turned off value retained Hiz/Input turned off Hiz/Input turned off Status Last state immediately retained before the shutdown retaine When High Impedance Enabled (SYSC_SSPECFGR. PSSPADCTRL=1) Watch *4 When High Impedance Disabled (SYSC_SSPECFGR. PSSPADCTRL=0) When High Impedance Enabled (SYSC_SSPECFGR. PSSPADCTRL=1) Stop *4 When High Impedance Disabled (SYSC_SSPECFGR. PSSPADCTRL=0) Sleep CPU Sleep Internal Reset Factor *2 After Issuing Internal Reset (Before Setting GPORT) External Reset Factor 3 While Issuing Internal Reset After Issuing Internal Reset (Before Setting GPORT) After Releasing External Factor While Issuing Internal Reset While Issuing Internal Reset Before Issuing Internal Reset After Issuing Internal Reset (Before Setting GPORT) External Reset Factor 2 While Generating External Factor P000/SOT2_1 P001/SCS20_1 P002/SCS21_1/TIOA0_1 P003/SCS22_1 P004/SCS23_1/TIOA1_1 P005/IN6_0/SIN3_0 P006/IN7_0/SOT3_0 P007/IN8_0/SCK18_1/SCK3_0 P008/IN9_0/SCS180_1/SCS30_0/TIOA0_0 10 11 12 GPORTEN Control After Releasing External Factor While Issuing Internal Reset Pin Name While Issuing Internal Reset Pin No. 端子番号 (144Pin) External Reset Factor 1 While Generating External Factor Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Last state retained (*3) Hiz/Input turned off (*1) Last state retained (*3) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) 43 D a t a S h e e t ( P r e l i m i n a r y ) Table 11-2Pin state table (2/2) When High Impedance Enabled (SYSC_SSPECFGR. PSSPADCTRL=1) Watch *4 When High Impedance Disabled (SYSC_SSPECFGR. PSSPADCTRL=0) When High Impedance Enabled (SYSC_SSPECFGR. PSSPADCTRL=1) Stop *4 When High Impedance Disabled (SYSC_SSPECFGR. PSSPADCTRL=0) Sleep CPU Sleep After Issuing Internal Reset (Before Setting GPORT) External Reset Factor 3 While Issuing Internal Reset After Issuing Internal Reset (Before Setting GPORT) While Issuing Internal Reset While Issuing Internal Reset After Releasing External Factor Internal Reset Factor *2 External Reset Factor 2 While Generating External Factor Before Issuing Internal Reset After Issuing Internal Reset (Before Setting GPORT) While Issuing Internal Reset GPORTEN Control After Releasing External Factor P216/SIN15_0 P217/SOT15_0 P218/SCK15_0/AN36/TEXT2_0 P219/SCS150_0/AN37/TEXT3_0 P220/IN6_2/SCS53_0/AN38 P221/SCS52_0 Hiz/Input turned off Hiz/Input turned off 77 96 P222/IN7_2/SIN5_0/AN39/INT7_0 Hiz/Input turned off (*1) Hiz/Input turned off (*1) 78 79 97 P223/IN8_2/PWU_AN0/SCS51_0/AN40 98 P224/IN9_2/PWU_AN1/TX0_2/SCS50_0/AN41 80 99 P225/IN10_2/PWU_AN2/RX0_2/SOT5_0/AN42/INT0_0 81 85 86 100 P226/IN11_2/PWU_AN3/SCK5_0/AN43/TIOA17_1 104 P227/PWU_AN4/SCK10_0/AN44/TIOA23_0 105 P228/PWU_AN5/TX0_1/SOT10_0/AN45/TIOA24_0 74 75 76 90 91 92 93 94 95 Pin Name While Issuing Internal Reset While Generating External Factor Pin No. 端子番号 (144Pin) External Reset Factor 1 87 106 P229/OUT0_0/PWU_AN6/RX0_1/SIN10_0/AN46/TIOA25_0/INT8_0 88 89 90 91 92 93 94 95 107 108 109 110 111 112 113 114 115 96 116 P306/TX0_0/SCS73_0/AN54 97 117 P307/RX0_0/SCS72_0/AN55/INT1_0 98 99 118 P308/IN0_1/SCK13_0/AN56/TIOA28_1 119 P309/IN1_1/SCS130_0/AN57/TIOA29_1 P230/OUT1_0/PWU_AN7/SCS103_0/AN47/TIOA26_0 P231/OUT2_0/SCS102_0/AN48/TIOA27_0 P300/OUT3_0/SCS101_0/AN49/TIOA28_0 P301/OUT4_0/SCS100_0/AN50/TIOA18_1 P302/SIN14_0/AN51/TIOA19_1 P303/SOT14_0 P304/SCK14_0/AN52/TIOA20_1/TEXT4_0 P305/SCS140_0/AN53/TIOA29_0/TEXT5_0 NMIX Controlled - Hiz/Input turned off Input enabled Hiz /Previous Hiz/Input value turned off retained Input enabled Hiz/Input turned off Input enabled Hiz/Input turned off Input enabled Status immediately Last state before the retained shutdown retaine Input enabled Input enabled Last state retained (*3) Controlled Hiz/Input turned off Hiz /Previous Hiz/Input value turned off retained Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off Input enabled Hiz/Input turned off Input enabled Hiz/Input turned off Status Last state immediately before the retained shutdown retaine Input enabled Input enabled Input enabled Input enabled 123 151 RSTX - - Input enabled Input enabled Hiz/Input turned off Hiz /Previous Hiz/Input value turned off retained Hiz/Input turned off Hiz/Input turned off Controlled - Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled - - - - - - - Controlled Hiz/Input turned off - Input enabled Hiz /Previous value retained Hiz/Input turned off Input enabled Hiz/Input turned off Hiz/Input turned off Input enabled Input enabled Status immediately Last state before the retained shutdown retaine Input enabled Input enabled Last state retained (*3) Last state retained (*3) 135 163 P409/SOT2_0/TIOA24_1/TRACEDATA6 164 P410/SCS70_1 140 171 P417/SOT7_1/SCS110_0/TIOA23_1/INT15_1 141 172 P418/SCS22_0/SIN12_0/INT14_0 173 P419/SCS23_0/SOT12_0/TIOA27_1 142 174 P420/SCK2_1/SCK12_0/TRACECLK 143 175 P421/SIN2_1/SCS120_0/TRACECTL 44 CONFIDENTIAL Hiz/Input turned off (*1) Last state retained (*3) Controlled Hiz/Input turned off Hiz /Previous Hiz/Input turned off value retained Hiz/Input turned off Hiz/Input turned off Status immediately Last state before the retained shutdown retaine - Hiz/Input turned off Last state retained (*3) Hiz/Input turned off Input enabled Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Last state retained (*3) Hiz/Input turned off Input enabled Hiz/Input turned off (*1) 134 162 P408/SIN2_0/INT12_0/TRACEDATA5 139 170 P416/IN5_0/SIN7_1/SCK11_0/TIOA22_1 Hiz/Input turned off Input enabled Hiz/Input turned off 132 160 P406/SOT9_0/TRACEDATA3 133 161 P407/SCK7_1/SCK9_0/TRACEDATA4 169 P415/SOT11_0/TIOA26_1/INT13_0 Hiz/Input turned off (*1) Hiz/Input turned off (*1) Status immediately Last state before the retained shutdown retaine 131 159 P405/IN4_0/SIN9_0/INT11_0/TRACEDATA2 138 168 P414/SCS21_0/SIN11_0 Hiz/Input turned off - 129 157 P403/IN2_0/TRACEDATA0 130 158 P404/IN3_0/TRACEDATA1 137 167 P413/SCS73_1/SCS20_0/INT14_1 Hiz/Input turned off Input enabled 128 156 P402/IN1_0/RX1_0/SCS63_1/SCS90_0/INT2_0 166 P412/SCS72_1/TIOA25_1 Hiz/Input turned off Hiz/Input turned off (*1) - 127 155 P401/IN0_0/TX1_0/SCS62_1 136 165 P411/SCS71_1/SCK2_0/INT13_1/TRACEDATA7 Last state retained (*3) Hiz/Input turned off (*1) Hiz/Input Hiz/Input turned off turned off Input enabled Input (Status Input enabled Input enabled Input enabled Input enabled enabled (Last state (Hiz/Input (Last state (Hiz/Input immediately (Last state retained (*3)) turned off) retained (*3)) turned off) before the retained) (*6) *6 (*6) *6 shutdown retaine) *6 *6 Input Input enabled Input enabled Input enabled enabled 139 P325/SIN21_0/INT10_0 122 150 P400/SCS61_1 Hiz/Input turned off (*1) Input enabled - 113 137 TMS 114 138 TCK 116 117 118 119 121 Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off Last state retained (*3) Hiz/Input turned off (*1) Hiz/Input turned off Last state retained (*3) (*5) 130 P320/PWUTRG/WOT 115 Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) 107 131 P321 110 134 TRST/P322 111 135 TDO/P323 P326/SOT21_0 P327/SCK6_1/SCK21_0 P328/SOT6_1/SCS210_0 P329/SIN6_1 P330 MD X0 X1 P331/SCS60_1 Last state retained (*3) Hiz/Input turned off (*1) 102 124 P314/IN4_1/SCK7_0/AN60/TIOA7_1 103 125 P315/IN5_1/SCS70_0/AN61/TIOA8_1 126 P316/TIOA21_1 104 127 P317/TX1_1/AN62/TIOA9_1/INT11_1 105 128 P318/RX1_1/TIOA10_1/INT9_0 106 129 P319/SIN7_0/AN63/INT12_1 140 141 142 143 144 145 146 147 149 Hiz/Input turned off (*1) Hiz/Input turned off (*1) 101 123 P313/IN3_1/SOT7_0/AN59/INT10_1 112 136 TDI/P324 Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off 120 P310/SIN13_0/INT15_0 121 P311/SOT13_0 100 122 P312/IN2_1/SCS71_0/AN58 Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off Last state retained (*3) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off Hiz/Input turned off (*1) Hiz/Input turned off (*1) Hiz/Input turned off Hiz/Input turned off S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) *1: Input disable is not valid when external interrupts are enabled. *2: Recovery from standby (power off) becomes a factor. *3: The pin state from the time that HOLDIO_PD2 was set (SYSC_SSPECFGR.HOLDIO_PD2=1) is retained. If power-off has not occurred and HOLDIO_PD2 has not been set (SYSC_SSPECFGR.HOLDIO_PD2=0), the last state is retained. *4: To power off power domains 2 and 3, be sure to set HOLDIO_PD2 (SYSC_SSPECFGR.HOLDIO_PD2=1). *5: When the PWU function is enabled, a change to output occurs. *6: The pin state when the PORT function is enabled is shown. -External Reset Factor 1 Power-on reset (PONR) RAM retention low-voltage detection reset (RVD) Internal power supply low-voltage detection reset (LVDL1R) RSTX pin + MD pin simultaneous assert reset (INITX) -External Reset Factor 2 RSTX pin input reset (RSTX) -External Reset Factor 3 Hardware watchdog reset (HWDR) Software watchdog reset (SWDR) PLL clock supervisor reset (CSVPRn) SSCG clock supervisor reset (CSVSRn) Profile error reset (PRFERR) Software trigger hard reset (SHRST) Software reset (SRST) -Internal Reset Factor 4 Standby transition reset/ Power domain reset June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 45 D a t a S h e e t ( P r e l i m i n a r y ) 12. ELECTRICAL CHARACTERISTICS 12.1 Absolute Maximum Ratings Parameter Symbol Power supply voltage*1, *2 *1 *2 Analog supply voltage , *1 Analog reference voltage *1 Rating Unit Max VCC VSS-0.3 VSS+6.0 V AVCC VSS-0.3 VSS+6.0 V Avcc≤Vcc AVRH VSS-0.3 VSS+6.0 V AVRH≤AVCC Input voltage VI VSS-0.3 VCC+0.3 V Analog pin input voltage*1 VIA VSS-0.3 VCC+0.3 V VO VSS-0.3 VCC+0.3 V ICLAMP - 4 mA *1 Output voltage Maximum clamp current Total maximum clamp current "L"-level maximum output current*3 "L"-level average output current*4 Remarks Min *7 Σ|ICLAMP | - 20 mA *7 IOL1 - 3.5 mA When setting is 1 mA*6 IOL2 - 7 mA When setting is 2 mA IOLAV1 - 1 mA When setting is 1 mA*6 IOLAV2 - 2 mA When setting is 2 mA ΣIOL - 40 mA *6 IOH1 - -3.5 mA When setting is 1 mA*6 IOH2 - -7 mA When setting is 2 mA IOHAV1 - -1 mA When setting is 1 mA*6 IOHAV2 - -2 mA When setting is 2 mA ΣIOH - -40 mA *6 Power consumption PD - 2000 mW Operating temperature TA -40 +105 ℃ Tstg -55 +150 ℃ "L"-level total output current*5 "H"-level maximum output current*3 "H"-level average output current*4 "H"-level total output current*5 Storage temperature S6J311EJAA *1: VSS=AVSS=0.0 V is used as a reference. *2: Take care that AVCC does not exceed VCC at, for example, the power-on time. *3: The definition of maximum output current is the peak current value of the relevant pin. *4: The definition of average output current is the average value of current flowing into the relevant pin for 10 ms. The average value means operating current x operating rate. *5: The definition of total output current is the maximum value of the current flowing into all the relevant pins. *6: Relevant pins: All general-purpose ports 46 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) *7: Relevant pins: All general-purpose ports and analog input pins − Use the device within the recommended operating conditions. − Use the device with direct voltage (current). − Be sure to connect a limiting resistor between a +B signal and microcontroller to apply the +B signal. − Set the limiting resistor value such that the current input into a microcontroller pin at the +B input time is equal to or less than the standard value regardless of whether it is instantaneous or stationary. − Note that +B input potential increases the potential of a Vcc pin through a diode under operating conditions where there is less drive current for the microcontroller (such as in low-power consumption mode). This characteristic may affect other devices. − If the microcontroller power is off (not fixed at 0 V) and there is +B input, power is supplied from pins. Note that faulty operation may occur in this case. − If there is +B input at the power-on time, power is supplied from pins. Note that the supply voltage may be insufficient for the operation of a power-on reset in this case. − Make sure that +B input pins are not open. Example of a recommended circuit WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings.Do not exceed any of these ratings. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 47 D a t a S h e e t ( P r e l i m i n a r y ) 12.2 Recommended operating conditions (VSS=AVSS=0.0 V) Parameter Supply voltage Rating Symbol Min Max Unit VCC 4.5 5.25 V AVCC 4.5 5.25 V VCC 3.5 5.25 V AVCC 3.5 5.25 V Smoothing capacitor* CS Operating temperature TA 4.7 -40 +105 Remarks Recommended operation assurance range Operation assurance range µF Tolerance of up to ±40% °C S6J311EJAA *: For the connections of smoothing capacitor CS, see the following diagram. ・C pin connection diagram C CS VSS VSS AVSS WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. 48 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 12.3 DC characteristics (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Symbol Pin Name Conditions Value Unit Min Typ Max 0.7×VCC - VCC+0.3 V 0.8×VCC - VCC+0.3 V Remarks P000 to P031, VIH1 P100 to P131, CMOS P200 to P231, Schmitt P300 to P320, input level P325 to P331, selected P400 to P421 "H" level input voltage Automotive VIH2 P401 to P421 input level selected VIH4 RSTX, NMIX - 0.7×VCC - VCC+0.3 V VIH5 MD - 0.7×VCC - VCC+0.3 V TTL 2.0 - VCC+0.3 V Vss-0.3 - 0.3×VCC V Vss-0.3 - 0.5×VCC V VIH6 TRST, TCK, TDI, TMS P000 to P031, VIL1 P100 to P131, CMOS P200 to P231, Schmitt P300 to P320, input level P325 to P331, selected P400 to P421 "L" level input voltage Automotive VIL2 P401 to P421 input level selected VIL4 RSTX, NMIX - Vss-0.3 - 0.3×VCC V VIL5 MD - Vss-0.3 - 0.3×VCC V TTL Vss-0.3 - 0.8 V VIL6 TRST, TCK, TDI, TMS June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 49 D a t a S h e e t ( P r e l i m i n a r y ) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Symbol Pin Name Conditions Value Unit Min Typ Max Vcc-0.5 - Vcc V Vcc-0.5 - Vcc V 0 - 0.4 V 0 - 0.4 V Remarks P000 to P031, P100 to P131, "H" level output voltage P200 to P231, VOH1 P300 to P320, P321 to P324 Vcc=4.5 V IOH=-2.0 mA P325 to P331, P400 to P421 P000 to P031, P100 to P131, "H" level output voltage VOH2 P200 to P231, Vcc=4.5 V P300 to P320, IOH=-1.0 mA P325 to P331, P400 to P421 P000 to P031, P100 to P131, "L" level output voltage P200 to P231, VOL1 P300 to P320, P321 to P324 Vcc=4.5 V IOL=2.0 mA P325 to P331, P400 to P421 P000 to P031, P100 to P131, "L" level output voltage VOL2 P200 to P231, Vcc=4.5 V P300 to P320, IOL=1.0 mA P325 to P331, P400 to P421 50 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Input leakage current Symbol Pin Name IIL All input pins RUP1 RSTX, NMIX Conditions Value Unit Min Typ Max -5 - +5 µA 25 - 100 kΩ 25 - 100 kΩ 25 - 100 kΩ 25 - 100 kΩ - 25 - 100 kΩ - - 5 15 pF Vcc=AVCC=5.25 V VSS < VI < VCC - Remarks P000 to P031, P100 to P131, Pull-up RUP2 resistor P200 to P231, Pull-up resistor P300 to P320, selected P325 to P331, P400 to P421 RUP3 TDI(P324),TMS, TCK - P000 to P031, P100 to P131, Pull-down Rdown1 resistor P200 to P231, Pull-down resistor P300 to P320, selected P325 to P331, P400 to P421 Rdown2 TRST(P322) Pins other than Input capacitance CIN VCC, VSS, AVCC0,AVCC1, AVSS0,AVSS1 June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 51 D a t a S h e e t ( P r e l i m i n a r y ) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Symbol Pin Name Conditions Normal operation ICC5 Flash write/erase Power Value Unit Typ Max - 140 320 mA Operating at 144 MHz - 160 343 mA Operating at 144 MHz Operating at 144 MHz ICCS5 CPU Sleep - 82 265 mA ICCT5 Timer mode - 946.0 2967.9 µA Stop mode - 945.1 2966.2 µA - 53.4 130.6 µA - 47.1 116.4 µA - 40.9 102.3 µA - 40.1 101.4 µA supply current S6J311EJ AA ICCH5 ICCP ICCT52 ICCH52 VCC PWU mode (Shutdown) Timer mode (Shutdown) Stop mode (Shutdown) Remarks Min TA=25°C Slow-CR source Oscillation TA=25°C TA=25°C (PWU operation cycle 16ms) TA=25°C (PWU operation cycle 32ms) TA=25°C Slow-CR source Oscillation TA=25°C Refer to Hardware manual “APPENDIX State transition” for Internal clock frequency setting / Setting of the power domain / Regulator setting. 52 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 12.4 AC characteristics 12.4.1 Source clock timing (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Source oscillation clock frequency Source oscillation clock cycle time CAN PLL jitter (when locked) Internal Slow CR oscillation frequency Internal Fast CR oscillation frequency Value Pin Cond Name itions Min Typ Max FC X0, X1 - - 4 - MHz tCYL X0, X1 - - 250 - ns tPJ - - -10 - +10 ns FCRS - - 50 100 150 kHz FCRF - - 2.4 4 6.0 MHz Symbol Unit Remarks * *: The maximum/minimum values have been standardized with the main clock and PLL clock in use. − X0 and X1 clock timing tCYL X0 − CAN PLL jitter A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles. t1 t2 t3 tn-1 tn Ideal clock Slow PLL output t1 t2 t3 tn-1 tn Fast June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 53 D a t a S h e e t ( P r e l i m i n a r y ) 12.4.2 Parameter Internal clock timing (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Symbol Pin Name Conditions S6J311EJAA Value Min Typ Max Unit Remarks FCD0_CLK - - - - 144 MHz CD0_CLK FCLK_CPU - - - - 144 MHz CLK_CPU FCLK_FCLK - - - - 72 MHz CLK_FCLK FCLK_ATB - - - - 72 MHz CLK_ATB FCLK_DBG - - - - 72 MHz CLK_DBG FCLK_HPM - - - - 36 MHz CLK_HPM FCLK_HPM2 - - - - 18 MHz CLK_HPM2 FCLK_DMA - - - - 36 MHz CLK_DMA FCLK_MEMC - - - - 36 MHz CLK_MEMC FCLK_SYSC1 - - - - 36 MHz CLK_SYSC1 FCLK_HAPP0A0 - - - - 36 MHz CLK_HAPP0A0 FCLK_HAPP0A1 - - - - 36 MHz CLK_HAPP0A1 FCLK_HAPP1B0 - - - - 36 MHz CLK_HAPP1B0 FCLK_HAPP1B1 - - - - 36 MHz CLK_HAPP1B1 Internal clock FCLK_LLPBM - - - - 144 MHz CLK_LLPBM frequency FCLK_LLPBM2 - - - - 72 MHz CLK_LLPBM2 FCLK_LCP - - - - 72 MHz CLK_LCP 54 CONFIDENTIAL FCLK_LCP0 - - - - 36 MHz CLK_LCP0 FCLK_LCP0A - - - - 36 MHz CLK_LCP0A FCLK_LAPPA0 - - - - 36 MHz CLK_LAPP0 FCLK_LAPPA0A - - - - 36 MHz CLK_LAPP0A FCLK_LAPP1 - - - - 36 MHz CLK_LAPP1 FCLK_LAPP1A - - - - 36 MHz CLK_LAPP1A FCLK_TRC - - - - 36 MHz CLK_TRC FCLK_SYSC0H - - - - 36 MHz CLK_SYSC0H FCLK_COMH - - - - 36 MHz CLK_COMH FCLK_RAM0H - - - - 36 MHz CLK_RAM0H FCLK_RAM1H - - - - 36 MHz CLK_RAM1H FCLK_SYSC0P - - - - 36 MHz CLK_SYSCP0 FCLK_COMP - - - - 36 MHz CLK_COMP S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) Parameter Symbol Pin Name Conditions S6J311EJAA Value Min Typ Max Unit Remarks tCD0_CLK - - 6.9 - - ns CD0_CLK tCLK_CPU - - 6.9 - - ns CLK_CPU tCLK_FCLK - - 13.8 - - ns CLK_FCLK tCLK_ATB - - 13.8 - - ns CLK_ATB tCLK_DBG - - 13.8 - - ns CLK_DBG tCLK_HPM - - 27.7 - - ns CLK_HPM tCLK_HPM2 - - 55.5 - - ns CLK_HPM2 tCLK_FMA - - 27.7 - - ns CLK_DMA tCLK_MEMC - - 27.7 - - ns CLK_MEMC tCLK_SYSC1 - - 27.7 - - ns CLK_SYSC1 tCLK_HAPP0A0 - - 27.7 - - ns CLK_HAPP0A0 tCLK_HAPP0A1 - - 27.7 - - ns CLK_HAPP0A1 tCLK_HAPP1B0 - - 27.7 - - ns CLK_HAPP1B0 tCLK_HAPP1B1 - - 27.7 - - ns CLK_HAPP1B1 Internal clock tCLK_LLPBM - - 6.9 - - ns CLK_LLPBM cycle time tCLK_LLPBM2 - - 13.8 - - ns CLK_LLPBM2 tCLK_LCP - - 13.8 - - ns CLK_LCP tCLK_LCP0 - - 27.7 - - ns CLK_LCP0 tCLK_LCP0A - - 27.7 - - ns CLK_LCP0A tCLK_LAPP0 - - 27.7 - - ns CLK_LAPP0 tCLK_LAPP0A - - 27.7 - - ns CLK_LAPP0A tCLK_LAPP1 - - 41.6 - - ns CLK_LAPP1 tCLK_LAPP1A - - 41.6 - - ns CLK_LAPP1A tCLK_TRC - - 27.7 - - ns CLK_TRC tCLK_SYSC0H - - 27.7 - - ns CLK_SYSC0H tCLK_COMH - - 27.7 - - ns CLK_COMH tCLK_RAM0H - - 27.7 - - ns CLK_RAM0H tCLK_RAM1H - - 27.7 - - ns CLK_RAM1H tCLK_SYSC0P - - 27.7 - - ns CLK_SYSCP0 tCLK_COMP - - 27.7 - - ns CLK_COMP June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 55 D a t a S h e e t ( P r e l i m i n a r y ) − Operation assurance range Relationship between the internal clock frequency and supply voltage 3.5 2 4 144 Internal clock frequency FCDO_CLK(MHz) Note: A supply voltage that is equal to or less than the set voltage for low-voltage detection causes a reset. Relationship between the oscillation clock frequency and internal clock frequency Oscillation Clock Frequency − Main Clock PLL Multiplier PLL Output Division Setting Setting PLL Clock 4 MHz 4 MHz 144 4 144 MHz 4 MHz 4 MHz 144 6 96 MHz Oscillation circuit example X0 X1 R C1 C2 Note: For the configuration of an oscillation circuit, request the oscillator manufacturer to perform a circuit matching evaluation before starting design. 56 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) The following measurement reference voltage values define the alternate current standard Input signal waveform − − Output signal waveform Output pin Hysteresis input pin (Automotive) 0.8Vcc 2.4V 0.5Vcc 0.8V Hysteresis input pin (CMOS Schmitt) 0.7Vcc 0.3Vcc Hysteresis input pin (TTL) 2.0V 0.8V 12.4.3 Reset input Parameter Symbol (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Pin Name Conditions Reset input time tRSTL Reset RSTX Value Unit Min Max 10 - µs 1 - µs Remarks - input reduction width tRSTL RSTX 0.2Vcc June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 0.2Vcc 57 D a t a S h e e t ( P r e l i m i n a r y ) 12.4.4 Power-on and power-on conditions (TA: Recommended operating conditions, VSS=0.0 V) Parameter Symbol Level detection voltage Level detection hysteresis width Level detection time Pin Name Conditions Value Min Typ Max Unit Remarks - VCC - 2.25 2.45 2.65 V - VCC - - 100 - mV - - - - - 30 μs *1 - - 4 mV/µs *2 50 - - ms *3 VCC = at level Slope detection undetected standard - VCC detection release level time Power off time - VCC - *1: If a power fluctuation precedes the low-voltage detection time, the detection may occur or be canceled after the supply voltage passes the detection voltage range. *2: This time is a period that begins when the power supply is turned off and ends when an internal charge is released and tilt detection becomes possible for the next power-on. *3: This time is to start the slope detection at next power on after power down and internal charge loss. 58 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 12.4.5 Multi-function serial 12.4.5.1 CSIO timing (SMR:MD2-0=0b010) (5-1-1) Normal synchronous transfer (SCR:SPI=0) and mark level "H" of serial clock output (SMR:SCINV=0) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Serial clock cycle time SCK falling -> SOT delay time Valid SIN -> SCK rising setup time SCK rising -> Valid SIN hold time Serial clock Symbol Pin Name tSCYC SCK0 to SCK21 tSLOVI tIVSHI tSHIXI Conditions Master mode SCK0 to SCK21 (CL=50pF, SOT0 to SOT21 IOL=-2mA, SCK0 to SCK21, (CL=20pF, SIN0 to SIN21 IOL=-1mA, IOH=2mA), IOH=1mA) tSHSL "H" pulse width Value Unit Min Max 4tCLK_LCP0A - ns -30 +30 ns 30 - ns 0 - ns tCLK_LCP0A +10 - ns 2tCLK_LCP0A -10 - ns - 45 ns 10 - ns 20 - ns - 5 ns - 5 ns Remarks SCK0 to SCK21 Serial clock tSLSH "L" pulse width SCK falling -> SOT delay time Valid SIN -> SCK rising setup time SCK rising -> Valid SIN hold time tSLOVE tIVSHE tSHIXE Slave SCK0 to SCK21, mode SOT0 to SOT21 (CL=50pF, SCK0 to SCK21, IOH=2mA), SIN0 to SIN21 (CL=20pF, IOL=-2mA, IOL=-1mA, SCK falling time tF SCK0 to SCK21 SCK rising time tR SCK0 to SCK21 IOH=1mA) Notes: − − − This table provides the alternate current standard for CLK synchronous mode. CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 59 D a t a S h e e t ( P r e l i m i n a r y ) tSCYC SCK VOH VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL SIN VIH VIL Master mode tSLSH SCK VIH tF SOT SIN VIL tSHSL VIL VIH tR VIH tIVSHE tSHIXE tSLOVE VOH VOL VIH VIL VIH VIL Slave mode 60 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) (5-1-2) Normal synchronous transfer (SCR:SPI=0) and mark level "L" of serial clock output (SMR:SCINV=1) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Serial clock cycle time SCK rising -> SOT Symbol Pin Name tSCYC SCK0 to SCK21 tSHOVI delay time Valid SIN -> SCK falling setup time SCK falling -> Valid SIN hold time Serial clock tIVSLI tSLIXI Conditions Master mode SCK0 to SCK21, (CL=50pF, SOT0 to SOT21 IOL=-2mA, SCK0 to SCK21, (CL=20pF, SIN0 to SIN21 IOL=-1mA, IOH=2mA), IOH=1mA) tSHSL "H" pulse width Value Unit Min Max 4tCLK_LCP0A - ns -30 +30 ns 30 - ns 0 - ns tCLK_LCP0A +10 - ns 2tCLK_LCP0A -10 - ns - 45 ns 10 - ns 20 - ns - 5 ns - 5 ns Remarks SCK0 to SCK21 Serial clock tSLSH "L" pulse width SCK rising -> SOT tSHOVE delay time Valid SIN -> SCK falling setup time SCK falling -> Valid SIN hold time tIVSLE tSLIXE Slave SCK0 to SCK21, mode SOT0 to SOT21 (CL=50pF, IOL=-2mA, SCK0 to SCK21, IOH=2mA), SIN0 to SIN21 (CL=20pF, IOL=-1mA, SCK falling time tF SCK0 to SCK21 SCK rising time tR SCK0 to SCK21 IOH=1mA) Notes: − − − This table provides the alternate current standard for CLK synchronous mode. CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 61 D a t a S h e e t ( P r e l i m i n a r y ) tSCYC VOH SCK VOL tSHOVI VO VOL SOT tIVSLI tSLIXI VIH VIL SIN VIH VIL Master mode tSHSL SCK VIL tR SOT VIH tSLSH VIH tF tSHOVE VIL VOH VOL tIVSLE SIN VIL VIH VIL tSLIXE VIH VIL Slave mode 62 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) (5-1-3) SPI supported (SCR:SPI=1), and mark level "H" of serial clock output (SMR:SCINV=0) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Serial clock cycle time SCK rising -> SOT delay time Valid SIN -> SCK falling setup time SCK falling -> Valid SIN hold time SOT -> SCK falling delay time Serial clock Symbol Pin Name tSCYC SCK0 to SCK21 tSHOVI tIVSLI tSLIXI tSOVLI Conditions Master SCK0 to SCK21, mode SOT0 to SOT21 (CL=50pF, IOL=-2mA, SCK0 to SCK21, IOH=2mA), SIN0 to SIN21 (CL=20pF, IOL=-1mA, SCK0 to SCK21, IOH=1mA) SOT0 to SOT21 tSHSL "H" pulse width Value Unit Min Max 4tCLK_LCP0A - ns -30 +30 ns 30 - ns 0 - ns 2tCLK_LCP0A -30 - ns tCLK_LCP0A +10 - ns 2tCLK_LCP0A -10 - ns - 45 ns 10 - ns 20 - ns - 5 ns - 5 ns Remarks SCK0 to SCK21 Serial clock tSLSH "L" pulse width SCK rising -> SOT delay time Valid SIN -> SCK falling setup time SCK falling -> Valid SIN hold time tSHOVE tIVSLE tSLIXE Slave SCK0 to SCK21, mode SOT0 to SOT21 (CL=50pF, IOL=-2mA, SCK0 to SCK21, IOH=2mA), SIN0 to SIN21 (CL=20pF, IOL=-1mA, SCK falling time tF SCK0 to SCK21 SCK rising time tR SCK0 to SCK21 IOH=1mA) Notes: − − − This table provides the alternate current standard for CLK synchronous mode. CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 63 D a t a S h e e t ( P r e l i m i n a r y ) tSCYC SCK VOH VOL tSOVLI VOL tSHO VOH VOL SOT VOH VOL tIVSLI VIH VIL SIN tSLIXI VIH VIL Master mode tSHSL tSLSH VIH SCK SIN VIL tF * SOT VIL tR VIH VIH tSHOV VOH VOL VIL VO VOL tIVSLE VIH VIL tSLIXE VIH VIL * Changes when writing to the TDR Slave mode 64 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) (5-1-4) SPI supported (SCR:SPI=1), and mark level "L" of serial clock output (SMR:SCINV=1) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Serial clock cycle time SCK falling -> SOT Symbol Pin Name tSCYC SCK0 to SCK21 tSLOVI delay time Valid SIN -> SCK rising tIVSHI setup time SCK rising -> Valid SIN tSHIXI hold time SOT -> SCK rising tSOVHI delay time Serial clock tSHSL "H" pulse width Serial clock tSLSH "L" pulse width SCK falling -> SOT tSLOVE delay time Valid SIN -> SCK rising tIVSHE setup time SCK rising -> Valid SIN tSHIXE hold time SCK falling time tF SCK rising time tR Conditions Master SCK0 to SCK21, mode SOT0 to SOT21 (CL=50pF, IOL=-2mA, SCK0 to SCK21, IOH=2mA), SIN0 to SIN21 (CL=20pF, IOL=-1mA, SCK0 to SCK21, IOH=1mA) SOT0 to SOT21 SCK0 to SCK21, SOT0 to SOT21 Slave SCK0 to SCK21, mode SOT0 to SOT21 (CL=50pF, IOL=-2mA, SCK0 to SCK21, IOH=2mA), SSIN0 to SIN21 (CL=20pF, IOL=-1mA, IOH=1mA) SCK0 to SCK21, SCK0 to SCK21 Value Unit Min Max 4tCLK_LCP0A - ns -30 +30 ns 30 - ns 0 - ns 2tCLK_LCP0A -30 - ns tCLK_LCP0A +10 - ns 2tCLK_LCP0A -10 - ns - 45 ns 10 - ns 20 - ns - 5 ns - 5 ns Remarks Notes: − − − This table provides the alternate current standard for CLK synchronous mode. CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 65 D a t a S h e e t ( P r e l i m i n a r y ) tSCYC VOH VOH SCK VOL tSOVH tSLOVI VOH VOL SOT VOH VOL tIVSHI tSHIXI VIH VIL SIN VIH VIL Master mode tSLSH tSHSL SCK VIL tR * SOT VIH tF VOH VOL VIL VIL VIH tSLO VOH VOL tSHIXE tIVSHE SIN VIH VIH VIL VIH VIL * Changes when writing to the TDR Slave mode 66 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) (5-1-5) Serial chip select used (SCSCR:CSEN=1) Mark level "H" of serial clock output (SMR, SCSFR:SCINV=0) Inactive level "H" of serial chip select (SCSCR, SCSFR:CSLVL=1) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter SCS falling -> SCK falling setup time Symbol Pin Name tCSSI SCK0 to SCK21 SCS0x to SCK rising -> SCS rising SCS21x tCSHI hold time Conditions Master mode (CL=50pF, IOL=-2mA, Value Unit Min Max tCSSU*1-50 - ns tCSHD*2+0 - ns - ns 3tCLK_LCP0A +30 - ns 0 - ns 3tCLK_LCP0A +30 - ns - 50 ns 0 - ns 3tCLK_LCP0A +0 3tCLK_LCP0A +50 ns Remarks IOH=2mA), SCS tCSDI deselect time SCS0x to (CL=20pF, tCSDS*3-50 SCS21x IOL=-1mA, +5tCLK_LCP0A IOH=1mA) SCS falling -> SCK falling setup time tCSSE SCK0 to SCK21 SCS0x to SCK rising -> SCS rising SCS21x tCSHE hold time SCS tCSDE deselect time SCS falling -> SOT delay time delay time mode (CL=50pF, SCS0x to IOL=-2mA, SCS21x IOH=2mA), tDSE SCS0x to tDEE SOT0 to SOT21 SCS21x SCS rising -> SOT Slave (CL=20pF, IOL=-1mA, IOH=1mA) Master mode round SCK falling -> SCS falling clock switching SCK0 to SCK21 tSCC SCS0x to SCS21x time operation (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) *1: tCSSU=SCSTR:CSSU7 to 0 x serial chip select timing operating clock *2: tCSHD=SCSTR:CSHD7 to 0 x serial chip select timing operating clock *3: tCSDS=SCSTR:CSDS15 to 0 x serial chip select timing operating clock For details on *1, *2, and *3 above, see the hardware manual. Notes: − − − This table provides the alternate current standard for CLK synchronous mode. CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 67 D a t a S h e e t ( P r e l i m i n a r y ) SCS VOH VOL tCSSI SCK VOL tCSHI VOH tCSDI VOH VOL SOT (Normal synchronous transfer) SOT (SPI support) Master mode SCS input VIH VIL tCSDE tCSHE VIL tCSSE SCK input VIH t DEE VIL SOT (Normal synchronous transfer) SOT (SPI support) VIH VOL tDSE VOH VOL Slave mode SCSx tSCC SCSy output SCK output VOL VOL Example of clock switching by a round operation in master mode (x,y=0,1,2,3: The x and y values differ from each other.) 68 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) (5-1-6) Serial chip select used (SCSCR:CSEN=1) Mark level "L" of serial clock output (SMR, SCSFR:SCINV=1) Inactive level "H" of serial chip select (SCSCR, SCSFR:CSLVL=1) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Symbol SCS falling -> SCK rising tCSSI setup time SCK falling -> SCS rising tCSHI hold time Pin Name Conditions Master SCK0 to SCK21 mode SCS0x to SCS21x (CL=50pF, IOL=-2mA, Value Unit Min Max tCSSU*1-50 - ns tCSHD*2+0 - ns - ns 3tCLK_LCP0A +30 - ns 0 - ns 3tCLK_LCP0A +30 - ns - 50 ns 0 - ns 3tCLK_LCP0A +0 3tCLK_LCP0A +50 ns Remarks IOH=2mA), SCS deselect time tCSDI SCK0 to SCK21 (CL=20pF, tCSDS*3-50+5 SCS0x to SCS21x IOL=-1mA, tCLK_LCP0A IOH=1mA) SCS falling -> SCK rising tCSSE setup time SCK falling -> SCS rising tCSHE hold time SCS tCSDE deselect time SCS falling -> SOT tDSE delay time SCS rising -> SOT tDEE delay time SCK0 to SCK21 Slave SCS0x to SCS21x mode (CL=50pF, SCS0x to SCS21x IOL=-2mA, IOH=2mA), (CL=20pF, SCS0x to SCS21x IOL=-1mA, SOT0 to SOT21 IOH=1mA) Master mode round operation SCK rising -> SCS falling clock switching tSCC time SCK0 to SCK21 (CL=50pF, SCS0x to SCS21x IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) *1: tCSSU=SCSTR:CSSU7 to 0 x serial chip select timing operating clock *2: tCSHD=SCSTR:CSHD7 to 0 x serial chip select timing operating clock *3: tCSDS=SCSTR:CSDS15 to 0 x serial chip select timing operating clock For details on *1, *2, and *3 above, see the hardware manual. Notes: − − − This table provides the alternate current standard for CLK synchronous mode. CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 69 D a t a S h e e t ( P r e l i m i n a r y ) SCS output VOH VOL tCSH VOL tCSSI VOH SCK output VOH tCSD I VOL SOT (Normal synchronous transfer) SOT (SPI support) Master mode SCS input VIH SCK input SOT (Normal synchronous transfer) SOT (SPI support) VIH VIL tCSDE tCSHE VIL tCSSE VIL VIH tDEE VOL tDSE VOH VOL Slave mode 70 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) SCSx output tSCC SCSy output SCK output VOL VOH Example of clock switching by a round operation in master mode (x,y=0,1,2,3: The x and y values differ from each other.) June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 71 D a t a S h e e t ( P r e l i m i n a r y ) (5-1-7) Serial chip select used (SCSCR:CSEN=1) Mark level "H" of serial clock output (SMR, SCSFR:SCINV=0) Inactive level "L" of serial chip select (SCSCR, SCSFR:CSLVL=0 (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Symbol Pin Name SCS rising -> SCK tCSSI setup time rising -> SCK0 to SCK21 SCS0x to SCS falling tCSHI SCS21x hold time tCSDI deselect time rising Unit Min Max tCSSU*1-50 - ns tCSHD*2+0 - ns - ns 3tCLK_LCP0A +30 - ns 0 - ns 3tCLK_LCP0A +30 - ns - 50 ns 0 - ns 3tCLK_LCP0A +0 3tCLK_LCP0A +50 ns Remarks mode (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, SCS SCS Value Master falling SCK Conditions -> falling IOL=-1mA, tCSDS*3-50+5 SCS21x IOH=1mA) tCLK_LCP0A SCK tCSSE setup time SCK0 to SCK21 SCS0x to SCK rising -> SCS falling SCS0x to tCSHE SCS21x hold time SCS deselect time SCS rising -> SOT delay time SCS falling -> SOT delay time Slave mode (CL=50pF, IOL=-2mA, tCSDE tDSE SCS0x to IOH=2mA), SCS21x (CL=20pF, SCS0x to SCS21x tDEE IOL=-1mA, IOH=1mA) SOT0 to SOT21 Master mode round SCK falling -> SCS rising clock switching time SCK0 to SCK21 tSCC SCS0x to SCS21x operation (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) *1: tCSSU=SCSTR:CSSU7 to 0 x serial chip select timing operating clock *2: tCSHD=SCSTR:CSHD7 to 0 x serial chip select timing operating clock *3: tCSDS=SCSTR:CSDS15 to 0 x serial chip select timing operating clock For details on *1, *2, and *3 above, see the hardware manual. 72 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) Notes: − − − This table provides the alternate current standard for CLK synchronous mode. CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 73 D a t a S h e e t ( P r e l i m i n a r y ) (5-1-8) Serial chip select used (SCSCR:CSEN=1) Mark level "L" of serial clock output (SMR, SCSFR:SCINV=1) Inactive level "L" of serial chip select (SCSCR, SCSFR:CSLVL=0) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter SCS rising -> SCK rising setup time SCK falling -> SCS falling hold time Symbol Pin Name tCSSI SCK0 to SCK21 SCS0x to tCSHI SCS21x Conditions Master mode (CL=50pF, IOL=-2mA, Value Unit Min Max tCSSU*1-50 - ns tCSHD*2+0 - ns - ns 3tCLK_LCP0A+30 - ns 0 - ns 3tCLK_LCP0A+30 - ns - 50 ns 0 - ns 3tCLK_LCP0A+0 3tCLK_LCP0A+50 ns Remarks IOH=2mA), SCS tCSDI deselect time SCS0x to (CL=20pF, tCSDS*3-50+5 SCS21x IOL=-1mA, tCLK_LCP0A IOH=1mA) SCS rising -> SCK rising setup time SCK falling -> SCS falling hold time SCS tCSSE SCS0x to tCSHE tCSDE deselect time SCS rising -> SOT delay time SCK0 to SCK21 SCS21x delay time mode (CL=50pF, SCS0x to IOL=-2mA, SCS21x IOH=2mA), tDSE SCS0x to tDEE SOT0 to SOT21 SCS21x SCS falling -> SOT Slave (CL=20pF, IOL=-1mA, IOH=1mA) Master mode round SCK0 to SCK21 SCK rising -> SCS rising clock switching time tSCC SCS0x to SCS21x operation (CL=50pF, IOL=-2mA, IOH=2mA), (CL=20pF, IOL=-1mA, IOH=1mA) *1: tCSSU=SCSTR:CSSU7 to 0 x serial chip select timing operating clock *2: tCSHD=SCSTR:CSHD7 to 0 x serial chip select timing operating clock *3: tCSDS=SCSTR:CSDS15 to 0 x serial chip select timing operating clock For details on *1, *2, and *3 above, see the hardware manual. 74 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) Notes: − − − CL is the load capability value connected to the pin at the test time. This table provides the alternate current standard for CLK synchronous mode. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 75 D a t a S h e e t ( P r e l i m i n a r y ) SCS output tCSDI VOH VOH VOH SCK output VOL tCSHI tCSSI VOL SOT (Normal synchronous transfer) SOT (SPI support) Master mode tCSDE SCS input VIH VIH SCK input VIL SOT (Normal synchronous transfer) SOT (SPI support) VIL tCSHE tCSSE tDEE VOL tDSE VOH VOL Slave mode tSCC SCSx VOH SCSy output SCK output VOH Example of clock switching by a round operation in master mode (x,y=0,1,2,3: The x and y values differ from each other.) 76 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 12.4.5.2 UART (asynchronous serial interface) timing (SMR:MD2-0=0b000, 0b001) (5-2-1) External clock selected (BGR:EXT=1) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Symbol Serial clock Pin Name tSLSH "L" pulse width Serial clock (CL=50pF, IOL=-2mA, tSHSL "H" pulse width SCK falling time tF SCK rising time tR SCK0 to VIL IOH=2mA), Value Ma tCLK_LCP0A +10 - ns tCLK_LCP0A +10 - ns - 5 ns - 5 ns IOL=-1mA, IOH=1mA) tF tSHSL VIH VIH Unit Min (CL=20pF, SCK21 tR SCK Conditions Remarks tSLSH VIL VIL VIH External clock selected June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 77 D a t a S h e e t ( P r e l i m i n a r y ) 12.4.5.3 LIN interface (v2.1) (LIN communication control interface (v2.1)) timing (SMR:MD2-0=0b011) (5-3-1) External clock selected (BGR:EXT=1) (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Serial clock "L" pulse width Serial clock "H" pulse width Symbol Pin Name Conditions tSLSH tSHSL SCK falling time tF SCK rising time tR (CL=50pF, IOL=-2mA, IOH=2mA), SCK0 to (CL=20pF, SCK21 IOL=-1mA, IOH=1mA) tR SCK VIL VIH Unit Min Max tCLK_LCP0A+10 - ns tCLK_LCP0A+10 - ns - 5 ns - 5 ns tF tSHSL VIH Value VIL Remarks tSLSH VIL VIH External clock selected 78 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 12.5 Timer input timing (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Symbol Input pulse width tTWH tTWL Pin Name Conditions IN0 to IN11 - TEXT0 to 5 - TIOA0 to TIOA29 − Min 4tCLK_LCP0A 100 4tCLK_LCP0A 100 4tCLK_LCP0A - TIOB0 to TIOB7 Value 100 Max Unit - ns - ns - ns Remarks 4tCLK_LCP0A ≥100 ns 4tCLK_LCP0A <100 ns 4tCLK_LCP0A ≥100 ns 4tCLK_LCP0A <100 ns 4tCLK_LCP0A ≥100 ns 4tCLK_LCP0A <100 ns Timer input timing INx TEXTx TIOAx,TIOBx tTIWH VIH June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL tTIWL VIH VIL VIL 79 D a t a S h e e t ( P r e l i m i n a r y ) 12.6 Trigger input timing (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Input pulse width Symbol tTRGH, tTRGL Pin Name Conditions INT0 to INT15 RX0 to RX1 INT0 to INT15 RX0 to RX1 − Value Unit Min Max - 100 - ns - 5tCLK_LLPBM2 - ns - 1 - µs Remarks Stop mode Trigger input timing tTRGH INTx RXx 80 CONFIDENTIAL VIH tTRGL VIH VIL VIL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 12.7 NMI input timing (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Input pulse width − Symbol tNMIL Pin Name Conditions NMIX - Value Min Max 300 - Unit Remarks ns NMIX input timing tNMIL NMIX VIH VIH VIL June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL VIL 81 D a t a S h e e t ( P r e l i m i n a r y ) 12.8 Low-voltage detection (external low-voltage detection) (TA: Recommended operating conditions, VSS=AVSS=0.0 V) Parameter Supply voltage range Symbol Pin Name Conditions VDP5 VCC - Value Min Typ Max 3.5 - 5.25 Unit Remarks V When power-supply Detection voltage VDL VCC *1 4.0 4.2 4.4 V voltage falls and detection level is set initially When Hysteresis width VHYS VCC - - 100 - mV power-supply voltage rises Low-voltage detection time Power supply voltage regulation Td - - - - 30 μs - VCC - -2 - 2 V/ms *2 *1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: Please suppress the change of the power supply within the range of the power-supply voltage regulation to do a low-voltage detection by detecting voltage (VDL) 82 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 12.9 Low-voltage detection (internal low-voltage detection) (TA: Recommended operating conditions, VSS=AVSS=0.0 V) Parameter Supply voltage range Symbol Pin Name Conditions VRDP5 - VRDL - Value Unit Min Typ Max - 0.6 - 1.4 V *1 0.9 0.95 1.0 V Remarks When Detection voltage power-supply voltage falls When Hysteresis width VRHYS - - - 75 - mV power-supply voltage rises Low-voltage detection time Supply voltage range TRd - - - - 30 μs VRDP5 - - 0.6 - 1.4 V *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. 12.10 Low-voltage detection (1.2 V power supply low-voltage detection) (TA: Recommended operating conditions, VSS=AVSS=0.0 V) Parameter Supply voltage range Symbol Pin Name Conditions VRDP5 - - Value Min Typ Max 0.6 - 1.4 Unit Remarks V When Detection voltage VRDL - *1 0.92 0.97 1.02 V power-supply voltage falls When Hysteresis width VRHYS - - - 75 - mV power-supply voltage rises Low-voltage detection time TRd - - - - 30 μs *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 83 D a t a S h e e t ( P r e l i m i n a r y ) 12.11 A/D converter 12.11.1 Electrical characteristics (TA: Recommended operating conditions, Vcc=5.0 V +5%/-10%, VSS=AVSS=0.0 V) Parameter Symbol Pin Name Resolution - Total Error Conditions Value Unit Min Typ Max - - - 12 bit - - - - ±12 LSB *3 Integral Non linearity - - - - ±4.0 LSB *4 Differential Non linearity - - - - ±1.9 LSB *4 VZT AN0 to AN63 Zero transition voltage AVRL -11.5LSB AVRH - +12.5LSB AVRH V *5 Full-scale transition voltage VFST AN0 to AN63 Sampling time tSMP - 0.3 - 12 µs *1 Compare time tCMP - 0.7 - 28 µs *1 A/D conversion time tCNV - 1.0 - 40 µs *1 Analog port input current IAIN AN0 to AN63 -1.0 - 1.0 µA Analog input voltage VAIN AN0 to AN63 AVSS - AVRH V AVRH AVRH0,AVRH1 4.5 - 5.25 V - 0.0 - V - 500 900 µA per one unit - 1.0 100 µA *2 - 1 2 mA per one unit - - 5.0 µA *2 AN0 to AN31 - - 4 LSB AN32 to AN63 - - 4 LSB Reference voltage AVRL IA Power supply current IAH IR IRH Variation between channels - AVRL0/AVSS0, AVRL1/AVSS1 AVCC AVRH -13.5LSB - AVRL +10.5LSB V VAVSS≤ VAIN≤VAVCC AVcc≥AVRH *1: Time per channel *2: Definition of the power supply current (when Vcc=AVcc=5.0 V) while the A/D converter is not operating and in stop mode *3: Total Error is a comprehensive static error that includes the linearity. 1LSB=(AVRH-AVRL)/4096 *4: 1LSB=(VFST-VZT)/4094 *5: 1LSB=(AVRH-AVRL)/4096 84 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 12.11.2 Notes on A/D converters About the output impedance of an external circuit for analog input When the external impedance is too high, the analog voltage sampling time may become insufficient. In this case, we recommend attaching a capacitor (about 0.1 µF) to an analog input pin. Analog input circuit model Comparator R C Analog input Sampling ON R 12-bit A/D 3.9 kiloohms (max) C 11.0 pF (max) (4.5 V≤Avcc≤5.25 V) Note: Use the numerical values provided here simply as a guide. June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 85 D a t a S h e e t ( P r e l i m i n a r y ) 12.11.3 Glossary Resolution: Analog change that can be identified by an A/D converter Integral linearity error: Deviation of the straight line connecting the zero transition point ("0000 0000 0000" <--> "0000 0000 0001") and full-scale transition point ("1111 1111 1110" <--> "1111 1111 1111") from actual conversion characteristics includes zero transition error, full-scale transition error, and non-linearity error. Differential linearity error: Deviation from the ideal value of the input voltage required for changing the output code by 1 LSB Total error : Difference between the actual value and the theoretical value. The total error Total error FFF FFE Actual conversion characteristics 1.5LSB {1 LSB (N - 1) + 0.5LSB} Digital output FFD V NT (Actually-measured value) 004 003 Actual conversion characteristics 002 001 AVRL (AVSS) Ideal characteristics 0.5LSB Analog input AVRH Total error of digital output N = 1LSB(Ideal value) = VNT- {1 LSB × (N-1) + 0.5LSB} 1LSB AVRH - AVRL 4096 [LSB] [V] N: A/D converter digital output value. VZT(Ideal value) = AVRL + 0.5LSB[V] VFST(Ideal value) = AVRH - 1.5LSB[V] VNT: Voltage at which the digital output changes from "(N – 1)" to "N". 86 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) Integral linearity error Differential linearity error Ideal characteristics FFE Actual conversion characteristics FFD {1 LSB (N - 1) + VZT} 004 003 002 N+1 V FST Digital output Digital output FFF V NT (measured value) Actual conversion characteristics Ideal characteristics Actual conversion characteristics N N-1 V (N+1)T (measured V NT value) (measured value) Actual conversion characteristics N-2 001 VZT (measured value) AVSS (AVRL) Analog input AVSS (AVRL) AVRH Integral linearity error of digital output N = Differential linearity error of digital output N = 1LSB = Analog input VNT- {1 LSB × (N-1) + VZT} 1LSB V(N+1) T- VNT 1LSB VFST - VZT 4094 AVRH [LSB] -1 LSB [LSB] [V] VZT: Voltage for which digital output changes from "0x000" to "0x001" VFST: Voltage for which digital output changes from "0xFFE" to "0xFFF". June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 87 D a t a S h e e t ( P r e l i m i n a r y ) 12.12 Flash memory Rating Parameter Unit Min Typ *3 Max - 540 TBD ms - 610 TBD ms Sector erase time Remarks 8-KB sector*1 Internal preprogramming time excluded 8-KB sector*1 Internal preprogramming time included 64-KB sector*1 - 540 TBD ms - 1100 TBD ms 8-bit write time - 15 TBD µs System-level overhead time excluded*1 16-bit write time - 20 TBD µs System-level overhead time excluded*1 32-bit write time - 30 TBD µs System-level overhead time excluded*1 64-bit write time - 50 TBD µs System-level overhead time excluded*1 ECC write time - 5 TBD µs System-level overhead time excluded*1 1,000/20 years, Erase count*2/ 10,000/10 years, Data retention time Internal preprogramming time excluded 64-KB sector*1 Internal preprogramming time included Temperature at write/erase time - - 100,000/5 years - Average temperature TA=+85 degrees Celsius *1: Guaranteed value for up to 100,000 erases *2: Number of erases for each sector *3: Target value Note: − Turning off an external power supply (VCC) during writing or erasing of Flash memory is prohibited. For an application that may lose VCC during a write operation, use an external low-voltage detector and simultaneous input reset of the MD and RSTX pins so that power-off is safe. Specifically, take the following action. 1. After simultaneous input from the MD and RSTX pins while VCC is within the recommended operating range, power off VCC in observance of the standard regarding the supply voltage fluctuation rate of the external low-voltage detector. 88 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 13. ORDERING INFORMATION Part Number Package S6J311xJAASEy0000 Plastic, LEP176 S6J311xJAAEEy0000 Plastic, LEP176 Note: − "x"/”y” is an part number option. For the part number option, see the following table. For details on each package, see "PACKAGE DIMENSIONS." 14. PART NUMBER OPTION Part Number Option “x” FLASH E 4MByte Part Number Option “y” 1 Sn-Bi & Halogen Free 2 PureSn & Halogen Free June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL 89 D a t a S h e e t ( P r e l i m i n a r y ) 15. PACKAGE DIMENSIONS 90 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014 D a t a S h e e t ( P r e l i m i n a r y ) 16. MAJOR CHANGES IN THIS EDITION Page Section Change Results Revision 0.1 - - June 25, 2014, S6J311E_DS708-00002-0v01-E CONFIDENTIAL Initial release 91 D a t a S h e e t ( P r e l i m i n a r y ) Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2014 Spansion TM ORNAND ® ® ® TM All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse , and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 92 CONFIDENTIAL S6J311E_DS708-00002-0v01-E, June 25, 2014