DISCRETE SEMICONDUCTORS DATA SHEET BF998WR N-channel dual-gate MOS-FET Product specification Supersedes data of 1995 Apr 25 1997 Sep 05 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR FEATURES PINNING High forward transfer admittance Short channel transistor with high forward transfer admittance to input capacitance ratio Low noise gain controlled amplifier up to 1 GHz. PIN SYMBOL 1 s, b 2 d drain 3 g2 gate 2 4 g1 gate 1 APPLICATIONS VHF and UHF applications with 12 V supply voltage, such as television tuners and professional communications equipment. DESCRIPTION source d 3 4 g 2 g1 DESCRIPTION Depletion type field-effect transistor in a plastic microminiature SOT343R package with source and substrate interconnected. The transistor is protected against excessive input voltage surges by integrated back-to-back diodes between gates and source. 2 1 s,b Top view MAM198 CAUTION Marking code: MB. The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. Fig.1 Simplified outline (SOT343R) and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage 12 V ID drain current 30 mA Ptot total power dissipation 300 mW Tj operating junction temperature 150 C yfs forward transfer admittance 24 mS Cig1-s input capacitance at gate 1 2.1 pF Crs reverse transfer capacitance f = 1 MHz 25 fF F noise figure f = 800 MHz 1 dB 1997 Sep 05 2 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage 12 V ID drain current 30 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation 300 mW Tstg storage temperature 65 +150 C Tj operating junction temperature +150 C up to Tamb = 45 C; see Fig.2; note 1 Note 1. Device mounted on a printed-circuit board. MLD154 400 handbook, halfpage Ptot (mW) 300 200 100 0 0 50 100 150 200 Tamb ( oC) Fig.2 Power derating curve. 1997 Sep 05 3 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth j-a thermal resistance from junction to ambient note 1 350 K/W Rth j-s thermal resistance from junction to soldering point note 2; Ts = 90 C 200 K/W Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 10 mA 6 20 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA 6 20 V V(P)G1-S gate 1-source cut-off voltage VG2-S = 4 V; VDS = 8 V; ID = 20 A 2.5 V V(P)G2-S gate 2-source cut-off voltage VG1-S = 0; VDS = 8 V; ID = 20 A 2 V IDSS drain-source current VG2-S = 4 V; VDS = 8 V; VG1-S = 0 2 18 mA IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 5 V 50 nA DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; ID = 10 mA; VDS = 8 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. yfs forward transfer admittance pulsed; Tj = 25 C 22 25 Cig1-s input capacitance at gate 1 f = 1 MHz 2.1 2.5 pF Cig2-s input capacitance at gate 2 f = 1 MHz 1.2 pF Cos drain-source capacitance f = 1 MHz 1.05 pF Crs reverse transfer capacitance f = 1 MHz 25 fF F noise figure 0.6 dB 1 dB f = 200 MHz; GS = 2 mS; BS = BSopt f = 800 MHz; GS = 3.3 mS; BS = BSopt 1997 Sep 05 4 UNIT mS NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR MGC470 MGC471 24 24 3V V G2 S = 4 V ID (mA) V G1 S = ID 2V 0.4 V (mA) 0.3 V 16 16 1V 0.2 V 0.1 V 0V −0.1 V 8 8 −0.2 V −0.3 V −0.4 V −0.5 V 0V 0 0 1 0 0 1 V G1 S (V) VDS = 8 V. Tamb = 25 C. 2 4 6 8 10 V DS (V) VG2-S = 4 V. Tamb = 25 C. Fig.3 Transfer characteristics; typical values. Fig.4 Output characteristics; typical values. MGC473 MGC472 24 30 4V y fs ID max typ (mS) 24 (mS) 3V 2V 1V 16 18 min 12 8 6 0.5 V V G2 − S = 0 V 0 −1600 −1200 −800 −400 0 0 400 VG1 (mV) 0 VDS = 8 V; VG2 = 4 V; Tamb = 25 C. Fig.5 8 12 16 20 I D (mA) VDS = 8 V; Tamb = 25 C. Drain current as a function of gate 1 voltage; typical values. 1997 Sep 05 4 Fig.6 5 Forward transfer admittance as a function of drain current; typical values. NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR MGC474 MGC475 1.5 30 V G2 S = 4 V y fs (mS) 24 Cos (pF) 1.4 3V 18 1.3 12 2V 6 1V 1.2 ID = 12 mA 10 mA 1.1 8 mA 0V 1.0 0 −1 0 4 1 VDS = 8 V; Tamb = 25 C. Fig.7 6 8 10 12 VG1-S (V) 14 VDS(V) VG2-S = 4 V; f = 1 MHz; Tamb = 25 C. Forward transfer admittance as a function of gate 1 voltage; typical values. Fig.8 Output capacitance as a function of drain-source voltage; typical values. MGC477 MGC476 2.4 2.4 Cis (pF) Cis (pF) 2.2 2.3 2.0 2.2 1.8 2.1 1.6 1.4 −2.4 −1.6 −0.8 2.0 6 0 0.8 VG1-S (mV) −2 0 VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 C. Gate 1 input capacitance as a function of gate 1-source voltage; typical values. 1997 Sep 05 2 VG2-S (V) VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 C. Fig.9 4 Fig.10 Gate 1 input capacitance as a function of gate 2-source voltage; typical values. 6 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR MGC466 MGC467 10 3 10 y is (mS) 10 3 ϕ y rs (μS) b is rs (deg) ϕ rs 10 2 1 10 2 y rs 10 1 10 10 g is 10 2 10 102 1 1 10 3 f (MHz) 10 VDS = 8 V; VG2-S = 4 V. ID = 10 mA; Tamb = 25 C. 102 f (MHz) 10 3 VDS = 8 V; VG2-S = 4 V. ID = 10 mA; Tamb = 25 C. Fig.11 Input admittance as a function of the frequency; typical values. MGC468 10 2 y fs MGC469 10 2 10 yos (mS) ϕ fs y fs (mS) Fig.12 Reverse transfer admittance and phase as a function of frequency; typical values. bos (deg) 1 ϕ 10 10 fs gos 10 1 1 1 10 102 f (MHz) 10 2 10 10 3 VDS = 8 V; VG2-S = 4 V. ID = 10 mA; Tamb = 25 C. f (MHz) 10 3 VDS = 8 V; VG2-S = 4 V. ID = 10 mA; Tamb = 25 C. Fig.13 Forward transfer admittance and phase as a function of frequency; typical values. 1997 Sep 05 102 Fig.14 Output admittance as a function of the frequency; typical values. 7 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR VDD 47 μF 1 nF VAGC 20 μH 1 nF 1 nF 1 nF 1.8 kΩ 47 kΩ L2 50 Ω input 1 nF C1 5.5 pF 1 nF 50 Ω input 360 Ω 15 pF L1 10 pF 140 kΩ VDD 1 nF D1 BB405 330 kΩ D2 BB405 330 kΩ 100 kΩ 1 nF V tun input output VDD = 12 V; GS = 2 mS; GL = 0.5 mS. L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm. L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm. Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS. Fig.15 Gain control testcircuit at f = 200 MHz. 1997 Sep 05 1 nF V tun 8 MGC481 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR VDD VAGC V DD 1 nF 140 kΩ 100 kΩ L1 1 nF 50 Ω input 1 nF ;; ;; L3 1 nF 1 nF L2 C1 2-18 pF ;; L4 270 kΩ 1 nF C2 0.5-3.5 pF 1.8 kΩ 360 Ω 1 nF C3 0.5-3.5 pF 50 Ω input C4 4-40 pF MGC480 V DD VDD = 12 V; GS = 3.3 mS; GL = 1 mS. L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm. L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane. L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane. Fig.16 Gain control test circuit at f = 800 MHz. MGC479 MGC478 0 0 ΔGtr ΔGtr (dB) (dB) −10 −10 −20 −20 −30 −30 −40 −50 −40 IDSS= max typ min 0 2 4 6 −50 8 10 VAGC(V) VDD = 12 V; f = 200 MHz; Tamb = 25 C. 0 2 4 6 8 10 VAGC(V) VDD = 12 V; f = 800 MHz; Tamb = 25 C. Fig.17 Automatic gain control characteristics measured in circuit of Fig.15. 1997 Sep 05 IDSS= max typ min Fig.18 Automatic gain control characteristics measured in circuit of Fig.16. 9 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR PACKAGE OUTLINE Plastic surface-mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 06-03-16 SOT343R 1997 Sep 05 EUROPEAN PROJECTION 10 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF998WR DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. DEFINITIONS Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. DISCLAIMERS Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected] © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/02/pp13 Date of release: 1997 Sep 05