DISCRETE SEMICONDUCTORS DATA SHEET BF904WR N-channel dual-gate MOS-FET Product specification Supersedes data of 1995 Apr 25 2010 Sep 15 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR FEATURES PINNING Specially designed for use at 5 V supply voltage Short channel transistor with high forward transfer admittance to input capacitance ratio Low noise gain controlled amplifier up to 1 GHz Superior cross-modulation performance during AGC. PIN SYMBOL DESCRIPTION 1 s, b 2 d drain 3 g2 gate 2 4 g1 gate 1 source APPLICATIONS VHF and UHF applications with 3 to 7 V supply voltage such as television tuners and professional communications equipment. d handbook, halfpage 3 4 DESCRIPTION g2 Enhancement type field-effect transistor in a plastic microminiature SOT343R package. The transistor consists of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. g1 2 1 Top view Marking code: MC* CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. s,b MAM192 * = - : made in Hong Kong * = p : made in Hong Kong * = t : made in Malaysia Fig.1 Simplified outline (SOT343R) and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage 7 V ID drain current 30 mA Ptot total power dissipation 280 mW Tj operating junction temperature 150 C yfs forward transfer admittance 22 25 30 mS Cig1-s input capacitance at gate 1 2.2 2.6 pF Crs reverse transfer capacitance f = 1 MHz 25 35 fF F noise figure f = 800 MHz 2 dB 2010 Sep 15 2 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage 7 V ID drain current 30 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation 280 mW Tstg storage temperature 65 +150 C Tj operating junction temperature +150 C up to Tamb = 50 C; see Fig.2; note 1 Note 1. Device mounted on a printed-circuit board. MLD150 300 handbook, halfpage Ptot (mW) 200 100 0 0 50 100 150 200 Tamb ( oC) Fig.2 Power derating curve. 2010 Sep 15 3 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth j-a thermal resistance from junction to ambient note 1 350 K/W Rth j-s thermal resistance from junction to soldering point Ts = 91 C; note 2 210 K/W Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS V(F)S-G1 MIN. MAX. UNIT VG2-S = VDS = 0; IG1-S = 10 mA 6 15 V gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA 6 15 V forward source-gate 1 voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S = 4V; VDS = 5 V; ID = 20 A 0.3 1 V VG2-S(th) gate 2-source threshold voltage VG1-S = VDS = 5 V; ID = 20 A 0.3 1.2 V IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 120 k; note 1 8 13 mA IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 5 V 50 nA Note 1. RG connects gate 1 to VGG = 5 V. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VDS = 5 V; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. yfs forward transfer admittance pulsed; Tj = 25 C 22 TYP. MAX. 25 30 UNIT mS Cig1-s input capacitance at gate 1 f = 1 MHz 2.2 2.6 pF Cig2-s input capacitance at gate 2 f = 1 MHz 1 1.5 2 pF Cos drain-source capacitance f = 1 MHz 1 1.3 1.6 pF Crs reverse transfer capacitance f = 1 MHz F noise figure 2010 Sep 15 25 35 fF f = 200 MHz; GS = 2 mS; BS = BSopt 1 1.5 dB f = 800 MHz; GS = GSopt; BS = BSopt 2 2.8 dB 4 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR MRA769 MLD268 40 0 handbook, gain halfpage reduction (dB) 10 Y fs (mS) 30 20 20 30 40 10 50 0 50 0 50 100 0 150 o T j ( C) 1 2 3 4 VAGC (V) f = 50 MHz. Tj = 25 C. Fig.3 Forward transfer admittance as a function of junction temperature; typical values. Fig.4 MLD270 MRA771 120 Typical gain reduction as a function of AGC voltage. 20 handbook, halfpage Vunw ID (dB μV) (mA) V G2 S = 4 V 110 15 100 10 3V 2.5 V 2V 1.5 V 5 90 1V 80 0 0 10 20 30 40 50 gain reduction (dB) 0 0.4 0.8 1.2 1.6 2.0 V G1 S (V) VGG = 5 V; fw = 50 MHz. funw = 60 MHz; Tamb = 25 C; RG1 = 120 k Fig.5 VDS = 5 V. Tj = 25 C. Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.19. 2010 Sep 15 Fig.6 Transfer characteristics; typical values. 5 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR MLD269 MLD271 20 150 handbook, halfpage handbook, halfpage V G1 S = 1.4 V ID (mA) 16 V G2 S = 4 V 3.5 V I G1 (μA) 1.3 V 3V 100 1.2 V 12 1.1 V 8 2.5 V 1.0 V 50 2V 0.9 V 4 0 0 0 2 4 6 8 10 V DS (V) 0 0.5 1.0 1.5 2.0 2.5 V G1 S (V) VDS = 5 V. Tj = 25 C. VG2-S = 4 V. Tj = 25 C. Fig.8 Fig.7 Output characteristics; typical values. Gate 1 current as a function of gate 1 voltage; typical values. MLD273 MLD272 16 40 handbook, halfpage handbook, halfpage y fs (mS) ID (mA) V G2 S = 4 V 12 30 3.5 V 3V 20 8 2.5 V 4 10 2V 0 0 0 4 8 12 16 0 20 I D (mA) VDS = 5 V. Tj = 25 C. Fig.9 2010 Sep 15 10 20 30 40 50 I G1 (μA) VDS = 5 V; VG2-S = 4 V. Tj = 25 C. Forward transfer admittance as a function of drain current; typical values. Fig.10 Drain current as a function of gate 1 current; typical values. 6 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR MLD275 MLD274 12 20 handbook, halfpage handbook, halfpage R G1 = 47 kΩ ID (mA) ID 68 kΩ 82 kΩ (mA) 15 100 kΩ 8 120 kΩ 150 kΩ 10 180 kΩ 220 kΩ 4 5 0 0 0 1 2 3 4 0 5 2 4 VGG (V) VDS = 5 V; VG2-S = 4 V. RG1 = 120 k (connected to VGG); Tj = 25 C. 6 V GG = V DS (V) VG2-S = 4 V. RG1 connected to VGG; Tj = 25 C. Fig.11 Drain current as a function of gate 1 supply voltage (= VGG); typical values; see Fig.19. Fig.12 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values; see Fig.19. MLD276 12 MLB945 40 handbook, halfpage handbook, halfpage V GG = 5 V 4.5 V ID I G1 (μA) 4V (mA) V GG = 5 V 30 3.5 V 8 8 4.5 V 3V 4V 3.5 V 20 3V 4 10 0 0 2 4 V G2 S (V) 0 6 0 VDS = 5 V; Tj = 25 C. RG = 120 k (connected to VGG). 4 V G2 S (V) 6 VDS = 5 V; Tj = 25 C. RG = 120 k (connected to VGG). Fig.13 Drain current as a function of gate 2 voltage; typical values; see Fig.19. 2010 Sep 15 2 Fig.14 Gate 1 current as a function of gate 2 voltage; typical values; see Fig.19. 7 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR MLD277 10 2 handbook, halfpage MLD278 10 3 y is (mS) 10 3 ϕ rs (deg) y rs (μS) 10 2 10 ϕ rs 10 2 y rs b is 1 10 10 g is 10 1 10 102 f (MHz) 1 1 10 3 10 102 f (MHz) 10 3 VDS = 5 V; VG2 = 4 V. ID =10 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C. Fig.15 Input admittance as a function of frequency; typical values. MLD279 10 2 y fs MLD280 10 2 10 handbook, halfpage yos (mS) ϕ fs y fs (mS) Fig.16 Reverse transfer admittance and phase as a function of frequency; typical values. (deg) bos 1 ϕ fs 10 10 gos 10 10 2 10 1 1 10 102 f (MHz) 10 3 VDS = 5 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C. 102 f (MHz) 10 3 VDS = 5 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C. Fig.17 Forward transfer admittance and phase as a function of frequency; typical values. 2010 Sep 15 1 Fig.18 Output admittance as a function of frequency; typical values. 8 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR VAGC R1 10 k Ω C1 4.7 nF C2 R GEN 50 Ω R2 50 Ω C3 DUT 4.7 nF 12 pF L1 ≈ 450 nH RL 50 Ω C4 R G1 4.7 nF VI VGG V DS Fig.19 Cross-modulation test set-up. 2010 Sep 15 9 MLD171 NXP Semiconductors Product specification N-channel dual-gate MOS-FET Table 1 f (MHz) BF904WR Scattering parameters: VDS =5 V; VG2-S = 4 V; ID = 10 mA s11 MAGNITUDE (ratio) 40 0.989 s21 ANGLE (deg) s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) 2.420 175.7 0.000 79.9 0.993 1.6 3.4 ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 100 0.985 8.3 2.414 169.1 0.001 78.3 0.992 3.9 200 0.976 16.4 2.368 158.8 0.003 80.3 0.987 7.8 300 0.958 24.1 2.301 148.5 0.004 73.7 0.980 11.4 400 0.942 32.0 2.251 138.8 0.005 70.7 0.974 15.2 500 0.918 39.3 2.170 129.5 0.005 67.2 0.966 18.7 600 0.899 46.0 2.080 120.7 0.005 67.8 0.958 22.2 700 0.876 52.6 2.001 112.1 0.005 68.6 0.951 25.5 800 0.852 58.8 1.924 103.2 0.005 72.9 0.944 28.9 900 0.823 64.9 1.829 94.7 0.005 78.7 0.937 32.1 1000 0.800 70.9 1.747 86.5 0.005 88.3 0.933 35.2 1200 0.750 82.4 1.621 70.7 0.005 120.5 0.928 41.7 1400 0.719 92.7 1.535 54.6 0.008 139.8 0.930 48.4 1600 0.682 102.5 1.424 39.4 0.010 137.8 0.924 54.9 1800 0.642 109.8 1.349 22.5 0.013 156.8 0.928 62.9 2000 0.602 116.5 1.283 1.1 0.018 175.1 0.928 73.1 2200 0.547 124.9 1.130 15.1 0.014 172.6 0.887 81.0 2400 0.596 128.7 1.018 49.1 0.040 163.9 0.837 95.8 2600 0.682 132.6 0.979 79.4 0.077 164.0 0.778 109.6 2800 0.771 142.5 0.804 116.2 0.120 178.8 0.629 119.5 3000 0.793 157.5 0.541 153.5 0.149 158.3 0.479 119.9 Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 10 mA opt f (MHz) Fmin (dB) (ratio) (deg) 800 2.00 .686 49.6 2010 Sep 15 10 rn 50.40 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR PACKAGE OUTLINE Plastic surface-mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 06-03-16 SOT343R 2010 Sep 15 EUROPEAN PROJECTION 11 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DISCLAIMERS property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 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NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2010 Sep 15 12 NXP Semiconductors Product specification N-channel dual-gate MOS-FET BF904WR Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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