DISCRETE SEMICONDUCTORS DATA SHEET BF998; BF998R Silicon N-channel dual-gate MOS-FETs Product specification Supersedes data of April 1991 File under Discrete Semiconductors, SC07 1996 Aug 01 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R FEATURES • Short channel transistor with high forward transfer admittance to input capacitance ratio d handbook, halfpage 4 3 • Low noise gain controlled amplifier up to 1 GHz. g2 g1 APPLICATIONS • VHF and UHF applications with 12 V supply voltage, such as television tuners and professional communications equipment. 1 2 s,b Top view DESCRIPTION MAM039 Marking code: MOp. Depletion type field effect transistor in a plastic microminiature SOT143 or SOT143R package with source and substrate interconnected. The transistors are protected against excessive input voltage surges by integrated back-to-back diodes between gates and source. Fig.1 Simplified outline (SOT143) and symbol; BF998. d handbook, halfpage 3 CAUTION 4 g2 The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. g1 2 PINNING 1 s,b PIN SYMBOL 1 s, b 2 d drain 3 g2 gate 2 4 g1 gate 1 Top view DESCRIPTION source MAM040 Marking code: MOp. Fig.2 Simplified outline (SOT143R) and symbol; BF998R. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT VDS drain-source voltage − 12 V ID drain current − 30 mA Ptot total power dissipation − 200 mW yfs forward transfer admittance 24 − mS Cig1-s input capacitance at gate 1 2.1 − pF Crs reverse transfer capacitance f = 1 MHz 25 − fF F noise figure f = 800 MHz 1 − dB Tj operating junction temperature − 150 °C 1996 Aug 01 2 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 12 V ID drain current − 30 mA ±IG1 gate 1 current − 10 mA ±IG2 gate 2 current Ptot total power dissipation; BF998 − 10 mA up to Tamb = 60 °C; see Fig.3; note 1 − 200 mW up to Tamb = 50 °C; see Fig.3; note 2 − 200 mW Ptot total power dissipation; BF998R up to Tamb = 50 °C; see Fig.4; note 1 − 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − 150 °C Notes 1. Device mounted on a ceramic substrate, 8 mm × 10 mm × 0.7 mm. 2. Device mounted on a printed-circuit board. MLA198 MGA002 handbook, halfpage handbook, halfpage 200 200 (2) Ptot max (1) Ptot max (mW) (mW) 100 100 0 0 0 100 200 Tamb 0 (o C) 100 200 Tamb (°C) (1) Ceramic substrate. (2) Printed-circuit board. Fig.3 Power derating curves; BF998. 1996 Aug 01 Fig.4 Power derating curve; BF998R. 3 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-a PARAMETER CONDITIONS thermal resistance from junction to ambient in free air; BF998 VALUE UNIT note 1 460 K/W note 2 500 K/W thermal resistance from junction to ambient in free air; BF998R note 1 500 K/W Notes 1. Device mounted on a ceramic substrate, 8 mm × 10 mm × 0.7 mm. 2. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT ±V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-SS = ±10 mA 6 20 V ±V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-SS = ±10 mA 6 20 V −V(P)G1-S gate 1-source cut-off voltage VG2-S = 4 V; VDS = 8 V; ID = 20 µA − 2.0 V −V(P)G2-S gate 2-source cut-off voltage VG1-S = 0; VDS = 8 V; ID = 20 µA − 1.5 V IDSS drain-source current VG2-S = 4 V; VDS = 8 V; VG1-S = 0; note 1 2 18 mA ±IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = ±5 V − 50 nA ±IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = ±5 V − 50 nA MAX. UNIT − mS Note 1. Measured under pulse condition. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VDS = 8 V; VG2-S = 4 V; ID = 10 mA. SYMBOL PARAMETER CONDITIONS MIN. TYP. yfs forward transfer admittance f = 1 kHz 21 24 Cig1-s input capacitance at gate 1 f = 1 MHz − 2.1 2.5 pF Cig2-s input capacitance at gate 2 f = 1 MHz − 1.2 − pF Cos output capacitance f = 1 MHz − 1.05 − pF Crs reverse transfer capacitance f = 1 MHz − 25 − fF F noise figure f = 200 MHz; GS = 2 mS; BS = BSopt − 0.6 − dB f = 800 MHz; GS = 3.3 mS; BS = BSopt − 1.0 − dB 1996 Aug 01 4 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGE813 24 MGE815 24 handbook, halfpage I handbook, halfpage I D (mA) D (mA) 20 VG1-S = 0.4 V 20 3V VG2-S = 4 V 2V 1V 0.3 V 16 0.2 V 12 0.1 V 16 12 0V 8 −0.1 V 8 −0.2 V 4 0 0 2 4 6 8 0V 4 −0.3 V −0.4 V −0.5 V 0 −1 10 0 VG2-S = 4 V; Tamb = 25 °C. 1 VG1 (V) VDS (V) VDS = 8 V; Tamb = 25 °C. Fig.5 Output characteristics; typical values. Fig.6 Transfer characteristics; typical values. MGE814 24 MGE811 30 handbook, I halfpage handbook, halfpage D (mA) 20 max 4V 3V 2V |yfs| (mS) 24 typ 1V 16 18 12 min 12 8 6 4 0 −1600 VG2-S = 0 V −1200 −800 −400 0 VG1 (mV) 0 400 0 1996 Aug 01 4 8 12 16 20 ID (mA) VDS = 8 V; VG2-S = 4 V; Tamb = 25 °C. Fig.7 0.5 V VDS = 8 V; Tamb = 25 °C. Drain current as a function of gate 1 voltage; typical values. Fig.8 5 Forward transfer admittance as a function of drain current; typical values. Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGE812 MGE810 30 1.5 handbook, halfpage handbook, halfpage VG2-S = 4 V |yfs| Cos (pF) (mS) 24 1.4 3V 18 1.3 2V 12 1.2 12 mA 1V 6 1.1 10 mA 8 mA 0V 0 −1 1.0 0 VG1 (V) 1 4 VDS = 8 V; Tamb = 25 °C. Fig.9 6 8 10 12 VDS (V) 14 VG2-S = 4 V; f = 1 MHz; Tamb = 25 °C. Forward transfer admittance as a function of gate 1 voltage; typical values. Fig.10 Output capacitance as a function of drain-source voltage; typical values. MBH479 MGE809 2.3 Cis 2.4 handbook, halfpage handbook, halfpage (pF) Cis (pF) 2.1 2.3 1.9 2.2 1.7 2.1 1.5 1.3 −2.4 −1.6 −0.8 2.0 0 0.8 VG1-S (V) 6 VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 °C. 2 0 −2 VG2−S (V) VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 °C. Fig.11 Gate 1 input capacitance as a function of gate 1-source voltage; typical values. 1996 Aug 01 4 Fig.12 Gate 1 input capacitance as a function of gate 2-source voltage; typical values. 6 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs MGC466 BF998; BF998R MGC467 10 3 10 y is (mS) 10 3 ϕ y rs (µS) b is rs (deg) ϕ rs 10 2 1 10 2 y rs 10 1 10 10 g is 10 2 10 102 10 VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C. MGC468 y fs f (MHz) 10 3 Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values. MGC469 10 2 10 yos (mS) ϕ fs y fs (mS) 102 VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C. Fig.13 Input admittance as a function of the frequency; typical values. 10 2 1 1 10 3 f (MHz) bos (deg) 1 ϕ 10 10 fs gos 10 1 1 1 10 102 f (MHz) 10 2 10 10 3 VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C. f (MHz) 10 3 VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C. Fig.15 Forward transfer admittance and phase as a function of frequency; typical values. 1996 Aug 01 102 Fig.16 Output admittance as a function of the frequency; typical values. 7 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R VDD handbook, full pagewidth 47 µF 1 nF Vagc 1 nF 1 nF 20 µH 1 nF 50 Ω output 1.8 kΩ 47 kΩ L2 1 nF 50 Ω input C1 5.5 pF 1 nF 360 Ω 15 pF 10 pF L1 140 kΩ VDD 1 nF D1 BB405 330 kΩ 100 kΩ 330 kΩ 1 nF 1 nF Vtun Vtun input output VDD = 12 V; GS = 2 mS; GL = 0.5 mS. L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm. L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm. Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS. Fig.17 Gain control test circuit at f = 200 MHz. 1996 Aug 01 D2 BB405 8 MGE802 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs Vagc VDD handbook, full pagewidth BF998; BF998R VDD 1 nF 1 nF 140 kΩ 100 kΩ 1 nF L4 270 kΩ 50 Ω input 1 nF L3 1 nF L1 L2 1 nF C1 2 to 18 pF C3 0.5 to 3.5 pF C2 0.5 to 3.5 pF 50 Ω output C4 4 to 40 pF MGE801 1.8 kΩ 360 Ω VDD VDD = 12 V; GS = 3.3 mS; GL = 1 mS. L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm. L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane. L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane. Fig.18 Gain control test circuit at f = 800 MHz. 1996 Aug 01 1 nF 9 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R MGE807 MGE808 0 0 handbook, halfpage handbook, halfpage ∆Gtr ∆Gtr (dB) (dB) −10 −10 −20 −20 −30 −30 IDSS = −40 −50 max typ min −40 max typ min 0 IDSS = −50 2 4 6 8 10 0 2 4 Vagc (V) VDD = 12 V; f = 200 MHz; Tamb = 25 °C. 8 Vagc (V) 10 VDD = 12 V; f = 800 MHz; Tamb = 25 °C. Fig.19 Automatic gain control characteristics measured in circuit of Fig.17. 1996 Aug 01 6 Fig.20 Automatic gain control characteristics measured in circuit of Fig.18. 10 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R PACKAGE OUTLINES handbook, full pagewidth 3.0 2.8 0.150 0.090 0.75 0.60 B 1.9 4 3 0.1 max o 10 max 0.2 M A B A 2.5 max 1.4 1.2 o 10 max 1 1.1 max o 30 max 0.88 2 0 0.1 0.48 0.1 M A B 0 0.1 MBC845 1.7 TOP VIEW Dimensions in mm. Fig.21 SOT143. 3.0 2.8 handbook, full pagewidth 0.150 0.090 0.40 0.25 B 1.9 3 4 0.1 max o 10 max 0.2 M A A 1.4 1.2 o 2.5 max 10 max 1 2 1.1 max o 30 max 0.48 0.38 0.88 0.78 1.7 0.1 M B TOP VIEW Dimensions in mm. Fig.22 SOT143R. 1996 Aug 01 11 MBC844 Philips Semiconductors Product specification Silicon N-channel dual-gate MOS-FETs BF998; BF998R DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Aug 01 12