IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT IDT74ALVCH16901 UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/ CHECKERS AND BUS-HOLD DESCRIPTION: FEATURES: This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction. The ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver. The ALVCH16901 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16901 has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM LEAB 2 1 CLKENAB 1 2 CLKENAB 32 CLKAB OEAB 2 3 30 35 1 A 1 -1 A 8 1 APAR 1 ERRB 18 5 61 2 A 1 -2 A 8 2 APAR 2 ERRB ODD/EVEN SEL 28 A-Port Parity Generate and Check B Data 18-Bit Storage 18 36 QB 18-Bit Storage 1 B 1 -1 B 8 18 QA OEBA B-Port Parity Generate and Check A Data 60 4 1 BPAR 1 ERRA 2 B 1 -2 A 8 37 18 29 2 BPAR 2 ERRA 34 31 62 2 64 33 63 CLKBA 1 CLKENBA 2 CLKENBA LEBA The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JUNE 2000 1 ©2000 Integrated Device Technology, Inc. DSC-4582/1 IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V °C 1CLKENAB 1 64 1CLKENBA LEAB 2 TSTG Storage Temperature –65 to +150 63 LEBA IOUT DC Output Current –50 to +50 mA CLKAB 3 62 CLKBA IIK ±50 mA 1ERRA 4 61 1ERRB Continuous Clamp Current, VI < 0 or VI > VCC IOK Continuous Clamp Current, VO < 0 –50 mA 1APAR 5 60 1BPAR mA 6 59 GND Continuous Current through each VCC or GND ±100 GND ICC ISS 1A1 7 58 1B1 1A2 8 57 1B2 1A3 9 56 1B3 VCC 10 55 VCC 1A4 11 54 1B4 1A5 12 53 1B5 1A6 13 52 1B6 GND 14 51 GND 1A7 15 50 1A8 16 2A1 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. CIN Input Capacitance VIN = 0V 5 7 pF 1B7 COUT Output Capacitance VOUT = 0V 7 9 pF 49 1B8 COUT I/O Port Capacitance VIN = 0V 7 9 pF 17 48 2B1 2A2 18 47 2B2 GND 19 46 GND 2A3 20 45 2B3 2A4 21 44 2B4 Pin Names 2A5 22 43 2B5 OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input LEBA B-to-A Latch Enable Input NOTE: 1. As applicable to the device type. PIN DESCRIPTION Description VCC 23 42 VCC 2A6 24 41 2B6 2A7 25 40 2B7 xCLKENAB A-to-B 9-bit Clock Enables 2A8 26 39 2B8 xCLKENBA B-to-A 9-bit Clock Enables GND 27 38 GND 2APAR 28 37 2BPAR 2ERRA 29 36 2ERRB OEAB 30 35 OEBA SEL 31 34 ODD/EVEN 2CLKENAB 32 33 2CLKENBA Unit CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input xERRA A Error-Signal Outputs xERRB B Error-Signal Outputs xAPAR A Port Parities xBPAR B Port Parities ODD/EVEN TSSOP TOP VIEW Parity Select Input SEL Parity Enables xAx A-to-B Data Inputs or B-to-A 3-State Outputs (1) xBx B-to-A Data Inputs or A-to-B 3-State Outputs (1) NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. 2 IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY FUNCTION TABLE(1,2) PARITY ENABLE Inputs CLKENAB OEAB LEAB INDUSTRIAL TEMPERATURE RANGE CLKAB xAx Outputs Inputs xBx SEL OEBA OEAB X H X X X Z X L H X L L X L H X H H H L L X X B(3) L L L ↑ L L L L L ↑ H H L L L L X B(3) L L L H X B(4) Operation or Function L L L L H L H L L H H L H H H L L H L H L Parity is checked on port A and is generated on port B. Parity is checked on port B and is generated on port A. Parity is checked on port B and port A. Parity is generated on port A and B if device is in FF mode. Parity functions are QA data to B, QB data to A disabled; device acts as QB data to A a standard 18-bit QA data to B H H H registered transceiver. Isolation NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW-to-HIGH Transition 2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKENBA. 3. Output level before the indicated steady-state conditions were established. 4. Output level before the indicated steady-state conditions were established, provided that CLKAB was LOW before LEAB went LOW. PARITY SEL L L L L L L L L L L L L L L L L L L L L L L L L L L OEBA H H H H L L L L H H H H L L L L H H H H H H H H L L OEAB L L L L H H H H L L L L H H H H H H H H H H H H L L ODD/EVEN L L L L L L L L H H H H H H H H L L L L H H H H L H Inputs ∑ OF INPUTS −A8 = H A1-− 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A Outputs ∑ OF INPUTS −B8 = H B1—− N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A NOTES: 1. Parity output is set to the level so that the specific bus side is set to even parity. 2. Parity output is set to the level so that the specific bus side is set to odd parity. 3 xAPAR L L H H N/A N/A N/A N/A L L H H N/A N/A N/A N/A L L H H L L H H N/A N/A xBPAR N/A N/A N/A N/A L L H H N/A N/A N/A N/A L L H H L L H H L L H H N/A N/A xAPAR N/A N/A N/A N/A L H L H N/A N/A N/A N/A H L H L N/A N/A N/A N/A N/A N/A N/A N/A PE(1) PO(2) xERRA H L L H Z Z Z Z L H H L Z Z Z Z H L L H L H H L Z Z xBPAR L H L H N/A N/A N/A N/A H L H L N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A PE(1) PO(2) xERRB Z Z Z Z H L L H Z Z Z Z L H H L H L L H L H H L Z Z IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V – 45 — — 45 — — — ±500 NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO VI = 0.7V VI = 0 to 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 4 — µA µA IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 6mA 2 — IOH = – 12mA 1.7 — 2.2 — VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled 5 VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 22 27 pF 5 8 IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay xAx to xBx or xBx to xAx Propagation Delay xAx to xBPAR or xBx to xAPAR Propagation Delay xAPAR to xBPAR or xBPAR to xAPAR Propagation Delay xAPAR to xERRA or xBPAR to xERRB Propagation Delay ODD/EVEN to xERRB or xERRA Propagation Delay ODD/EVEN to xAPAR or xBPAR Propagation Delay SEL to xAPAR or xBPAR Propagation Delay LEBA to xAx or LEAB to xBx Propagation Delay LEBA to xAPAR or LEAB to xBPAR (parity feed through) Propagation Delay LEBA to xAPAR or LEAB to xBPAR (parity generated) Propagation Delay LEBA to xERRB or LEAB to xERRA Propagation Delay CLKBA to xAx or CLKAB to xBx Propagation Delay CLKBA to xAPAR or CLKAB to xBPAR(parity feed through) Propagation Delay CLKBA to xAPAR or CLKAB to xBPAR(parity generated) Propagation Delay CLKBA to xERRB or CLKAB to x ERRA 6 VCC = 2.7V VCC = 3.3V ± 0.3V Min. 125 1 Max. — 5.2 Min. 125 — Max. — 4.8 Min. 125 1 Max. — 4.4 Unit MHz ns 2 8.9 — 7.6 2 6.7 ns 1 5.7 — 5.2 1 4.7 ns 2 9.7 — 8.7 2 7.5 ns 1.5 8.7 — 7.9 1.5 6.8 ns 1.5 8.3 — 7.6 1.5 6.5 ns 1 6.1 — 5.9 1 5.1 ns 1 6 — 5.5 1 4.8 ns 1.5 6.7 — 6 1.5 5.3 ns 2.5 9.8 — 8.3 2 7.4 ns 2.5 9.9 — 8.5 2 7.5 ns 1 6.4 — 5.8 1 5.1 ns 1.5 7.1 — 6.3 1.5 5.6 ns 2.5 10.2 — 8.7 2 7.7 ns 2.5 10.5 — 8.9 2 7.9 ns IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS (CONTINUED)(1) VCC = 2.5V ± 0.2V Symbol tPZH tPZL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ tSU tSU tSU tH tH tH tW tW tSK(o) Parameter Output Enable Time OEAB or OEBA to xBx, xBPAR or xAx, xAPAR Output Enable Time OEAB or OEBA to xERRA or xERRB Output Enable Time SEL to xERRA or xERRB Output Disable Time OEAB or OEBA to xBx, xBPAR or xAx, xAPAR Output Disable Time OEAB or OEBA to xERRA or xERRB Output Disable Time SEL to xERRA or xERRB Set-up Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR before CLK↑ Set-up Time, HIGH or LOW, xCLKENAB or xCLKENBA before CLK↑ Set-up Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR before LE↓ Hold Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR after CLK↑ Hold Time, HIGH or LOW, xCLKENAB or xCLKENBA after CLK↑ Hold Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR after LE↓ Pulse Width LEAB or LEBA HIGH Pulse Width CLKAB or CLKBA HIGH or LOW Output Skew(2) VCC = 3.3V ± 0.3V Min. 1.4 Max. 6.3 Min. — Max. 6.1 Min. 1 Max. 5.3 Unit ns 1.4 6.2 — 5.5 1 4.9 ns 1.4 6.7 — 6.5 1 5.5 ns 1.3 6.1 — 5.2 1.5 4.9 ns 1.3 7.3 — 6.5 1 5.7 ns 1.3 6.4 — 5.4 1.5 4.9 ns 1.9 — 2 — 1.7 — ns 2.1 — 2.1 — 1.7 — ns 1.4 — 1.3 — 1.2 — ns 0.4 — 0.4 — 0.5 — ns 0.5 — 0.5 — 0.7 — ns 0.9 — 1.1 — 0.9 — ns 3 3 — — — — 3 3 — — — — 3 3 — — — 500 ns ns ps NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 7 VCC = 2.7V IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) VIN VIH VT 0V ALVC Link DISABLE ENABLE GND tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL ALVC Link Test Circuit for All Outputs tPHL CONTROL INPUT D.U.T. RT tPLH Propagation Delay VOUT Pulse Generator tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION tPLZ VLOAD/2 VT VIH VT 0V VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Test VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open INPUT OUTPUT 1 tSK (x) VOH VT VOL tSK (x) OUTPUT 2 tH LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT ALVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU Set-up, Hold, and Release Times VIH VT 0V VOH VT VOL tPLH2 tREM ALVC Link tPHL1 tPLH1 tH TIMING INPUT Switch Open Drain Disable Low Enable Low tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 8 IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX ALVC X Bus-Hold Temp. Range XXX Family XXX XX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PA Thin Shrink Small Outline Package 901 18-Bit Universal Bus Transceiver with Parity Generators/Checkers 16 Double-Density, ±24mA H Bus-Hold 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 9 for Tech Support: [email protected] (408) 654-6459