IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS, BUS-HOLD, 5V TOLERANT I/O FEATURES: – – – – – – – – – IDT74LVCH16901A CMOS technology. The LVCH16901A is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction. Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.50mm pitch TSSOP package Extended commercial range of -40°C to +85°C VCC = 3.3V ±0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion The LVCH16901A features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. Drive Features for LVCH16901A: – High Output Drivers: ±24mA – Reduced system switching noise APPLICATIONS: The LVCH16901A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems The LVCH16901A has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. DESCRIPTION: This 18-bit universal bus transceiver is built using advanced dual metal FUNCTIONAL BLOCK DIAGRAM LEAB 2 1 CLKENAB 1 2 CLKENAB 32 CLKAB OEAB 2 3 30 35 1 A 1 -1 A 8 1 APAR 1 ERRB 18 5 61 2 A 1 -2 A 8 2 APAR 2 ERRB ODD/EVEN SEL 28 36 A-Port Parity Generate and Check B Data 18-Bit Storage 18 QB 18-Bit Storage 1 B 1 -1 B 8 18 QA OEBA B-Port Parity Generate and Check A Data 60 4 1 BPAR 1 ERRA 2 B 1 -2 A 8 37 18 29 2 BPAR 2 ERRA 34 31 62 2 64 33 63 EXTENDED COMMERCIAL TEMPERATURE RANGE CLKBA 1 CLKENBA 2 CLKENBA LEBA JUNE 2000 1 c 2000 Integrated Device Technology, Inc. DSC-5412/- IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY PIN CONFIGURATION EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol VTERM Description Terminal Voltage with Respect to GND Max. – 0.5 to +6.5 1 C LKEN AB 1 64 1 C LKEN BA TSTG Storage Temperature – 65 to +150 °C LEAB 2 63 LEBA IOUT DC Output Current – 50 to +50 mA C LKAB 3 62 C LKBA 61 1 ER R B 1 APAR 5 60 1 BPAR Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through mA 1 ER R A IIK IOK ICC – 50 4 ±100 mA GN D 6 59 GN D ISS each VCC or GND 1A 1 7 58 1B 1 1A 2 8 57 1B 2 1A 3 9 56 1B 3 V CC 10 55 V CC 1A 4 11 54 1B 4 1A 5 12 53 1B 5 1A 6 13 52 1B 6 GN D 14 SO64-1 51 1A 7 15 50 1B 7 1A 8 16 49 1B 8 2A 1 17 48 2B 1 2A 2 18 47 2B 2 GN D 19 46 GN D 2A 3 20 45 2B 3 2A 4 21 44 2B 4 2A 5 22 43 2B 5 V CC 23 42 V CC 2A 6 24 41 2B 6 2A 7 25 40 2B 7 2A 8 26 39 GN D 27 2 APAR LVC Link NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25oC, f = 1.0MHz) GN D Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 6.5 8 pF VIN = 0V 6.5 8 pF CI/O LVC Link NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names OEAB Description A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input 2B 8 LEBA B-to-A Latch Enable Input 38 GN D xCLKENAB A-to-B 9-bit Clock Enables 28 37 2 BPAR xCLKENBA B-to-A 9-bit Clock Enables 2 ER R A 29 36 2 ER R B CLKAB A-to-B Clock Input OEAB 30 35 OEBA CLKBA B-to-A Clock Input xERRA A Error-Signal Outputs xERRB B Error-Signal Outputs xAPAR A Port Parities xBPAR B Port Parities ODD/EVEN Parity Select Input SEL Parity Enables xAx A-to-B Data Inputs or B-to-A 3-State Outputs(1) xBx B-to-A Data Inputs or A-to-B 3-State Outputs(1) SEL 2 C LKEN AB 31 34 OD D /EVEN 32 33 2 C LKEN BA TSSOP TOP VIEW NOTE: 1. These pins have “Bus-hold”. All other pins are standard inputs, outputs, or I/Os. c Unit V 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE PARITY ENABLE FUNCTION TABLE (1,2) CLKENAB OEAB Inputs LEAB CLKAB xAx Outputs xBx SEL X H X X X Z L X L H X L L L X L H X H H L L H L L X X B0(3) L L L ↑ L L L L L ↑ H H L L L L X B0(3) L L L H X B0(4) Inputs OEBA OEAB H Operation or Function L Parity is checked on port A and is generated on port B. L H Parity is checked on port B and is generated on port A. H H Parity is checked on port B and port A. L L Parity is generated on port A and B if device is in FF H L L Parity functions are QA data to B, QB data to A H L H disabled; device acts as QB data to A H H L a standard 18 bit registered QA data to B H H H transceiver. mode. Isolation NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKENBA. 2. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ = LOW-to-HIGH Transition 3. Output level before the indicated steady-state input conditions were established. 4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. PARITY SEL L L L L L L L L L L L L L L L L L L L L L L L L L OEBA H H H H L L L L H H H H L L L L H H H H H H H H L OEAB L L L L H H H H L L L L H H H H H H H H H H H H L ODD/EVEN L L L L L L L L H H H H H H H H L L L L H H H H L Inputs ∑ OF INPUTS A1−A8 = H 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A L L L H N/A Outputs ∑ OF INPUTS B1−B8 = H N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A N/A N/A N/A 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7 N/A xAPAR L L H H N/A N/A N/A N/A L L H H N/A N/A N/A N/A L L H H L L H H N/A xBPAR N/A N/A N/A N/A L L H H N/A N/A N/A N/A L L H H L L H H L L H H N/A xAPAR N/A N/A N/A N/A L H L H N/A N/A N/A N/A H L H L N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A NOTES: 1. Parity output is set to the level so that the specific bus side is set to even parity. 2. Parity output is set to the level so that the specific bus side is set to odd parity. 3 xBPAR L H L H N/A N/A N/A N/A H L H L N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A PE(1) xERRA H L L H Z Z Z Z L H H L Z Z Z Z H L L H L H H L Z PE(1) xERRB Z Z Z Z H L L H Z Z Z Z L H H L H L L H L H H L Z PO(2) Z PO(2) Z IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40OC to +85OC Symbol VIH VIL Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) — Max. — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Test Conditions Input LOW Voltage Level Unit V V IIH IIL IOZH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V ICCL ICCH ICCZ Quiescent Power Supply Current VCC = 3.6V ∆ICC Quiescent Power Supply Current Variation — 100 — mV VIN = GND or VCC — — 10 µA 3.6 ≤ VIN ≤ 5.5V(2) — — 10 — — 500 One input at VCC - 0.6V other inputs at VCC or GND µA LVC Link NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current VCC = 3.0V Test Conditions VI = 2.0V Min. – 75 Typ.(2) — Max. — VI = 0.8V 75 — — IBHL IBHH Bus-Hold Input Sustain Current VCC = 2.3V IBHL IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 1.7V — — — VI = 0.7V — — — VI = 0 to 3.6V — — ± 500 Unit µA µA µA IBHLO LVC Link NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 4 IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA Min. VCC – 0.2 Max. — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3.0V 2.4 — VCC = 3.0V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V LVC Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to +85°C. OPERATING CHARACTERISTICS, TA = 25oC Symbol Parameter VCC = 1.8V VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Typical Unit CPD Power Dissipation Capacitance Outputs enabled CL = 0pF 37 52 68 pF CPD Power Dissipation Capacitance Outputs disabled f = 10Mhz 16 22 28 pF 5 IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS (1) VCC = 1.8V (2) Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay xAx to xBx or xBx to xAx Propagation Delay xAx to xBPAR or xBx to xAPAR Propagation Delay xAPAR to xBPAR or xBPAR to xAPAR Propagation Delay xAPAR to xERRA or xBPAR to xERRB Propagation Delay ODD/EVEN to xERRB or xERRA Propagation Delay ODD/EVEN to xAPAR or xBPAR Propagation Delay SEL to xAPAR or xBPAR Propagation Delay LEBA to xAx or LEAB to xBx Propagation Delay LEBA to xAPAR or LEAB to xBPAR (parity feed through) Propagation Delay LEBA to xAPAR or LEAB to xBPAR (parity generated) Propagation Delay LEBA to xERRB or LEAB to xERRA Propagation Delay CLKBA to xAx or CLKAB to xBx Propagation Delay CLKBA to xAPAR or CLKAB to xBPAR (parity feed through) Propagation Delay CLKBA to xAPAR or CLKAB to xBPAR (parity generated) Propagation Delay CLKBA to xERRB or CLKAB to x ERRA VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V Min. 125 Max. — Min. 125 Max. — Min. 125 Max. — Min. 125 Max. — Unit MHz — 7 1 6.2 — 5.8 1 5.4 ns — 12.7 2 9.9 — 8.6 2 7.7 ns — 8.4 1 6.7 — 6.2 1 5.7 ns — 13 2 10.7 — 9.7 2 8.5 ns — 9.9 1.5 9.7 — 8.9 1.5 7.8 ns — 10.4 1.5 9.3 — 8.6 1.5 7.5 ns — 9.5 1 7.1 — 6.9 1 6.1 ns — 9.5 1 7 — 6.5 1 5.8 ns — 11 1.5 7.7 — 7 1.5 6.3 ns — 14.5 2.5 10.8 — 9.3 2 8.4 ns — 15.3 2.5 10.9 — 9.5 2 8.5 ns — 10.5 1 7.4 — 6.8 1 6.1 ns — 11.5 1.5 8.1 — 7.3 1.5 6.6 ns — 15.5 2.5 11.2 — 9.7 2 8.7 ns — 16.5 2.5 11.5 — 9.9 2 8.9 ns (CONTINUED ON NEXT PAGE) 6 IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS (CONTINUED) (1) VCC = 1.8V (2) Symbol tPZH tPZL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ tSU VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V Min. — Max. 8.4 Min. 1.4 Max. 7.3 Min. — Max. 7.1 Min. 1 Max. 6.3 Unit ns — 9 1.4 7.2 — 6.5 1 5.9 ns — 9.5 1.4 7.7 — 7.5 1 6.5 ns — 8.1 1.3 7.1 — 6.2 1.5 5.9 ns — 9.3 1.3 8.3 — 7.5 1 6.7 ns — 9.2 1.3 7.4 — 6.4 1.5 5.9 ns 4.7 — 2.7 — 2.8 — 2.5 — ns 4.5 — 2.9 — 2.9 — 2.5 — ns 0 — 2.2 — 2.1 — 2 — ns 0 — 1.2 — 1.2 — 1.3 — ns 0 — 1.3 — 1.3 — 1.5 — ns 1.7 — 1.7 — 1.9 — 1.7 — ns tW Parameter Output Enable Time OEAB or OEBA to xBx, xBPAR or xAx, xAPAR Output Enable Time OEAB or OEBA to xERRA or xERRB Output Enable Time SEL to xERRA or xERRB Output Disable Time OEAB or OEBA to xBx, xBPAR or xAx, xAPAR Output Disable Time OEAB or OEBA to xERRA or xERRB Output Disable Time SEL to xERRA or xERRB Set-up Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR before CLK↑ Set-up Time, HIGH or LOW, xCLKENAB or xCLKENBA before CLK↑ Set-up Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR before LE↓ Hold Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR after CLK↑ Hold Time, HIGH or LOW, xCLKENAB or xCLKENBA after CLK↑ Hold Time, HIGH or LOW, xAx, xAPAR or xBx, xBPAR after LE↓ Pulse Width LEAB or LEBA HIGH 3 — 3 — 3 — 3 — ns tW Pulse Width CLKAB or CLKBA HIGH or LOW 4 — 3 — 3 — 3 — ns — — — — — — — 500 ps tSU tSU tH tH tH tSK(o) Output Skew (1) NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Based on IDT characterization. 3. Skew between any two outputs of the same package and switching in the same direction. 7 IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit 2 x Vcc V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF V IH VT 0V SAME PHASE INPUT TRANSITION t PLH t PHL tPLH t PHL VOH VT V OL OUTPUT V IH VT 0V OPPOSITE PHASE INPUT TRANSITION LVC Link TEST CIRCUITS FOR ALL OUTPUTS LVC Link ENABLE AND DISABLE TIMES V LOAD V CC Open 500 Ω Pulse (1, 2) Generator V IN DISABLE ENABLE GND V OUT t PZL D.U.T. OUTPUT SW ITCH NORM ALLY CLOSED LOW tPZH OUTPUT SW ITCH NORM ALLY OP EN HIGH 500 Ω RT CL LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 0V t PLZ V LOAD/2 V LOAD/2 VT V OL+ V LZ V OL t PHZ V OH V OH- V HZ VT 0V 0V LVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. SET-UP, HOLD, AND RELEASE TIMES SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests V IH VT CONTROL INPUT Switch VLOAD DATA INPUT GND TIMING INPUT Open ASYNCHRONOUS CONTROL t SU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH t REM LVC Link OUTPUT SKEW INPUT TSK SYNCHRONOUS CONTROL (x) tPLH1 t SU tH LVC Link V IH VT 0V tPHL1 PULSE WIDTH V OH OUTPUT 1 tSK (x) tSK (x) LOW -HIGH-LOW PULSE VT V OL tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT LVC Link tPLH2 t PHL2 t SK (x) = t PLH2 - t PLH1 or t PHL2 - t PHL1 LVC NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. Link 8 IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION Vcc = 1.8V LOAD CIRCUIT TEST 2 X VCC 1 kΩ S1 OPEN FROM OUTPUT UNDER TE ST GND S1 tPD Open tPLZ/tPZL 2 x Vcc tPHZ/tPZH GND 1 kΩ C L = 30pF (1) VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tW VCC VCC TIMING INPUT INPUT V C C /2 V C C /2 V C C /2 0V 0V t SU tH VCC DATA INPUT V C C /2 V C C /2 VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES 0V OUTPUT CONTROL (LOW LEVEL ENABLING) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES V C C /2 0V OUTPUT W AVEFORM 1 (2) S1 AT 2 X Vcc V C C /2 V C C /2 V C C /2 tPLZ tPZL VCC INPUT VCC VCC V C C /2 V OL + 0.15 V 0V t PLH V OL tPZH tPH L tPH Z V OH V OH V C C /2 OUTPUT W AVEFORM 1 (2) S1 AT OPEN V C C /2 OUTPUT V OL V C C /2 NOTES: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Zo = 50Ω, tR ≤ 2ns, tF ≤ 2ns. 4. The outputs are measured one at a tiime with one transition per measurement. 5. tPLZ and tPHZ are the same as tDIS. 6. tPZL and tPZH are the same as tEN. 7. tPLH and tPHL are the same as tPD. 9 V OH 0V – 0.15 V IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION Vcc = 2.5V ± 0.2V LOAD CIRCUIT 2 X VCC 500 Ω TEST S1 O PEN FR OM O UTPUT UN DER TEST G ND 500 Ω C L = 30pF S1 tPD Open tPLZ/tPZL 2 x Vcc tPHZ/tPZH GND (1) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION V CC TIM IN G IN PUT V CC /2 tW 0V t SU V CC tH IN PUT V CC /2 V CC /2 V CC DATA IN PUT V CC /2 0V V CC /2 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES O UTPUT CO NTR OL (LO W LEVEL EN ABLING ) V CC V CC /2 V CC /2 0V O UTPUT W AVEFOR M 1 (2) S1 AT 2 X Vcc V CC /2 V CC /2 IN PUT 0V t PLH t PLZ t PZL V CC V CC V CC /2 V OL + 0.15 V t PH L V OL t PZH V OH t PHZ V OH V CC /2 V CC /2 O UTPUT O UTPUT W AVEFOR M 1 (2) S1 AT G ND V OL V CC /2 NOTES: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Zo = 50Ω, tR ≤ 2ns, tF ≤ 2ns. 4. The outputs are measured one at a tiime with one transition per measurement. 5. tPLZ and tPHZ are the same as tDIS. 6. tPZL and tPZH are the same as tEN. 7. tPLH and tPHL are the same as tPD. 10 V OH – 0.15 V 0V IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION Vcc = 2.7V and 3.3V ± 0.3V LOAD CIRCUIT 6V S1 500 Ω OPEN FROM OUTPUT UNDER TEST GND 500 Ω C L = 50pF TEST S1 tPD Open tPLZ/tPZL 2 x Vcc tPHZ/tPZH GND (1) VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tW 2.7V TIMING INPUT 2.7V 1.5V INPUT 0V tSU 1.5V 1.5V 0V tH 2.7V DATA INPUT 1.5V 1.5V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES OUTPUT CONTROL (LOW LEVEL ENABLING) 2.7V 1.5V 1.5V 0V t PLZ tPZL 2.7V OUTPUT W AVEFORM 1 (2) S1 AT 6V 1.5V 1.5V INPUT 0V tPLH 3V 1.5V V OL tPH L tPZH tPHZ V OH 1.5V V OL + 0.3 V V OH 1.5V OUTPUT W AVEFORM 1 (2) S1 AT GND OUTPUT V OL 1.5V NOTES: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Zo = 50Ω, tR ≤ 2ns, tF ≤ 2ns. 4. The outputs are measured one at a tiime with one transition per measurement. 5. tPLZ and tPHZ are the same as tDIS. 6. tPZL and tPZH are the same as tEN. 7. tPLH and tPHL are the same as tPD. 11 V OH 0V – 0.3 V IDT74LVCH16901A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX Tem p. Range X XXX XXX XX Bus-Hold Fam ily Device Type Package LVC PA Thin Shrink Small Outline Package (SO64-1) 901A 18-Bit Universal Bus Transceiver with Parity Generators/ Checker 16 Double-Density with Resistors, ±24mA H Bus-Hold 74 -40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 12