TI SN74ALVCH16901DGG

SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
D
D
D
D
D
D
D
D
D
DGG PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus+ Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Simultaneously Generates and Checks
Parity
Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Packaged in Thin Shrink Small-Outline
Package
1CLKENAB
LEAB
CLKAB
1ERRA
1APAR
GND
1A1
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
2A5
VCC
2A6
2A7
2A8
GND
2APAR
2ERRA
OEAB
SEL
2CLKENAB
description
This 18-bit (dual-octal) noninverting registered
transceiver is designed for 1.65-V to 3.6-V VCC
operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit
parity transceiver with registers. The device can
operate as a feed-through transceiver or it can
generate/check parity from the two 8-bit data
buses in either direction.
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
1CLKENBA
LEBA
CLKBA
1ERRB
1BPAR
GND
1B1
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
2B5
VCC
2B6
2B7
2B8
GND
2BPAR
2ERRB
OEBA
ODD/EVEN
2CLKENBA
The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and
dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of
data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL is
high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16901 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
Function Tables
FUNCTION†
INPUTS
LEAB
CLKAB
A
OUTPUT
B
H
X
X
X
Z
L
H
X
L
L
X
L
H
X
H
H
L
L
X
X
H
B0‡
L
L
L
↑
L
L
L
L
L
↑
H
L
L
L
X
H
B0‡
CLKENAB
OEAB
X
X
L
X
B0§
† A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA,
LEBA, and CLKENBA.
‡ Output level before the indicated steady-state input conditions were
established
§ Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low
L
L
L
H
PARITY ENABLE
INPUTS
2
OPERATION OR FUNCTION
SEL
OEBA
OEAB
L
H
L
Parity is checked on port A and is generated on port B.
L
L
H
Parity is checked on port B and is generated on port A.
L
H
H
Parity is checked on port B and port A.
L
L
L
Parity is generated on port A and B if device is in FF mode.
H
L
L
H
L
H
H
H
L
H
H
H
QA data to B, QB data to A
Parity functions are disabled;
device acts as a standard
18-bit
18
bit registered transceiver.
POST OFFICE BOX 655303
QB data to A
QA data to B
Isolation
• DALLAS, TEXAS 75265
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
Function Tables (Continued)
PARITY
INPUTS
OUTPUTS
SEL
OEBA
OEAB
ODD/EVEN
Σ OF INPUTS
A1–A8 = H
Σ OF INPUTS
B1–B8 = H
APAR
BPAR
APAR
ERRA
BPAR
ERRB
L
H
L
L
0, 2, 4, 6, 8
N/A
L
N/A
N/A
H
L
Z
L
H
L
L
1, 3, 5, 7
N/A
L
N/A
N/A
L
H
Z
L
H
L
L
0, 2, 4, 6, 8
N/A
H
N/A
N/A
L
L
Z
L
H
L
L
1, 3, 5, 7
N/A
H
N/A
N/A
H
H
Z
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
L
L
Z
N/A
H
L
L
H
L
N/A
1, 3, 5, 7
N/A
L
H
Z
N/A
L
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
H
L
Z
N/A
L
L
L
H
L
N/A
1, 3, 5, 7
N/A
H
H
Z
N/A
H
L
H
L
H
0, 2, 4, 6, 8
N/A
L
N/A
N/A
L
H
Z
L
H
L
H
1, 3, 5, 7
N/A
L
N/A
N/A
H
L
Z
L
H
L
H
0, 2, 4, 6, 8
N/A
H
N/A
N/A
H
H
Z
L
H
L
H
1, 3, 5, 7
N/A
H
N/A
N/A
L
L
Z
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
L
H
Z
N/A
L
L
L
H
H
N/A
1, 3, 5, 7
N/A
L
L
Z
N/A
H
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
H
H
Z
N/A
H
L
L
H
H
N/A
1, 3, 5, 7
N/A
H
L
Z
N/A
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
Z
H
Z
H
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
L
L
Z
L
Z
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
Z
L
Z
L
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
H
H
Z
H
Z
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
Z
L
Z
L
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
L
L
Z
H
Z
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
Z
H
Z
H
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
H
H
Z
L
Z
L
PE†
PO‡
Z
PE†
PO‡
Z
L
L
L
L
N/A
N/A
N/A
N/A
L
L
L
H
N/A
N/A
N/A
N/A
Z
Z
† Parity output is set to the level so that the specific bus side is set to even parity.
‡ Parity output is set to the level so that the specific bus side is set to odd parity.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
functional block diagram
LEAB
1CLKENAB
2CLKENAB
CLKAB
OEAB
2
1, 32
2
3
30
35
1A1–1A8
1APAR
1ERRB
5
61
2A1–2A8
2APAR
2ERRB
ODD/EVEN
SEL
28
36
18-Bit
Storage
18
A-Port
Parity
Generate
and
Check
B Data
18
QB
18-Bit
Storage
1B1–1B8
18
QA
18
OEBA
60
B-Port
Parity
Generate
and
Check
A Data
4
1BPAR
1ERRA
2B1–2B8
37
29
2BPAR
2ERRA
34
31
62
2
64, 33
63
CLKBA
1CLKENBA
2CLKENBA
LEBA
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed..
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
MIN
MAX
1.65
3.6
2
0.35 × VCC
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
0.7
VCC = 2.7 V to 3.6 V
IOL
∆t/∆v
High level output current
High-level
VCC = 2.7 V
VCC = 3 V
VCC = 1.65 V
VCC = 2.3 V
Low level output current
Low-level
VCC = 2.7 V
VCC = 3 V
Input transition rise or fall rate
V
1.7
VIL
IOH
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 1.65 V
VCC = 2.3 V
UNIT
V
0.8
VCC
VCC
V
V
–4
–12
–12
mA
–24
4
12
12
mA
24
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
1.65 V
IOH = –6 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
IOZ§
ICC
∆ICC
Ci
Cio
Co
A or B ports
2
2.3 V
1.7
UNIT
2.7 V
2.2
3V
2.4
3V
2
V
0.2
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
±5
3.6 V
VI = 0.58 V
VI = 1.07 V
1.65 V
25
1.65 V
–25
VI = 0.7 V
VI = 1.7 V
2.3 V
45
2.3 V
–45
VI = 0.8 V
VI = 2 V
3V
75
3V
–75
V
µA
µA
VI = 0 to 3.6 V‡
3.6 V
±500
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
750
µA
One input at VCC – 0.6 V,
Control inputs
2.3 V
0.45
IOL = 24 mA
VI = VCC or GND
II(hold)
(
)
MAX
VCC–0.2
1.2
1.65 V
IOL = 12 mA
II
TYP†
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
VOL
MIN
IO = 0
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
3.3 V
3
pF
3.3 V
7.5
pF
VO = VCC or GND
3.3 V
6
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ For I/O ports, the parameter IOZ includes the input leakage current.
6
ERR ports
3 V to 3.6 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
MIN
fclock
tw
tsu
th
Clock frequency
Pulse
duration
Setup time
Hold time
MAX
†
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 2.7 V
MIN
125
MAX
VCC = 3.3 V
± 0.3 V
MIN
125
125
CLK↑
†
3
3
3
LE high
†
3
3
3
A, APAR or B, BPAR before CLK↑
†
1.9
2
1.7
CLKEN before CLK↑
†
2.1
2.1
1.7
A, APAR or B, BPAR before LE↓
†
1.4
1.3
1.2
A, APAR or B, BPAR after CLK↑
†
0.4
0.4
0.5
CLKEN after CLK↑
†
0.5
0.5
0.7
A, APAR or B, BPAR after LE↓
†
0.9
1.1
0.9
UNIT
MAX
MHz
ns
ns
ns
† This information was not available at the time of publication.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
TO
(OUTPUT)
MIN
†
fmax
A or B
APAR or BPAR
ODD/EVEN
SEL
tpd
CLKAB or CLKBA
LEAB or LEBA
TYP
VCC = 2.5 V
± 0.2 V
MIN
MAX
125
VCC = 2.7 V
MIN
MAX
125
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
125
MHz
B or A
†
1
5.2
4.8
1
4.4
BPAR or APAR
†
2
8.9
7.6
2
6.7
BPAR or APAR
†
1
5.7
5.2
1
4.7
ERRA or ERRB
†
2
9.7
8.7
2
7.5
ERRA or ERRB
†
1.5
8.7
7.9
1.5
6.8
BPAR or APAR
†
1.5
8.3
7.6
1.5
6.5
BPAR or APAR
†
1
6.1
5.9
1
5.1
A or B
†
1
6.4
5.8
1
5.1
BPAR or APAR
parity feedthrough
†
1.5
7.1
6.3
1.5
5.6
BPAR or APAR
parity generated
†
2.5
10.2
8.7
2
7.7
ERRA or ERRB
†
2.5
10.5
8.9
2
7.9
A or B
†
1
6
5.5
1
4.8
BPAR or APAR
parity feedthrough
†
1.5
6.7
6
1.5
5.3
BPAR or APAR
parity generated
†
2.5
9.8
8.3
2
7.4
ERRA or ERRB
†
2.5
9.9
8.5
2
7.5
ns
ten
OEAB or OEBA
B, BPAR or A,
APAR
†
1.4
6.3
6.1
1
5.3
ns
tdis
OEAB or OEBA
B, BPAR or A,
APAR
†
1.3
6.1
5.2
1.5
4.9
ns
ten
OEAB or OEBA
ERRA or ERRB
†
1.4
6.2
5.5
1
4.9
ns
tdis
OEAB or OEBA
ERRA or ERRB
†
1.3
7.3
6.5
1
5.7
ns
ERRA or ERRB
†
1.4
6.7
6.5
1
5.5
ns
tdis
ERRA or ERRB
SEL
† This information was not available at the time of publication.
†
1.3
6.4
5.4
1.5
4.9
ns
ten
SEL
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
pF
VCC = 1.8 V
TYP
†
f = 10 MHz
† This information was not available at the time of publication.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
†
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
22
27
5
8
UNIT
pF
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
Input
1.5 V
0V
1.5 V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
3V
1.5 V
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated