SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus+ Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Simultaneously Generates and Checks Parity Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down-Mode Operation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class I Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in Thin Shrink Small-Outline Package 1CLKENAB LEAB CLKAB 1ERRA 1APAR GND 1A1 1A2 1A3 VCC 1A4 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 2A5 VCC 2A6 2A7 2A8 GND 2APAR 2ERRA OEAB SEL 2CLKENAB 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 1CLKENBA LEBA CLKBA 1ERRB 1BPAR GND 1B1 1B2 1B3 VCC 1B4 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 2B5 VCC 2B6 2B7 2B8 GND 2BPAR 2ERRB OEBA ODD/EVEN 2CLKENBA description This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver, or it can generate/check parity from the two 8-bit data buses in either direction. The SN74LVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of data flow is controlled by output-enable (OEAB and OEBA) inputs. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered transceiver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 description (continued) Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74LVCH16901 is characterized for operation from –40°C to 85°C. Function Tables FUNCTION† INPUTS LEAB CLKAB A OUTPUT B H X X X Z L H X L L X L H X H H L L X X H B0‡ L L L ↑ L L L L L ↑ H L L L L X H B0‡ B0§ CLKENAB OEAB X X L L L H X † A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA, LEBA, and CLKENBA. ‡ Output level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low PARITY ENABLE INPUTS 2 OPERATION OR FUNCTION SEL OEBA OEAB L H L Parity is checked on port A and is generated on port B. L L H Parity is checked on port B and is generated on port A. L H H Parity is checked on port B and port A. L L L Parity is generated on port A and B if device is in FF mode. H L L H L H H H L H H H QA data to B, QB data to A Parity functions are disabled; device acts as a standard 18-bit 18 bit registered transceiver. POST OFFICE BOX 655303 QB data to A QA data to B Isolation • DALLAS, TEXAS 75265 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 Function Tables (Continued) PARITY INPUTS OUTPUTS SEL OEBA OEAB ODD/EVEN Σ OF INPUTS A1–A8 = H Σ OF INPUTS B1–B8 = H APAR BPAR APAR ERRA BPAR ERRB L H L L 0, 2, 4, 6, 8 N/A L N/A N/A H L Z L H L L 1, 3, 5, 7 N/A L N/A N/A L H Z L H L L 0, 2, 4, 6, 8 N/A H N/A N/A L L Z L H L L 1, 3, 5, 7 N/A H N/A N/A H H Z L L H L N/A 0, 2, 4, 6, 8 N/A L L Z N/A H L L H L N/A 1, 3, 5, 7 N/A L H Z N/A L L L H L N/A 0, 2, 4, 6, 8 N/A H L Z N/A L L L H L N/A 1, 3, 5, 7 N/A H H Z N/A H L H L H 0, 2, 4, 6, 8 N/A L N/A N/A L H Z L H L H 1, 3, 5, 7 N/A L N/A N/A H L Z L H L H 0, 2, 4, 6, 8 N/A H N/A N/A H H Z L H L H 1, 3, 5, 7 N/A H N/A N/A L L Z L L H H N/A 0, 2, 4, 6, 8 N/A L H Z N/A L L L H H N/A 1, 3, 5, 7 N/A L L Z N/A H L L H H N/A 0, 2, 4, 6, 8 N/A H H Z N/A H L L H H N/A 1, 3, 5, 7 N/A H L Z N/A L L H H L 0, 2, 4, 6, 8 0, 2, 4, 6, 8 L L Z H Z H L H H L 1, 3, 5, 7 1, 3, 5, 7 L L Z L Z L L H H L 0, 2, 4, 6, 8 0, 2, 4, 6, 8 H H Z L Z L L H H L 1, 3, 5, 7 1, 3, 5, 7 H H Z H Z H L H H H 0, 2, 4, 6, 8 0, 2, 4, 6, 8 L L Z L Z L L H H H 1, 3, 5, 7 1, 3, 5, 7 L L Z H Z H L H H H 0, 2, 4, 6, 8 0, 2, 4, 6, 8 H H Z H Z H L H H H 1, 3, 5, 7 1, 3, 5, 7 H H Z L Z L PE† PO‡ Z PE† PO‡ Z L L L L N/A N/A N/A N/A L L L H N/A N/A N/A N/A Z Z † Parity output is set to the level so that the specific bus side is set to even parity. ‡ Parity output is set to the level so that the specific bus side is set to odd parity. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 functional block diagram LEAB 2 1CLKENAB 2CLKENAB CLKAB OEAB OEBA 1A1–1A8 1APAR 1ERRB 2A1–2A8 2APAR 2ERRB 18-Bit Storage 18 A-Port Parity Generate and Check B Data 18 QB 18-Bit Storage 1B1–1B8 18 QA 18 B-Port Parity Generate and Check A Data 1BPAR 1ERRA 2B1–2B8 2BPAR 2ERRA ODD/EVEN SEL CLKBA 2 1CLKENBA 2CLKENBA LEBA absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 recommended operating conditions (see Note 4) VCC VIH Operating Supply voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI Input voltage VO Output voltage IOH Low level output current Low-level ∆t/∆v Input transition rise or fall rate MAX 3.6 1.5 UNIT V 0.65 × VCC V 1.7 2 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V High level output current High-level IOL MIN 1.65 0.7 V 0.8 0 5.5 V High or low state 0 3 state 0 VCC 5.5 V VCC = 1.65 V VCC = 2.3 V –4 VCC = 2.7 V VCC = 3 V –12 –8 mA –24 VCC = 1.65 V VCC = 2.3 V 4 VCC = 2.7 V VCC = 3 V 12 8 mA 24 5 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA IOH = –8 mA VOH 12 mA IOH = –12 IOH = –24 mA IOL = 100 µA VOL II II(hold) ( ) Control inputs A or B ports 2.2 3V 2.4 3V 2.2 0.2 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 VI = 0 to 5.5 V 3.6 V ±5 V µA 25 VI = 0.58 V VI = 1.07 V 1 65 V 1.65 VI = 0.7 V VI = 1.7 V 23V 2.3 VI = 0.8 V VI = 2 V 3V VO = 0 to 5.5 V VI = VCC or GND 3.6 V ≤ VI ≤ 5.5 V¶ UNIT V 0.45 IOZ§ Ci 1.7 2.7 V 1.65 V VI or VO = 5.5 V IO = 0 One input at VCC – 0.6 V, Control inputs 2.3 V MAX 1.65 V to 3.6 V Ioff ∆ICC 1.65 V VCC–0.2 1.2 TYP† IOL = 4 mA IOL = 8 mA VI = 0 to 3.6 V‡ ICC MIN –25 45 µA –45 75 –75 3.6 V ±600 0 ±10 µA 3.6 V ±10 µA 20 36V 3.6 Other inputs at VCC or GND 20 2.7 V to 3.6 V VI = VCC or GND 3.3 V 500 7 µA µA pF Cio A or B ports VO = VCC or GND 3.3 V 9.5 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § For I/O ports, the parameter IOZ includes the input leakage current, but not II(hold). ¶ This applies in the disabled state only. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V† MIN fclock Clock frequency tw Pulse duration tsu Setup time th Hold time MAX VCC = 2.5 V ± 0.2 V MIN MAX 125 VCC = 2.7 V MIN 125 MAX VCC = 3.3 V ± 0.3 V MIN 125 125 CLK↑ 4 3 3 3 LE high 3 3 3 3 A, APAR or B, BPAR before CLK↑ 4.7 2.7 2.8 2.5 CLKEN before CLK↑ 4.5 2.9 2.9 2.5 A, APAR or B, BPAR before LE↓ 0 2.2 2.1 2 A, APAR or B, BPAR after CLK↑ 0 1.2 1.2 1.3 CLKEN after CLK↑ 0 1.3 1.3 1.5 A, APAR or B, BPAR after LE↓ 1 1.7 1.9 1.7 UNIT MAX MHz ns ns ns † Texas Instruments SPICE simulation data switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V† TYP MIN fmax A or B APAR or BPAR ODD/EVEN SEL tpd CLKAB or CLKBA LEAB or LEBA VCC = 2.5 V ± 0.2 V MAX VCC = 2.7 V MIN MAX 125 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 125 125 B or A 5.9 1 6.2 5.8 125 1 5.4 MHz BPAR or APAR 12.7 2 9.9 8.6 2 7.7 BPAR or APAR 7 1 6.7 6.2 1 5.7 ERRA or ERRB 13 2 10.7 9.7 2 8.5 ERRA or ERRB 9.9 1.5 9.7 8.9 1.5 7.8 BPAR or APAR 10.4 1.5 9.3 8.6 1.5 7.5 BPAR or APAR 6.9 1 7.1 6.9 1 6.1 A or B 6.9 1 7.4 6.8 1 6.1 BPAR or APAR parity feedthrough 8.5 1.5 8.1 7.3 1.5 6.6 BPAR or APAR parity generated 14.1 2.5 11.2 9.7 2 8.7 ERRA or ERRB 14.3 2.5 11.5 9.9 2 8.9 A or B 6.8 1 7 6.5 1 5.8 BPAR or APAR parity feedthrough 7.9 1.5 7.7 7 1.5 6.3 BPAR or APAR parity generated 13.6 2.5 10.8 9.3 2 8.4 ns ERRA or ERRB 13.5 2.5 10.9 9.5 2 8.5 ten OEAB or OEBA B, BPAR or A, APAR 6.8 1.4 7.3 7.1 1 6.3 ns tdis OEAB or OEBA B, BPAR or A, APAR 6.9 1.3 7.1 6.2 1.5 5.9 ns ten OEAB or OEBA ERRA or ERRB 7.4 1.4 7.2 6.5 1 5.9 ns tdis OEAB or OEBA ERRA or ERRB 9.3 1.3 8.3 7.5 1 6.7 ns ten SEL ERRA or ERRB 7.6 1.4 7.7 7.5 1 6.5 ns tdis SEL ERRA or ERRB 7.8 1.3 7.4 6.4 1.5 5.9 ns † Texas Instruments SPICE simulation data POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Outputs enabled Power dissipation capacitance per transceiver Cpd VCC = 1.8 V TYP Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 37 52 68 16 22 28 UNIT pF PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 Output Control (low-level enabling) VCC VCC/2 VCC/2 0V tPLH Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VOH VCC/2 VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) VOL + 0.15 V VOL tPHZ tPZH tPHL VCC/2 0V tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145A – OCTOBER 1998 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V tPZH tPHL 1.5 V VOL 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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