IDT 840272AGILFT

Synchronous Ethernet Frequency Translator
ICS840272I
DATA SHEET
General Description
Features
The ICS840272I is a PLL-based Frequency Translator intended for
use in Synchronous Ethernet applications. This high performance
device is optimized to generate 25MHz and 8kHz LVCMOS clock
outputs. The ICS840272I accepts the following differential or
single-ended input signals: 161.1328125MHz (10GbE Mode),
156.25MHz (1GbE Mode), or 125MHz (Recovered clock from
10/100/1000BaseT Ethernet PHY). The extended temperature
range supports telecommunication and networking end equipment
requirements.
•
Two single-ended outputs (LVCMOS or LVTTL levels),
output impedance: 17Ω
•
•
•
Single-ended lock detect output (LVCMOS or LVTTL levels)
•
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
•
Selectable input frequencies: 161.1328MHz, 156.25MHz or
125MHz
•
•
•
•
Output frequency: 25MHz, 8kHz
Pin Assignment
VDD
LOCK_DT
REF_SEL
SEL0
SEL1
OE
VDDA
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDO
QA
QB
GND
CLK0
nCLK0
CLK1
nCLK1
Two selectable differential clock inputs
Differential input pair (CLKx, nCLKx) accepts LVPECL, LVDS,
LVHSTL, SSTL, HCSL input levels
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
ICS840272I
16 Lead TSSOP
4.40mm x 5.0mm x 0.925mm package body
G Package
Top View
Block Diagram
LOCK_DT
CLK0
0
Pulldown
nCLK0 Pullup/Pulldown
0
P
CLK1 Pulldown
Pullup/Pulldown
QA
25MHz
N
PLL
1
1
nCLK1
÷3125
REF_SEL Pulldown
QB
8kHz
M
Input Control
SEL[1:0] Pulldown:Pullup
00 = PLL Bypass, 25MHz Input
01 = 161.1328125MHz (default)
10 = 156.25MHz
11 = 125MHz
OE Pulldown
ICS840272AGI REVISION A JULY 26, 2010
1
©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Table 1. Pin Descriptions
Number
Name
1
VDD
Power
Type
Description
Core supply pin.
2
LOCK_DT
Output
Lock detect. Logic HIGH when PLL is locked.
3
REF_SEL
Input
Pulldown
4
SEL0
Input
Pullup
Selects the input reference frequency and the PLL bypass mode. See Table 3A.
LVCMOS/LVTTL interface levels.
5
SEL1
Input
Pulldown
Selects the input reference frequency and the PLL bypass mode. See Table 3A.
LVCMOS/LVTTL interface levels.
6
OE
Input
Pulldown
8kHz output enable pin. When LOW, QB is disabled. When HIGH, QB is enabled.
LVCMOS/LVTTL interface levels. See Table 3B.
7
VDDA
Power
Analog supply pin.
8, 13
GND
Power
Power supply ground.
9
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
10
CLK1
Input
Pulldown
Non-inverting differential clock input.
11
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
12
CLK0
Input
Pulldown
Non-inverting differential clock input.
14
QB
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
15
QA
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
16
VDDO
Power
Output supply pin.
Selects the input reference clock. When LOW, selects CLK0, nCLK0.
When HIGH, selects CLK1, nCLK1. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
17
Ω
ICS840272AGI REVISION A JULY 26, 2010
Test Conditions
VDDO = 3.465V
2
Minimum
Typical
Maximum
Units
©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Function Tables
Table 3A. SEL[1:0] Function Table
Inputs
Function
Output (MHz)
SEL1
SEL0
CLKx, nCLKx (MHz)
Mode
QA
0
0
25
PLL Bypass
25
0 (default)
1 (default)
161.1328125
PLL Enabled
25
1
0
156.25
PLL Enabled
25
1
1
125
PLL Enabled
25
Table 3B. OE Function Table
Control Input
Function
OE
QB Output
0 (default)
Disabled (High impedance)
1
Enabled
ICS840272AGI REVISION A JULY 26, 2010
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©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVCMOS)
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
81.2°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.11
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
57
mA
IDDA
Analog Supply Current
11
mA
IDDO
Output Supply Current
5
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
VIL
IIH
IIL
Test Conditions
Minimum
Input High Voltage
VDD = 3.465V
Input Low Voltage
VDD = 3.465V
Input High Current
Input Low Current
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
OE, SEL1,
REF_SEL
VDD = VIN = 3.465V
150
µA
SEL0
VDD = VIN = 3.465V
5
µA
OE, SEL1,
REF_SEL
VDD = 3.465V, VIN = 0V
-5
µA
SEL0
VDD = 3.465V, VIN = 0V
-150
µA
2.6
V
VOH
Output High Voltage
IOH = -12mA
VOL
Output Low Voltage
IOL = 12mA
ICS840272AGI REVISION A JULY 26, 2010
4
0.5
V
©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage;
NOTE 1, 2
Minimum
Typical
Maximum
Units
150
µA
CLK[0:1],
nCLK[0:1]
VDD = VIN = 3.465V
CLK[0:1]
VDD = 3.465V, VIN = 0V
-5
µA
nCLK[0:1]
VDD = 3.465V, VIN = 0V
-150
µA
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
Maximum
Units
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
QA
25MHz, Integration Range:
12kHz – 10MHz
tjit(cc)
Cycle-to-Cycle Jitter
QA
25MHz
tR / t F
Output Rise/Fall Time
QA
20% to 80%
QB
20% to 80%
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
QA
25
MHz
QB
8
kHz
1.1
ps
37
ps
450
1100
ps
450
1100
ps
QA
47
53
%
QB
47
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to Phase Noise plot.
ICS840272AGI REVISION A JULY 26, 2010
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©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Typical Phase Noise at 25MHz
Noise Power
dBc
Hz
Additive Phase Jitter @ 25MHz
12kHz to 10MHz = 1.1ps (typical)
Offset Frequency (Hz)
ICS840272AGI REVISION A JULY 26, 2010
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©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Parameter Measurement Information
1.65V±5%
1.65V±5%
VDD
SCOPE
VDD,
VDDO
nCLK[0:1]
VDDA
Qx
LVCMOS
V
V
Cross Points
PP
CMR
CLK[0:1]
GND
GND
-1.65V±5%
LVCMOS Output Load AC Test Circuit
Differential Input Level
V
DDO
2
QA, QB
80%
80%
tR
tF
t PW
t
PERIOD
QA, QB
odc =
t PW
20%
20%
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
Noise Power
Phase Noise Plot
V
V
V
DDORx
DDORx
2
DDORx
2
tcycle n
➤
QA, QB
➤
2
tcycle n+1
➤
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
f1
Offset Frequency
f2
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter
ICS840272AGI REVISION A JULY 26, 2010
Cycle-to-Cycle Jitter
7
©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS840272I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA and VDDO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVCMOS Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
All unused LVCMOS output can be left floating. There should be no
trace attached.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
ICS840272AGI REVISION A JULY 26, 2010
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©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VDD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS840272AGI REVISION A JULY 26, 2010
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©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the VPP and VCMR
input requirements. Figures 3A to 3F show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 3A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
R1
50Ω
IDT
LVHSTL Driver
R1
50Ω
Differential
Input
LVHSTL
R2
50Ω
Differential
Input
LVPECL
nCLK
R2
50Ω
R2
50Ω
Figure 3A. CLK/nCLK Input
Driven by an IDT Open Emitter LVHSTL Driver
Figure 3B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
R3
125Ω
3.3V
R4
125Ω
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
Differential
Input
LVPECL
R1
84Ω
R2
84Ω
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 3C. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
*R3
33Ω
R3
120Ω
Zo = 50Ω
R4
120Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33Ω
R1
50Ω
R2
50Ω
Differential
Input
SSTL
R1
120Ω
R2
120Ω
Differential
Input
*Optional – R3 and R4 can be 0Ω
Figure 3F. CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
ICS840272AGI REVISION A JULY 26, 2010
10
©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Schematic Example
Figure 4 shows an example of ICS840272I applications schematic. In
this example, the device is operated at VDD = 3.3V. The input is driven
by either a 3.3V LVPECL or LVDS driver. Two examples of LVCMOS
terminations are shown in this schematic. The decoupling capacitors
should be located as close as possible to the power pin.
Logic Control Input Examples
Set Logic
Input to '1'
VDD
Set Logic
Input to '0'
VDD
RU1
1K
R8
35
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
RD2
1K
To Logic
Input
pins
U1
C3
0.1u
VDD
VDDA
R1
10
C1
10uF
Zo = 50 Ohm
VDD
C2
0.01u
1
2
3
4
5
6
7
8
LVCMOS
VDD
VDDO
LOCK_DT
QA
REF_SEL
QB
SEL0
GND
SEL1
CLK0
OE
nCLK0
VDDA
CLK1
GND
nCLK1
16
15
14
13
12
11
10
9
VDD
C4
0.1u
LD1
LED
R9
100
Zo = 50 Ohm
R10
100
R2
2.7K
LVCMOS
VDD
LVDS
Optional Termination
Zo = 50 Ohm
R3
100
Zo = 50 Ohm
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
VDD
VDD
Zo = 50 Ohm
R4
125
R6
125
Zo = 50 Ohm
LVPECL
R5
84
R7
84
Figure 4. ICS840272I Schematic Example
ICS840272AGI REVISION A JULY 26, 2010
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©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS840272I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS840272I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD + IDDA+ IDDO) = 3.465V *(57mA + 11mA + 5mA) = 252.9mW
•
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 17Ω)] = 25.86mA
•
Total Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 17Ω * (25.86mA)2 = 11.4mW per output
Total Power (ROUT) = 11.4mW * 2 = 22.8mW
Total Power Dissipation
•
Total Power
= Power (core)MAX + Total Power (ROUT)
= 252.9mW + 22.8mW
= 275.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 81.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.276W *81.2°C/W = 107.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS840272AGI REVISION A JULY 26, 2010
0
1
2.5
81.2°C/W
73.9°C/W
70.2°C/W
12
©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Reliability Information
Table 7. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
81.2°C/W
73.9°C/W
70.2°C/W
Transistor Count
The transistor count for ICS840272I: 3326
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 8. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS840272AGI REVISION A JULY 26, 2010
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©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Ordering Information
Table 9. Ordering Information
Part/Order Number
840272AGILF
840272AGILFT
Marking
40272AIL
40272AIL
Package
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS840272AGI REVISION A JULY 26, 2010
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©2010 Integrated Device Technology, Inc.
ICS840272I Data Sheet
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
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