Low Skew, 1-to-6, Differential-toLVDS Fanout Buffer ICS854S006I DATA SHEET GENERAL DESCRIPTION FEATURES The ICS854S006I is a low skew, high perforICS mance 1-to-6 Differential-to-LVDS Fanout Buffer. HiPerClockS™ The CLK, nCLK pair can accept most standard differential input levels. The ICS854S006I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output skew characteristic s make the ICS854S006I ideal for those clock distribution applications demanding well defined performance and repeatability. • Six differential LVDS outputs • One differential clock input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1.7GHz • Translates any single ended input signal to LVDS levels with resistor bias on nCLK input • Output skew: 55ps (maximum) • Propagation delay: 850ps (maximum) • Additive phase jitter, RMS: 0.067ps (typical) • Full 3.3V or 2.5V power supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT Q0 nQ0 CLK Pullup nCLK Pulldown nCLK CLK VDD VDDO Q0 nQ0 GND Q1 nQ1 VDDO Q2 nQ2 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GND GND VDD VDDO nQ5 Q5 GND nQ4 Q4 VDDO nQ3 Q3 ICS854S006I 24-Lead TSSOP 4.40mm x 7.8mm x 0.925mm package body G Package Top View ICS854S006AGI REVISION B JANUARY 18, 2010 1 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 nCLK Input 2 CLK Input Description Pulldown Inver ting differential clock input. Pullup Non-inver ting differential clock input. 3, 22 VDD Power Positive supply pins. 4, 10, 15, 21 VDDO Power Output supply pins. 5, 6 Q0, nQ0 Output Differential output pair. LVDS interface levels. 7, 18, 23, 24 GND Power Power supply ground. 8, 9 Q1, nQ1 Output Differential output pair. LVDS interface levels. 11, 12 Q2, nQ2 Output Differential output pair. LVDS interface levels. 13, 14 Q3, nQ3 Output Differential output pair. LVDS interface levels. 16, 17 Q4, nQ4 Output Differential output pair. LVDS interface levels. 19, 20 Q5, nQ5 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs CLK Outputs nCLK Q0:Q5 nQ0:nQ5 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". ICS854S006AGI REVISION B JANUARY 18, 2010 2 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, IO (LVDS) Continuous Current Surge Current 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the -0.5V to VDD + 0.5 V device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond 10mA 15mA those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- Package Thermal Impedance, θJA 70°C/W (0 mps) Storage Temperature, TSTG tended periods may affect product reliability. -65°C to 150°C (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Positive Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 55 mA IDDO Output Supply Current 105 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Positive Supply Voltage Test Conditions 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 55 mA IDDO Output Supply Current 102 mA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current CLK nCLK CLK IIL Input Low Current nCLK Test Conditions VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VPP Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; VCMR NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode voltage is defined as VIH. ICS854S006AGI REVISION B JANUARY 18, 2010 Minimum 3 Typical Maximum Units 10 µA 150 µA -150 µA -10 µA 0.15 1. 3 V GND + 0.5 VDD - 0.85 V ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Maximum Units 326 Typical 526 mV 50 mV 1.28 1.44 V 50 mV NOTE: Please refer to Parameter Measurement Information for output information. TABLE 4E. LVDS DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Test Conditions Minimum Maximum Units 305 Typical 505 mV 50 mV 1.1 1.45 V 50 mV VOS Magnitude Change Δ VOS NOTE: Please refer to Parameter Measurement Information for output information. NOTE: Maximum value is a design target spec. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time tjit tR / tF Test Conditions Minimum Typical 300 622.08MHz, Integration Range: 12kHz – 20MHz 20% to 80% Maximum Units 1.7 GH z 850 ps 55 ps 0.067 50 ps 250 ps odc Output Duty Cycle ≤ 1.2GHz 47 53 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time tjit tR / tF odc Output Duty Cycle For NOTES, see Table 5A. ICS854S006AGI REVISION B JANUARY 18, 2010 Test Conditions Minimum Typical 300 622.08MHz, Integration Range: 12kHz – 20MHz Maximum Units 1.7 GH z 800 ps 55 ps 0.067 ps 20% to 80% 50 250 ps ≤ 1.2GHz 47 53 % 4 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz Input/Output Additive Phase Jitter @ SSB PHASE NOISE dBc/HZ 622.08MHz (12kHz to 20MHz) = 0.067ps (typical) OFFSET FROM CARRIER FREQUENCY (HZ) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the ICS854S006AGI REVISION B JANUARY 18, 2010 5 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION SCOPE SCOPE 3.3V±5% POWER SUPPLY + Float GND – Qx VDD, VDDO 2.5V±5% POWER SUPPLY + Float GND – LVDS Qx VDD, VDDO LVDS nQx nQx 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT VDD nQx Qx nCLK V nQy V Cross Points PP CMR CLK Qy tsk(o) GND DIFFERENTIAL INPUT LEVEL OUTPUT SKEW nCLK nQ0:nQ5 80% 80% CLK VOD Q0:Q5 nQ0:nQ5 20% 20% tR tF Q0:Q5 tPD OUTPUT RISE/FALL TIME ICS854S006AGI REVISION B JANUARY 18, 2010 PROPAGATION DELAY 6 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION, CONTINUED VDD out nQ0:nQ5 DC Input t PW odc = PERIOD t PW out ➤ VOS/Δ VOS ➤ t LVDS ➤ Q0:Q5 x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OFFSET VOLTAGE SETUP VDD LVDS 100 ➤ VOD/Δ VOD out ➤ DC Input ➤ out DIFFERENTIAL OUTPUT VOLTAGE SETUP ICS854S006AGI REVISION B JANUARY 18, 2010 7 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVDS OUTPUTS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. ICS854S006AGI REVISION B JANUARY 18, 2010 8 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK Differential Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver Differential Input LVPECL R2 50 R1 50 R2 50 R2 50 FIGURE 2A. CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER LVHSTL DRIVER FIGURE 2B. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 Zo = 50Ω Zo = 50Ω CLK CLK R1 100 Zo = 50Ω nCLK R1 84 R2 84 nCLK Zo = 50Ω Differential Input LVPECL Receiver LVDS FIGURE 2C. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 2D. CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33 R1 50 R2 50 Differential Input SSTL R1 120 R2 120 Differential Input *Optional – R3 and R4 can be 0Ω FIGURE 2F. CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 2E. CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER ICS854S006AGI REVISION B JANUARY 18, 2010 9 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION ICS854S006AGI REVISION B JANUARY 18, 2010 10 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS854S006I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S006I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 190.575mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 105mA = 363.825mW Total Power_MAX = 190.575mW + 363.825mW = 554.4mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 70°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.554W * 70°C/W = 123.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards ICS854S006AGI REVISION B JANUARY 18, 2010 11 0 1 2.5 70°C/W 65°C/W 62°C/W ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS854S006I is: 293 PACKAGE OUTLINE & DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS854S006AGI REVISION B JANUARY 18, 2010 12 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 854S006AGI ICS854S006AGI 24 lead TSSOP tube -40°C to 85°C 854S006AGIT ICS854S006AGI 24 lead TSSOP 2500 tape & reel -40°C to 85°C 854S006AGILF ICS854S006AIL 24 lead "Lead-Free" TSSOP tube -40°C to 85°C 854S006AGILFT ICS854S006AIL 24 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS854S006AGI REVISION B JANUARY 18, 2010 13 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER REVISION HISTORY SHEET Rev A Table T4D, T4E T9 Page 4 13 T1 T4C 1 2 3 B T5A, T5B 4 9 Description of Change LVDS DC Characteristics Table - changed VOD units from V to mV. Ordering Information Table - deleted "ICS" prefix from Par t/Order column. Changed style of header/footer. Block Diagram - changed CLK to "pullup" and nCLK to "pulldown". Pin Descriptions - changed CLK and nCLK "Type" to reflect block diagram. Differential DC Characteristics Table - IIH parameters, changed CLK levels from 150uA max. to 10uA max.; nCLK levels from 5uA max. to 150uA max. IIL parameters, changed CLK levels from -5uA min. to -150uA min.; nCLK levels from -150uA min. to -10uA min. Added thermal note. Updated Differential Clock Input Interface section. ICS854S006AGI REVISION B JANUARY 18, 2010 14 Date 7/20/09 1/18/10 ©2010 Integrated Device Technology, Inc. ICS854S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER www.IDT.com 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Techical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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