IDT IDTSSTE32882HLBAKG

DATASHEET
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST
AND QUAD CHIP SELECT
Description
This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock
driver with parity is designed for 1.35V and 1.5V VDD operation.
All inputs are 1.35V and 1.5V CMOS compatible, except the
reset (RESET) and MIRROR inputs which are LVCMOS. All
outputs are 1.35V and 1.5V CMOS edge-controlled drivers
optimized to drive single terminated 25 to 50 traces in DDR3
RDIMM applications, except the open-drain error (ERROUT)
output. The clock outputs (Yn and Yn) and control net outputs
QnCKEn, QnCSn and QnODTn are designed with a different
strength and skew to compensate for different loading and
equalize signal travel speed.
The SSTE32882HLB has two basic modes of operation
associated with the Quad Chip Select Enable (QCSEN) input.
When the QCSEN input pin is open (or pulled high), the
component has two chip select inputs, DCS0 and DCS1, and two
copies of each chip select output, QACS0, QACS1, QBCS0 and
QBCS1. This is the "QuadCS disabled" mode. When the
QCSEN input pin is pulled low, the component has four chip
select inputs DCS[3:0], and four chip select outputs, QCS[3:0].
This is the "QuadCS enabled" mode. Through the remainder of
this specification, DCS[n:0] will indicate all of the chip select
inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS
enabled. QxCS[n:0] will indicate all of the chip select outputs.
SSTE32882HLB
has occurred on the open-drain ERROUT pin (active low). The
convention is even parity; i.e., valid parity is defined as an even
number of ones across the DIMM-independent data inputs
combined with the parity input bit. To calculate parity, all
DIMM-independent D-inputs must be tied to a known logic state.
The DIMM-dependent signals (DCKEn, DODTn, and DCSn) are
not included in the parity check computation.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the low state during
power-up.
The SSTE32882HLB is available in a 176-ball BGA with
0.65mm ball pitch in a 11 x 20 grid. It is also available in a
176-ball Thin-Profile Fine-Pitch BGA with 0.65mm ball pitch in
an 8x22 grid. The device pinout supports outputs on the outer two
left and right columns to support easy DIMM signal routing.
Corresponding inputs are placed in a-way that two devices can be
placed back-to-back for four Rank modules while the data inputs
share the same vias. Each input and output is located close to an
associated no ball position or on the outer two rows to allow low
cost via technology combined with the small 0.65mm ball pitch.
The SSTE32882HLB includes a high-performance, low-jitter,
low-skew buffer that distributes a differential clock input (CK
and CK) to four differential pairs of clock outputs (Yn and Yn),
and to one differential pair of feedback clock outputs (FBOUT
and FBOUT). The clock outputs are controlled by the input
clocks (CK and CK), the feedback clocks (FBIN and FBIN), and
the analog power inputs (AVDD and AVSS). When AVDD is
grounded, the PLL is turned off and bypassed for test purposes.
The SSTE32882HLB operates from a differential clock (CK and
CK). Data are registered at the crossing of CK going high, and
CK going low. The data is either driven to the corresponding
device outputs if exactly one of the DCS[n:0] input signals is
driven low.
Based on the control register settings, the device can change its
output characterisitics to match different DIMM net topologies.
The timing can be changed to compensate for different flight time
of signals within the target application. By disabling unused
outputs the power consumption is reduced.
The SSTE32882HLB accepts a parity bit from the memory
controller on the parity (PAR_IN) input, compares it with the data
received on the DIMM-independent data inputs (DAn, DBAn,
DRAS, DCAS, and DWE), and indicates whether a parity error
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
1
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Features
•
•
•
•
•
•
Pinout optimizes DDR3 RDIMM PCB layout
•
•
•
•
Supports CKE Power Down operation modes
1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
Supports LVCMOS switching levels on the RESET and MIRROR inputs
Checks priority on DIMM-independent data inputs
Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations
and MRS command pass-through
Supports Quad Chip Select operation features
RESET input disables differential input recievers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
Provides access to internal control words for configuring the device features and adapting in different RDIMM and system
applications
• Latch-up performance exceeds 100mA
• ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)
• Available in 176 Ball Grid Array package
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
2
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Block Diagram - Register and PLL Logic Diagram (Positive Logic)
DRAS
DCAS
DWE
VREF
DA3..DA9,
DA11,
DA13..DA15,
DBA0..DBA2
Output
Inversion
QxA3..QxA9,
QxA11,
QxA13..QxA15,
QxBA0..QxBA2
D
0
Q
R CE
1
3
DA0..DA2, DBA2
DA0-DA2,
DA10, DA12,
DRAS, DCAS,
DWE
4
DA3, DA4, DBA0, DBA1
B-Enable
Control Word
A-Enable
State Machine and
Y0..Y3Control Logic
Enable
D
Q
R CE
CMR
Access
PreLaunch
4
(1)
DCS[n:0]
D
(1)
0
Q
R
DCKE0,
DCKE1
QxA0-QxA2,
QxA10,
QxA12,
QxRAS,
QxCAS,
QxWE
1/4 CK
delay
QxCS[n:0]
1
CS
Logic
D
DODT0,
DODT1
QACKEn
0
Q
R
1/4 CK
delay
1
QBCKEn
D
QAODTn
0
Q
R
1/4 CK
delay
RESET
1
QBODTn
OE0
Y0
Y0
OE1
Y1
CK
CK
Y1
10K~100K
FBIN
FBIN
PLL
OE2
0
1/4 CK
delay
Y2
1
Y2
OE3
Y3
Y3
FBOUT
FBOUT
1 DCS[n:0] indicates all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0]
indicates all of the chip select outputs.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
3
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Block Diagram - Parity Logic Diagram (Positive Logic)
VREF
DRAS
DCAS
DWE
DA0..DA15,
DBA0..DBA2,
DRAS, DCAS,
DWE
Output Inversion Disabled
3T Timing Enabled
D
Q
R
PAR_IN
Internal Logic
CE
D
Q
R CE
Parity Generator
and
Error Check
QA0..QA15,
QBA0..QBA2,
QRAS, QCAS,
QWE
ERROUT
(1)
DCS[n:0]
D
(1)
Q
Internal Logic
Q
Internal Logic
QxCS[n:0]
R
CS Logic
DCKE0,
DCKE1
D
QACKEn
QBCKEn
R
DODT0,
DODT1
QAODTn
D
Q
Internal Logic
QBODTn
R
RESET
Y0
Y0
Y1
CK
Internal Logic
CK
10K - 100K
Y1
Y2
Y2
Y3
PLL
FBIN
Y3
FBIN
FBOUT
FBOUT
1 DCS[n:0] indicates all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0]
indicates all of the chip select outputs.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
4
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Pinout Configuration
Package options include a 176-ball Thin-Profile Fine-Pitch BGA (TFBGA) with 0.65mm ball pitch, 11 x 20 grid, 8.0mm x 13.5mm. It
uses the mechanical outline MO-246 variation F. The device pinout supports outputs on the outer two left and right columns to support
easy DIMM signal routing. Corresponding inputs are placed in a way that two devices can be placed back to back for 4 Rank modules
while the data inputs share the same vias. Each input and output is located close to an associated no-ball position or on the outer two
rows to allow low cost via technology combined with the small 0.65mm ball pitch.
1
2
3
4 5 6
7
8
9 10 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
176-ball Thin Profile Fine Pitch BGA (TFBGA) 11x20 Grid
Top View
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
5
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Pin Descriptions
The device has symmetric pinout with the inputs on the south side and the outputs on the east and west sides. This allows
back-to-back mounting on both sides of the PCB if more than one device is needed.
Ball Assignment: MIRROR = LOW, QCSEN = HIGH or float
This table specifies the pinout for SSTE32882HLB in the front configuration (QuadCS mode disabled).
Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and
connecting pad on the module are required in these locations. Also, balls Y2 and R6 are “do not use” balls reserved for DCS2
and DCS3 in the QuadCS mode, and must not be connected on the system. The device is designed to tolerate floating on these
pins. Blank spaces indicate no ball is populated at that gridpoint, and vias on the module may be located in these areas.
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
QAA13
QAA14
QAA9
QAA11
QAA2
QAA1
QAA0
QAA12
QABA2
QAA15
QAWE
QAA10
QACAS
QARAS
DCKE1
DCKE0
DA12
DA9
DA8
DA7
2
3
QAA8
QCSEN
QAA7
QAA6
VDD
QAA5
VSS
QAA4
VDD
QAA3
VSS
QABA1
VDD
QABA0
VSS
VDD
QACS1
QACKE0
VSS
QACS0
VDD
QACKE1
VSS
QAODT0
VDD
QAODT1
DA3
DA14
DA15
DCS0
DBA2
DA11
DA6
FBIN
RSVD
FBIN
4
5
6
7
8
9
10
11
VSS
RESET
MIRROR
ERROUT
VSS
RSVD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DA5
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
RSVD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DA2
PVSS
PVSS
AVSS
AVDD
VDD
VSS
CK
CK
PVDD
PVDD
RSVD
VREFCA
QBA8
QBA7
QBA6
QBA5
QBA4
QBA3
QBBA1
QBBA0
QBCS1
QBCKE0
QBCS0
QBCKE1
QBODT0
QBODT1
DA10
DCS1
DA13
DRAS
DA0
PAR_IN
QBA13
QBA14
QBA9
QBA11
QBA2
QBA1
QBA0
QBA12
QBBA2
QBA15
QBWE
QBA10
QBCAS
QBRAS
DODT1
DODT0
DCAS
DWE
DBA0
DBA1
Y1
Y1
Y3
Y3
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
6
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
DA4
DA1
Y0
Y0
Y2
Y2
FBOUT
FBOUT
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Ball Assignment: MIRROR = HIGH, QCSEN = HIGH or float
This table specifies the pinout for SSTE32882HLB in the back configuration (QuadCS mode disabled).
Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and
connecting pad on the module are required in these locations. Also, balls Y10 and R6 are “do not use” balls reserved for DCS2
and DCS3 in the QuadCS mode, and must not be connected on the system. The device is designed to tolerate floating on these
pins. Blank spaces indicate no ball is populated at that gridpoint, and vias on the module may be located in these areas.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1
2
3
4
5
6
7
8
9
10
11
QAA13
QAA14
QAA9
QAA11
QAA2
QAA1
QAA0
QAA12
QABA2
QAA15
QAWE
QAA10
QACAS
QARAS
DODT1
DODT0
DCAS
DWE
DBA0
DBA1
QAA8
QAA7
QAA6
QAA5
QAA4
QAA3
QABA1
QABA0
QACS1
QACKE0
QACS0
QACKE1
QAODT0
QAODT1
DA10
DCS1
DA13
DRAS
DA0
PAR_IN
QCSEN
VSS
RESET
MIRROR
ERROUT
VSS
RSVD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DA2
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
RSVD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DA5
PVSS
PVSS
AVSS
AVDD
VDD
VSS
CK
CK
PVDD
PVDD
RSVD
VREFCA
QBA8
QBA7
QBA6
QBA5
QBA4
QBA3
QBBA1
QBBA0
QBCS1
QBCKE0
QBCS0
QBCKE1
QBODT0
QBODT1
DA14
DCS0
DBA2
DA11
DA6
RSVD
QBA13
QBA14
QBA9
QBA11
QBA2
QBA1
QBA0
QBA12
QBBA2
QBA15
QBWE
QBA10
QBCAS
QBRAS
DCKE1
DCKE0
DA12
DA9
DA8
DA7
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
DA4
DA1
FBIN
FBIN
Y1
Y1
Y3
Y3
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
7
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
DA3
DA15
Y0
Y0
Y2
Y2
FBOUT
FBOUT
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Ball Assignment: MIRROR = LOW, QCSEN = LOW
This table specifies the pinout for SSTE32882HLB in the front configuration (QuadCS mode enabled).
Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and
connecting pad on the module are required in these locations. Blank spaces indicate no ball is populated at that gridpoint, and
vias on the module may be located in these areas.
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
QAA13
QAA14
QAA9
QAA11
QAA2
QAA1
QAA0
QAA12
QABA2
QAA15
QAWE
QAA10
QACAS
QARAS
DCKE1
DCKE0
DA12
DA9
DA8
DA7
2
3
QAA8
QCSEN
QAA7
QAA6
VDD
QAA5
VSS
QAA4
VDD
QAA3
VSS
QABA1
VDD
QABA0
VSS
VDD
QCS1
QACKE0
VSS
QCS0
VDD
QACKE1
VSS
QAODT0
VDD
QAODT1
DA3
DA14
DA15
DCS0
DBA2
DA11
DA6
FBIN
FBIN
DCS2
4
5
6
7
8
9
10
11
VSS
RESET
MIRROR
ERROUT
VSS
RSVD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DA5
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DCS3
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DA2
PVSS
PVSS
AVSS
AVDD
VDD
VSS
CK
CK
PVDD
PVDD
RSVD
VREFCA
QBA8
QBA7
QBA6
QBA5
QBA4
QBA3
QBBA1
QBBA0
QCS3
QBCKE0
QCS2
QBCKE1
QBODT0
QBODT1
DA10
DCS1
DA13
DRAS
DA0
PAR_IN
QBA13
QBA14
QBA9
QBA11
QBA2
QBA1
QBA0
QBA12
QBBA2
QBA15
QBWE
QBA10
QBCAS
QBRAS
DODT1
DODT0
DCAS
DWE
DBA0
DBA1
Y1
Y1
Y3
Y3
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
DA4
DA1
8
Y0
Y0
Y2
Y2
FBOUT
FBOUT
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Ball Assignment: MIRROR = HIGH, QCSEN = LOW
This table specifies the pinout for SSTE32882HLB in the back configuration (QuadCS mode enabled).
Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and
connecting pad on the module are required in these locations. Blank spaces indicate no ball is populated at that gridpoint, and
vias on the module may be located in these areas.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1
2
3
4
5
6
7
8
9
10
11
QAA13
QAA14
QAA9
QAA11
QAA2
QAA1
QAA0
QAA12
QABA2
QAA15
QAWE
QAA10
QACAS
QARAS
DODT1
DODT0
DCAS
DWE
DBA0
DBA1
QAA8
QAA7
QAA6
QAA5
QAA4
QAA3
QABA1
QABA0
QCS1
QACKE0
QCS0
QACKE1
QAODT0
QAODT1
DA10
DCS1
DA13
DRAS
DA0
PAR_IN
QCSEN
VSS
RESET
MIRROR
ERROUT
VSS
RSVD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DA2
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DCS3
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
DA5
PVSS
PVSS
AVSS
AVDD
VDD
VSS
CK
CK
PVDD
PVDD
RSVD
VREFCA
QBA8
QBA7
QBA6
QBA5
QBA4
QBA3
QBBA1
QBBA0
QCS3
QBCKE0
QCS2
QBCKE1
QBODT0
QBODT1
DA14
DCS0
DBA2
DA11
DA6
DCS2
QBA13
QBA14
QBA9
QBA11
QBA2
QBA1
QBA0
QBA12
QBBA2
QBA15
QBWE
QBA10
QBCAS
QBRAS
DCKE1
DCKE0
DA12
DA9
DA8
DA7
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
DA4
DA1
FBIN
FBIN
Y1
Y1
Y3
Y3
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
9
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
DA3
DA15
Y0
Y0
Y2
Y2
FBOUT
FBOUT
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Pinout configuration narrow package1
As an option, the device is available as a176-ball Thin-Profile Fine-Pitch BGA (TFBGA) with 0.65mm ball pitch, 8 x 22 grid,
6.0mm x 15mm. It is using the mechanical outline MO-246 variation B. Equivalent to the 11 x 20 grid configuration the device
pinout supports outputs on the outer two left and right columns. Corresponding inputs are placed in a way that two devices can
be placed back to back for 4 Rank modules while the data inputs share the same vias.
1
2 3
4
5 6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
176-ball Thin Profile Fine Pitch BGA (TFBGA) 8x22 Grid
Top View
1. This package may only be used in new DIMM designs. It is not intended for use in the existing DIMM’s.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
10
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Ball Assignment; MIRROR=LOW, QCSEN=HIGH (or Float)
The table below specifies the pinout for SSTE32882 in front configuration with QuadCS mode disabled. The device has
symmetric pinout with inputs at the south side and outputs to east and west sides. This allows back to back mounting on both
sides of the PCB if more than one device is needed.
1
2
3
4
5
6
7
8
QAA13
QAA8
QCSEN
RESET
ERROUT
RSVD
QBA8
QBA13
A
QAA14
QAA7
VSS
VSS
MIRROR
VSS
QBA7
QBA14
B
QAA9
QAA6
VDD
VDD
VDD
VDD
QBA6
QBA9
C
QAA11
QAA5
VSS
VSS
VSS
VSS
QBA5
QBA11
D
QAA2
QAA4
VDD
VDD
VDD
VDD
QBA4
QBA2
E
QAA1
QAA3
VSS
VSS
VSS
VSS
QBA3
QBA1
F
QAA0
QABA1
VDD
VDD
VDD
VDD
QBBA1
QBA0
G
QAA12
QABA0
VSS
VSS
VSS
VSS
QBBA0
QBA12
H
QABA2
QACS1
VDD
VDD
VDD
VDD
QBCS1
QBBA2
J
QAA15
QACKE0
VSS
VSS
VSS
VSS
QBCKE0
QBA15
K
QAWE
QACS0
VDD
VDD
VDD
VDD
QBCS0
QBWE
L
QAA10
QACKE1
VSS
VSS
VSS
VSS
QBCKE1
QBA10
M
QACAS
QAODT0
VDD
VDD
VDD
VDD
QBODT0
QBCAS
N
QARAS
QAODT1
VSS
VSS
VSS
VSS
QBODT1
QBRAS
P
DA14
DCKE1
VDD
VDD
VDD
VDD
DODT1
DA10
R
DCS0
DCKE0
VSS
VSS
VSS
VSS
DODT0
DCS1
T
DA12
DA3
Y1
PVSS
PVDD
Y0
DA4
DCAS
U
DA5
DA9
Y1
PVSS
PVDD
Y0
DWE
DA2
V
DA8
DA15
Y3
PVSS
PVDD
Y2
DA1
DBA0
W
DA7
DBA2
Y3
AVSS
AVDD
Y2
DA13
DBA1
Y
DA11
RSVD
FBIN
CK
RSVD
FBOUT
PAR_IN
DRAS
AA
DA6
RSVD
FBIN
CK
VREFCA
FBOUT
RSVD
DA0
AB
Pins A6, AA2, AA5, AB2 and AB7 are reserved for future functions must not be connected on system.
The system must provide a solder pad for these pins. The device design needs to tolerate floating on these
pins. A3 may be left floating since it has an internal pull-up resistor.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
11
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Ball Assignment; MIRROR=HIGH, QCSEN=HIGH (or Float)
The table below specifies the pinout for SSTE32882 in back configuration with QuadCS mode disabled.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
1
2
3
4
5
6
7
8
QAA13
QAA8
QCSEN
RESET
ERROUT
RSVD
QBA8
QBA13
QAA14
QAA7
VSS
VSS
MIRROR
VSS
QBA7
QBA14
QAA9
QAA6
VDD
VDD
VDD
VDD
QBA6
QBA9
QBA11
QAA11
QAA5
VSS
VSS
VSS
VSS
QBA5
QAA2
QAA4
VDD
VDD
VDD
VDD
QBA4
QBA2
QAA1
QAA3
VSS
VSS
VSS
VSS
QBA3
QBA1
QAA0
QABA1
VDD
VDD
VDD
VDD
QBBA1
QBA0
QAA12
QABA0
VSS
VSS
VSS
VSS
QBBA0
QBA12
QABA2
QACS1
VDD
VDD
VDD
VDD
QBCS1
QBBA2
QAA15
QACKE0
VSS
VSS
VSS
VSS
QBCKE0
QBA15
QAWE
QACS0
VDD
VDD
VDD
VDD
QBCS0
QBWE
QAA10
QACKE1
VSS
VSS
VSS
VSS
QBCKE1
QBA10
QACAS
QAODT0
VDD
VDD
VDD
VDD
QBODT0
QBCAS
QARAS
QAODT1
VSS
VSS
VSS
VSS
QBODT1
QBRAS
DA10
DODT1
VDD
VDD
VDD
VDD
DCKE1
DA14
DCS1
DODT0
VSS
VSS
VSS
VSS
DCKE0
DCS0
DCAS
DA4
Y1
PVSS
PVDD
Y0
DA3
DA12
DA2
DWE
Y1
PVSS
PVDD
Y0
DA9
DA5
DBA0
DA1
Y3
PVSS
PVDD
Y2
DA15
DA8
DBA1
DA13
Y3
AVSS
AVDD
Y2
DBA2
DA7
DRAS
PAR_IN
FBIN
CK
RSVD
FBOUT
RSVD
DA11
DA0
RSVD
FBIN
CK
VREFCA
FBOUT
RSVD
DA6
Pins A6, AA5, AA7, AB2 and AB7 are reserved for future functions must not be connected on system. The
system must provide a solder pad for these pins. The device design needs to tolerate floating on these pins.
A3 may be left floating since it has an internal pull-up resistor.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
12
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Ball Assignment; MIRROR=LOW, QCSEN=LOW
The table below specifies the pinout for SSTE32882 in front configuration with QuadCS mode enabled.
1
2
3
4
5
6
7
8
QAA13
QAA8
QCSEN
RESET
ERROUT
RSVD
QBA8
QBA13
A
QAA14
QAA7
VSS
VSS
MIRROR
VSS
QBA7
QBA14
B
QAA9
QAA6
VDD
VDD
VDD
VDD
QBA6
QBA9
C
QAA11
QAA5
VSS
VSS
VSS
VSS
QBA5
QBA11
D
QAA2
QAA4
VDD
VDD
VDD
VDD
QBA4
QBA2
E
QAA1
QAA3
VSS
VSS
VSS
VSS
QBA3
QBA1
F
QAA0
QABA1
VDD
VDD
VDD
VDD
QBBA1
QBA0
G
QAA12
QABA0
VSS
VSS
VSS
VSS
QBBA0
QBA12
H
QABA2
QCS1
VDD
VDD
VDD
VDD
QCS3
QBBA2
J
QAA15
QACKE0
VSS
VSS
VSS
VSS
QBCKE0
QBA15
K
QAWE
QCS0
VDD
VDD
VDD
VDD
QCS2
QBWE
L
QAA10
QACKE1
VSS
VSS
VSS
VSS
QBCKE1
QBA10
M
QACAS
QAODT0
VDD
VDD
VDD
VDD
QBODT0
QBCAS
N
QARAS
QAODT1
VSS
VSS
VSS
VSS
QBODT1
QBRAS
P
DA14
DCKE1
VDD
VDD
VDD
VDD
DODT1
DA10
R
DCS0
DCKE0
VSS
VSS
VSS
VSS
DODT0
DCS1
T
DA12
DA3
Y1
PVSS
PVDD
Y0
DA4
DCAS
U
DA5
DA9
Y1
PVSS
PVDD
Y0
DWE
DA2
V
DA8
DA15
Y3
PVSS
PVDD
Y2
DA1
DBA0
W
DA7
DBA2
Y3
AVSS
AVDD
Y2
DA13
DBA1
Y
DA11
DCS2
FBIN
CK
RSVD
FBOUT
PAR_IN
DRAS
AA
DA6
RSVD
FBIN
CK
VREFCA
FBOUT
DCS3
DA0
AB
Pins A6, AA5 and AB2 are reserved for future functions must not be connected on system. The system
must provide a solder pad for these pins. The device design needs to tolerate floating on these pins. A3
must be tied LOW for this configuration.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
13
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Ball Assignment; MIRROR=HIGH, QCSEN=LOW)
The table below specifies the pinout for SSTE32882 in back configuration with QuadCS mode enabled.
.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
1
2
3
4
5
6
7
8
QAA13
QAA8
QCSEN
RESET
ERROUT
RSVD
QBA8
QBA13
QAA14
QAA7
VSS
VSS
MIRROR
VSS
QBA7
QBA14
QAA9
QAA6
VDD
VDD
VDD
VDD
QBA6
QBA9
QBA11
QAA11
QAA5
VSS
VSS
VSS
VSS
QBA5
QAA2
QAA4
VDD
VDD
VDD
VDD
QBA4
QBA2
QAA1
QAA3
VSS
VSS
VSS
VSS
QBA3
QBA1
QAA0
QABA1
VDD
VDD
VDD
VDD
QBBA1
QBA0
QAA12
QABA0
VSS
VSS
VSS
VSS
QBBA0
QBA12
QABA2
QCS1
VDD
VDD
VDD
VDD
QCS3
QBBA2
QAA15
QACKE0
VSS
VSS
VSS
VSS
QBCKE0
QBA15
QAWE
QCS0
VDD
VDD
VDD
VDD
QCS2
QBWE
QAA10
QACKE1
VSS
VSS
VSS
VSS
QBCKE1
QBA10
QACAS
QAODT0
VDD
VDD
VDD
VDD
QBODT0
QBCAS
QARAS
QAODT1
VSS
VSS
VSS
VSS
QBODT1
QBRAS
DA10
DODT1
VDD
VDD
VDD
VDD
DCKE1
DA14
DCS1
DODT0
VSS
VSS
VSS
VSS
DCKE0
DCS0
DCAS
DA4
Y1
PVSS
PVDD
Y0
DA3
DA12
DA2
DWE
Y1
PVSS
PVDD
Y0
DA9
DA5
DBA0
DA1
Y3
PVSS
PVDD
Y2
DA15
DA8
DBA1
DA13
Y3
AVSS
AVDD
Y2
DBA2
DA7
DRAS
PAR_IN
FBIN
CK
RSVD
FBOUT
DCS2
DA11
DA0
RSVD
FBIN
CK
VREFCA
FBOUT
DCS3
DA6
Pins A6, AA5 and AB2 are reserved for future functions must not be connected on system. The system must
provide a solder pad for these pins. The device design needs to tolerate floating on these pins. A3 must be
tied LOW for this configuration.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
14
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Terminal Functions
Signal Group
Signal Name
Type
Ungated inputs
DCKEn, DODTn
Chip Select
gated inputs
DAn, DBAn, DRAS,
DCAS, DWE
Chip Select
inputs
DCS0, DCS1
1.35V/1.5V
CMOS Inputs1
DCS2, DCS3
1.35V/1.5V
CMOS Inputs1
Re-driven
outputs
Parity input
1.35V/1.5V
CMOS Inputs1
1.35V/1.5V
CMOS Inputs1
QxAn, QxBAn, QxCSn, 1.35V/1.5V
QxCKEn, QxODTn,
CMOS Outputs2
QxRAS, QxCAS,
QxWE
PAR_IN
1.35V/1.5V
CMOS Inputs1
Parity error
output
ERROUT
Open drain
Clock inputs
CK, CK
Feedback
FBIN, FBIN
Clock
FBOUT, FBOUT
Clock Outputs
Yn, Yn
Miscellaneous
inputs
RESET
1.35V/1.5V
CMOS Inputs1
1.35V/1.5V
CMOS Inputs1
1.35V/1.5V
CMOS Outputs2
1.35V/1.5V
CMOS Outputs2
CMOS3
MIRROR
CMOS3
QSCEN
CMOS3
Description
DRAM corresponding register function pins not associated with
Chip Select.
DRAM corresponding register inputs, re-driven only when either
chip select is LOW. If both chip selects are low the register maintains
the state of the previous input clock cycle at its outputs
DRAM corresponding register Chip Select signals. These pins
initiate DRAM address/command decodes, and as such exactly one
will be low when a valid address/command is present which should
be re-driven.
DRAM corresponding register Chip Select signals when QuadCS
mode is enabled. DCS2 and DCS3 inputs are disabled when QuadCS
mode is disabled.
Outputs of the register, valid after the specified clock count and
immediately following a rising edge of the clock. x is A or B;
outputs are grouped as A or B and may be enabled or disabled via
RC0.
Input parity is received on pin PAR_IN and should maintain parity
across the Chip Select Gated inputs (see above), at the rising edge of
the input clock, one input clock cycle after corresponding data and
one or both chip selects are LOW.
When LOW, this output indicates that a parity error was identified
associated with the address and/or command inputs. ERROUT will
be active for two clock cycles, and delayed by 3 clock cycles to the
corresponding input data
Differential master clock input pair to the PLL; has weak internal
pull-down resistors (10K~100K.
Feedback clock input
Feedback clock output
Re-driven Clock
Active low asynchronous reset input. When LOW, it causes a reset of
the internal latches and disables the outputs, thereby forcing the
outputs to float. Once RESET becomes high the Q outputs get
enabled and are driven LOW (ERROUT is driven high) until the first
access has been performed. RESET also resets the ERROUT signal.
Selects between two different ballouts for front or back operation.
When the MIRROR input is high, the device Input Bus Termination
(IBT) is turned off on all inputs, except the DCSn and DODTn
inputs.
Enables the QuadCS mode. The QSCEN input has a weak internal
pullup resistor (10K - 100K).
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
15
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Signal Group
Power
Signal Name
Vrefca
Type
1
Description
Reference Voltage Input reference voltage for the differential data inputs, VDD/2
(0.75V) nominal.
Register Power
Power supply voltage (Register)
Register Ground Ground (Register)
Analog Power
Analog supply voltage (PLL)
Analog Ground
Analog ground (PLL)
PLL Power
Clock logic and clock output driver power supply (PLL)
PLL Ground
Clock logic and clock output driver ground (PLL)
I/O
Reserved pins, must be left floating (PLL)
Vdd
Vss
AVdd
AVss
PVdd
PVss
RSVD
1
2
3
COMMERCIAL TEMPERATURE
1.35V/1.5V CMOS inputs use VREFCA as the switching point reference for these recievers.
These outputs are optimized for memory applications to drive DRAM inputs to 1.35V/1.5V signaling levels.
Voltage levels according standard JESD8-11A, wide range, non terminated logic.
Function Table (Each Flip Flop) with QuadCS Mode Disabled
RESET
DCS0
DCS1
Inputs
CK2
CK
2
ADDR3
4
CMD
CTRL5
Control
Word
X
Control
Word
X
H
L
L


H
X
X
L or H
H or L
Control
Word
X
H
L
H


X
X
X
H
X
X
L
L
X
X
X
H
H
L


X
X
X
H
H
H


X or float
X
L
X or
float
X or
float
X or
float
X or
float
X or
float
X or
float
X or float
X or
float
Qn
6
QxCS0
Outputs1
QxCS1
QxODTn
QxCKEn
Q0
H
H
Q0
Q0
Q0
Follows
Input
float
Follows
Input
Q0 or
float7
Q0
Q0
L
H
float
float
H
L
H
H
Q0
Follows
Input
float
Follows
Input
Follows
Input
Q0
Follows
Input
L
Follows
Input
Follows
Input
float
float
float
L
float
1
Q0 means the output does not change state.
2
It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and HIGH) when
RESET is driven HIGH.
3
ADDR = DA[15:0], DBA[2:0]
4
CMD = DRAS, DCAS, DWE.
5
6
CTRL = DODTn, DCKEn.
Qn = QxAn, QxRAS, QxCAS, QxWE, and QxBAn.
7
Depending on Control Word RC0 Bit DA4. If RC0 DA4 is cleared, previous state (Q0) is maintained. Address floating is
disabled independent of control word RC0 once 3T timing is activated.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
16
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Function Table (Each Flip Flop) with QuadCS Mode Enabled
RESET
Inputs
DCS[3:0]
CK1
1
2
CK
A/C/E
Qn


Control
Word
No
change
XXXX
L or H
H or L
X
H
LHHH


Dn
No
change
Dn
H
HLHH


Dn
H
HHLH


H
HHHL

H
LHLH
H
HLLH
H
H
H
H
LLHH
HHLL
LLLL
H
Outputs
QCS[3:0]
QxODTn
QxCKEn
HHHH
No change
No change
No change
No change
No change
LHHH
DODTn
DCKEn
Dn
HLHH
DODTn
DCKEn
Dn
Dn
HHLH
DODTn
DCKEn

Dn
Dn
HHHL
DODTn
DCKEn


Dn
Dn
LHLH
DODTn
DCKEn


Dn
Dn
HLLH
DODTn
DCKEn
LHHL


Dn
Dn
LHHL
DODTn
DCKEn
H
H
HLHL
XXXX

L

L
Dn
X
HLHL
float
DODTn
float
DCKEn
L
H
HHHH


X
Dn
float
No
change
or float3
HHHH
DODTn
DCKEn
H
H
H
H
LLLH
LLHL
LHLL
HLLL


X
L
X or float
X or
float
X or
float
X or float
Ilegal Input States
float
float
float
L
1 It is illegal to hold both the CK and CK inputs at static logic high levels or static complementary logic levels (low
and high) when RESET is driven high.
2 A/C/E = DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE, DODTn, DCKEn
3 Depending on Control Word RC0 Bit DA4. If RC0 DA4 is cleared, previous state is maintained. Address floating
is disabled independent of control word RC0 once 3T timing is activated
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
17
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Parity, Low Power and Standby with QuadCS Mode Disabled
RESET
H
H
H
H
H
H
H
H
H
H
H
L
DCS0
DCS1
Inputs
CK1
1
2
 of C/A
PAR_IN
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
X
X
X or floating
L
L
H
H
L
L
H
H
X
X
X
X or floating
CK
L
X


L
X


L
X


L
X


X
L


X
L


X
L


X
L


H
H


X
X
L or H
H or L
X
X
L
L
X or floating X or floating X or floating X or floating
3
Output
ERROUT4
H
L
L
H
H
L
L
H
H5
ERROUT0
H6
H
1
It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels
(LOW and HIGH) when RESET is driven HIGH.
2 C/A= DAn, DBAn, DRAS, DCAS, DWE. Inputs DCKEn, DODTn, and DCSn are not included in this range. This
column represents the sum of the number of C/A signals that are electrically HIGH.
3 PAR_IN arrives one clock cycle after the data to which it applies, ERROUT is issued three clock cycles after the
failing data.
4 This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ERROUT is low,
it stays latched low for exactly two clock cycles or until RESET is driven low.
5 Same three cycle delay for ERROUT is valid for the de-select phase (see diagram)
6 The system is not allowed to pull CK and CK low while ERROUT is asserted.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
18
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Parity, Low Power and Standby with QuadCS Mode Enabled
RESET
DCS[3:0]
H
LXXX
XLXX
XXLX
XXXL
LXXX
XLXX
XXLX
XXXL
LXXX
XLXX
XXLX
XXXL
LXXX
XLXX
XXLX
XXXL
HHHH
XXXX
XXXX
X or floating
H
H
H
H
H
H
L
Inputs
CK1
CK
 of A/C
PAR_IN


Even
L
H


Odd
L
L


Even
H
L


Odd
H
H
1
2
3


X
X
L or H
H or L
X
X
L
L
X
X
X or floating X or floating X or floating X or floating
Output
ERROUT4
H5
ERROUTn0
H6
H
1 It is illegal to hold both the CK and CK inputs at static logic high levels or static complementary logic levels (low
and high) when RESET is driven high.
2
A/C = DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE. Inputs DCKE0, DCKE1, DODT0, DODT1, DCS0
and DCS1 are not included in this range. This column represents the sum of the number of A/C signals that are electrically high.
3
PAR_IN arrivesone clock cycle afterdata to which it applies, ERROUT is issued three clock cycles after the failing data.
4
This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ERROUT is
low, it stays latched low for exactly two clock cycles or until RESET is driven low.
5 Same three-cycle delay for ERROUT is valid for the de-select phase (see diagram)
6 The system is not allowed to pull CK and CK low while ERROUT is asserted.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
PLL Function Table
Inputs
Outputs
PLL
RESET
AVDD
OEn1
CK2
CK2
Yn
Yn
FBOUT
FBOUT
L
X
X
X
X
Float
Float
Float
Float
Off
H
VDD nominal
L
L
H
L
H
L
H
On
H
VDD nominal
L
H
L
H
L
H
L
On
H
VDD nominal
H
L
H
Float
Float
L
H
On
H
VDD nominal
H
H
L
Float
Float
H
L
On
H
VDD nominal
X
L
L
Float
Float
Float
Float
Off
H
GND3
L
L
H
L
H
L
H
Bypassed/Off
H
GND3
L
H
L
H
L
H
L
Bypassed/Off
H
GND3
H
L
H
Float
Float
L
H
Bypassed/Off
H
GND3
H
H
L
Float
Float
H
L
Bypassed/Off
H
GND3
X
L
L
Float
Float
Float
Float
Bypassed/Off
H
X
X
H
H
Reserved
1 The Output Enable (OEn) to disable the output buffer is not an input signal to the SSTE32882HLB, but an internal signal
from the PLL powerdown control and test logic. It is controlled by setting or clearing the corresponding bit in the Clock Driver
mode register.
2 It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and
HIGH) when RESET is driven HIGH.
3 This is a device test mode and all register timing parameters are not guaranteed.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Absolute Maximum Ratings
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability
Symbol
Parameter
Conditions
AVDD, PVDD,
Supply voltage
VDD
Receiver input voltage1
VI
VREF
Reference voltage
voltage1
Unit
–0.4
+1.975
V
–0.4
VDD + 0.5
V
–0.4
VDD + 0.5
V
–0.4
VDD + 0.5
V
Driver output
IIK
Input clamp current
VI < 0 or VI > VDD
-50
mA
IOK
Output clamp current
VO < 0 or VO > VDD
±50
mA
IO
Continuous output current
0 < VO < VDD
Continuous current through each VDD or GND pin
TSTG
Storage temperature
–65
RJA
Package Thermal Impedance, Junction-to-Ambient2
RJB
Package Thermal Impedance, Junction-to-Board2
RJC
2
Max
VO
ICCC
1
Min
Package Thermal Impedance,
0m/s Airflow
1m/s Airflow
Junction-to-Case2
±50
mA
±100
mA
+150
43.8
35.5
C
C/W
22
C/W
16.2
C/W
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are
observed. This value is limited to 1.975 V maximum.
The package thermal impedance is calculated in accordance with JESD51-2.
DC and AC Specifications
The SSTE32882HLB parametric values are specified for the device default control word settings, unless otherwise stated. Note that
RC10 setting does not affect any of the paramteric values.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
DC Specifications - Voltage
The SSTE32882 parametric values are specified for the device default control word settings, unless otherwise stated. Note
that the RC10 setting does not affect any of the parametric values.
Symbol
VDD
Min
Nom
Max
Unit
DC Supply voltage (1.5V Operation)
Parameter
Signals
1.425
1.5
1.575
V
DC Supply voltage (1.35V Operation)
1.282
1.35
1.451
V
0.49 x VDD
0.50 x VDD
0.51 x VDD
V
VREF
DC Reference voltage
VTT
DC Termination voltage
VREF – 40 mV
VREF
VREF + 40 mV
V
VIH(AC)
AC HIGH-level input voltage (1.5V Operation,
DDR3-800/1066/1333)
Data inputs1
VREF + 175 mV
–
VDD + 0.4
V
AC HIGH-level input voltage (1.5V Operation, DDR3-1600)
Data inputs1
VREF + 150 mV
–
VDD + 0.4
V
AC HIGH-level input voltage (1.35V Operation,
DDR3L-800/1066/1333)
Data inputs1
VREF + 150 mV
–
VDD + 0.2
V
AC HIGH-level input voltage (1.35V Operation, DDR3L-1600) Data inputs1
VREF + 135 mV
–
VDD + 0.2
V
–0.4
–
VREF – 175 mV
V
VIL(AC)
VIH(DC)
VIL(DC)
AC LOW-level input voltage (1.5V Operation,
DDR3-800/1066/1333)
Data inputs
AC LOW-level input voltage (1.5V Operation, DDR3-1600)
Data inputs1
–0.4
–
VREF – 150 mV
V
inputs1
–0.2
–
VREF – 150 mV
V
–0.2
–
VREF – 135 mV
V
VREF + 100 mV
–
VDD + 0.4
V
1
AC LOW-level input voltage(1.35V Operation,
DDR3L-800/1066/1333)
Data
AC LOW-level input voltage (1.35V Operation, DDR3L-1600)
Data inputs1
DC HIGH-level input voltage(1.5V Operation)
Data inputs
DC HIGH-level input voltage(1.35V Operation)
Data inputs1
1
DC LOW-level input voltage(1.5V Operation)
Data inputs
DC LOW-level input voltage(1.35V Operation)
Data inputs1
VIH(CMO HIGH-level input voltage
1
CMOS inputs
2
S)
VIL(CMO LOW-level input voltage
CMOS inputs2
S)
VIL
(Static)
Static LOW-level input voltage3
CK, CK,
VIX(AC)
Differential input crosspoint voltage range(1.5V Operation,
DDR3-800/1066/1333/1600)
CK, CK, FBIN, FBIN
VREF + 90 mV
–
VDD + 0.2
V
–0.4
–
VREF – 100 mV
V
–0.2
–
VREF – 90 mV
V
0.65 x VDD
–
VDD
V
0
–
0.35 x VDD
V
-
–
0.35 x VDD
V
0.5xVDD - 175
mV
0.5 x VDD
0.5xVDD + 175
mV
V
0.5xVDD - 200
mV
Differential input crosspoint voltage range(1.35V Operation,
DDR3L-800/1066/1333/1600)
CK, CK, FBIN, FBIN
4
0.5xVDD - 150
mV
0.5xVDD - 180
mV5
VID(AC)
Differential input voltage6 (1.5V Operation,
DDR3-800/1066/1333)
CK, CK
Differential input voltage6(1.5V Operation, DDR3-1600)
CK, CK
6(1.35V
Differential input voltage
DDR3-800/1066/1333)
Operation,
Differential input voltage6 (1.35V Operation, DDR3-1600)
IOH
HIGH-level output current
IOL
LOW-level output current7
7
0.5 x VDD
0.5 x VDD
0.5 x VDD
0.5xVDD + 200
mV4
0.5xVDD + 150
mV
0.5xVDD + 180
mV5
V
V
V
350
–
VDD
mV
300
–
VDD
mV
300
–
VDD
mV
CK, CK
270
–
VDD
mV
All outputs except
ERROUT
-11
–
–
mA
All outputs except
ERROUT
11
–
–-
mA
CK, CK
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Symbol
IOL
VOD
VOX
Parameter
Signals
Min
Nom
Max
Unit
LOW-level output current
ERROUT
25
–
–
mA
Differential re-driven clock swing (1.5V Operation)
Yn, Yn
500
–
VDD
mV
Differential re-driven clock swing (1.35V Operation)
Yn, Yn
450
–
VDD
mV
Differential Output Crosspoint Voltage (1.5V Operation)
Yn, Yn
0.5xVDD – 100
mV
–
0.5xVDD + 100
mV
V
Differential Output Crosspoint Voltage (1.35V Operation)
Yn, Yn
0.5xVDD – 90 mV
–
0.5xVDD + 90 mV
V
DDR3-1066
DDR3-133
3
DDR3-1600
1089
1069
1039
DDR3-800
Tcase
COMMERCIAL TEMPERATURE
Case temperature8
1099
(max)
o
C
1 DCKE0/1, DODT0/1, DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE, PAR_IN, DCS[1:0] when QCSEN = HIGH, DCS[3:0] when QCSEN = LOW.
2 RESET, MIRROR
3 This spec applies only when both CK and CK are actively driven LOW. It does not apply when CK/CK are floating.
4 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended
swing VSEL / VSEH of at least VDD/2 +/-275 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns.
5 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended
swing VSEL / VSEH of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 3.6 V/ns
6 VID is the magnitude of the difference between the input level on CK and the input level on CK See Diagram (Voltage waveforms; input clock)
7 Default settings
8 Measurement procedure JESD51-2
9 This spec is meant to guarantee a Tj of 125C by the SSTE32882 device. Since Tj cannot be measured or observed by users, Tcase is specified instead.
Under all thermal condition, the Tj of a SSTE32882 device shall not be higher than 125 oC.
Voltage waveforms; input clock
VIX(AC)
VIX(AC)
VID
VIX(AC) = 0.5XVDD±175 mV (1.5V operation) or 0.5xVDD±150 mV (1.35 V operation)
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
DC Current Specifications
Operating Electrical Characteristics
Symbol
II
Parameter1
Input current
RESET, MIRROR, VI = VDD or GND
QCSEN input current
QCSEN, VI = VDD or GND
IID
Input current
IOH
HIGH-level output current
IOL
IDD6
Conditions
LOW-level output current
Min
Typ2
Max
±5
-150
5
Unit
A
±5
A
150
A
Data inputs3, VI = VDD or GND
CK, CK4; VI = VDD or GND
-5
Qn5
-11
mA
Yn, Yn, FBOUT, FBOUT
-11
mA
Qn5
11
mA
Yn, Yn, FBOUT, FBOUT
11
mA
ERROUT
25
mA
Static standby current
RESET = GND and CK = CK = VIL(AC)
5
mA
Low-Power Static Operating
RESET = VDD and CK = CK = VIL(AC), MIRROR =
VDD, DCS[1:0] = [0,1]
15
mA
Dynamic operating -- input clock
only; active outputs
RESET = VDD, MIRROR = VDD, VI = VIH(AC) or
VIL(AC), RC0[DBA0]=0, RC0[DBA1]=0, CK and CK
switching 50% duty cycle, IO = 0, DCS0 = L, DCS1 =
H. VDD = VDDMAX
68
A/MHz
Dynamic operating -- per each data
input
RESET = VDD, MIRROR = VDD, VI = VIH(AC) or
VIL(AC), CK and CK switching 50% duty cycle. One
data input switching at one half clock frequency, 50%
duty cycle; RC0[DBA0]=0, RC0[DBA1]=0, IO = 0,
DCS0 = L, DCS1 = H. VDD = VDDMAX
16
A/Clock
MHz/
D Input
ICCD
1 The RESET and MIRROR inputs of the device must be held at valid voltage levels (not floating) to ensure proper device
operation. The differential inputs must not be floating unless RESET is LOW.
2 All typical values are at VDD = 1.5V, TA = 25°C.
3
4
5
DCKEn, DODTn, DAn, DBAn, DRAS, DCAS, DWE, DCSn, PAR_IN are measured while RESET is pulled LOW.
The CK and CK inputs have pull-down resistors in the range of 10K to 100K.
Qn = QxAn, QxCSn, QxCKEn, QxODTn, QxRAS, QxCAS, QxWE, and QxBAn.
6
The supply current is measured as the total current consumption on the AVDD, PVDD, and VDD supply current pins. Io = 0.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Capacitance Values
Symbol
Parameter
Input capacitance, Data inputs
Conditions
1
see footnote
Input capacitance, CK, CK, FBIN,
FBIN
see footnote
Input capacitance, CK, CK, FBIN,
FBIN
(1.35 V operation)
see footnote1
CO
Output capacitance, Re-driven and
Clock Outputs
QxA0..QxA15, QxBA0..QxBA2, QxCS0/1,
QxCKE0/1, QxODT0/1, QxRAS, QxCAS,
QxWE, Y0, Y0.. Y3, Y3
CI
Delta capacitance over all inputs
CIR
Input capacitance, RESET, MIRROR,
QCSEN
CI
1
VI = VDD or GND; VDD = 1.5 V
Min
Typ
Max
Unit
1.5
-
2.5
pF
2
-
3
pF
1.5
-
2.5
pF
1
-
2
pF
-
-
0.5
pF
-
-
3
pF
1 This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according
to JEP147 ("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)")
with VDD, VSS, AVDD, AVSS, PVDD, PVSS, VREF applied and all other pins (except the pin under test) floating. Input capacitance
are measured with the device default settings when MIRROR=Low.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Timing Requirements
Symbol
fCLOCK
fTEST
tCH/tCL
Parameter
Input Clock Frequency
Input Clock Frequency
Conditions
Application Frequency
Test
1
Frequency2
Pulse Duration, CK, CK HIGH or
LOW
DDR3-800/
1066/1333
DDR3-1600
Unit
Min
Max
Min
Max
300
670
300
810
MHz
70
300
70
300
MHz
0.4
0.4
tCK3
Inputs active time before RESET is
taken HIGH4
DCKE0/1 = LOW and DCS[n:0] =
HIGH
8
8
tCK3
Command word to command word
programming delay
Number of clock cycles between
two command programming
accesses
8
8
tCK3
tINDIS
Input Buffers disable time after
DCKE[1:0] is LOW
DCKE[1:0] = LOW; RESET =
HIGH; CK/CK = Toggling;
RC9[DBA1] = 1 and RC9[DBA0]
= 0 or 1
1
4
1
4
tCK3
tQDIS
Output Buffers Hi-Z after QxCKEn is
driven LOW
DCKE[1:0] = LOW; RESET =
HIGH; CK/CK = Toggling;
RC9[DBA1] = 1 and RC9[DBA0]
= 0 or 1
1.5
1.5
1.5
1.5
tCK3
tCKOFF
Number of tCK required for both
DCKE0 and DCKE1 to remain LOW
before both CK/CK are driven low
DCKE[1:0] = LOW;
RESET = HIGH;
CK/CK = Toggling
5
5
tCK3
tCKEV
Input buffers (DCKE0 and DCKE1)
disable time after CK/CK = LOW
DCKE[1:0] = LOW;
RESET = HIGH;
CK/CK = LOW
2
2
tCK3
tACT
tMRD
tFixedoutputs
tSU
tH
Static Register Output after DCKE0 or RC9[DBA1] = 1 and RC9[DBA0]
DCKE1 is HIGH at the input (exit from = 0 or 1
Power Saving state)
Setup Time5
Hold
Time6
1
3
1
4
tCK3
Input valid before CK/CK
100
50
ps
Input to remain valid after CK/CK
175
125
ps
1 All specified timing parameters apply.
2 Timing parameters specified for frequency band 2 apply.
3 Clock cycle time.
4 This parameter is not necessarily production tested (see figure below).
5 Setup (tSU) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and first
crossing of VIH(AC) min. Setup (tSU) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIL(AC) max. If the actual signal is always earlier than the nominal slew rate line between
shaded ‘VREF(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate
line anywhere between shaded ‘VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to
dc level is used for derating value .
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
6 Hold (tH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)MAX and the
first crossing of VREF(DC). Hold (tH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VIH(DC)MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between
shaded ‘dc level to VREF(DC) region’ use nominal slew rate for derating value. If the actual signal is earlier than the nominal
slew rate line anywhere between shaded ‘dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the
dc level to VREF(DC) level is used for derating value.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Voltage Waveforms for Setup and Hold Times–Hold Time Calculation
tSU
tH
tSU
tH
CK
CK
VDDQ
VIH(AC) MIN
VIH(DC) MIN
to VREF
region
DC
nominal
slew rate
VREF(DC)
nominal
slew rate
to VREF
region
DC
VIL(DC) MAX
VIL(AC) MAX
VSS
TF
TR
VREF(DC) - VIL(DC) MAX
Hold Slew Rate
=
Rising Signal
TR
VIH(DC) MIN - VREF(DC)
Hold Slew Rate
=
Falling Signal
TF
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Voltage Waveforms for Setup and Hold Times–Setup Time Calculation
tSU
tH
tSU
tH
CK
CK
VDDQ
VIH(ac) min
VIH(dc) min
VREF to ac
region
nominal
slew rate
VREF(dc)
nominal
slew rate
VREF to ac
region
VIL(dc) max
VIL(ac) max
TF
TR
VSS
Setup Slew Rate VREF(dc) - VIL(ac)max
Falling Signal =
TF
Setup Slew Rate VIH(ac)min - VREF(dc)
Rising Signal =
TR
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
AC Specifications - Output Timing Requirements
Parameter1
Symbol
Conditions
output2
tPDM
tDIS
tEN
Propagation delay, single-bit switching
CKCK to
(1.5V operation)
Propagation delay, single-bit switching
CKCK to output2
3
(1.35V operation)
Output disable time (1/2-Clock pre-launch) Yn/Yn (falling edge)
to output float4
Output disable time (3/4-Clock pre-launch)
Output enable time (1/2-Clock pre-launch) Yn/Yn (falling edge)
output driving
Output enable time (3/4-Clock pre-launch)
DDR3-800/
1066/1333
Min
Max
Min
Max
0.65
1.0
0.65
1.0
0.65
1.2
0.65
1.2
0.5+
tQSK1(min)
0.25+
tQSK2(min)
0.5tQSK1(max)
0.75tQSK2(max)
DDR3-1600
Unit
ns
0.5+
tQSK1(min)
0.25+
tQSK2(min)
0.5tQSK1(max)
0.75tQSK2(max)
ps
ps
1 See “Qn and Yn Load Circuit” diagram.
2 See “Propagation Delay Timing” diagram below.
3 tPDM range (tPDM_max - tPDM_min) must remain as 350 ps. For example, if tPDM_min for a device is 0.65 ns, it’s tPDM_max
cannot be more than 1.0 ns, If tPDM_max for a device is 1.2 ns, it’s tPDM_min cannot be less than 0.85 ns.
4 See “Voltage Waveforms Address Floating” diagram.
Propagation Delay Timing
n
Input
n+1
n+2
n+3
n+4
n+5
n+6
CK(1)
DCS
C/A
CA0
Standard
Yn(1)
QxCSx
QxCKEx,
QxODTx
Qn(C/A)
C/A
prelaunch
RCA0(2)
Yn(1)
QxCSx,
QxCKEx,
QxODTx
RCA0
Qn(C/A)
tPDM
3/4 Clock Qn(C/A) pre-launch time
1 CK and Yn left out for better visibility.
2 RCA0 is re-driven command address signal based on input CA0.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Output Buffer Characteristics - edge rates over specified operating free-air temperature
range
Symbol
dV/dt_r
dV/dt_f
dV/dt_D2
Parameter
Conditions
DDR3DDR3L800/1066/1333
DDR3/DDR3L1600
Min
Max
Min
Max
rising edge slew rate 1 (1.5V operation)
2
7
2.0
5.5
rising edge slew rate 1 (1.35V operation)
1.8
5.0
1.8
5.0
falling edge slew rate 1 (1.5V operation)
2
7
2.0
5.5
1.8
5.0
1.8
5.0

1

1
1
falling edge slew rate (1.35V operation)
absolute difference between dV/dt_r and dV/dt_f 1
Unit
V/ns
V/ns
V/ns
1 Measured into test load at default register setting.
2 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Clock Driver Characteristics at Application Frequency (frequency band 1)
Symbol
Parameter
tJIT(CC+)
tJIT(CC-)
tSTAB
tFDYN
Cycle-to-cycle period jitter
Cycle-to-cycle period jitter
Stabilization time
Dynamic phase offset
Fractional Clock Output
tCKSK
skew1
tJIT(PER) Yn Clock Period jitter
tJIT(HPER) Half period jitter
tPWH/PWL
tQSK12
tQSK24
tSTAOFF
tDYNOFF6
Conditions
DDR3-800
DDR3-1066 DDR3-1333 DDR3-1600 Unit
Min
Max
Min
Max
Min
Max
Min
Max
0
-40
-50
-
40
0
6
50
15
0
-40
-50
-
40
0
6
50
15
0
-40
-50
-
40
0
6
50
15
0
-30
-40
-
30
0
6
40
10
ps
ps
µs
ps
ps
-40
-50
40
50
-40
-50
40
50
-40
-50
40
50
-30
-40
30
40
ps
ps
tPW = 1/2tCK ItJIT(hper)minI to
1.200 1.300 0.888 0.988 0.700 0.800 0.585 0.665
1/2tCK ItJIT(hper)maxI
Qn Output to Yn clock
Output Inversion
-100
200
-100
200
-100
200
-100
100
tolerance (Standard
enabled
1/2-Clock Pre-Launch)
Output Inversion
-100
300
-100
300
-100
300
-100
200
disabled
Qn Output to Yn clock
Output Inversion
-100
200
-100
200
-100
200
-100
100
tolerance (3/4 Clock
enabled
Pre-Launch)
Output Inversion
-100
300
-100
300
-100
300
-100
200
disabled
Standard 1/2-Clock
Pre-Launch
1.9
2.25
1.59
1.94
1.40
1.75
1.28 1.63
Average delay through the
tSTAOFF = tPDM + 1/2
register beween the input
tCK
clock and output clock over
3/4 Clock
“n” cycles5.
Pre-Launch
(1.5V operation)
2.53
2.88
2.06
2.41
1.77
2.12
1.59 1.94
tSTAOFF = tPDM + 3/4
tCK
Standard 1/2-Clock
Pre-Launch
1.90
2.45
1.59
2.14
1.40
1.95
1.28 1.63
Average delay through the tSTAOFF = tPDM + 1/2
tCK
register beween the input
clock and output clock5.
3/4 Clock
(1.35V operation)
Pre-Launch
2.53
3.08
2.06
2.61
1.77
2.32
1.59 1.94
tSTAOFF = tPDM + 3/4
tCK
Maximum variation in
160
130
110
delay between the input &
90
output clock
Yn pulse width HIG/LOW
duration3
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
ns
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ps
ns
ns
ns
ps
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Symbol
tBAND
Parameter
Conditions
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3
dB from unity gain)
DDR3-800
0.00
30
-0.5
257
COMMERCIAL TEMPERATURE
DDR3-1066 DDR3-1333 DDR3-1600 Unit
33
0.00
307
30
-0.5
33
0.00
357
30
-0.5
30
0.00
33
-0.5
kHz
%
407
-
MHz
1. This skew represents the absolute output clock skew and contains the pad skew and package skew (See “Clock Output (Yn) Skew”). This
parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to left side clock pairs between
Y0/Y0 and Y2/Y2, as well as right side of the clock pairs between Y1/Y1 and Y3/Y3. This is not a tested parameter and has to be considered
as a design goal only.
2. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package
routing skew (See “Qn Output Skew for Standard 1/2-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn
output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related
to simultaneous switching noise (SSO).
3. The parameter is a measure of the output clock pulse width HIGH/LOW. The output clock duty cycle can be calculated based on tPW.
4. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package
routing skew (See “Qn Output Skew for Standard 3/4-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn
output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related
to simultaneous switching noise (SSO).
5. This parameter measures the delay from the rising differential input clock which samples incoming C/A to the rising differential output
clock that will be used to sample the same C/A data. tSTAOFF may vary by the amount of tDYNOFF based on voltage and temperature drift as
well as tracking error and jitter. Including this variation tSTAOFF may not exceed the limits set by tSTAOFF(MIN) and tSTAOFF(MAX).
6. See “Measurement Requirement for tSTAOFF and tDYNOFF“.
7. Implies a -3 dB bandwidth and jitter peaking of 3 dB.
Clock Output (Yn) Skew
tCK
Y0
Y0
tCKSK
Y2
Y2
tCKSK
Y2
Y2
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Qn Output Skew for Standard 1/2-Clock Pre-Launch
tCK
Yn
Yn
tCK/2 tCK/2
Qn(C/A) Ideal
tQSK1 max
Qn(C/A) Late
tQSK1 min
Qn(C/A) Early
Qn Output Skew for 3/4-Clock Pre-Launch
tCK
Yn
Yn
3/4*tCK
tCK/4
Qn(C/A) Ideal
tQSK2 max
Qn(C/A) Late
tQSK2 min
Qn(C/A) Early
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Clock Driver Characteristics at Test Frequency (frequency band 2)
Symbol
tJIT(CC)
tSTAB
Parameter
Conditions
Min.
Max.
Unit
Cycle-to-cycle period jitter
0
160
ps
Stabilization time

15
us
1
tCKSK
tJIT(PER)
tJIT(HPER)
tQSK13
tQSK1SSO4
tQSK25
tQSK2SSO6
tDYNOFF
Total Clock Output skew
100
Fractional Clock Output skew2
Yn Clock Period jitter
Half period jitter
TBD
Output Inversion
Enabled
Output Inversion
Disabled
Output Inversion
Enabled
Output clock tolerance (3/4 Clock Pre-Launch)
Output Inversion
Disabled
Qn Output to clock tolerance (Standard
1/2-Clock Pre-Launch)
Maximum re-driven dynamic clock offset7
-160
-200
160
200
-100
TBD
-100
TBD
-100
TBD
-100
TBD
-500
500
ps
ps
ps
ps
ps
ps
1
This skew represents the absolute output clock skew and contains the pad skew and package skew.
2
This skew represents the absolute output clock skew and contains the pad skew and package skew (see “Clock Output (Yn)
Skew”). This parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to the
left side of the clock pair between Y0/Y0 and Y2/Y2, as well as the right side of the clock pair between Y1/Y1 and Y3/Y3.
3
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
and package routing skew (see “Qn Output Skew for Standard 1/2 Clock Pre-Launch”). The output clock jitter is not included in
this skew. This parameter applies to each side of the register independently. The Qn output can either be early or late.
4
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
and package routing skew. The output clock jitter is not included in this skew. This parameter applies to each side of the register
independently. This parameter includes the skew related to Simultaneous Switching Noise (SSO). The Qn output can either be
early or late.
5
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
and package routing skew (see “Qn Output Skew for Standard 3/4 Clock Pre-Launch”). The output clock jitter is not included in
this skew. This parameter applies to each side of the register independently. The Qn output can either be early or late.
6
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad skew, clock skew,
and package routing skew. The output clock jitter is not included in this skew. This parameter applies to each side of the register
independently. This parameter includes the skew related to Simultaneous Switching Noise (SSO). The Qn output can either be
early or late.
7 The re-driven clock signal is ideally centered in the address/control signal eye. This parameter describes the dynamic deviation
from this ideal position including jitter and dynamic phase offset.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Initialization
The SSTE32882HLB can be powered-on at 1.5V or 1.35V. After the voltage transition, stable power is provided for a
minimum of 200 µs with RESET asserted.
When the reset input (RESET) is low, all input receivers are disabled, and can be left floating. The RESET input is referenced
to VDD/2, therefore the reference voltage (VREF) is not required to be stable during reset. In addition, when RESET is low, all
control registers are restored to their default states. The QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs must drive low
during reset, and all other outputs must float. As long as the RESET input is pulled low the register is in low power state and
input termination is not present.
A certain period of time (tACT) before the RESET input is pulled high the reference voltage needs to be stable within
specification, the clock input signal must be stable, the register inputs DCS[n:0] must be pulled high to prevent any fortuitous
access to the control registers. Also, DCKE0 and DCKE1 inputs must be pulled low for the complete stabilization time (tSTAB).
After reset and after the stabilization time (tSTAB), the register must meet the input setup and hold specification before
accepting and transfering data from the register inputs to the register outputs. The RESET input must always be held at a valid
logic level once the input clock is present.
To ensure defined outputs from the register before a stable clock has been supplied, the register must enter the reset state during
power-up. It may leave this state only after a low to high transition on RESET while a stable clock signal is present on CK and
CK.
In the DDR3 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore,
no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs
will float quickly (except for QACKE0, QACKE1, QBCKE0 and QBCKE1, which are driven low), relative to the time to
disable the differential input receivers. The figure below shows the system timing of clock and data during the initialization
sequence.
Timing of clock and data during initialization sequence
Step 0,1 Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
CK(1)
VDD
RESET
DCKE[0:1]
Controller guarantees low logic
DA/C(2)
Controller guarantees valid logic
DODT[0:1]
Controller guarantees valid logic
Controller guarantees high logic
DCS0
DCS[n:1](4)
Controller guarantees high logic
Y[0:3](1)
QxCKE[0:1]
Register guarantees low logic
QxODT[0:1]
QxCS[n:0](4)
QxA/C(3)
ERROUT
High or Low
Register guarantees high logic
tACT = 8 cycles
PLL lock 6 s
tINIT = 200 s
Register drives CKE low until ready to transfer input signals
Register proper function and timing starting from here
1 CK is left out for better visibility.
2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range.
3 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
4 QxCKEn, QxODTn, QxCSn are not included in this range.
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
From a device perspective, the initialization sequence must be as shown in the following Device Initialization table.
SSTE32882HLB Device Initialization Sequence1.
Step
Power
VDD, AVDD,
PVDD
Inputs: Signals provided by the controller
RESET Vref
DCS
[n:0]2
DODT
[0:1]
DCKE DA/C
[0:1]
PAR_IN
Outputs: Signals provided by the device
CK,CK
QCS
[n:0]
QODT
[0:1]
QCKE
[0:1]
Z
Z
QxA/C ERROUT Y[0:3]
Y[0:3]
2
X or Z
X or
Z
X or
Z
X or Z
X or Z
Z
0
0V
X or Z
X or Z
X or
Z
1
0-->VDD
X or Z
X or Z
X or
Z
X or Z
X or
Z
X or
Z
X or Z
L
X or
Z
24
VDD
1.5V-->1.35V
1.35V-->1.5V
L
X or Z
X or
Z
X or Z
X or
Z
X or
Z
X or Z
L
Z
3
VDD
L
X or Z
X or
Z
X or Z
X or
Z
X or
Z
X or Z
running
4
VDD
L
X or Z
H
X or Z
L
X or
Z
X or Z
5
VDD
L
stable
voltage
H
X
L
X
6
VDD
H
stable
voltage
H
X
L
77
VDD
H
stable
voltage
H
X
X
Z
FB
OUT3
Z
Z
Z
X or Z X or Z X or Z
X or Z
X or Z
X or Z
Z
L5
Z
H5
Z
Z
Z
Z
L
Z
H
Z
Z
running
Z
Z
L
Z
H
Z
Z
X
running
Z
Z
L
Z
H
Z
Z
X
X
running
H
L6
L
X
H
running
running
X
X
running device Function Tables.
After Step 6 (Step 7 and beyond), the device outputs are as defined in the
1. x=Logic low or lolgic high. Z=floating.
2. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
3. The feedback clock (FBOUT and FBOUT) pins may or may not be actively driven by the device.
4. The system may power up using either 1.5V or 1.35V. The BIOS reads the SPD and adjusts the voltage if needed from 1.35V to 1.5V or from 1.5V to 1.35V.
After the voltage transition, stable power is provided for a minimum of 200 uS with RESET asserted.
5. QxCKEn and ERROUT will be driven to these logic states by the register after RESET is driven low and VDD is 1.5V or 1.35V (nominal).
6. This indicates the state of QxODTx after RESET switches from low-to-high and before the rising CK edge (falling CK edge). After the first rising CK edge,
within (tSTAB - tACT) us, the state of QxODTx is a function of DODTx (high or low).
7. Step 7 is a typical usage example and is not a register requirement.
Reset Initialization with Stable Power
The timing diagram in the following diagram depicts the initialization sequence with stable power and clock. This will apply to
the situation when we have a soft reset in the system. RESET will be asserted for minimum 100ns. This RESET timing is based
on DDR3 DRAM Reset Initialization with Stable Power requirement, and is a minimum requirement. Actual RESET timing
can vary base on specific system requirement, but it cannot be less than 100ns as required by JESD79-3 Specification.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Timing of clock and data during initialization sequence with stable power
Step 0,1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
CK(1)
VDD
RESET
DCKE[0:1]
Controller guarantees low logic
H or L
(2)
DA/C
Controller guarantees valid logic
DODT[0:1]
Controller guarantees valid logic
DCS0
H or L
Controller guarantees high logic
DCS[n:1]
H or L
Controller guarantees high logic
(1)
Y[0:3]
QxCKE[0:1] H or L
Register guarantees low logic
(3)
QxA/C
H or L
QxODT[0:1]
H or L
Hi-Z
QxCS[0:1]
H or L
Hi-Z
ERROUT
H or L
High or Low
Register guarantees high logic
tACT = 8 cycles
PLL lock 6 s
tINIT_Power_Stable = 100 nS
Register drives CKE low until ready to transfer input signals
Register proper function and timing starting from here
1 CK is left out for better visibility.
2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range.
3 QxCKEn, QxODTn, QxCSn are not included in this range.
4 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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COMMERCIAL TEMPERATURE
SSTE32882HLB Device Initialization Sequence1 when Power and Clock are Stable
Step Power
Inputs: Signals provided by the controller
Vref
Outputs: Signals provided by the device
QODT
[0:1]
QCKE
[0:1]
QxA/C
ERROUT
X
X
X
X
X
running running
running
X
X
X
X
X
running running
X
running
Z
Z
L4
Z
H4
Z
Z
X
X
running
Z
Z
L
Z
H
Z
Z
L
X
X
running
Z
Z
L
Z
H
Z
Z
X
L
X
X
running
Z
Z
L
Z
H
Z
Z
H
X
L
X
X
running
H
L5
L
X
H
H
X
X
X
X
running
VDD,
AVDD,
PVDD
RESET
DCS
[n:1]2
DODT DCKE
[0:1]
[0:1]
DA/C
PAR_I
N
CK, CK
QCS
[0:1]
0
VDD
H
stable
voltage
X
X
X
X
X
running
1
VDD
H
stable
voltage
X
X
X
X
X
2
VDD
L
stable
voltage
X
X
X
X
3
VDD
L
stable
voltage
X
X
X
4
VDD
L
stable
voltage
H
X
5
VDD
L
stable
voltage
H
6
VDD
H
stable
voltage
7
VDD
H
stable
voltage
Y[0:3]
Y[0:3]
FB
OUT3
running running
After Step 6 (Step 7 and beyond), the device outputs are as
defined in the device Function Tables.
1. x=Logic low or lolgic high. Z=floating.
2. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
3. The feedback clock (FBOUT and FBOUT) pins may or may not be actively driven by the device.
4. QxCKEn and ERROUT will be driven to these logic states by the register after RESET is driven low and VDD is 1.35V or 1.5V (nominal).
5. This indicates the state of QxODTx after RESET switches from low-to-high and before the rising CK edge (falling CK edge). After the first rising CK edge,
within (tSTAB - tACT) us, the state of QxODTx is a function of DODTx (high or low)
Parity
The SSTE32882HLB includes a parity checking function. The SSTE32882HLB accepts a parity bit from the memory
controller at its input pin PAR_IN one cycle after the corresponding data input, compares it with the data received on the
D-inputs and indicates on its open-drain ERROUT pin (active low) whether a parity error has occurred. The computation only
takes place for data which is qualified by at least one of the DCS[n:0] signals being LOW.
If an error occurs, and ERROUT is driven low with the third input clock edge after the corresponding data on the D-inputs. It
becomes high impedance with the 5th input clock cycle after the data corresponding with a parity error. In case of consecutive
errors ERROUT becomes high impedance with the 5th input clock cycle after the last data corresponding with a parity error.
The DIMM-dependent signals (DCKE0, DCKE1, DCS0, DCS1, DODT0 and DODT1) are not included in the parity check
computations.
Parity Timing Scheme Waveforms
The PAR_IN signal arrives one input clock cycle after the corresponding data input signals. ERROUT is generated three input
clock cycles after the corresponding data is registered. If ERROUTgoes low, it stays low for a minimum of two input clock
cycles or until RESET is driven low. The following figure shows the parity diagram with single parity-error occurrence and
assumes the occurrence of only one parity error when data is clocked in at the n input clock cycle (PAR_IN clocked in on the
n+1 input clock cycle).
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Timing of clock, data and parity signals
n
Input
n+1
n+2
n+3
CA1
CA2
P0
P1
n+4
n+5
n+6
CK(1)
CA0
CA
PAR_IN
P2
ERROUT
ERROUT resulting from CA0 - P0
1 CK left out for better visibility.
The next figure shows the parity diagram with two consecutive parity-error occurrences and assumes the occurrence of both
parity errors when data is clocked in at the n and n+1 input clock cycles (PAR_IN clocked in on the n+1 and n+2 input clock
cycles).
Two Consecutive Parity-Error Occurrences
n
Input
n+1
n+2
n+3
CA1
CA2
P0
P1
n+4
n+5
n+6
CK(1)
CA0
CA
PAR_IN
P2
ERROUT
ERROUT resulting from CA0 - P0, followed by 2nd error in CA1 -
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences separated by a clock cycle with no error
occurrence. The diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+2 input clock
cycles (PAR_IN clocked in on the n+1 and n+3 input clock cycles).
Two Parity-Error Occurrences Separated by a Clock Cycle of no Error Occurrence
Input
n
n+1
n+2
n+3
n+4
n+5
CA0
CA1
CA2
CA3
CA4
CA5
P0
P1
P2
P3
P4
n+6
n+7
n+8
n+9
CK(1)
CA
PAR_IN
P5
ERROUT
ERROUT resulting from CA0 - P0, followed by 2nd error in CA2 - P2
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences separated by two input clock cycles with no error
occurrence. The diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+3 input clock
cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles).
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
40
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Two Parity-Error Occurrences Separated by two Clock Cycles of no Error Occurrence
Input
n
n+1
n+2
n+3
n+4
n+5
n+6
CA0
CA1
CA2
CA3
CA4
CA5
P0
P1
P2
P3
P4
n+7
n+8
n+9
CK(1)
CA
PAR_IN
P5
ERROUT
ERROUT resulting from CA0 - P0, followed by 2nd error in CA3 - P3
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences; during chip-select and chip-deselect modes. The
diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+1 input clock cycles (PAR_IN
clocked in on the n+1 and n+2 input clock cycles). Parity error in the chip-select mod is detected, but parity error in the
chip-deselect mode is ignored.
Parity-Error Occurrence In Chip-Deselect Mode
n
Input
n+1
n+2
CA1
CA2
P0
P1
n+3
n+4
n+5
n+6
CK(1)
CA
CA0
PAR_IN
P2
DCSx
ERROUT
ERROUT resulting from CA0 - P0, subsequent parity errors during DCSx high ignored
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences; during normal operation and during control
register programming. The diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+3 input
clock cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles). The data on the n+3 input clock pulse is intended for
the control mode register. Parity error during control mode register programming is detected and the parity functionality is the
same as during normal operation. If a parity error occurs, the command is ignored.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
41
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Parity-Error Occurrences During Control Word Programming
n
Input
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
CK(1)
CA
CA0
PAR_IN
CA1
CA2
CA3
CA4
CA5
P0
P1
P2
P3
P4
P5
DCS0
DCS1
ERROUT
ERROUTresulting from CA0 - P0, followed by 2nd error during control word access in CA3 - P3
1 CK left out for better visibility.
POWER SAVING MODES
The device supports different power saving mechanisms.
When both inputs CK and CK are being held low the device stops operation and enters low-power static and standby operation.
It stops its PLL and floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1 which are kept driven low. Before
the device is taken out of standby operation by applying a stable input clock signal, the register inputs DCS[n:0] must be pulled
high to prevent accidential access to the control registers and DCKE0 as well as DCKE1 must be pulled low for a certain period
of time (tACT). The input clock must be stable for a time (tSTAB) before any access to the device takes place. Stopping the
clocks (CK = CK = low) will only put the SSTE32882HLB in low-power mode and will not clear the content of the control
words. The control words will reset only when RESET is diven low.
A float feature can be enabled by setting the corresponding bit in the control register. This causes the device to monitor all the
DCS[n:0] inputs and to float all outputs corresponding with the chip select gated inputs when all the DCS[n:0] inputs are high.
If any one of the DCS[n:0] inputs are low, the Qn outputs will function normally.
Once all the DCS[n;0] inputs are high, the gated address command inputs to the register can float to conserve input termination
power. DCKE0, DCKE1, DODT0 and DODT1 need to be driven by the system all the time.
The RESET input has priority over all other power saving mechanisms. When RESET is driven low, it will force the Qn
outputs to float, the ERROUT output high, the QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs low, and disables Input
Bus Termination (IBT).
REGISTER CKE POWER DOWN
If RC9[DBA1] is set to “1”, the SSTE32882HLB monitors both DCKEn input signals and enters into power saving state when
it latches Low on both DCKEn inputs and at least one of the DCKEn input has transitioned from High to Low. If any input
Chip Select signal (DCS[n:0]) is asserted together with DCKEn, the SSTE32882HLB transfers the corresponding command to
its outputs together with QxCKEn Low.
There are two modes of CKE Power Down selected by RC9. Bit DBA0 in RC9 indicates whether the register turns off IBT or
keeps IBT on.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
REGISTER CKE POWER DOWN WITH IBT OFF
Upon entry into CKE Power Down mode with IBT off, all register input buffers including IBT are disabled except for CK/CK,
DCKEn, FBIN/FBIN, and RESET. The SSTE32882HLB disables input buffers within tInDIS clocks after latching both
DCKEn Low. In order to eliminate and false parity check error, the PAR_IN input buffer has to be kept active for 1 tCK after
Address and Command input buffers disabled. After tInDIS, the register can tolerate floating input except for CK/CK, DCKEn
and RESET. The SSTE32882HLB also disables all its output buffers except for Yn/Yn, QxODTn, QxCKEn and
FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal. The
QxODTn and QxCKEn outputs are driven Low. The register output buffers are Hi-Z tQDIS clock after QxCKEn is driven Low.
This is shown in the next figure.
Power Down Mode Entry and Exit with IBT Off
n-1
n
n+4
n+8
n+12
n+16
n+20
CK
High
RESET
Hi-z
DAn,DBAn
DRAS,
DCAS,
DWE
Hi-z
Hi-z
PAR_IN
DODTn
Hi-z
High or Low
High or Low
tInDIS
Either or both DCKEn inputs are driven High
Low
DCKEn
High
DCS[i,0]
High or Low
DCS[j,1]
High or Low
High
n-1
n
High
Hi-z
H or L
High
Hi-z
n+4
H or L
n+8
Low
n+12
n+16
n+20
Yn
QxAn,
QxBAn
QxRAS,
QxCAS,
QxWE
QxODTn
Hi-z
tFixedoutput
High or Low
Hi-z
High or Low
Output buffers are Hi-z
High or Low
tQDIS
QxCKEn
High
QxCS[i,0]
High or Low
QxCS[j,1]
High or Low
Low
Low
High
High or Low
Either or both QxCKEn outputs are driven High
Low
Hi-z
see Note 3
Hi-z
see Note 3
High
High
Low
tEN
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882 into
Register Control Word access mode.
(3)Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is. For
all other operation QxCSn outputs will follow DCSn inputs.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
43
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
To re-enable the register from this power saving state, valid logic levels are required at all register inputs when either or both
DCKEn inputs are driven high. Upon either DCKE0 or DCKE1 input going High, the register immediately starts driving High
on the appropriate QxCKEn signal. The QxCSn signals are driven High and QxODTn signals are driven Low. Other output
signals QxRAS, QxCAS, QxWE, and QxAddr are driven either high or low to ensure stable valid logic an all register outputs
when QxCKEn goes High. The register drives output signals to these levels for tFIXEDOUTPUT to allow input receivers to be
stabilized. After the input recievers are stabilized, the register output follow their corresponding input levels. When exiting
CKE power down mode, either one of the Chip Select register inputs DCSn can be asserted for 1 tCK. For QuadCS capable
register, when working in quad rank mode, either two of the Chip Select register inputs DCSn can be asserted for 1 tCK. The
register guarantees that input receivers are stabilized within tFIXEDOUTPUT clocks after DCKEn input is driven High. This is
shown in the previous diagram.
REGISTER CKE POWER DOWN WITH IBT ON
Upon entry into CKE Power Down Mode with IBT on, all register input buffers excluding IBT are disabled except for CK/CK,
DCKEn, DODTn, FBIN/FBIN, and RESET. The SSTE32882HLB disables input buffers within tInDIS clocks after latching
both DCKEn Low. In order to eliminate any false parity check error, the PAR_IN input buffer has to be kept active for 1 tCK
after the Address and Command input buffers are disabled. After tInDIS, the register can tolerate floating input except for
CK/CK, DCKEn, DODTn and RESET. The SSTE32882HLB also disables all its output buffers except for Yn/Yn, QxODTn,
QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal.
The QxCKEn outputs are driven Low. The register output buffers are Hi-Z tQDIS clock after QxCKEn is driven Low. This is
shown below.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
44
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Power Down Mode Entry and Exit with IBT On
n-1
n
n+4
n+8
n+12
n+16
n+20
CK
tFixedoutput
High
RESET
DAn,DBAn
H, L or Hi-Z
DRAS,
DCAS,
DWE
H, L or Hi-Z
PAR_IN
H, L or Hi-Z
Hi-z
H, L or Hi-Z
Hi-z
H, L or Hi-Z
Hi-z
H, L or Hi-Z
High, Low or Toggling
DODTn
tInDIS
Low
H or L
DCKEn
High
DCS[i,0]
Hi-z
High or Low
High
Hi-z
High or Low
DCS[j,1]
n-1
n
Either or both DCKEn inputs are driven High
n+4
H or L
High
High or Low
H or L
High
High or Low
n+8
n+12
n+16
n+20
Yn
tFixedoutput
QxAn,
QxBAn
QxRAS,
QxCAS,
QxWE
High or Low
Hi-z
High or Low
Output buffers are Hi-z
QxODTn
QxCKEn
QxCS[i,0]
QxCS[j,1]
Hi-z
Follows Input (High, Low or Toggling)
H or L
tQDIS
High
High or Low
High
High or Low
Either or both QxCKEn outputs are driven High
Low
Hi-z
see Note 3
Hi-z
see Note 3
High
tEN
Follows Input (High or Low)
High
Follows Input (High or Low)
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882 into Register
Control Word access mode.
(3) UPon CKE Power Down exit, QxCSn will be held HIGH for a maximum of 1 tCK regardless of what DCSn input level is. For all other
operation, QxCSn outputs will follow DCSn inputs.
To re-enable the SSTE32882HLB from this Power Down Mode with IBT on, valid logic levels are required at all device inputs
when either or both DCKEn inputs are driven High. Upon either DCKE0 or DCKE1 input going High, the SSTE32882HLB
immediately starts driving High on the appropriate QxCKEn signals. The QxCSn signals are driven high and the QxODTn
signals follow the inputs. Other output signals QxRAS, QxCAS, QxWE and QxAddr are driven either high or low to ensure
stable valid logic on all device outputs when QxCKEn goes High. The device drives output signals to these levels for
tFIXEDOUTPUT to allow input receivers to be stablized. After the input receivers are stablized, the register output follow their
corresponding input levels. When exiting CKE power down mode, either one of the Chip Select register inputs DCSn can be
asserted for 1 tCK. For QuadCS capable register, when working in quad rank mode, either two of the Chip Select register
inputs DCSn can be asserted for 1 tCK. The device guarantees that input receivers are stablized within tFIXEDOUTPUT clocks
after DCKEn input is driven High. This is shown in the previous diagram.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
CLOCK STOPPED POWER DOWN MODE
To support S3 Power Management mode or any other operation that allows Yn clocks to float, the SSTE32882HLB supports a
Clock Stopped power down mode. When both inputs CK and CK are being held LOW, (VIL(static)) or float (will eventually
settle at LOW because of the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer, the device stops operation and
enters low-power static and standby operation. The corresponding timing are shown in “Clock Stopped Power Down Entry and
Exit with IBT On” and “Clock Stopped Power Down Entry and Exit with IBT Off“. The register device will stop its PLL and
floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1, which must be kept driven LOW.
The Clock Stopped power down mode can only be utilized once the DRAM received a self refresh command. In this state, the
DRAM ignores all inputs except CKE. Hence, all register outputs besides QxCKE0 and QxCKE1 can be disabled.
Clock Stopped Power Down Mode Entry
To enter Clock Stopped Power Down mode, the register will first enter CKE power down mode. Once in CKE power down
mode, the host will deasserts DCKEn for a minimum of one tCKoff before pulling CK and CK LOW. After holding CK and
CK LOW (VIL(static)) for at least one tCKEV, both CK and CK can be floated (because of the (10K-100K Ohm) pulldown
resistor in the CK/CK input buffer, CK/CK will stay at LOW even though they are not being driven).The register is now in
Clock Stopped Power Down mode.
After CK and CK are pulled LOW, the host has to keep DCKEn stable for at least one tCKEV before it can float DCKEn. At this
point, all input receivers and input termination of the SSTE32882HLB are disabled. The only active input circuits are CK and
CK, which are required to detect the wake up request from the host.
Clock Stopped Power Down Mode Exit
To wake up the register after Clock Stopped power down, the host must drive the register inputs DCS[n:0] must be driven to
HIGH (to prevent accidental access to the control registers), and DCKEn to LOW. After that, the host can apply a frequency
and phase accurate input clock signal. Within tACT after CK and CK resumed normal operation, the SSTE32882HLB outputs
start becoming a function of their corresponding inputs. The state of the DCS[n:0] inputs must not be changed before the end
of tSTAB. The input clock CK and CK must be stable for a time equal or greater than tSTAB before any access to the
SSTE32882HLB can takes place.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
46
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Clock Stopped Power Down Entry and Exit with IBT On
Input
n-1
n+4
n
m
CK/CK
RESET
High
DRAS
DCAS
DWE
PAR_IN
DCKEn
Hi-Z
H, L or Hi-Z
DAn, DBAn
DODTn
m+8
m+4
L or Float*
H, L or Hi-Z
H, L or Hi-Z
Hi-Z
High, Low or Toggling
tInDIS
Low
High
DCS[i,0] High or Low
H, L or Hi-Z
Hi-Z
H, L or Hi-Z
H or L
H, L or Hi-Z
Hi-Z
ODT8 ODT9 ODT10High,
ODT11Low
ODT12
ODT13 ODT14 ODT15 ODT16 ODT17
or Toggling
Hi-Z
Low
Either or both DCKEn inputs are driven High
tFixedoutput
Hi-Z
High or Low
High
High
Hi-Z
DCS[j,1] High or Low
tCKoff
tCKEV
x
High or Low
High
x
tACT
tSTAB
Output
n-1
n
n+4
Yn
QxAn,
QxBAn
Hi-Z
QxRAS,
QxCAS,
QxWE
Hi-Z
QxODTn
QxCKEn
Follows Input (High, Low or Toggling)
H or L
tQDIS
High
QxCS[i,0] High or Low
High
p
Hi-Z
tFixedoutput
High or Low
Follows Input (High, Low or Toggling)
driven Low
Hi-Z
qp+7
High or Low
Hi-Z
Hi-Z
p+4
Either or both QxCKEn outputs are driven High
see Note 3
High
Follows Input (H or L)
High
Follows Input (H or L)
see Note 3 tEN
QxCS[j,1] High or Low
QxCSn and QxODTn transfer from Hi-Z to high/low with in-accurate phase
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) With RC9 DBA0=’0’.
(3) When CK/CK inputs are floated, CK/CK inputs are pulled LOW by the (10K-100K Ohm) pulldown resistor in the CK/CK
input buffer.
(4) Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is.
For all other operation QxCSn outputs will follow DCSn inputs.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Clock Stopped Power Down Entry and Exit with IBT Off
Input
n-1
n+4
n
m
RESET
High
Hi-Z
DAn, DBAn
DRAS
DCAS
DWE
PAR_IN
DODTn
DCKEn
m+8
m+4
L or Float*
CK/CK
Hi-Z
Hi-Z
Hi-Z
High or Low
tInDIS
H or L
Low
High
ODT8 ODT9 ODT10High
ODT11or ODT12
Low ODT13 ODT14 ODT15 ODT16 ODT17
Hi-Z
Low
Either or both DCKEn inputs are driven High
tFixedoutput
Hi-Z
DCS[i,0] High or Low
High
High
x
Hi-Z
DCS[j,1] High or Low
tCKoff
High
Low
x
tACT
tCKEV
tSTAB
Output
n-1
n
n+4
Yn
QxAn,
QxBAn
Hi-Z
QxRAS,
QxCAS,
QxWE
Hi-Z
QxODTn
QxCKEn
p+4
tQDIS
tFixedoutput
High or Low
Hi-Z
High
Hi-Z
QxCS[i,0] High or Low
High or Low
driven Low
High
qp+7
High or Low
Hi-Z
High or Low
H or L
p
Hi-Z
Either or both QxCKEn outputs are driven High
see Note 3
see Note 3 tEN
High
High
QxCS[j,1] High or Low
Low
QxCSn and QxODTn transfer from Hi-Z to high/low with in-accurate phase
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) With RC9 DBA0=’1’.
(3) When CK/CK inputs are floated, CK/CK inputs are pulled LOW by the (10K-100K Ohm) pulldown resistor in the CK/CK
input buffer.
(4) Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is.
For all other operation QxCSn outputs will follow DCSn inputs.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
48
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
DYNAMIC 1T/3T TIMING TRANSACTION AND OUTPUT INVERSION ENABLING/DISABLING
Output Inversion is always enabled by default, after RESET is de-asserted, to conserve power and reduce simultaneous output
switching current. All A-outputs will follow the equivalent inputs, however the following B-outputs will be driven to the
complement of the matching A-outputs: QBA3 - QBA9, QBA11, QBA13 - QBA15, QBBA0 - QBBA2.
Output Inversion Functional Diagram
MRS
Register
QAxxx output
QBxxx output
Decoder
Dxxx input
The Output Inversion feature is not used during DRAM MRS command access. When Output Inversion is disabled, all
corresponding A and B output drivers of the SSTE32882HLB are driven to the same logic levels. Output Inversion must be
disabled when the MRS and EMRS commands must be issued to the DRAMs, for example, to assure that the same
programming is issued to all DRAMs in a rank.
With Output Inversion disabled during MRS access, in order to allow correct DRAM accesses with the consequently increased
simultaneous switching propagation delay the devices supports 3T timing. If this feature is invoked the device drives the
received data on its outputs for thee cycles instead of one. The only exceptions are the QxCS[n:0] outputs, which are the
QACS0, QACS1, QBCS0, and QBCS1 outputs in the QuadCS disabled mode and are QCS[3:0] in the QuadCS enabled mode.
When the device decodes the MRS command (DRAS=0, DCAS=0, DWE=0 and only one DCSn=0), it will disable the Output
Inversion function and pass the DRAM MRS command with an additional (one) clock delay on the appropriate QnCSx signal
to the DRAM. Back-to-back MRS command via the SSTE32882HLB must have a minimum of three clock delays. The
SSTE32882HLB will automatically enable Output Inversion if there is no DRAM MRS command three clocks after the
previous MRS command.
The inputs and outputs relationships for 1T timing and 3T timing are shown in the following three diagrams.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
1T Timing During Normal Operation
n
Input
n+1
n+2
n+3
n+4
CK(1)
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
DCKE[1:0]
DA[15:0], DBA[2:0]
DODT[1:0]
DRAS
DCAS, DWE
DCS0
DCS[n:1](2)
Outputs
@ 1T
n
n+1
n+2
n+3
Yn(1)
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
QCKE[1:0]
QAA[15:0], QABA[2:0],
QBA12, QBA10,
QBA[2:0]
QBA[15:13], QBA11,
QBA[9:13], QBBA[2:0]
QODT[1:0]
QRAS
QCAS, QWE
QCS0
QCS[n:1](2)
1 CK and Yn left out for better visibility.
2 n = 1 for QuadCS disabled, n = 3 for QuadCS enabled.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
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SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
3T Timing During DRAM MRS Command
n
Input
n+1
n+2
n+3
n+4
CK(1)
n+5
n+6
n+8
n+7
n+9
n+10
n+11
n+12
n+13
DCKE[1:0]
DA[15:0], DBA[2:0]
DODT[1:0]
Output Inversion Disabled
DRAS
Output Inversion enabled
DCAS, DWE
DCS0
DCS[n:1](2)
Outputs
@ 3T
n
n+1
n+2
n+3
Yn(1)
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
QCKE[1:0]
QAA[15:0], QABA[2:0],
QBA12, QBA10,
QBA[2:0]
QBA[15:13], QBA11,
QBA[9:3], QBBA[2:0]
QODT[1:0]
QRAS
QCAS, QWE
QCS0
QCS[n:1](2)
1 CK and Yn left out for better visibility.
2 n = 1 for QuadCS disabled, n = 3 for QuadCS enabled.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
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SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
3T Timing During Multiple DRAM MRS Commands
n
Input
n+1
n+2
n+3
n+4
CK(1)
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
DCKE[1:0]
DA[15:0], DBA[2:0]
DODT[1:0]
Output Inversion Disabled
Output Inversion enabled
DRAS
DCAS, DWE
DCS0
DCS[n:1](2)
Outputs
@ 3T
n
n+1
n+2
n+3
Yn(1)
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
QCKE[1:0]
QAA[15:0], QABA[2:0],
QBA12, QBA10,
QBA[2:0]
QBA[15:13], QBA11,
QBA[9:3], QBBA[2:0]
QODT[1:0]
QRAS
QCAS, QWE
QCS0
QCS[n:1](2)
1 CK and Yn left out for better visibility.
2 n = 1 for QuadCS disabled, n = 3 for QuadCS enabled.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
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SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
CONTROL WORDS
The SSTE32882HLB registers have internal control bits for adapting the configuration of certain device features. The control
bits are accessed by the simultaneous assertion of both DCS0 and DCS1 in the QuadCS disabled mode. In the QuadCS enabled
mode, the simultaneous assertion of both DCS2 and DCS3 during normal operation, and the assertion of all four DCS[3:0]
inputs also results in control word access. However, assertion of any three DCS[3:0] inputs is not legal. Register Qn outputs
including QxCKE0, QxCKE1, QxODT0 and QxODT1 remain in their previous state. Select signals QxCS[n:0] are set to high
during control word access.
The SSTE32882HLB allocates decoding for up to 16 words of control bits, RC0 through RC15. Selection of each word of
control bits is presented on inputs DA0 through DA2 and DBA2. Data to be written into the configuration registers need to be
presented on DA3, DA4, DBA0 and DBA1. Bits DA[15:5] need to be low, and at least one DCKEn input must be high, for
valid data access. If Power Down mode is enabled in RC9[DBA1], at least one DCKE must be high for valid control word
access. The inputs on DRAS, DCAS, DWE, and DODT[1:0] can be either high or low, and are ignored by the SSTE32882HLB
during control word access. In all cases Address and command parity is checked during control word write operations.
ERROUT is asserted and the command is ignored if a parity error is detected. Using this mechanism, controllers may use the
SSTE32882HLB to validate the address and command bus signal integrity to the module as long as one or more of the parity
checked input signals DA3-DA15, DBA0, DBA1, DRAS, DCAS, DWE are kept high.
Control word access must be possible at any defined frequency independent of the current setting of DBA1 control registers.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Control Words
The device features a set of control words, which allow the optimization of the device properties for different raw card designs.
The different control words and settings are described below. Any change to these control words requires some time for the
device to settle. For changes to the control word setting, except for RC2 (bits DBA1 and DA3) and RC10, the controller needs
to wait tMRD after the last control word access, before further access to the DRAM can take place. For any changes to the clock
timing (RC2: bits DBA1 and DA3) and RC10, this settling may take up to tSTAB time. All chip select inputs (DCS[n:0]) must
be kept high during that time. The Control Words can be accessed and written to when running within any one defined
frequency band.
CONTROL WORD DECODING
The values to be programmed into each control word are presented on signals DA3, DA4, DBA0 and DBA1 simultaneously
with the assertion of the control word access through DCS0 and DCS1, or DCS2 and DCS3 in the QuadCS enabled mode, and
the address of the control word on DA0, DA1, DA2 and DBA2.
The reset default state of Control Words 0 .. 5 and Control Words 8 .. 15 is “0”. The reset default state for Control Words 6 and
7 is vendor specific. Every time the device is reset, its default state is restored. Stopping the clocks (CK = CK = low) to put the
device in low-power mode will not alter the control word settings.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Control Word Decoding with QuadCS Mode Disabled
Signal
Control Word
Symbol
DCS0
DCS1
DBA2
DA2
DA1
DA0
Meaning
None
None
Control word 0
Control word 1
Control word 2
Control word 3
Control word 4
Control word 5
Control word 6
Control word 7
Control word 8
Control word 9
Control word 10
Control word 11
n/a
n/a
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
RC10
RC11
H
X
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
L
L
L
L
L
L
L
H
H
H
H
X
X
L
L
L
L
H
H
H
H
L
L
L
L
X
X
L
L
H
H
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
L
H
L
H
No control word access
No control word access
Global Features Control word
Clock Driver Enable Control word
Timing Control word
CA Signals Driver Characteristics Control word
Control Signals Driver Characteristics Control word
CK Driver Characteristics Control word
Reserved, free to use by vendor
Reserved, free to use by vendor
Additional IBT Setting Control Word
Power Saving Settings Control word
Encoding for RDIMM Operating Speed
Encoding for RDIMM Operating VDD
Control word 12
Control word 13
Control word 14
Control word 15
RC12
RC13
RC14
RC15
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Control Word Decoding with QuadCS Mode Enabled
Signal
Control
Word
Symbol
DCS[3:0]
None
None
None
None
None
None
None
None
Control word 0
Control word 1
Control word 2
Control word 3
Control word 4
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
RC0
RC1
RC2
RC3
RC4
HXHX
HXXH
XHHX
XHXH
HLLL
LHLL
LLHL
LLLH
Control word 5
Control word 6
Control word 7
Control word 8
Control word 9
Control word 10
Control word 11
Control word 12
Control word 13
Control word 14
Control word 15
RC5
RC6
RC7
RC8
RC9
RC10
RC11
RC12
RC13
RC14
RC15
LLHH
or
HHLL
or
LLLL
DBA2 DA2
DA1
DA0
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
X
X
X
X
X
X
L
L
H
H
L
X
X
X
X
X
X
X
X
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Meaning
No control word access
Ilegal Input States
Global Features Control word
Clock Driver Enable Control word
Timing Control word
CA Signals Driver Characteristics Control word
Control Signals Driver Characteristics Control
word
CK Driver Characteristics Control word
Reserved, free to use by vendor
Reserved, free to use by vendor
Additional IBT Setting Control Word
Power Saving Settings Control word
Encoding for RDIMM Operating Speed
Encoding for RDIMM Operating VDD
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
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SSTE32882HLB
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SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
CONTROL WORD FUNCTIONS
The following sections describe the contents of each control word.
RC0: Global Features Control Word
Input
DBA1
DBA0
DA4
DA3
x
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
x
x
Definition
Encoding
Output Inversion
Output Inversion enabled
Output Inversion disabled
Float outputs
Float disabled
A outputs disabled
A outputs enabled
Float enabled
A outputs disabled
B outputs disabled
B outputs enabled
B outputs disabled
Output Inversion: When Output Inversion is disabled, all A and B output drivers of the SSTE32882HLB are driven to the same
levels.
Output Inversion may be enabled to conserve power, reducing simultaneous switching output currents in the SSTE32882HLB.
When Output Inversion is enabled, all A outputs will follow the equivalent inputs, however the following B outputs will be
driven to the complement of the matching A output: QBA03-QBA9, QBA11, QBA13 - QBA15, QBBA0 - QBBA2. Output
Inversion does not affect SSTE32882HLB control word programming.
Output Inversion Functional Diagram
RC0-DA3
Register
QAxxx output
Control Bit
Dxxx input
QBxxx output
Output floating refers to allowing many A/B outputs to enter a hi-Z state when they are not being used. This is to conserve
power when the outputs are resistively terminated to a voltage (e.g., VDD, VTT, or VSS). When output floating is enabled, the
following outputs (on both matching A and B outputs) are hi-Z when not actively driven: QxAn, QxBAn, QxRAS, QxCAS,
and QxWE. Output floating is independent of Output Inversion and does not affect SSTE32882HLB control word
programming.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
A or B output disable allows the use of the SSTE32882HLB in reduced parts count applications such as DDR3 Mini-RDIMMs.
When output disable is asserted, all outputs on the corresponding side of the register, including the clock drivers, remain in
Hi-Z at all times. When RC0[DBA0] = 1, all A-side Q-outputs and Y1 and Y3 outputs will be disabled. When RC0[DBA1] =
1, all B-side Q-outputs and Y0 and Y2 outputs will be disabled. When RC0[DBA0] = 1 and RC0[DBA1] = 1, all A-side and
B-side Q-outputs and Yn outputs will be disabled.
RC1: Clock Driver Enable Control Word
Input
DBA1
DBA0
DA4
DA3
x
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
x
x
Definition
Encoding
Disable Y0/Y0 clock
Y0/Y0 clock enabled
Y0/Y0 clock disabled
Disable Y1/Y1 clock
Y1/Y1 clock enabled
Y1/Y1 clock disabled
Disable Y2/Y2 clock
Y2/Y2 clock enabled
Y2/Y2 clock disabled
Disable Y3/Y3 clock
Y3/Y3 clock enabled
Y3/Y3 clock disabled
Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine
which clock outputs are used by the module. The PLL remains locked on CK/CK unless the system stops the clock inputs to
the SSTE32882HLB to enter the lowest power mode.
RC2: Timing Control Word
Input
Definition
Encoding
Address- and command-nets pre-launch
(Control Signals QxCKE, QxCS, QxODT
do not apply)
Address and command nets pre-launch (3/4
Clock)
DBA1
DBA0
DA4
DA3
x
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
x
150 
0
x
x
x
Operation (Frequency Band 1)
1
x
x
x
Standard (1/2 Clock)
1T timing
1T/3T Output timing
3T timing(1)
100 
Input Bus Termination(2)
Frequency Band Select
Test Mode (Frequency Band 2)
1 There is no floating once 3T timing is activated.
2 If MIRROR is ‘HIGH’ then Input Bus Termination (IBT) is turned off, or on all inputs except the DCSn and DODTn
inputs.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
The IBT control is also located in this control word, with two options of 100 or 150 which can be selected to adapt to
different system scenarios. At power-up, the SSTE32882HLB IBT defaults to 100. The system controller can reprogram the
termination resistance to 150 by setting this bit. Only the DAn, DBAn, DRAS, DCAS, DWE, DCSn, DODTn, DCKEn, and
PAR_IN inputs have the IBT. The CK, CK, FBIN, FBIN, RESET, and MIRROR inputs do not have IBT.
Effective IBT Tolerance Requirement
Total Effective IBT Value Tolerance1
Min
Max
-10%
+10%
1 Example: for 100 Ohm IBT, Min = 90 Ohms, Max = 110 Ohms
Mismatch Tolerance Between R-IBT-Up and R-IBT-Down
Max
Mismatch Tolerance Between R-IBT-Up
ABS(5%)
and R-IBT-Down1
1 (1 - R-IBT-Up/R-IBT-Down) *100% < ABS(5%)
If MIRROR is ‘HIGH’ then it is assumed the register is located on the back side of a module where two registers are tied
together on the input side. In this case, for the register on the back side, the IBT are turned off on all inputs except the DCSn
and DODTn inputs.
The following diagram illustrates the pre-launch feature whereby double loaded nets in a 2-rank configuration can be driven
with an earlier signal compared to output clock and control in order to compensate for the slower signal travel speed. This
timing applies at all supported frequencies.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Standard versus Address and Command-Nets pre-launch Timing
n
Input
n+1
n+2
n+3
n+4
n+5
n+6
CK(1)
DCS
C/A
CA0
Standard
Yn(1)
QxCSx,
QxCKEx,
QxODTx
Qn(C/A)
C/A
prelaunch
RCA0(2)
Yn(1)
QxCSx,
QxCKEx,
QxODTx
Qn(C/A)
RCA0
3/4 Clock Qn(C/A) pre-launch time
1 CK and Yn left out for better visibility.
2 RCA0 is re-driven command address signal based on input CA0.
Output driver characteristics are separately controlled for outputs that are often loaded with twice as many DRAMs as the other
outputs. Outputs are grouped as follows:
•
•
•
CA Signals =QxA0-QxAn, QxBA0-QxBAn, QxRAS, QxCAS, QxWE
Control Signals = QxCSn, QxCKEn, QxODTn
CK = Yn .. Yn
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
RC3: CA Signals Driver Characteristics Control Word
Input
Definition
Encoding
DBA1
DBA0
DA4
DA3
x
x
0
0
x
x
0
1
x
x
1
0
x
x
1
1
Reserved
0
0
x
x
Light Drive (4 or 5 DRAM Loads)
0
1
x
x
1
0
x
x
1
1
x
x
Light Drive (4 or 5 DRAM Loads)
Command/Address
Driver-A Outputs
Command/Address
Driver-B Outputs
Moderate Drive (8 or 10 DRAM Loads)
Strong Drive (16 or 20 DRAM Loads)
Moderate Drive (8 or 10 DRAM Loads)
Strong Drive (16 or 20 DRAM Loads)
Reserved
RC4: Control Signals Driver Characteristics Control Word
Input
Definition
Encoding
0
Light Drive (4 or 5 DRAM Loads)
1
Control Driver-A
Outputs
Moderate Drive (8 or 10 DRAM Loads)
DBA1
DBA0
DA4
DA3
x
x
0
x
x
0
x
x
1
0
x
x
1
1
0
0
x
x
Light Drive (4 or 5 DRAM Loads)
0
1
x
x
Moderate Drive (8 or 10 DRAM Loads)
1
0
x
x
1
1
x
x
Reserved
Reserved
Control Driver-B
Outputs
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Reserved
Reserved
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SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
RC5: CK Driver Characteristics Control Word
Input
Definition
Encoding
DBA1
DBA0
DA4
DA3
x
x
0
0
x
x
0
1
x
x
1
0
x
x
1
1
Reserved
0
0
x
x
Light Drive (4 or 5 DRAM Loads)
0
1
x
x
1
0
x
x
1
1
x
x
Light Drive (4 or 5 DRAM Loads)
Clock Y1, Y1, Y3, and Y3
Output Drivers
Clock Y0, Y0, Y2, and Y2
Output Drivers
Moderate Drive (8 or 10 DRAM Loads)
Strong Drive (16 or 20 DRAM Loads)
Moderate Drive (8 or 10 DRAM Loads)
Strong Drive (16 or 20 DRAM Loads)
Reserved
RC8: Additional IBT Setting Control Word
Input
Definition
Encoding
IBT Compatibility Settings
IBT as defined in RC2
DBA1
DBA0
DA4
DA3
x
0
0
0
0
x
x
x
1
x
x
x
x
0
0
1
Reserved
x
0
1
0
200
x
0
1
1
Reserved
x
1
0
0
x
1
0
1
Reserved
x
1
1
0
Reserved
x
1
1
1
Off3
Mirror Mode
IBT Off when MIRROR is HIGH1
IBT On when MIRROR is HIGH2
300
Input Bus Termination1
1 If MIRROR is HIGH, then Input Bus Termination (IBT) is turned off on all inputs, except DCSn and DODTn inputs.
2 When DBA0 = 1, DA4 = 1, or DA3 = 1, IBT on all inputs is turned off no matter what the DBA1 setting
may be.
3 With this setting, no matter what the logic level of the MIRROR input pin may be, IBT on all inputs (including DCSn and DODTn) is turned off.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
RC9: Power Saving Settings Control Word
Input
DBA1
DBA0
DA4
DA3
x
x
x
0
x
x
x
1
x
x
0
x
x
x
1
x
1
0
x
x
1
1
x
x
0
x
x
x
1
x
x
x
Definition
Encoding
Floating
Weak Drive Mode
Reserved
CKE Power Down Mode
Typical weak drive enabled1
Weak Driver Impedance:
70 (min), 100 (nom), 120 (min)
Reserved
Reserved
CKE power down with IBT ON, QxODT is a function
of DxODT
CKE power down with IBT off, QxODT held LOW
CKE Power Down Mode
Enable
Disabled
Enabled
1
To get optimum power saving while keeping the VIL DC (max) limit for SDRAM, the Weak Drive Mode Impedance
should be 70 (min), 100 (nom), 120 (min).
The SSTE32882HLB features a weak drive mode, which is a variant of the floating mode set in RC0. If Bit DA4 of RC0 is set
to ‘1’, then Bit DA3 of RC9 selects between floating mode and weak drive mode.
The SSTE32882HLB register supports different power down modes. By default, the Power Down feature is disabled
(RC9[DBA1]=0). The register ignores CKE Power Down mode setting when this function is disabled. If the CKE Power
Down mode is enabled (RC9[DBA1]=1), then power down is invoked once both DCKE0 and DCKE1 are low. Bit DBA0
selects how IBT and ODT behaves.
RC10: Encoding for RDIMM Operating Speed
The encoding value is used to inform the register the operating speed that it is being run at in a system. It is not an indicator of how fast
or slow a register can run
Input
Definition
Encoding
0
f < 800 MTS
DDR3-800 (default)
0
1
800 MTS < f < 1066 MTS
DDR3-1066
0
1
0
1066 MTS < f < 1333 MTS
DDR3-1333
x
0
1
1
1333 MTS < f < 1600 MTS
DDR3-1600
x
1
0
0
Reserved
Reserved
x
1
0
1
Reserved
Reserved
x
1
1
0
Reserved
Reserved
x
1
1
1
Reserved
Reserved
DBA1
DBA0
DA4
DA3
x
0
0
x
0
x
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
RC11: Operating Voltage VDD Control Word
RC11 is used to inform the SSTE32882HLB under what operating voltage VDD will be used. The register can use the
information to optimize functionality and performance LV condition.
Input
Definition
Encoding
DBA1
DBA0
DA4
DA3
x
x
0
0
x
x
0
1
x
x
1
0
x
x
1
1
Reserved
0
0
x
x
Reserved
0
1
x
x
Reserved
1
0
x
x
Reserved
1
1
x
x
Reserved
DDR3 Normal 1.5V mode
DDR3L 1.35V mode
Register VDD Operating Voltage
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Reserved
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SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Test Circuits and Switching Waveforms
Parameter Measurement Information
All input pulses are supplied by generators having the following characteristics: 300MHz PRR  810 MHz; Zo = 50 ; input
slew rate = 1 V/ns ± 20%, unless otherwise specified. The outputs are measured one at a time with one transition per
measurement.
Qn and Yn Load circuit for propagation delay and slew measurement
DUT
TL = 50
CK
CK Inputs
CK
Test point
OUT
Test point
RL=50
VTT
CL<2.5pF(1)
RL = 100
Trace delay matched on load board
Test point
1 CL is parasitic (probe and jig capacitance).
Voltage waveforms; propagation delay times
CK
VICR
VICR
tPDM1
tPDM2
VI(P-P)
CK
Q Output
VTT
VTT
VTT = VDD/2
VICR Cross Point Voltage
VI(P-P) = 500mV (1.5V operation) or 450mV (1.35V operation)
tPDM1, tPDM2 the larger number of both has to be taken when performing tPDM max measurement, the smaller number of both
has to be taken when performing tPDM min measurement.
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Voltage waveforms address floating
CK
CK
DCSn
QxCSn
Yn
VOX
VOX
VOD
Yn
tEN
tDIS
Outputs
virtual VTT crossing*
Refer to “Calculating the virtual VREF crossing point”.
Enabling and disabling the CA outputs must not violate DRAM setup and hold time requirements. Therefore a tDIS transition
may not occure earlier than a regular (HL/LH) transition and a tEN transition may not occure later than a regular (HL/LH)
transition. Regular transitions are measured between CK/CK and CA/VTT crossings however a VTT crossing is not available in
the state where the outputs are Hi-Z. To allow a correct and not overly conservative measurement a virtual VTT crossing point
is defined below. The calculation of the virtual VTT crossing point is shown in the Figure, “Calculating the virtual VTT crossing
point”. The voltage levels for yxa and yxb are measured from VTT (VDD/2) and should be selected such that the region between
t1 and t2 covers a linear range and represents a typical slope of the waveform within the transition area. They have to be used
signed in the formula.
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Calculating the virtual VTT crossing point
Yn
UCK=UCK
Yn
tEN
tDIS
t1a
t1b
t2a
t2b
VOH
VTT
actual waveform
y1a
y1a
y2a
y2b
y2a
VTT=VDD/2
tEN = t1a + y1a(t1a-t2a)/(y2a-y1a)
y2b
y1b
VTT
y1b
VOL
tDIS = t1b + y1b(t1b-t2b)/(y2b-y1b)
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Voltage waveforms, HIGH-to-LOW slew rate measurement
VOH
OUTPUT
+ AC Level
dv_f
Vtt
- AC Level
VOL
dt_f
Voltage waveforms, LOW-to-HIGH slew rate measurement
dt_r
VOH
+ AC Level
Vtt
dv_r
- AC Level
VOL
OUTPUT
AC Level for Slew Rate Measurement
DDR3-800/1066/1333/1600
AC Level (1.5V)
150mV
AC Level (1.35V)
135mV
Error Output Load Circuit and Voltage Measurement Information
All input pulses are supplied by generators having the following characteristics: 300MHz  PRR  810MHz; Zo = 50 ; input
slew rate = 1 V/ns ± 20%, unless otherwise specified.
Load circuit, ERROUT Outputs
VDD
DUT
RL=50
OUT
Test point
RL=10pF
See Note (1)
1 CL includes probe and jig capacitance.
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The output driver characteristics are separately controlled for outputs that are often loaded with twice as many DRAMs as the other
outputs. Outputs are grouped as follows:
•
•
•
CA Signals =QxA0-QxAn, QxBA0-QxBAn, QxRAS, QxCAS, QxWE
Control Signals = QxCSn, QxCKEn, QxODTn
CK = Yn .. Yn
The register Output Slew-Rate & R-on for Each Drive Strength as shown below.
Output Slew-Rate & R-on (targets)
Drive Settings
Output Driver R-on Targets
(Ohms)
Output Slew-Rate (V/ns)
DDR3-800/1066/1333
DDR3-1600
DDR3L-800/1066/1333
/1600
Min
Nom
Max
Min
Max
Min
Max
Min
Max
Light
22
26
30
2
7
2
5.5
1.8
5.0
Moderate
16
19
22
2
7
2
5.5
1.8
5.0
Strong
12
14
16
2
7
2
5.5
1.8
5.0
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Measurement Requirement for tstaoff and tdynoff
CK
CK
tstaoff(max)1
tstaoff1
tstaoff(min)1
Yn
Yn
tdynoff2
1. tstaoff = propagation delay for clock signal (rising CK input clock edge to rising Yn output clock edge).
2. tdynoff = maximum tstaoff variation over voltage and temperature.
This includes all sources of jitter and drift (e.g.Thermal noise, supply noise, voltage/temperature drift,
SSC tracking, SSO, etc) except reference clock noise.
Voltage waveforms, Reset to ERROUT tPLH Measurement
CMOS RESET
INPUT
VDD
VDD/2
0V
tPLH
OUTPUT
Open Drain ERROUT
VOH
0.65V
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0V
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Voltage waveforms, CK to ERROUT tHL Measurement
CK
VICR
VID
CK
tLH
Open Drain Output ERROUT
VOH
VTT
VOL
VTT = VDD/2
Voltage waveforms, CK to ERROUT tLH Measurement
CK
VID
VICR
CK
tLH
VOH
0.65V
Open Drain Output ERROUT
0V
Recommended Filtering for the Analog Power Supply (AVDD)
VIA
CARD
R1
BEAD
AVDD
VDDQ
1
4.7uF
0.1uF
2200pF
GND
SSTE32882
SSTEF32882
AGND
VIA
CARD
Place the 2200pF capacitor close to the PLL.
Use a wide trace for the PLL analog power and ground.
Connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL).
Bead is 0.8 DC max, 600 at 100MHz.
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Ordering Information
SSTE
XXXX
XX
X
X
Device
Type
Package
Temp.
Range
Shipping
Carrier
8
Tape and Reel
Blank
Commercial (0o C to +70o C)
AKG
Low Profile, Fine Pitch, Ball Grid Array - Green
BKG
(0.65mm ball pitch, 11 x 20 grid, 8.0mm x 13.5mm
Thin Profile, Fine Pitch, Ball Grid Array - Green
(0.65mm ball pitch, 8 x 22 grid, 6.0mm x 15mm)
32882HLB Registering Clock Driver with Parity Test
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Discover what IDT know-how can do for you. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
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